Pen

Abstract

Provided is a pen that can suppress circuit area and power consumption and transmit signals at a sufficient high voltage. The pen (1) includes: an electrode (P0); a power supply circuit (30) that supplies a first voltage (= VDD1); an LVIC (10) connected to the power supply circuit (30) and outputting a downlink signal at the first voltage; an HVIC (20) including a level converter (22) that outputs a downlink signal at a second voltage (= VDD2 - VSS2) higher than the first voltage; an inter-IC Tx wiring (WTx0) that supplies the downlink signal at the first voltage from the LVIC (10) to the HVIC (20); an electrode wiring (WP0) that supplies the downlink signal at the second voltage from the HVIC (20) to the electrode (P0); and a booster circuit (40) connected to the power supply circuit (30) and supplying the second voltage to the level converter (22).

Description

Technical Field

[0001] The present invention relates to a pen, and more particularly to a pen having a function of transmitting a signal at a high voltage of several tens of V. Background Art

[0002] Among pens (electronic pens) used with a position detection device such as a tablet terminal, there are pens that transmit signals at a high voltage of several tens of V. For example, Patent Document 1 discloses a pen that transmits a high voltage signal of 10 V to 20 V to a position detection device. In addition, Patent Document 2 discloses a pen having a booster section using a charge pump and a booster section using a transformer.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: US Patent No. 8,866,767 Specification

[0006] Patent Document 2: Japanese Patent No. 6,148,423 Specification Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] When the internal circuit of a pen that transmits a signal at a high voltage is incorporated in one integrated circuit (IC), all circuits have to be fabricated using a high breakdown voltage process. As a result, the circuit scale becomes large, the circuit area becomes large. In addition, the power consumption also increases. Therefore, there is a need for a pen that can suppress the circuit area and power consumption and transmit a signal at a sufficient high voltage.

[0009] Therefore, one object of the present invention is to provide a pen that can suppress the circuit area and power consumption and transmit a signal at a sufficient high voltage.

[0010] Means for Solving the Problems

[0011] The pen of the present invention includes: an electrode; a power supply circuit that supplies a predetermined voltage; an LVIC connected to the power supply circuit and outputting a transmission signal at a first voltage; an HVIC including a level converter that outputs the transmission signal at a second voltage higher than the first voltage; an inter-IC wiring that supplies the transmission signal at the first voltage from the LVIC to the HVIC; an electrode wiring that supplies the transmission signal at the second voltage from the HVIC to the electrode; and a booster circuit connected to the power supply circuit and supplying the second voltage to the level converter.

[0012] Advantages of the Invention

[0013] According to the present invention, since an LVIC that can be manufactured by a low breakdown voltage process is used to generate a transmission signal, the circuit area and power consumption of an HVIC that requires manufacturing under a high breakdown voltage process can be correspondingly reduced. Therefore, it is possible to suppress the circuit area and power consumption and transmit a signal at a sufficient high voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a diagram showing a pen 1 and a position detection device 2 according to a first embodiment of the present invention.

[0015] Figure 2 FIG. 2 is a diagram showing the internal structure of the pen 1.

[0016] Figure 3 FIG. 3 is a diagram showing a structural example of a high voltage switch 23.

[0017] Figure 4 FIG. 4(a) is a diagram showing the internal structure of switch circuits 26 and 27, FIG. 4(b) is a diagram showing the internal structure of a buffer circuit 53 shown in FIG. 4(a), and FIG. 4(c) is a waveform diagram for explaining the operation of the switch circuits 26 and 27.

[0018] Figure 5 FIG. 5(a) is a diagram showing the internal structure of an Rx unit 13, FIG. 5(b) is a diagram showing the relationship between the reception level of an uplink signal US and the amplitude level of a signal output from a variable gain amplifier 61, and FIG. 5(c) is a diagram showing the relationship between the reception level of the uplink signal US and the gain of the variable gain amplifier 61.

[0019] Figure 6 FIG. 6 is a diagram showing the internal structure of a pen 1 according to a second embodiment of the present invention.

[0020] Figure 7 FIG. 7 is a waveform diagram for explaining the operation of a logic circuit 12 in a reflection mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the Figure 1 accompanying drawings.

[0022] Figure 1 FIG. 1 is a diagram showing a pen 1 and a position detection device 2 according to a first embodiment of the present invention. As shown in this figure, the pen 1 is a pen-shaped device configured to be used by a user while held in the hand. The position detection device 2 is a computer such as a tablet terminal having an input surface, and is configured to include a sensor 3. Although not shown, the sensor 3 is configured to include a plurality of linear electrodes arranged so as to cover the entire input surface.

[0023] An electrode (the tip electrode P0 and the ring electrode P1 described later) is provided at the tip of the pen 1, and the pen 1 is configured to be able to bidirectionally transmit and receive signals with the position detection device 2 via this electrode. Hereinafter, the signal transmitted from the position detection device 2 toward the pen 1 among the signals transmitted and received in this way is referred to as the uplink signal US (received signal), and the signal transmitted from the pen 1 toward the position detection device 2 is referred to as the downlink signal DS (transmitted signal). Details will be described later. The downlink signal DS is composed of the downlink signal DS1 transmitted from the tip electrode P0 described later and the downlink signal DS2 transmitted from the ring electrode P1 described later. Specifically, as Figure 1 shown, the transmission and reception of the uplink signal US and the downlink signal DS are achieved via the electrostatic capacitance formed between the electrode of the pen 1 and each linear electrode constituting the sensor 3.

[0024] Figure 2 FIG. is a diagram showing the internal structure of the pen 1 according to the present embodiment. As shown in this figure, the pen 1 is configured to include a tip electrode P0 (first electrode), a ring electrode P1 (second electrode), a low-voltage integrated circuit (LVIC) 10 that can be manufactured by a low breakdown voltage process, a high-voltage integrated circuit (HVIC) 20 that requires manufacturing under a high breakdown voltage process, a power supply circuit 30, and a booster circuit 40. Among them, the power supply circuit 30 is a circuit having a function of generating three power supply potentials VDD1, VDD2, and VDD3 (for example, 1.8V, 5.0V, and 2.3V, respectively). It should be noted that, details will be described later, and a part of the elements constituting the booster circuit 40 (specifically, the DCDC circuit 21 described later) is arranged in the HVIC20.

[0025] The tip electrode P0 is an electrode provided at the tip, and is connected to the HVIC20 via the electrode wiring WP0 (first electrode wiring). In addition, the ring electrode P1 is a ring-shaped electrode arranged so as to surround the pen shaft, and is connected to the HVIC20 via the electrode wiring WP1 (second electrode wiring). The electrode wiring WP0 is shared by the downlink signal DS1 and the uplink signal US. In addition, the electrode wiring WP1 is shared by the downlink signal DS2 and the uplink signal US.

[0026] At least four inter-IC wirings that are independently constituted connect between the LVIC10 and the HVIC20. These four inter-IC wirings include an inter-IC Rx wiring WRx for supplying an uplink signal US from the HVIC20 to the LVIC10, an inter-IC Tx wiring WTx0 (first inter-IC Tx wiring) for supplying a downlink signal DS1 from the LVIC10 to the HVIC20, an inter-IC Tx wiring WTx1 (second inter-IC Tx wiring) for supplying a downlink signal DS2 from the LVIC10 to the HVIC20, and an inter-IC control wiring WCtrl for supplying a control signal from the LVIC10 to the HVIC20. In the following description, the output terminal of the HVIC20 connected to the inter-IC Rx wiring WRx (the terminal that outputs the uplink signal US that will reach the tip electrode P0 or the ring electrode P1) is called the Rx terminal, the input terminal of the HVIC20 connected to the inter-IC Tx wiring WTx0 (the terminal that receives the supply of the downlink signal DS1) is called the Tx0 terminal (first Tx terminal), and the input terminal of the HVIC20 connected to the inter-IC Tx wiring WTx1 (the terminal that receives the supply of the downlink signal DS2) is called the Tx1 terminal (second Tx terminal).

[0027] Inside the LVIC10, an MCU11, a logic circuit 12, an Rx section 13, and a pen pressure detection section 14 are provided. Among them, the MCU11 is a micro control unit that undertakes the overall control of the pen 1. In addition, the Rx section 13 is a functional section that receives the uplink signal US via the inter-IC Rx wiring WRx, demodulates the uplink signal US, and outputs it to the logic circuit 12. Details of the Rx section 13 will be described in detail later with reference to Figure 5 The pen pressure detection section 14 is a functional section that detects the pen pressure based on the capacitance of a capacitance element (not shown) configured to change capacitance according to the pressure applied to the tip of the pen (pen pressure). The pen pressure detected by the pen pressure detection section 14 is supplied to the logic circuit 12.

[0028] The logic circuit 12 is a circuit that receives the uplink signal US via the Rx section 13 and generates downlink signals DS1 and DS2 corresponding to the content of the uplink signal US. The downlink signals DS1 and DS2 generated by the logic circuit 12 are respectively supplied to the HVIC20 via the inter-IC Tx wirings WTx0 and WTx1.

[0029] Here, the uplink signal US and the downlink signals DS1 and DS2 will be described in detail. First, the uplink signal US is a signal composed of a symbol example including a specified detection mode and an instruction for controlling the pen 1. Figure 1The position detection device 2 shown is configured to transform each of the symbols constituting the uplink signal US into spreading codes (chip strings), modulate the obtained spreading codes using a prescribed modulation method (e.g., pulse width modulation), and then transmit them from each linear electrode constituting the sensor 3.

[0030] The downlink signal DS1 is a signal that sequentially includes a burst signal and a data signal. The burst signal is an unmodulated sine wave signal and is used to enable the position detection device 2 to detect the position of the pen 1. The data signal is a signal obtained by modulating the sine wave signal with the data required to be transmitted by an instruction in the uplink signal US. As an example of the data transmitted by the data signal, the pen pressure detected by the pen pressure detection unit 14 can be cited. In addition, when the pen 1 has side switches and tail switches, the on / off information of these switches can be transmitted by the data signal. When a unique pen ID is assigned to the pen 1, this pen ID can be transmitted by the data signal.

[0031] The downlink signal DS2 is a sine wave signal having a frequency different from that of the downlink signal DS1 and is used to enable the position detection device 2 to detect the tilt of the pen 1. The downlink signal DS2 can be an unmodulated signal as a whole, or can be a signal including a burst signal and a data signal like the downlink signal DS1.

[0032] Returning to the description of the logic circuit 12, although not shown, a drive circuit is provided at the output stage of the logic circuit 12, and a power supply potential VDD1 is supplied to this drive circuit from the power supply circuit 30. Therefore, the downlink signals DS1 and DS2 output from the logic circuit 12 become signals that oscillate between the power supply potential VDD1 and the ground potential VSS. That is, the logic circuit 12 is configured to output the downlink signals DS1 and DS2 at the power supply potential VDD1 (first voltage).

[0033] In addition, the logic circuit 12 also functions to generate various control signals for controlling the HVIC 20 and supply them to the HVIC 20. The control signals supplied in this way include a control signal DCEN (first control signal) for controlling a DCDC circuit 21 (boost circuit 40) described later and a control signal ULEN (second control signal) for controlling a high voltage switch 23 described later. Details will be described when each circuit is explained.

[0034] A DCDC circuit 21, a level converter 22, and a high voltage switch 23 are provided inside the HVIC 20.

[0035] The DCDC circuit 21 is a circuit that, together with the transistor 41, external coil 42, resistor 43, diode 44, and capacitor 45 provided outside the LVIC 10 and HVIC 20, constitutes a boost circuit 40, and is configured to operate by receiving the supply of the power supply potential VDD2 from the power supply circuit 30. The basic function of the DCDC circuit 21 is to control the on / off of the transistor 41 through the feedback input based on the output of the boost circuit 40, that is, the power supply potential VSS2, so as to control the on / off of the current flowing through the external coil 42 in such a way that the difference between the power supply potential VDD2 and the power supply potential VSS2 becomes a specified value (for example, 20V). The DCDC circuit 21 plays the role of causing the boost circuit 40 to generate the power supply potential VSS2 (second voltage) by performing this control.

[0036] The on / off control of the transistor 41 by the DCDC circuit 21 is achieved by controlling the duty ratio of the rectangular wave signal BA supplied to the control electrode of the transistor 41. In addition, the DCDC circuit 21 is configured to be controllable by the control signal DCEN supplied from the logic circuit 12. When the control signal DCEN is activated, the duty ratio of the rectangular wave signal BA is controlled. On the other hand, when the control signal DCEN is inactive, the rectangular wave signal BA is fixed to be inactive. Therefore, the boost circuit 40 generates the power supply potential VSS2 when the control signal DCEN is activated, and does not generate the power supply potential VSS2 when the control signal DCEN is inactive.

[0037] Hereinafter, the structure and operation of the boost circuit 40 will be described in detail. In the following description, the output terminal of the boost circuit 40 that outputs the power supply potential VSS2 is referred to as the first node n 1 , the ground terminal of the boost circuit 40 that receives the supply of the ground potential VSS is referred to as the second node n 2 , and the input terminal of the boost circuit 40 that receives the supply of the power supply potential VDD3 from the power supply circuit 30 is referred to as the third node n 3 .

[0038] The transistor 41, external coil 42, and resistor 43 are sequentially connected in series between the third node n 3 and the second node n 2 . The transistor 41 is, for example, a PNP bipolar transistor, with its emitter connected to the third node n 3 , and its collector connected to the external coil 42. The rectangular wave signal BA is supplied from the DCDC circuit 21 to the base of the transistor 41. As the external coil 42, a coil with an inductance of 1 μH or more is used so that the absolute value of the power supply potential VSS2 can be made sufficiently large. The cathode of the diode 44 is connected to the collector of the transistor 41, and the anode is connected to the first node n 1。The capacitor 45 is connected between the first node n 1 and the second node n 2 .

[0039] With the above structure, when the rectangular wave signal BA is activated and the transistor 41 is turned on, a current flows from the first node n 1 towards the second node n 2 through the diode 44 and the external coil 42. As a result, the voltage of the first node n 1 (= power supply potential VSS2) drops, so the difference between the power supply potential VDD2 and the power supply potential VSS2 expands. In this way, the boosting of the boost circuit 40 is achieved.

[0040] The DCDC circuit 21 monitors the power supply potential VSS2 as a feedback input. When the power supply potential VSS2 becomes below a specified value (for example, -15V or less), the rectangular wave signal BA is made inactive. As a result, the transistor 41 turns off and the boosting operation of the boost circuit 40 stops, and the difference between the power supply potential VDD2 and the power supply potential VSS2 gradually shrinks. The DCDC circuit 21 also continues to monitor the power supply potential VSS2 thereafter. When the power supply potential VSS2 rises above the specified value, the rectangular wave signal BA is restored to the active state. As a result, the transistor 41 turns on and the boosting operation of the boost circuit 40 starts again, and the difference between the power supply potential VDD2 and the power supply potential VSS2 gradually expands. The boost circuit 40 generates the power supply potential VSS2 as described above.

[0041] Returning to the description of the internal structure of the HVIC20. The level converter 22 is a circuit that supplies the downlink signals DS1 and DS2, which are amplified by individually amplifying the downlink signals DS1 and DS2 supplied from the LVIC10 via the IC - to - IC Tx wirings WTx0 and WTx1, with a voltage (= VDD2 - VSS2. Second voltage) corresponding to the difference between the power supply potential VDD2 supplied from the power supply circuit 30 and the power supply potential VSS2 supplied from the boost circuit 40. The downlink signals DS1 and DS2 output from the level converter 22 are signals that oscillate between the power supply potential VDD2 and the power supply potential VSS2.

[0042] The high-voltage switch 23 is a switch having a function of switching the connection object of the electrode wiring WP0 between the Rx terminal and the Tx0 terminal and switching the connection object of the electrode wiring WP1 between the Rx terminal and the Tx1 terminal, and is configured to be controllable by a control signal ULEN supplied from the LVIC 20. Since the high-voltage switch 23 needs to pass the high-voltage downlink signals DS1 and DS2, it is configured to be able to withstand at least the voltages of the downlink signals DS1 and DS2 output from the level converter 22 (= VDD2 - VSS2). For example, when the voltages of the downlink signals DS1 and DS2 are 10V, the high-voltage switch 23 needs to be configured to be able to withstand at least 10V voltage.

[0043] Figure 3 FIG. is a diagram showing a structural example of the high-voltage switch 23. As shown in this figure, the high-voltage switch 23 may be configured to include drive circuits 24, 25 and switch circuits 26, 27. Hereinafter, these circuits will be described in detail.

[0044] The drive circuits 24 and 25 are circuits that function as buffers for the downlink signals DS1 and DS2, respectively. Specifically, it is preferable to configure the drive circuits 24 and 25 using a circuit including CMOS. The downlink signal DS1 after being output from the level converter 22 is supplied to the electrode wiring WP0 via the drive circuit 24. In addition, the downlink signal DS2 after being output from the level converter 22 is supplied to the electrode wiring WP1 via the drive circuit 24.

[0045] The switch circuit 26 is a circuit that switches the connection state between the Rx terminal and the electrode wiring WP0 according to the control signal ULEN supplied from the logic circuit 12. In addition, the switch circuit 27 is a circuit that switches the connection state between the Rx terminal and the electrode wiring WP1 according to the control signal ULEN supplied from the logic circuit 12. The logic circuit 12 generates the control signal ULEN in such a manner that the Rx terminal is connected to both the electrode wirings WP0 and WP1 during reception of the uplink signal US and the Rx terminal is disconnected from both the electrode wirings WP0 and WP1 during transmission of the downlink signals DS1 and DS2. The Rx terminal and the Rx wiring WRx between the ICs are provided in a common manner with the electrodes P0 and P1, and the switch circuits 26 and 27 operate to connect the electrode wirings WP0 and WP1 to the Rx terminal by converging at the illustrated junction 28 during reception of the uplink signal US.

[0046] The switch circuits 26 and 27 also function as Rx protection circuits to prevent the downlink signals DS1 and DS2 from flowing into the Rx terminal. This function is necessary because when the electrode wirings WP0 and WP1 are connected to the Rx terminal in order to receive the uplink signal US, the high voltage remaining in the electrode wirings WP0 and WP1 will flow into the Rx terminal, and the Rx unit 13 may be damaged. Figure 4 Provide detailed explanation.

[0047] Figure 4 (a) is a diagram showing the internal structure of the switch circuits 26 and 27. Figure 4 (b) is shown Figure 4 (a) is a diagram showing the internal structure of the buffer circuit 53, Figure 4 (c) is a waveform diagram for explaining the operation of the switch circuits 26 and 27.

[0048] First refer to Figure 4 (a) The switch circuits 26 and 27 are respectively configured to include CMOS switch circuits 50 and 51 , an NMOS 52 , and a buffer circuit 53 .

[0049] like Figure 4 As shown in (b), the buffer circuit 53 is configured to include a constant current circuit 55, a CMOS gate circuit 56, and a capacitor 57. A control signal ULEN is supplied to the input end of the CMOS gate circuit 56, and a control signal ULEN_dl is output from the output end of the CMOS gate circuit 56. The constant current circuit 55 is provided at Figure 2 The power supply circuit 30 shown is provided between a power supply line to which the power supply potential VDD1 is supplied and a high-voltage power supply terminal of the CMOS gate circuit 56. A capacitor 57 is provided between the output terminal of the CMOS gate circuit 56 and the ground terminal.

[0050] The control signal ULEN is Figure 4 (c) When such a control signal ULEN is input to the input terminal of the CMOS gate circuit 56, a signal is output from the CMOS gate circuit 56, but the signal is used for charging the capacitor 57 until the charging of the capacitor 57 is completed. As a result, Figure 4 As shown in (c), the control signal ULEN_d1 output from the buffer circuit 53 becomes a signal whose rising edge is delayed by a predetermined time Δ compared with the control signal ULEN. Hereinafter, the timing when the control signal ULEN rises is referred to as time t1, the timing when the control signal ULEN_d1 rises is referred to as time t2, and the timing when the control signals ULEN and ULEN_d1 fall together is referred to as time t3.

[0051] Refer again Figure 4(a), the CMOS switch circuits 50 and 51 are inserted between the electrode wiring WP0 or the electrode wiring WP1 and the Rx terminal in sequence. Hereinafter, the wiring connecting the output terminal of the CMOS switch circuit 50 and the input terminal of the CMOS switch circuit 51 is referred to as "intermediate wiring MIDW". A control signal ULEN is supplied to the control terminal of the CMOS switch circuit 50, and a control signal ULEN_dl is supplied to the control terminal of the CMOS switch circuit 51. In addition, an NMOS 52 is connected between the intermediate wiring MIDW and a power supply wiring to which a ground potential VSS is supplied. An inverted signal of the control signal ULEN_dl is supplied to the control terminal of the NMOS 52.

[0052] With the above structure, as Figure 4 (c) shows, the CMOS switch circuit 50 is turned on at time t1 and turned off at time t3. Therefore, from time t1 to time t3, the CMOS switch circuit 51 is connected to the electrode wiring WP0 or the electrode wiring WP1. On the other hand, the CMOS switch circuit 50 is turned on at time t2 and turned off at time t3. Therefore, the Rx terminal is connected to the electrode wiring WP0 or the electrode wiring WP1 between time t2 and time t3.

[0053] Here, if it is assumed that the NMOS 52 does not exist, when a high voltage remains on the electrode wirings WP0 and WP1, the intermediate wiring MIDW becomes a high voltage at time t1, and the Rx terminal becomes a high voltage at time t2. However, in this case, the Rx unit 13 connected to the other end of the Rx terminal will be damaged, so the NMOS 52 is provided in the switch circuits 26 and 27. As Figure 4 (c) shows, the NMOS 52 is configured to be turned on until time t2, temporarily turned off at time t2, and then turned on again at time t3. Therefore, even if a high voltage remains on the electrode wirings WP0 and WP1 at the time point of time t1, the potential of the intermediate wiring MIDW is forcibly neutralized to the ground potential VSS during the period from time t1 to time t2. Therefore, the possibility that the Rx terminal becomes a high voltage at time t2 is eliminated, so it can be said that the switch circuits 26 and 27 function as an Rx protection circuit for preventing the downlink signals DS1 and DS2 from flowing into the Rx terminal.

[0054] It should be noted that the initial state of the switch circuits 26 and 27 is preferably set to a state where the electrode wirings WP0 and WP1 are connected to the Rx terminal. This is to enable the reception of the uplink signal US at any time. It should be noted that according to Figure 4(a)'s structure, when the Rx terminal is disconnected from the electrode wirings WP0 and WP1, the disconnection is quickly performed according to the inactivation of the control signal ULEN. Therefore, it can be considered that there is no possibility of the situation where "when the level converters 22 start to output the downlink signals DS1 and DS2, the disconnection of the Rx terminal by the switch circuits 26 and 27 is too late, and a part of the downlink signals DS1 and DS2 is supplied to the Rx terminal".

[0055] Next, the details of the Rx unit 13 will be described. Figure 5 (a) is a diagram showing the internal structure of the Rx unit 13, Figure 5 (b) is a diagram showing the relationship between the reception level of the uplink signal US and the amplitude level of the signal output from the variable gain amplifier 61, Figure 5 (c) is a diagram showing the relationship between the reception level of the uplink signal US and the gain of the variable gain amplifier 61.

[0056] First, refer to Figure 5 (a). The Rx unit 13 is configured to include a bypass filter 60, a variable gain amplifier 61, a demodulation circuit 62, a matched filter 63, and a level detection circuit 64.

[0057] The bypass filter 60 is used to remove high-order harmonics that appear in the Rx wiring WRx, and is constituted by, for example, an RC circuit as shown in Figure 5 (a). The variable gain amplifier 61 is a receiving amplifier circuit (reception amplifier) configured to be able to control the gain, and functions to amplify the uplink signal US supplied via the Rx wiring WRx from the HVIC 20. The demodulation circuit 62 is a circuit that demodulates the uplink signal US output from the variable gain amplifier 61 using a prescribed modulation method (for example, pulse width modulation) to obtain the above-mentioned spread code string. The matched filter 63 is a circuit that calculates the correlation between the spread code obtained by the demodulation circuit 62 and each of a plurality of pre-stored spread codes and supplies the resulting symbol string to the logic circuit 12. The logic circuit 12 receives the uplink signal US (detection mode and instruction) transmitted by the position detection device 2 based on the symbol string supplied in this way.

[0058] The level detection circuit 64 is a circuit that detects the amplitude level of the signal output from the variable gain amplifier 61 by referring to the demodulation result of the demodulation circuit 62. The level detection circuit 64 has two types of outputs, high (High) and low (Low), and is configured to activate the high output when the detected amplitude level exceeds the Figure 5 (b) shown threshold Vth, and when the detected amplitude level is lower than Figure 5(b) When the threshold Vtl (<Vth) is shown, the low output is activated. The MCU 11 monitors the output of the level detection circuit 64 and generates a control signal GC for controlling the gain of the variable gain amplifier 61 based on the result.

[0059] If the details of the gain control based on the control signal GC are described, the MCU 11 is configured to control the gain of the variable gain amplifier 61 in multiple stages. Specifically, it is configured to reduce the gain of the variable gain amplifier 61 by one stage according to the high output activation of the level detection circuit 64, and increase the gain of the variable gain amplifier 61 by one stage according to the low output activation of the level detection circuit 64. Through this control, as Figure 5 (c) shows, the greater the reception level of the uplink signal US (the amplitude level at the time point when it reaches the electrodes P0, P1), the smaller the gain of the variable gain amplifier 61 in stages. Therefore, as a result, as Figure 5 (b) shows, it is possible to make the amplitude level of the signal output from the variable gain amplifier 61 be between the threshold Vth and the threshold Vtl on the condition that the reception level is within a specified range.

[0060] As described above, according to the pen 1 of the present embodiment, since the LVIC 10 that can be manufactured by a low breakdown voltage process is used to generate the downlink signals DS1, DS2, the circuit area and power consumption of the HVIC 20 that requires manufacturing under a high breakdown voltage process can be correspondingly reduced. Therefore, it is possible to suppress the circuit area and power consumption and transmit the downlink signals DS1, DS2 with a sufficient high voltage.

[0061] In addition, according to the pen 1 of the present embodiment, since the external coil 42 of 1 μH or more that cannot be arranged in the integrated circuit is arranged outside the LVIC 10 and the HVIC 20, and the boost circuit 40 is configured to include the external coil 42, high voltage (for example, 20V) downlink signals DS1, DS2 can be obtained within the HVIC 20.

[0062] In addition, according to the pen 1 of the present embodiment, since the switch circuits 26, 27 have the function of an Rx protection circuit, it is possible to prevent the destruction of the Rx unit 13 caused by the downlink signals DS1, DS2.

[0063] In addition, according to the pen 1 of the present embodiment, since the receiving amplifier in the Rx unit 13 is set as the variable gain amplifier 61 and the gain of the variable gain amplifier 61 is controlled based on the amplitude level of its output signal, it is possible to make the amplitude level of the signal output from the variable gain amplifier 61 be between the threshold Vth and the threshold Vtl.

[0064] Next, the pen 1 of the second embodiment of the present invention will be described. The pen 1 of this embodiment is different from the pen 1 of the first embodiment in that it is configured to be able to operate in the following mode, which is a mode in which the position detection device 2 detects the pen 1 as a finger by performing an operation of transmitting a second signal from the tip electrode P0 or the ring electrode P1 (hereinafter referred to as the "reflection mode"), and the second signal is a signal obtained by inverting the phase of the first signal received by the tip electrode P0 or the ring electrode P1. Here, the first signal is a signal intermittently transmitted by the position detection device 2, specifically, a finger detection signal supplied by the position detection device 2 to the sensor 3 for finger detection. In other respects, it is the same as the pen 1 of the first embodiment. Therefore, the same reference numerals are given to the same structures as those of the first embodiment below, and the description will be made focusing on the differences from the first embodiment.

[0065] Figure 6 is a diagram showing the internal structure of the pen 1 of this embodiment. From the comparison of this diagram with Figure 2 it can be understood that the pen 1 of this embodiment is different from the pen 1 of the first embodiment in that the output terminal of the Rx terminal and the variable gain amplifier 61 (see Figure 5 ) is directly electrically connected to the logic circuit 12.

[0066] The logic circuit 12 after starting the operation in the reflection mode controls the high-voltage switch 23 so as to connect the electrode wiring WP1 (and / or the electrode wiring WP0) to the Rx terminal. Thus, when the first signal is received by the ring electrode P1 (and / or the tip electrode P0), the first signal is supplied to the Rx terminal.

[0067] The logic circuit 12 operating in the reflection mode monitors whether the first signal has reached the Rx terminal by referring to the output of the variable gain amplifier 61. And when it is detected that the first signal has reached the Rx terminal, the logic circuit 12 generates a second signal obtained by inverting the phase of the first signal, and at a timing corresponding to the reception timing of the first signal, controls the high-voltage switch 23 so as to disconnect the electrode wiring WP1 from the Rx terminal (switch to the Tx0 terminal and Tx1 terminal sides), and supplies the second signal to one or both of the Tx0 terminal and the Tx1 terminal. Thus, the second signal is transmitted from one or both of the tip electrode P0 and the ring electrode P1, so from the perspective of the position detection device 2, it is as if the first signal has been absorbed. Therefore, the pen 1 can be detected as a finger.

[0068] In addition, the logic circuit 12 is configured to execute a silent logic that grounds the Rx terminal at a timing corresponding to the reception timing of the first signal. Thus, it is possible to prevent the second signal from being introduced into the Rx terminal side and causing oscillation.

[0069] Figure 7It is a waveform diagram showing the operation of the logic circuit 12 in the reflection mode. While referring to this Figure 7 While explaining the reflection mode in more detail, first, the variable gain amplifier 61 operates with a prescribed reference potential as the center, such that the output is high at the rising edge of the first signal and low at the falling edge of the first signal. The logic circuit 12 is configured such that when it detects that the first signal has arrived at the Rx terminal by referring to the output of such a variable gain amplifier 61, from the timing (time t5) corresponding to this timing (time t4), it activates the masking signal, which is an internal signal, within a prescribed time T. It should be noted that time t5 is preferably set to a time after sufficient time has passed since time t4 for the logic circuit 12 to generate the second signal. During the period when the masking signal is activated, the logic circuit 12 fixes the potential of the Rx terminal to the above-mentioned reference potential (silent logic), and generates the second signal obtained by inverting the phase of the first signal, and supplies it to one or both of the Tx0 terminal and the Tx1 terminal. Thus, as described above, the position detection device 2 can detect the pen 1 as a finger, and oscillation caused by the second signal leaking into the Rx terminal side can be prevented.

[0070] As described above, according to the pen 1 of the present embodiment, in addition to the effects achieved in the first embodiment, it further has the effect that the position detection device 2 can detect the pen 1 as a finger and oscillation caused by the second signal leaking into the Rx terminal side can be prevented.

[0071] Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments at all, and the present invention can of course be implemented in various ways without departing from its gist.

[0072] Reference Numeral Explanation

[0073] 1 Pen

[0074] 2 Position Detection Device

[0075] 3 Sensor

[0076] 10 LVIC

[0077] 11 MCU

[0078] 12 Logic Circuit

[0079] 13 Rx Unit

[0080] 14 Pen Pressure Detection Unit

[0081] 20 HVIC

[0082] 21 DCDC Circuit

[0083] 22 Level Converter

[0084] 23 High-Voltage Switch

[0085] 24, 25 Driver Circuit

[0086] 26, 27 Switch Circuit

[0087] 28 Junction

[0088] 30 Power Supply Circuit

[0089] 40 Boost Circuit

[0090] 41 Transistor

[0091] 42 External Coil

[0092] 43 Resistor

[0093] 44 Diode

[0094] 45, 57 Capacitor

[0095] 50, 51 CMOS Switch Circuit

[0096] 52 NMOS

[0097] 53 Buffer Circuit

[0098] 55 Constant-Current Circuit

[0099] 56 CMOS Gate Circuit

[0100] 60 Bypass Filter

[0101] 61 Variable-Gain Amplifier

[0102] 62 Demodulation Circuit

[0103] 63 Matched Filter

[0104] 64 Horizontal Detection Circuit

[0105] DCEN, ULEN, ULEN_dl, GC Control Signal

[0106] DS, DS1, DS2 Downlink Signal

[0107] MIDW Middle Wiring

[0108] P0 Tip Electrode

[0109] P1 Ring Electrode

[0110] US Uplink Signal

[0111] Power potentials of VDD1, VDD2, VDD3, and VSS2

[0112] Ground potential of VSS

[0113] Inter-IC control wiring of WCtrl

[0114] Electrode wirings of WP0 and WP1

[0115] Inter-IC Rx wiring of WRx

[0116] Inter-IC Tx wirings of WTx0 and WTx1.

Claims

1. A pen, comprising: an electrode; a power supply circuit that supplies a first voltage during operation; a first integrated circuit connected to the power supply circuit, wherein the first integrated circuit outputs a transmission signal at the first voltage during operation; a second integrated circuit including a level shifter that outputs the transmission signal at a second voltage higher than the first voltage during operation; inter-integrated circuit wiring that supplies the transmission signal at the first voltage from the first integrated circuit to the second integrated circuit during operation; electrode wiring that supplies the transmission signal at the second voltage from the second integrated circuit to the electrode during operation; and a booster circuit connected to the power supply circuit, wherein the booster circuit supplies the second voltage to the level shifter during operation, wherein the second integrated circuit further includes: an Rx terminal that outputs a reception signal received by the electrode during operation; a Tx terminal that receives the transmission signal during operation, and a switch that switches the connection destination of the electrode wiring between the Rx terminal and the Tx terminal during operation, wherein the inter-integrated circuit wiring includes: inter-integrated circuit Rx wiring connected to the Rx terminal, and inter-integrated circuit Tx wiring connected to the Tx terminal, wherein the inter-integrated circuit Rx wiring and the inter-integrated circuit Tx wiring are independently formed, wherein the electrode wiring is shared by the transmission signal and the reception signal during operation, wherein the electrode includes: a first electrode provided at the tip of the pen, and a second electrode having a ring shape, wherein the electrode wiring includes: first electrode wiring connected to the first electrode, and second electrode wiring connected to the second electrode, wherein the Tx terminal includes: a first Tx terminal corresponding to the first electrode, and a second Tx terminal corresponding to the second electrode, wherein the inter-integrated circuit Tx wiring includes: first inter-integrated circuit Tx wiring connected to the first Tx terminal, and second inter-integrated circuit Tx wiring connected to the second Tx terminal, and wherein the Rx terminal and the inter-integrated circuit Rx wiring are provided in a manner common to the first electrode and the second electrode, respectively.

2. The pen according to claim 1, wherein, the booster circuit includes an external coil provided outside the first integrated circuit and the second integrated circuit, and wherein the external coil can be controlled by a first control signal supplied from the first integrated circuit during operation.

3. The pen according to claim 2, wherein, the booster circuit includes the external coil and a circuit provided in the second integrated circuit.

4. The pen according to claim 2, wherein, the booster circuit generates the second voltage by controlling the on / off of the current flowing through the external coil during operation.

5. The pen according to claim 1, wherein, the switch includes an Rx protection circuit that prevents the transmission signal from flowing into the Rx terminal during operation.

6. The pen according to claim 5, wherein, the Rx protection circuit neutralizes the potential of the wiring connected to the Rx terminal to a specified potential during operation.

7. The pen according to claim 1, wherein, in the initial state of the switch, the electrode wiring is connected to the Rx terminal.

8. The pen according to claim 1, wherein, the switch is subjected to the second voltage during operation.

9. The pen according to claim 8, wherein, the switch is subjected to a voltage of 10 V during operation.

10. The pen according to claim 1, wherein, the second integrated circuit includes a convergence section that connects the first electrode wiring and the second electrode wiring to the Rx terminal during reception of the received signal during operation.

11. The pen according to claim 1, wherein, the switch is controlled by a second control signal supplied from the first integrated circuit during operation.

12. The pen according to claim 1, wherein, the first integrated circuit includes a receiving amplifier that amplifies the received signal during operation.

13. The pen according to claim 1, wherein, the pen operates in a reflection mode, and in the reflection mode, the position detection device detects the pen by transmitting a second signal from the first electrode or the second electrode, and the second signal is obtained by inverting the phase of the first signal received by the first electrode or the second electrode.

14. The pen according to claim 13, wherein, the second signal is transmitted at a timing based on the reception timing of the first signal.

15. The pen according to claim 14, wherein, the potential of the Rx terminal is fixed to a specified reference potential at a timing based on the reception timing of the first signal.

Images