Display device and electronic device

Abstract

Provided is a display device capable of improving image quality. One aspect of the present invention includes a first pixel circuit and a second pixel circuit. A storage node is provided in each pixel circuit, and a first signal can be held in the storage node. The first signal is capacitively coupled to an added second signal and can be supplied to a display element. Accordingly, a corrected image can be displayed in the display device. In addition, by commonly using signal lines in the first pixel circuit and the second pixel circuit, the aperture ratio of pixels can be increased.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification etc. relates to an object, a method, or a manufacturing method. Further, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Thus, more specifically, as an example of the technical field of one aspect of the present invention disclosed in this specification, a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, a imaging device, a driving method of these devices, or a manufacturing method of these devices can be cited.

[0003] Note that in this specification etc., a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. Further, a storage device, a display device, a imaging device, and an electronic device sometimes include a semiconductor device. Background Art

[0004] As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known. As other materials, oxide semiconductors have received attention. As oxide semiconductors, for example, in addition to single metal oxides such as indium oxide and zinc oxide, multi-metal oxides are also known. Among multi-metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) has been particularly active.

[0005] Through research on IGZO, in oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous have been discovered (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 disclose that even in an oxide semiconductor having a lower crystallinity than the CAAC structure and the nc structure, there are minute crystals.

[0006] A transistor using IGZO for an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8).

[0007] In addition, Patent Document 1 discloses a storage device having a structure in which a transistor with an extremely low off-state current is used for a storage cell.

[0008] [Prior Art Documents]

[0009] [Patent Documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-119674

[0011] [Non-Patent Documents]

[0012] [Non-Patent Document 1] S.Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186

[0013] [Non-Patent Document 2] S.Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10

[0014] [Non-Patent Document 3] S.Ito et al., “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p.151-154

[0015] [Non-Patent Document 4] S.Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022

[0016] [Non-Patent Document 5] S.Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p.155-164

[0017] [Non-Patent Document 6] K.Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7

[0018] [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217

[0019] [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626-629 Summary of the Invention

[0020] Technical Problem to be Solved by the Invention

[0021] The resolution of display devices has been continuously improved, and hardware capable of displaying images with a resolution of 8K4K (number of pixels: 7680×4320) or higher has been developed. In addition, the introduction of HDR (High Dynamic Range) display technology for improving image quality by adjusting brightness has been promoted.

[0022] In order for a display device to perform proper display, it is necessary to make the image data correspond to the resolution of the display device. For example, when the resolution of the display device is 8K4K and the image data is for 4K2K (number of pixels: 3840×2160), full-screen display cannot be performed unless the amount of data is converted to 4 times. On the contrary, when the resolution of the display device is 4K2K and the image data is for 8K4K, the amount of data needs to be converted to 1 / 4.

[0023] In addition, there is a problem that dedicated circuits are required for the generation of image data and the conversion of the amount of data in HDR processing, resulting in increased power consumption. It is preferable to input the original image data into the pixels of the display device without at least converting it.

[0024] Therefore, one of the objectives of one aspect of the present invention is to provide a display device capable of improving image quality. Another objective of one aspect of the present invention is to provide a display device capable of performing proper display without converting image data. Another objective of one aspect of the present invention is to provide a display device capable of performing HDR display. Another objective of one aspect of the present invention is to provide a display device capable of performing upconversion operation. Another objective of one aspect of the present invention is to provide a display device capable of increasing the brightness of the displayed image. Another objective of one aspect of the present invention is to provide a display device capable of overlappingly displaying two images.

[0025] Furthermore, one of the objectives of one embodiment of the present invention is to provide a display device with low power consumption. In addition, one of the objectives of one embodiment of the present invention is to provide a display device with high reliability. Furthermore, one of the objectives of one embodiment of the present invention is to provide a novel display device and the like. Additionally, one of the objectives of one embodiment of the present invention is to provide a driving method for the above-mentioned display device. Moreover, one of the objectives of one embodiment of the present invention is to provide a novel semiconductor device and the like.

[0026] Note that the description of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily need to achieve all of the above objectives. Additionally, objectives other than the above are obvious from the descriptions in the specification, drawings, claims, etc., and objectives other than the above can be extracted from the descriptions in the specification, drawings, claims, etc.

[0027] Means for Solving Technical Problems

[0028] Another embodiment of the present invention is a display device, comprising: a first pixel circuit; a second pixel circuit; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a sixth wiring, wherein the first pixel circuit includes a first transistor, a second transistor, a first capacitor, and a first circuit block, the second pixel circuit includes a third transistor, a fourth transistor, a second capacitor, and a second circuit block, one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the second transistor is electrically connected to the first circuit block, one of the source and drain of the third transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and drain of the fourth transistor, one of the source and drain of the fourth transistor is electrically connected to the second circuit block, the gates of the second transistor and the fourth transistor are electrically connected to the first wiring, the gate of the first transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the fourth wiring, the other of the source and drain of the first transistor and the other of the source and drain of the third transistor are electrically connected to the fifth wiring, the other of the source and drain of the fourth transistor is electrically connected to the sixth wiring, the first circuit block includes a first display element, and the second circuit block includes a second display element.

[0029] Another aspect of the present invention is a display device, comprising: a first pixel circuit; a second pixel circuit; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; and a sixth wiring, wherein the first pixel circuit includes a first transistor, a second transistor, a first capacitor, and a first circuit block, the second pixel circuit includes a third transistor, a fourth transistor, a second capacitor, and a second circuit block, one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the second transistor is electrically connected to the first circuit block, one of the source and drain of the third transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and drain of the fourth transistor, one of the source and drain of the fourth transistor is electrically connected to the second circuit block, the gate of the second transistor is electrically connected to the first wiring, the gate of the fourth transistor is electrically connected to the second wiring, the gates of the first transistor and the third transistor are electrically connected to the third wiring, the other of the source and drain of the first transistor is electrically connected to the fourth wiring, the other of the source and drain of the second transistor and the other of the source and drain of the fourth transistor are electrically connected to the fifth wiring, the other of the source and drain of the third transistor is electrically connected to the sixth wiring, the first circuit block includes a first display element, and the second circuit block includes a second display element.

[0030] In the above display device, preferably, the first circuit block includes a fifth transistor, a sixth transistor, a third capacitor, and a first organic EL element as the first display element, the second circuit block includes a seventh transistor, an eighth transistor, a fourth capacitor, and a second organic EL element as the second display element, one electrode of the first organic EL element is electrically connected to one of the source and drain of the sixth transistor, the other of the source and drain of the sixth transistor is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to one of the source and drain of the fifth transistor, the gate of the fifth transistor is electrically connected to the other electrode of the third capacitor, the other electrode of the third capacitor is electrically connected to the other electrode of the first capacitor, one electrode of the second organic EL element is electrically connected to one of the source and drain of the eighth transistor, the other of the source and drain of the eighth transistor is electrically connected to one electrode of the fourth capacitor, one electrode of the fourth capacitor is electrically connected to one of the source and drain of the seventh transistor, the gate of the seventh transistor is electrically connected to the other electrode of the fourth capacitor, and the other electrode of the fourth capacitor is electrically connected to the other electrode of the second capacitor.

[0031] In the above display device, preferably, the first circuit block includes a ninth transistor, a fifth capacitor, and a first liquid crystal element as a first display element, the second circuit block includes a tenth transistor, a sixth capacitor, and a second liquid crystal element as a second display element, one electrode of the first liquid crystal element is electrically connected to one electrode of the fifth capacitor, one electrode of the fifth capacitor is electrically connected to one of the source and drain of the ninth transistor, the other of the source and drain of the ninth transistor is electrically connected to the other electrode of the first capacitor, one electrode of the second liquid crystal element is electrically connected to one electrode of the sixth capacitor, one electrode of the sixth capacitor is electrically connected to one of the source and drain of the tenth transistor, and the other of the source and drain of the tenth transistor is electrically connected to the other electrode of the second capacitor.

[0032] In the above display device, preferably, the second transistor includes a metal oxide in the channel formation region, and the metal oxide contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0033] Another aspect of the present invention is an electronic device including the above display device and a camera.

[0034] Advantages of the Invention

[0035] By using one aspect of the present invention, a display device capable of improving image quality can be provided. By using one aspect of the present invention, a display device capable of performing appropriate display without converting image data can be provided. By using one aspect of the present invention, a display device capable of performing HDR display can be provided. By using one aspect of the present invention, a display device capable of performing up-conversion operation can be provided. By using one aspect of the present invention, a display device capable of increasing the brightness of a displayed image can be provided. By using one aspect of the present invention, a display device capable of overlappingly displaying two images can be provided.

[0036] In addition, a display device with low power consumption can be provided. Furthermore, a display device with high reliability can be provided. Additionally, a novel display device etc. can be provided. Additionally, a driving method for the above display device can be provided. Additionally, a novel semiconductor device etc. can be provided.

[0037] Brief Description of the Drawings

[0038] Figure 1 A diagram illustrating a pixel circuit.

[0039] Figure 2A and Figure 2B A timing diagram illustrating the operation of the pixel circuit.

[0040] ​​​Figure 3 Figure showing the pixel circuit.

[0041] Figure 4A and Figure 4B Figure showing the operation of the pixel circuit.

[0042] Figure 5A and Figure 5B Figure showing the correction of image data and image synthesis.

[0043] Figures 6A to 6C Figure showing the circuit block.

[0044] Figures 7A to 7C Figure showing the circuit block.

[0045] Figure 8A and Figure 8B Figure showing the pixel circuit.

[0046] Figures 9A to 9C Figure showing the block diagram of the display device.

[0047] Figure 10A and Figure 10B Figure showing an example of the structure of the neural network.

[0048] Figure 11 Figure showing the structure of the pixel array for simulation.

[0049] Figures 12A to 12C Figure showing the simulation results.

[0050] Figures 13A to 13C Figure showing the simulation results.

[0051] Figure 14 Figure showing the structure of the pixel.

[0052] Figure 15 Figure showing the aperture ratio of the pixel.

[0053] Figures 16A to 16C Figure showing the display device.

[0054] Figure 17A and Figure 17B Figure showing the touch screen.

[0055] Figure 18A and Figure 18B Figure showing the display device.

[0056] Figure 19 Figure showing the display device.

[0057] Figure 20A1 , Figure 20A2 , Figure 20B1 ​​​​​​​​​​​​​​​​​, Figure 20B2 , Figure 20C1 and Figure 20C2 Diagrams illustrating transistors.

[0058] Figure 21A1 , Figure 21A2 , Figure 21B1 , Figure 21B2 , Figure 21C1 and Figure 21C2 Diagrams illustrating transistors.

[0059] Figure 22A1 , Figure 22A2 , Figure 22B1 , Figure 22B2 , Figure 22C1 and Figure 22C2 Diagrams illustrating transistors.

[0060] Figure 23A1 , Figure 23A2 , Figure 23B1 , Figure 23B2 , Figure 23C1 and Figure 23C2 Diagrams illustrating transistors.

[0061] Figures 24A to 24F Diagrams illustrating electronic devices.

[0062] Modes for Carrying Out the Invention

[0063] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is readily understood by those of ordinary skill in the art that the modes and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments. Note that in the structures of the invention described below, the same reference numerals are used in different drawings to denote the same parts or parts having the same functions, and the repeated description thereof is omitted. Note that the shading of the same constituent elements may be appropriately omitted or changed in different drawings.

[0064] (Embodiment 1)

[0065] In this embodiment, a display device according to one mode of the present invention will be described with reference to the accompanying drawings.

[0066] One mode of the present invention is a display device having a function of correcting image data in pixels. A storage node is provided in each pixel, and first data can be held in the storage node. Second data is added to the first data by capacitive coupling, and the first data can be supplied to the display element. Alternatively, after writing the second data to the storage node, the first data may be added by capacitive coupling. ​​​​

[0067] Accordingly, the display device can display a corrected image. Through this correction, upscaling of the image can be performed. Alternatively, a part or the whole of the image in the display unit can be corrected to perform HDR display. Alternatively, by using the same image data as the first data and the second data, the brightness of the displayed image can be significantly increased. Alternatively, by using different image data as the first data and the second data, arbitrary images can be displayed overlapped.

[0068] In addition, by using one aspect of the present invention, appropriate display can be performed without upscaling or downscaling two image data for high resolution and low resolution. In the case of high-resolution display, different data are supplied to each pixel via a first transistor included in each pixel. When displaying at low resolution, the same data are supplied to a plurality of pixels via a second transistor electrically connected to the plurality of pixels.

[0069] Here, the high-resolution image data corresponds to data including an amount of information corresponding to 8K4K (number of pixels: 7680×4320), for example. In addition, the low-resolution image data corresponds to data including an amount of information corresponding to 4K2K (number of pixels: 3840×2160), for example. That is, it is assumed that the effective ratio of the data amounts (corresponding to the number of effective pixels) of the high-resolution image data and the low-resolution image data is 4:1.

[0070] In addition, as long as the ratio of the data amounts (number of pixels) is 4:1, the high-resolution image data may be data corresponding to 4K2K and the low-resolution image data may be data corresponding to FullHD (number of pixels: 1920×1080), without being limited to the above example. Alternatively, the high-resolution image data may be data corresponding to 16K8K (number of pixels: 15360×8640), and the low-resolution image data may be data corresponding to 8K4K.

[0071] <Example structure 1 of pixel>

[0072] Figure 1 FIG. is a diagram illustrating a pixel circuit 10 of a display device that can be used in one aspect of the present invention.

[0073] The pixel circuit 10[k, n] includes a transistor 101a, a transistor 103a, a capacitor 104a, and a circuit block 110a. The pixel circuit 10[k, n+1] is adjacent to the pixel circuit 10[k, n] and includes a transistor 101b, a transistor 103b, a capacitor 104b, and a circuit block 110b.

[0074] Circuit blocks 110a and 110b each include transistors, capacitors, display elements, etc. Various elements can be used as the display element, and typically, light-emitting elements, liquid crystal elements, etc. can be used. As the light-emitting element, light-emitting elements such as LED (Light Emitting Diode), OLED (Organic LED), QLED (Quantum-dot LED), semiconductor laser, etc. can be cited. In addition, it is preferable to use a small-sized LED (also referred to as a micro LED), for example, the area of the die is 10000 μm 2 The following LEDs. As the liquid crystal element, transmissive, reflective, transflective, etc. can be used. As the display element, a MEMS (Micro Electro Mechanical Systems) element of a shutter type or a light interference type or a display element adopting a microcapsule method, an electrophoresis method, an electrowetting method, or an electronic ink (registered trademark) method, etc. can be used.

[0075] In the pixel circuit 10[k, n], one of the source and drain of the transistor 101a is electrically connected to one electrode of the capacitor 104a. The other electrode of the capacitor 104a is electrically connected to one of the source and drain of the transistor 103a. One of the source and drain of the transistor 103a is electrically connected to the circuit block 110a.

[0076] In the pixel circuit 10[k, n+1], one of the source and drain of the transistor 101b is electrically connected to one electrode of the capacitor 104b. The other electrode of the capacitor 104b is electrically connected to one of the source and drain of the transistor 103b. One of the source and drain of the transistor 103b is electrically connected to the circuit block 110b.

[0077] Here, the node connected to the transistor 103a, the capacitor 104a, and the circuit block 110a is referred to as the node N1a. The node connected to the transistor 103b, the capacitor 104b, and the circuit block 110b is referred to as the node N1b. Note that the components of the circuit block 110a and the circuit block 110b can respectively make the nodes N1a and N1b in a floating state.

[0078] The node connected to the transistor 101a and the capacitor 104a is referred to as N2a. The node connected to the transistor 101b and the capacitor 104b is referred to as N2b.

[0079] The gate of transistor 101a is electrically connected to wiring 122[k]. The gate of transistor 101b is electrically connected to wiring 123[k]. The gates of transistor 103a and transistor 103b are electrically connected to wiring 121[k]. The other of the source and drain of transistor 101a and the other of the source and drain of transistor 101b are electrically connected to wiring 125[m]. In other words, transistors 101a and 101b share wiring 125[m]. The other of the source and drain of transistor 103a is electrically connected to wiring 124[n]. The other of the source and drain of transistor 103b is electrically connected to wiring 124[n + 1].

[0080] Wiring 121[k], wiring 122[k], and wiring 123[k] may function as signal lines for controlling the operation of the transistors. Wiring 124[n], wiring 124[n + 1], and wiring 125[m] may function as signal lines for supplying first data or second data.

[0081] In one aspect of the present invention, one signal line (wiring 125[m]) can be used to supply first data or second data to two adjacent pixels in the row direction. That is, pixels can be formed using fewer wirings.

[0082] Note that in this specification and the like, the extending direction of wiring 121 is described as the row direction or the horizontal direction, and the extending direction of wiring 125 is described as the column direction or the vertical direction.

[0083] Node N1a is a storage node. By turning on transistor 103a, the data supplied to wiring 124[n] can be written into node N1a. Further, by turning off transistor 103a, the data can be held in node N1a. Node N1b is a storage node. By turning on transistor 103b, the data supplied to wiring 124[n + 1] can be written into node N1b. Further, by turning off transistor 103b, the data can be held in node N1b.

[0084] By using transistors with an extremely low off-state current as transistors 103a and 103b, the potentials of nodes N1a and N1b can be held for a long time. Such a transistor can be, for example, a transistor including a metal oxide in a channel formation region (hereinafter, an OS transistor).

[0085] The OS transistor can be used not only for transistors 103a and 103b but also for other transistors constituting the pixel. Transistors 103a and 103b can also use transistors containing Si in the channel formation region (hereinafter referred to as Si transistors), or both OS transistors and Si transistors. Examples of the above Si transistors include transistors containing amorphous silicon, transistors containing crystalline silicon (typically low-temperature polysilicon, single-crystalline silicon), and the like.

[0086] As the semiconductor material for the OS transistor, a metal oxide having a band gap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, etc. can be used. For example, CAAC-OS or CAC-OS mentioned later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. CAC-OS exhibits high mobility characteristics and is suitable for transistors for high-speed driving.

[0087] The semiconductor layer included in the OS transistor has a large band gap and the OS transistor exhibits extremely low off-state current characteristics. Different from Si transistors, the OS transistor is not easily subject to impact ionization, avalanche breakdown, short-channel effect, etc., and thus a highly reliable circuit can be formed.

[0088] As the semiconductor layer in the OS transistor, for example, a film represented by "In-M-Zn-based oxide" containing indium, zinc, and M (metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be adopted.

[0089] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of the metal elements of the sputtering target preferably used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic ratio of the formed semiconductor layer may vary within the range of ±40% of the atomic ratio of the metal elements in the above sputtering target.

[0090] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, as the semiconductor layer, a carrier density of 1×10 17 / cm 3 Hereinafter, preferably 1×10 15 / cm 3 Hereinafter, more preferably 1×1013 / cm 3 Hereinafter, it is further preferably 1×10 11 / cm 3 Hereinafter, it is even more preferably less than 1×10 10 / cm 3 , 1×10 -9 / cm 3 or more of the oxide semiconductor. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect energy levels and thus can be said to be an oxide semiconductor having stable characteristics.

[0091] Note that the present invention is not limited to the above description, and a semiconductor layer having an appropriate composition can be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistor. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the required semiconductor characteristics of the transistor.

[0092] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen defects increase and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0093] In addition, sometimes when an alkali metal and an alkaline earth metal bond to the oxide semiconductor, carriers are generated and the off-state current of the transistor increases. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0094] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons as carriers are generated, the carrier density increases and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have a normally-on characteristic. Therefore, the nitrogen concentration in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 or less.

[0095] In addition, the semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure includes, for example, a crystalline CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a c-axis orientation, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0096] The oxide semiconductor film having an amorphous structure, for example, has a disordered atomic arrangement and does not have a crystalline component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and does not have a crystalline part.

[0097] In addition, the semiconductor layer may also be a mixed film of two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure. The mixed film sometimes has, for example, a single layer structure or a stacked structure including two or more of the above regions.

[0098] Hereinafter, the structure of CAC (Cloud-Aligned Composite)-OS of one mode of the non-single crystal semiconductor layer will be described.

[0099] CAC-OS refers to a structure in which elements contained in the oxide semiconductor are unevenly distributed, and the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in the oxide semiconductor and regions containing the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size is also referred to as a mosaic-like or patch-like state.

[0100] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to this, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.

[0101] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be particularly referred to as CAC-IGZO) refers to a material divided into indium oxide (hereinafter, referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, referred to as In X2 Zn Y2 O Z2(X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0)) etc. to form a mosaic pattern, and the mosaic InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film structure (hereinafter also referred to as cloud-like).

[0102] In other words, CAC-OS is a composite oxide semiconductor having a structure in which regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 are mixed together. In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region.

[0103] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number) can be cited as a crystalline compound.

[0104] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystalline structure in which multiple nanocrystals of IGZO have c-axis orientation and are connected in a non-oriented manner on the a-b plane.

[0105] On the other hand, CAC-OS is related to the material composition of the oxide semiconductor. CAC-OS refers to the following composition: in a material composition containing In, Ga, Zn, and O, nanoparticle-like regions mainly composed of Ga are observed in some parts, and nanoparticle-like regions mainly composed of In are observed in some parts, and they are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0106] CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga.

[0107] Note that sometimes, the distinct boundary between the region mainly composed of GaO X3 and the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 cannot be observed.

[0108] When one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. are included in CAC-OS to replace gallium, CAC-OS refers to the following composition: nanoparticle-like regions mainly composed of the metal element are observed in part, and nanoparticle-like regions mainly composed of In are observed in part, and they are randomly dispersed in a mosaic pattern.

[0109] CAC-OS can be formed, for example, by sputtering under the condition of not heating the substrate. When forming CAC-OS by sputtering, as the film-forming gas, one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used. In addition, the lower the flow ratio of oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow ratio of oxygen gas is set to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0110] CAC-OS has the following characteristics: when measured by θ / 2θ scanning using the Out-of-plane method, one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods, no distinct peak is observed. That is, according to X-ray diffraction measurement, it can be known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0111] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nano-beam), a bright annular region and multiple bright spots within the annular region are observed. Thus, from the electron diffraction pattern, it can be known that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0112] In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis image (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that: there are regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 OZ2 or InO X1 a structure in which regions mainly composed of... are unevenly distributed and mixed

[0113] The structure of CAC-OS is different from that of the IGZO compound in which metal elements are evenly distributed, and it has properties different from those of the IGZO compound. In other words, CAC-OS has regions mainly composed of GaO X3 etc. and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 a mosaic-like structure in which the regions mainly composed of... are separated from each other

[0114] Here, the conductivity of the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is higher than that of the region mainly composed of GaO X3 etc. In other words, when carriers flow through the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 it exhibits the conductivity of an oxide semiconductor. Therefore, when the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is distributed in a cloud-like manner in the oxide semiconductor, a high field-effect mobility (μ) can be achieved.

[0115] On the other hand, the insulation of the region mainly composed of GaO X3 etc. is higher than that of the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 In other words, when the region mainly composed of GaO X3 etc. is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0116] Therefore, when CAC-OS is used for a semiconductor element, high on-state current (I on ) and high field-effect mobility (μ) can be achieved through the complementary action of the insulation due to GaO X3 etc. and the conductivity due to In X2 Zn Y2 O Z2 or InO X1

[0117] ​In addition, semiconductor devices using CAC-OS have high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0118] Refer to Figure 2A The timing chart shown in the figure illustrates an example of the operation of adding correction data to image data in pixel circuits 10[k, n] and pixel circuit 10[k, n + 1]. In the following description, "H" represents a high potential, "L" represents a low potential, and "Vcom" represents a common potential. In addition, the correction data is "Vpa" and "Vpb", and the image data is "Vs". Additionally, "Vpa" and "Vpb" may be referred to as arbitrary first data, and "Vs" may be referred to as arbitrary second data. Here, detailed variations in the circuit structure, operating timing, etc. are not considered in terms of potential distribution, coupling, or loss. The potential change caused by capacitive coupling depends on the capacitance ratio between the supply side and the side being supplied, but for the sake of simplicity, it is assumed that the capacitance value of the node is sufficiently small.

[0119] At time T1, when the potential of wiring 121[k] is "H", the potential of wiring 122[k] is "H", and the potential of wiring 123[k] is "H", transistors 101a, 103a, 101b, and 103b are turned on.

[0120] During T1 - T2, when the potential of wiring 124[n] is "Vpa" and the potential of wiring 124[n + 1] is "Vpb", the potential of wiring 124[n] (correction data "Vpa") is written to node N1a, and the potential of wiring 124[n + 1] (correction data "Vpb") is written to node N1b. When the potential of wiring 125[m] is "Vcom", the potential of wiring 125[m] ("Vcom") is written to node N2a and node N2b, respectively.

[0121] At time T2, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "H", and the potential of wiring 123[k] is "H", transistors 103a and 103b are turned off, node N1a holds the correction data "Vpa", and node N1b holds the correction data "Vpb". In addition, capacitor 104a holds "Vpa - Vcom", and capacitor 104b holds "Vpb - Vcom".

[0122] Note that when no correction is performed, in the above operation, the same potential as "Vcom" can be supplied as the correction data "Vpa" and "Vpb".

[0123] During T2 - T3, when the potential of wiring 125[m] is "Vs", the potential of wiring 125[m] (image data "Vs") is written to node N2a. The potential of wiring 125[m] "Vs" is added to the potential of node N1a by the capacitive coupling of capacitor 104a. At this time, the potential of node N1a is "Vpa - Vcom + Vs", and when not considering parasitic capacitance other than transistor 101a, when "Vcom" = 0, the potential of node N1a is "Vpa + Vs".

[0124] At time T3, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "L", and the potential of wiring 123[k] is "H", transistor 101a is non-conductive, and the potential of node N1a is held at "Vpa + Vs".

[0125] During T3 - T4, when the potential of wiring 125[m] is "Vs", the potential of wiring 125[m] (image data "Vs") is written to node N2b. The potential of wiring 125[m] "Vs" is added to the potential of node N1b by the capacitive coupling of capacitor 104b. At this time, the potential of node N1b is "Vpb - Vcom + Vs", and when not considering parasitic capacitance other than transistor 101a, when "Vcom" = 0, the potential of node N1b is "Vpb + Vs".

[0126] At time T4, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "L", and the potential of wiring 123[k] is "L", transistor 101b is non-conductive, and the potential of node N1b is held at "Vpb + Vs".

[0127] Then, in each of the display elements included in circuit block 110a and circuit block 110b, display operations corresponding to the potentials of node N1a and node N1b are performed.

[0128] Figure 2B Shows an example different from Figure 2A the timing diagram shown. Figure 2B Different from Figure 2A the timing diagram shown is that the potential of wiring 122[k] is "L" during T2 - T3. By adopting Figure 2B the timing diagram shown, unnecessary driving in pixel circuit 10[k, n + 1] can be reduced.

[0129] Note that Figure 2A 、 Figure 2B the operations can be continuously performed within one horizontal period.

[0130] <Example of pixel structure 2>

[0131] Figure 3 It is a diagram showing the pixel circuit 11 of a display device that can be used in one embodiment of the present invention.

[0132] Figure 3 The pixel circuit 11 shown is Figure 1 different from the pixel circuit 10 shown in the connection structure of each transistor and each wiring. The pixel circuit 11[k, n+1] is adjacent to the pixel circuit 11[k, n]. Since the structure in the pixel circuit 11[k, n] can be referred to the description of the pixel circuit 10[k, n], the detailed description is omitted. The structure in the pixel circuit 11[k, n+1] can be referred to the description of the pixel circuit 10[k, n+1], so the detailed description is omitted.

[0133] The gate of the transistor 101a is electrically connected to the wiring 123[k]. The gate of the transistor 101b is electrically connected to the wiring 123[k]. The gate of the transistor 103a is electrically connected to the wiring 121[k]. The gate of the transistor 103b is electrically connected to the wiring 122[k]. The other of the source and drain of the transistor 103a and the other of the source and drain of the transistor 103b are electrically connected to the wiring 125[m]. In other words, the transistors 103a and 103b share the wiring 125[m]. The other of the source and drain of the transistor 101a is electrically connected to the wiring 124[n]. The other of the source and drain of the transistor 101b is electrically connected to the wiring 124[n+1].

[0134] Refer to Figure 4A the timing chart shown to illustrate an example of the operation of adding correction data to the image data in the pixel circuits 11[k, n] and 11[k, n+1].

[0135] At time T1, when the potential of the wiring 121[k] is "H", the potential of the wiring 122[k] is "H", and the potential of the wiring 123[k] is "H", the transistors 101a, 103a, 101b, and 103b are turned on.

[0136] During T1-T2, when the potential of the wiring 125[m] is "Vs", the potential of the wiring 125[m] (image data "Vs") is written to the node N1a. When the potential of the wiring 124[n] is "Vcom" and the potential of the wiring 124[n+1] is "Vcom", the potential of the wiring 124[n] ("Vcom") is written to the node N2a.

[0137] At time T2, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "H", and the potential of wiring 123[k] is "H", transistor 103a is non-conductive, and node N1a holds the image data "Vs". In addition, capacitor 104a holds "Vs-Vcom".

[0138] During T2-T3, when the potential of wiring 124[n] is "Vpa", the potential of wiring 124[n] (correction data "Vpa") is written to node N2a. The potential of wiring 124[n], "Vpa", is added to the potential of node N1a by the capacitive coupling of capacitor 104a. At this time, the potential of node N1a is "Vs-Vcom+Vpa", and when "Vcom" = 0 without considering the parasitic capacitance other than transistor 101a, the potential of node N1a is "Vpa+Vs". When the potential of wiring 125[m] is "Vs", the potential of wiring 125[m] (image data "Vs") is written to node N1b. When the potential of wiring 124[n+1] is "Vcom", the potential of wiring 124[n+1] ("Vcom") is written to node N2b.

[0139] At time T3, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "H", and the potential of wiring 123[k] is "H", transistor 103b is non-conductive, and node N1b holds the image data "Vs". In addition, capacitor 104b holds "Vs-Vcom".

[0140] During T3-T4, when the potential of wiring 124[n+1] is "Vpb", the potential of wiring 124[n+1] (correction data "Vpb") is written to node N2b. The potential of wiring 124[n+1], "Vpb", is added to the potential of node N1b by the capacitive coupling of capacitor 104b. At this time, the potential of node N1b is "Vs-Vcom+Vpb", and when "Vcom" = 0 without considering the parasitic capacitance other than transistor 101a, the potential of node N1b is "Vpb+Vs". Note that when no correction is performed, in the above operations, the same potential as "Vcom" can be supplied as the correction data "Vpa" and "Vpb".

[0141] At time T4, when the potential of wiring 121[k] is "L", the potential of wiring 122[k] is "L", and the potential of wiring 123[k] is "L", transistors 101a and 101b are non-conductive, the potential of node N1a is "Vpa+Vs", and the potential of node N1b is held as "Vpb+Vs".

[0142] Then, in each of the display elements included in circuit block 110a and circuit block 110b, display operations corresponding to the potentials of node N1a and node N1b are performed.

[0143] Figure 4B Shows an example different from Figure 4A the timing chart shown. Figure 4B Different from Figure 4A the timing chart shown is that the potential of wiring 122[k] is made "L" during T1 - T2. By adopting Figure 4B the timing chart shown, unnecessary driving in pixel circuit 10[k, n + 1] can be reduced.

[0144] Note that Figure 4A and Figure 4B the operations can be continuously performed during one horizontal period.

[0145] Here, with reference to Figure 5A the correction operation of image data is described.

[0146] Figure 5A The figure shown shows four pixels (P1 to P4) in the horizontal and vertical directions. The input image data (Vs1, Vs2, Vs3), the input correction data (+Vp1, Vp0, -Vp1), and the generated corrected image data are shown from the left. Note that in the following description, the display element can perform high - brightness display when the potential of the image data is relatively high, and can perform low - brightness display when the potential of the image data is relatively low.

[0147] For example, in pixel P1, when the image data "Vs1" is combined with the positive correction data "+Vp1", the image data is "Vs1 + Vp1", and the brightness increases. In pixels P2 and P3, when the image data "Vs2" is combined with the correction data "Vp0" with substantially no correction, the image data is "Vs2 + Vp0 = Vs2", and the brightness does not change. In pixel P4, when the image data "Vs3" is combined with the negative correction data "-Vp1", the image data is "Vs3 - Vp1", and the brightness decreases.

[0148] Such combinations of image data and correction data can perform up - conversion, HDR display, correction of inherent display non - uniformity of the display device, correction of the threshold voltage of the transistors included in the pixels, etc.

[0149] In the up - conversion operation, for example, the same image data is supplied to all of the four pixels. Through correction, each pixel can display a different image. For example, data applicable to a specific one pixel of a display device with a pixel count of 4K×2K can be input to specific four pixels of a display device with a pixel count of 8K×4K, so as to perform high - resolution display.

[0150] In addition, different images can be displayed overlappingly, which is correction of image data in a broad sense. Figure 5B An image showing the entire display unit is shown. From the left, a first image composed of image data "Vs", a second image composed of correction data "Vpa" and "Vpb", and an image obtained by synthesizing the first image and the second image are shown.

[0151] Thus, the combination of image data and correction data can not only synthesize and display different images, but also improve the brightness of the entire displayed image and the like. For example, it can be applied to text insertion and AR (Augmented Reality) display and the like.

[0152] In Figures 6A to 6C a structure in which a circuit block 110 including an EL element in a display element is shown as a circuit block that can be applied to circuit block 110a and circuit block 110b is shown.

[0153] Figure 6A The structure shown includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain of the transistor 111 is electrically connected to one electrode of the EL element 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to node N1a or node N1b.

[0154] The other of the source and drain of the transistor 111 is electrically connected to the wiring 128. The other electrode of the EL element 114 is electrically connected to the wiring 129. The wirings 128 and 129 have a function of supplying power. For example, the wiring 128 can supply a high-potential power supply. In addition, the wiring 129 can supply a low-potential power supply.

[0155] In Figure 6A the structure shown, when the potential at node N1a or node N1b becomes equal to or higher than the threshold voltage of the transistor 111, current flows through the EL element 114. As a result, sometimes Figure 2A the light emission of the EL element 114 starts at the stage of time T1 in the timing chart shown, and thus the use of this structure may be limited.

[0156] Figure 6B is a structure in which a transistor 112 is added to the Figure 6A structure. One of the source and drain of the transistor 112 is electrically connected to one of the source and drain of the transistor 111. The other of the source and drain of the transistor 112 is electrically connected to the EL element 114. The gate of the transistor 112 is electrically connected to the wiring 126. The wiring 126 can have a function of a signal line for controlling the conduction of the transistor 112.

[0157] In this structure, when the potential of node N1a or node N1b is above the threshold voltage of transistor 111 and transistor 112 is turned on, current flows through EL element 114. Therefore, the light emission of EL element 114 can start after time T4 in the timing diagram shown below, and thus this structure is suitable for the operation accompanied by correction. Figure 2A shown below, and thus this structure is suitable for the operation accompanied by correction.

[0158] Figure 6C is a structure in which transistor 115 is added to the Figure 6B structure. One of the source and drain of transistor 115 is electrically connected to one of the source and drain of transistor 111. The other of the source and drain of transistor 115 is electrically connected to wiring 130. The gate of transistor 115 is electrically connected to wiring 131. Wiring 131 can function as a signal line for controlling the conduction of transistor 115. In addition, the gate of transistor 115 can also be electrically connected to wiring 122.

[0159] Wiring 130 can be electrically connected to a supply source of a specific potential such as a reference potential. By supplying a specific potential from wiring 130 to one of the source and drain of transistor 111, the writing of image data can also be stabilized.

[0160] Furthermore, wiring 130 can be connected to circuit 120 and can function as a monitoring line. Circuit 120 can have one or more of the functions of supplying the above-mentioned specific potential, obtaining the electrical characteristics of transistor 111, and generating correction data.

[0161] When wiring 130 is used as a monitoring line, circuit 120 generates potentials for correcting the threshold voltage of transistor 111 as the above-mentioned correction data "Vpa" and "Vpb".

[0162] In Figures 7A to 7C as an example of a structure of circuit block 110 applicable to circuit blocks 110a and 110b, a structure including a liquid crystal element in a display element is shown.

[0163] Figure 7A The structure shown below includes capacitor 116 and liquid crystal element 117. One electrode of liquid crystal element 117 is electrically connected to one electrode of capacitor 116. One electrode of capacitor 116 is electrically connected to node N1a or N1b.

[0164] The other electrode of capacitor 116 is electrically connected to wiring 132. The other electrode of liquid crystal element 117 is electrically connected to wiring 133. Wirings 132 and 133 have the function of supplying power. For example, wirings 132 and 133 can supply a reference potential such as GND and 0V or an arbitrary potential.

[0165] In this structure, the operation of the liquid crystal element 117 starts when the potential of the node N1a or N1b becomes equal to or higher than the operating threshold of the liquid crystal element 117. Thus, sometimes the display operation starts at the stage of time T1 in the timing chart shown in Figure 2A , so the use of this structure may be limited. Note that in the case of a transmissive liquid crystal display device, by also performing operations such as turning off the backlight until the time T4 shown in Figure 2A , it is possible to suppress the visibility of unwanted display operations.

[0166] Figure 7B is a structure in which a transistor 118 is added to the structure of Figure 7A . One of the source and drain of the transistor 118 is electrically connected to one electrode of the capacitor 116. The other of the source and drain of the transistor 118 is electrically connected to the node N1a or N1b. The gate of the transistor 118 is electrically connected to the wiring 126. The wiring 126 can function as a signal line for controlling the conduction of the transistor 118.

[0167] In this structure, the potential of the node N1a or N1b is applied to the liquid crystal element 117 while the transistor 118 is conducting. Thus, the operation of the liquid crystal element can start after the time T4 in the timing chart shown in Figure 2A , so this structure is suitable for operations accompanied by correction.

[0168] In addition, since the potentials supplied to the capacitor 116 and the liquid crystal element 117 are continuously maintained while the transistor 118 is in the non-conducting state, it is preferable to reset the potentials supplied to the capacitor 116 and the liquid crystal element 117 before rewriting the image data. In this reset, for example, a reset potential is supplied to the wiring 124 and the transistor 118 is made to conduct simultaneously.

[0169] Figure 7C is a structure in which a transistor 119 is added to the structure of Figure 7B . One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and drain of the transistor 119 is electrically connected to the wiring 130. The gate of the transistor 119 is electrically connected to the wiring 131. The wiring 131 can function as a signal line for controlling the conduction of the transistor 119. In addition, the gate of the transistor 119 can also be electrically connected to the wiring 122.

[0170] The circuit 120 electrically connected to the wiring 130 can also have the function of resetting the potentials supplied to the capacitor 116 and the liquid crystal element 117, similarly to the description in Figure 6C above.

[0171] In addition, as in Figure 8A , Figure 8BAs shown, the transistors 101a, 103a, 101b, and 103b may also adopt a structure provided with a back gate. Figure 8A A structure in which the back gate is electrically connected to the front gate is shown, and this structure has the effect of increasing the turn-on current. Figure 8B A structure in which the back gate is electrically connected to the wiring 134 capable of supplying a constant potential is shown, and this structure can control the threshold voltage of the transistor. Additionally, a back gate may also be provided for the transistors included in the Figures 6A to 6C and Figures 7A to 7C circuit block 110 shown.

[0172] Figure 9A This is an example of a block diagram of a display device according to an aspect of the present invention. The display device includes a pixel array 17 in which pixel circuits 11 are arranged in a matrix, a row driver 13, a column driver 14, a circuit 15, and a selection circuit 16.

[0173] The row driver 13 may, for example, adopt a structure combining a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, data is output to the wiring 121 or the wiring 122.

[0174] The column driver 14 may, for example, adopt a structure combining a shift register 22 and a buffer circuit 23. By controlling the conduction of the buffer circuit 23, data can be output to the wiring 124 and the wiring 125.

[0175] The circuit 15 has the function of generating correction data. Note that the circuit 15 may also be regarded as an external device for generating correction data.

[0176] The row driver 13 can control the conduction of the transistors 101a, 103a, 101b, and 103b. The column driver 14 can supply correction data or image data to the wiring 124 and the wiring 125.

[0177] High-resolution image data “VsH” (e.g., 8K4K data) or low-resolution image data “VsL” (e.g., 4K2K data) is input to the circuit 15. When the image data “VsH” is input, correction data “Vp1” is generated, and when the image data “VsL” is input, correction data “Vp2” is generated.

[0178] In addition to the correction data “Vp1” and “Vp2” generated by the circuit 15, the selection circuit 16 can output correction data “Vp1” and “Vp2” or image data “VsH” and “VsL” generated externally to the column driver 14.

[0179] In Figure 9AIn the structure shown, for example, when performing uncorrected display work at a low resolution, the output stage of each driver can be halved, thereby reducing power consumption.

[0180] Circuit 15 can have a neural network. For example, a deep neural network that has been trained using a large number of images as supervised data can be used to generate high-precision correction data.

[0181] As Figure 10A shown, the neural network NN can be composed of an input layer IL, an output layer OL, and an intermediate layer (hidden layer) HL. The input layer IL, the output layer OL, and the intermediate layer HL all include one or more neurons (units). Note that the intermediate layer HL can be one layer or two or more layers. A neural network including two or more layers of the intermediate layer HL can be called a DNN (deep neural network), and the learning using a deep neural network can be called deep learning.

[0182] Each neuron in the input layer IL is input with input data, each neuron in the intermediate layer HL is input with the output signals of the neurons in the previous layer or the next layer, and each neuron in the output layer OL is input with the output signals of the neurons in the previous layer. Note that each neuron can be connected (fully connected) to all the neurons in the previous layer and the next layer, or can be connected to some neurons.

[0183] Figure 10B An example of the operation using a neuron is shown. Here, a neuron N and two neurons in the previous layer that output signals to the neuron N are shown. The neuron N is input with the output x1 of the neuron in the previous layer and the output x2 of the neuron in the previous layer. In the neuron N, the sum x1w1 + x2w2 of the multiplication result (x1w1) of the output x1 and the weight w1 and the multiplication result (x2w2) of the output x2 and the weight w2 is calculated, and then a bias b is added to it as needed, thereby obtaining a value a = x1w1 + x2w2 + b. The value a is transformed by the activation function h, and the output signal y = h(a) is output from the neuron N.

[0184] Thus, the operation using a neuron includes an operation of adding the products of the outputs of the neurons in the previous layer and the weights, that is, a sum-of-products operation (the above x1w1 + x2w2). This sum-of-products operation can be performed either by a program in software or by hardware. When performing the sum-of-products operation by hardware, a sum-of-products operation circuit can be used. As this sum-of-products operation circuit, either a digital circuit or an analog circuit can be used.

[0185] The product-sum operation circuit can be composed of Si transistors or OS transistors. In particular, since OS transistors have an extremely small off-state current, they are preferably used as the transistors for the analog memory that constitutes the product-sum operation circuit. Note that the product-sum operation circuit can also be composed of both Si transistors and OS transistors.

[0186] In addition, the generation of the correction data is not limited to using circuit 15, but can also be performed using the above-mentioned circuit 120 (refer to Figure 9B ). In addition, the correction data can also be generated based on the data of the luminance of the display performed in the display unit and read by the luminance meter, or the data of the photograph of the display. In addition, a sensor 24 capable of detecting the luminance of the display and a circuit 25 capable of detecting the deterioration of the display element to generate the correction data can be provided (refer to Figure 9C ).

[0187] Regarding the use of the Figure 7A shown circuit block for Figure 1 the pixel circuits 10[k, n] and 10[k, n + 1] shown (refer to Figure 11 ), the simulation results will be described.

[0188] The size of the transistors is all L / W = 4 μm / 4 μm, the capacitance values of the capacitors 104a and 104b are 100 fF, the capacitance values of the capacitors 116a and 116b are 50 fF, the capacitance values of the liquid crystal elements 117a and 117b are 20 fF, and the potentials of the common wirings 132 and 133 are both 0 V. Note that SPICE is used as the circuit simulation software.

[0189] Figures 12A to 12C 、 Figures 13A to 13C shows the simulation results of the operations of the pixel circuit 10[k, n] and the pixel circuit 10[k, n + 1]. In Figures 12A to 12C 、 Figures 13A to 13C , the vertical axis represents the potential of each wiring, and the horizontal axis represents the time according to the timing diagram.

[0190] Figure 12A is a diagram showing the potentials of the wirings 121[k] and 122[k] connected to the gates of the transistors 101a and 103a in the pixel circuit 10[k, n]. Figure 12B is a diagram showing the potentials of the wiring 124[n] for supplying the correction data "Vpa" and the wiring 125[m] for supplying the image data "Vs". Figure 12C is a diagram showing the simulation results of the potentials of the nodes N1a and N2a of the pixel circuit 10[k, n].

[0191] Figure 13AIt is a diagram showing the potentials of wirings 121[k] and 123[k] connected to the gates of transistors 101b and 103b in pixel circuit 10[k, n+1]. Figure 13B It is a diagram showing the potentials of wiring 124[n+1] for supplying correction data "Vpb" and wiring 125[m] for supplying image data "Vs". Figure 13C It is the simulation result of the potentials of nodes N1b and N2b in pixel circuit 10[k, n+1].

[0192] As Figure 12C shown, it can be confirmed that in pixel circuit 10[k, n], during T1-T2, the potential of wiring 124[n] (Vpa) is written to node N1a, and during T2-T3, the potential of node N1a rises due to capacitive coupling. In addition, as Figure 13C shown, it can be confirmed that in pixel circuit 10[k, n+1], during T1-T2, the potential of wiring 124[n+1] (Vpb) is written to node N1b, and during T3-T4, the potential of node N1b drops due to capacitive coupling.

[0193] Figure 14 This is an example of applying the pixel of one embodiment of the present invention to an EL display device capable of color display. Generally, the pixels of a display device capable of color display have a combination of sub-pixels that emit each color of R (red), G (green), and B (blue). In Figure 14 , three sub-pixels of each color of sub-pixel circuits 10R, 10G, and 10B arranged in the horizontal direction constitute one pixel, and a total of six pixels representing two pixels in the horizontal direction and three pixels in the vertical direction are shown. As described above, in one embodiment of the present invention, adjacent pixels can share wiring 125.

[0194] Although in the stripe arrangement, it is preferable to arrange each sub-pixel at the same interval, in the case where each sub-pixel shares wirings and transistors, it is sometimes difficult to keep the intervals of each sub-pixel (the intervals of components having the same function) constant.

[0195] Therefore, when the pixel electrodes connected to sub-pixel circuits 10R, 10G, and 10B are electrodes 26R, 26G, and 26B respectively, as Figure 14 shown, it is preferable to adopt a structure in which electrodes 26R, 26G, and 26B are arranged at the same interval. Note that although pixel electrodes can also be said to be components of each sub-pixel, for simplicity, they are shown as different components here. This structure is effective for a top-emission type EL display device or a reflective liquid crystal display device.

[0196] Here, refer to Figure 15 to explain the aperture ratio of the pixel. Figure 15 This is an example of the layout of pixels using one mode of the present invention. Figure 15 This shows an example in which three sub-pixels of each color, namely sub-pixel 31R, sub-pixel 31G, and sub-pixel 31B, arranged in the horizontal direction form one pixel 31, representing a total of two pixels (six sub-pixels), which are two pixels in the horizontal direction and one pixel in the vertical direction. Note that for ease of understanding the description, Figure 15 only the wirings 121, 122, 123, 124, and 125 are shown, and the pixel circuit is omitted.

[0197] When the areas occupied by the wirings 121, 122, 123, 124, and 125 are large, the aperture ratio of the pixel sometimes becomes small. Therefore, in the pixel, the areas occupied by the wirings 121, 122, 123, 124, and 125 are preferably small.

[0198] In Figure 15 the vertical length of the pixel 31 is H31, and the horizontal length is W31. The horizontal lengths of the sub-pixels 31R, 31G, and 31B are W31R, W31G, and W31B respectively. Figure 15 This shows an example where W31R, W31G, and W31B are equal. In addition, this shows an example where H31 is equal to W31, that is, the pixel 31 is square. Therefore, in Figure 15 W31R, W31G, and W31B are respectively equal to one-third of H31.

[0199] The area occupied by the wiring is described using the sub-pixel 31R. As described above, in one mode of the present invention, the adjacent sub-pixels 31R and 31G share the wiring 125[m], and there are three wirings including the wirings 121[k], 122[k], and 123[k] in the horizontal direction. By sharing the wiring 125[m], when adding one wiring in the horizontal direction and the added wiring is the wiring 123[k], the area occupied by the wiring 123 in one sub-pixel is W31R×W123. By sharing the wiring 125[m], the area occupied by the wiring 125[m] in one sub-pixel is H31×W124÷2. Therefore, when W123 is equal to W125, compared with the increased amount of the area W31R×W123, the decreased amount H31×W124÷2 is larger, whereby the area of the wiring occupied in the pixel can be reduced. That is, in one mode of the present invention, the aperture ratio of the pixel can be increased.

[0200] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0201] (Embodiment 2)

[0202] This embodiment describes structural examples of a display device using a liquid crystal element and a display device using an EL element. Note that the constituent elements, operations, and functions of the display device described in Embodiment 1 are omitted in this embodiment.

[0203] Figures 16A to 16C Shows the structure of a display device capable of using one aspect of the present invention.

[0204] In Figure 16A , a sealant 4005 is provided so as to surround a display portion 215 provided on a first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and a second substrate 4006.

[0205] The display portion 215 is provided with the pixel array shown in Embodiment 1. Note that the scan line driving circuit described below corresponds to a row driver, and the signal line driving circuit corresponds to a column driver.

[0206] In Figure 16A , the scan line driving circuit 221a, the signal line driving circuit 231a, the signal line driving circuit 232a, and the common line driving circuit 241a all include a plurality of integrated circuits 4042 provided on a printed circuit board 4041. The integrated circuit 4042 is formed of single-crystalline semiconductor or polycrystalline semiconductor. The signal line driving circuit 231a and the signal line driving circuit 232a have the functions of the column driver shown in Embodiment 1. The scan line driving circuit 221a has the functions of the row driver shown in the embodiment. The common line driving circuit 241a has the function of supplying a specified potential to wirings and the like shown in Embodiment 1.

[0207] Various signals and potentials are supplied to the scan line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal line driving circuit 232a through an FPC (Flexible Printed Circuit) 4018.

[0208] The integrated circuits 4042 included in the scan line driving circuit 221a and the common line driving circuit 241a have the function of supplying selection signals to the display portion 215. The integrated circuits 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a have the function of supplying image data to the display portion 215. The integrated circuit 4042 is mounted in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0209] Note that there is no particular limitation on the connection method of the integrated circuit 4042, and methods such as wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), and COF (Chip On Film) can be used.

[0210] Figure 16B An example of mounting the integrated circuit 4042 included in the signal line driving circuit 231a and the signal line driving circuit 232a using the COG method is shown. In addition, by forming a part or the whole of the driving circuit on the substrate on which the display unit 215 is formed, a system-on-panel can be formed.

[0211] Figure 16B An example of forming the scan line driving circuit 221a and the common line driving circuit 241a on the substrate on which the display unit 215 is formed is shown. By forming the driving circuit and the pixel circuit in the display unit 215 simultaneously, the number of components can be reduced. Thereby, the productivity can be improved.

[0212] In addition, in Figure 16B , a sealant 4005 is provided so as to surround the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a provided on the first substrate 4001. A second substrate 4006 is provided on the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a. Thus, the display unit 215, the scan line driving circuit 221a, and the common line driving circuit 241a are sealed together with the display element through the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0213] Although Figure 16B shows an example in which the signal line driving circuit 231a and the signal line driving circuit 232a are separately formed and mounted on the first substrate 4001, one aspect of the present invention is not limited to this structure, and the scan line driving circuit can also be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit can be separately formed and mounted. In addition, as Figure 16C shows, the signal line driving circuit 231a and the signal line driving circuit 232a can also be formed on the substrate on which the display unit 215 is formed.

[0214] In addition, a display device sometimes includes a panel in which a display element is in a sealed state and a module in which an IC including a controller is mounted in the panel.

[0215] The display unit and the scan line driving circuit provided on the first substrate include a plurality of transistors. As the transistor, the transistor shown in the above embodiment can be applied.

[0216] The structures of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit may have the same structure or different structures. The transistors included in the peripheral driving circuit may all have the same structure or may combine two or more structures. Similarly, the transistors included in the pixel circuit may all have the same structure or may combine two or more structures.

[0217] In addition, an input device 4200 may be provided on the second substrate 4006. Figures 16A to 16C The structure in which the input device 4200 is provided for the display device shown can be used as a touch screen.

[0218] There is no particular limitation on the sensing element (also referred to as a sensing component) included in the touch screen of one embodiment of the present invention. Various sensors capable of detecting the approach or contact of a detection object such as a finger or a stylus can also be used as the sensing element.

[0219] For example, as a sensor type, various types such as capacitive, resistive film, surface acoustic wave, infrared, optical, and piezoresistive can be used.

[0220] In the present embodiment, a touch screen including a capacitive sensing element will be described as an example.

[0221] As capacitive, there are surface capacitive, projected capacitive, etc. In addition, as projected capacitive, there are self-capacitive, mutual-capacitive, etc. It is preferable to use mutual-capacitive because multi-point sensing can be performed simultaneously.

[0222] A touch screen of one embodiment of the present invention can adopt various structures such as a structure in which a separately manufactured display device and a sensing element are bonded, a structure in which electrodes constituting the sensing element are provided on one or both of a substrate supporting the display element and an opposing substrate, etc.

[0223] Figure 17A and Figure 17B An example of the touch screen is shown. Figure 17A is a perspective view of the touch screen 4210. Figure 17B is a perspective schematic view of the input device 4200. Note that, for clarity, only typical components are shown.

[0224] The touch screen 4210 has a structure in which a separately manufactured display device and a sensing element are bonded.

[0225] The touch screen 4210 includes an input device 4200 and a display device which are overlapped and arranged.

[0226] The input device 4200 includes a substrate 4263, electrodes 4227, electrode 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. In addition, the electrode 4228 can be electrically connected to the wiring 4239. The FPC 4272b can be electrically connected to the plurality of wirings 4237 and the plurality of wirings 4238 respectively. The FPC 4272b can be provided with an IC 4273b.

[0227] A touch sensor can be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element can be used in addition to the capacitive touch sensor.

[0228] Figure 18A and Figure 18B is a cross-sectional view along the dotted line N1 - N2 in Figure 16B . Figure 18A and Figure 18B The display device shown in and includes an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 4018 through an anisotropic conductive layer 4019. In addition, in Figure 18A and Figure 18B , the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0229] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source electrodes and drain electrodes of the transistors 4010 and 4011 are formed using the same conductive layer.

[0230] In addition, the display unit 215 and the scan line driving circuit 221a provided on the first substrate 4001 include a plurality of transistors. In Figure 18A and Figure 18B , the transistors 4010 in the display unit 215 and the transistors 4011 in the scan line driving circuit 221a are shown. Although Figure 18A and Figure 18B show bottom-gate transistors as the transistors 4010 and 4011, top-gate transistors can also be used.

[0231] In Figure 18A and Figure 18B , an insulating layer 4112 is provided on the transistors 4010 and 4011. In addition, in Figure 18B , a partition wall 4510 is formed on the insulating layer 4112.

[0232] In addition, the transistor 4010 and the transistor 4011 are provided on the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 include an electrode 4017 formed on the insulating layer 4111. The electrode 4017 can be used as a back gate electrode.

[0233] In addition, Figure 18A and Figure 18B the shown display device includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and the drain electrode. Each electrode overlaps with each other with the insulating layer 4103 therebetween.

[0234] Generally, the capacitance of the capacitor provided in the pixel portion of the display device is set in consideration of the leakage current of the transistors arranged in the pixel portion so that it can hold the charge for a specified period. The capacitance of the capacitor can be set in consideration of the off-state current of the transistor or the like.

[0235] The transistor 4010 provided in the display portion 215 is electrically connected to the display element. Figure 18A is an example of a liquid crystal display device using a liquid crystal element as the display element. In Figure 18A it, the liquid crystal element 4013 as the display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that the insulating layers 4032 and 4033 used as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the side of the second substrate 4006, and the first electrode layer 4030 overlaps with the second electrode layer 4031 with the liquid crystal layer 4008 therebetween.

[0236] The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and it is provided to control the interval (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Note that spherical spacers can also be used.

[0237] In addition, according to needs, optical members (optical substrates) such as a black matrix (light-shielding layer), a coloring layer (color filter), a polarization member, a retardation member, and an antireflection member can be appropriately provided. For example, circular polarization using a polarization substrate and a retardation substrate can also be used. In addition, as the light source, a backlight or a side light or the like can also be used. As the above backlight or side light, Micro-LED or the like can also be used.

[0238] In Figure 18A the shown display device, a light-shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.

[0239] As materials that can be used for the light-shielding layer, carbon black, titanium black, metals, metal oxides, or composite oxides such as solid solutions containing multiple metal oxides can be cited. The light-shielding layer can also be a film containing a resin material or a thin film containing an inorganic material such as a metal. In addition, a laminated film of a film containing a material of a colored layer can also be used for the light-shielding layer. For example, a laminated structure of a film containing a material of a colored layer for transmitting light of a certain color and a film containing a material of a colored layer for transmitting light of other colors can be adopted. By making the materials of the colored layer and the light-shielding layer the same, not only can the same equipment be used, but also the process can be simplified, which is therefore preferable.

[0240] As materials that can be used for the colored layer, metal materials, resin materials, resin materials containing pigments or dyes, etc. can be cited. The light-shielding layer and the colored layer can be formed, for example, by an inkjet method or the like.

[0241] In addition, Figure 18A and Figure 18B The display device shown includes an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer that does not easily allow impurity elements to pass through is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, the mixing of impurities from the outside can be prevented.

[0242] In addition, as a display element included in the display device, a light-emitting element using electroluminescence (also referred to as an EL element) can be applied. The EL element has a layer containing a light-emitting compound (also referred to as an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, and thereby, the light-emitting compound contained in the EL layer emits light.

[0243] EL elements are distinguished according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0244] In an organic EL element, by applying a voltage, electrons are injected into the EL layer from one electrode, and holes are injected into the EL layer from the other electrode. Through the recombination of these carriers (electrons and holes), the light-emitting organic compound forms an excited state and emits light when returning from this excited state to the ground state. Due to this mechanism, this light-emitting element is called a current-excited type light-emitting element.

[0245] The EL layer can also include, in addition to the light-emitting compound, a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property), etc.

[0246] The EL layer can be formed by methods such as evaporation (including vacuum evaporation), transfer printing, printing, inkjet printing, coating, etc.

[0247] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. The dispersed inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination-type luminescence using donor levels and acceptor levels. The thin-film inorganic EL element has a structure in which the light-emitting layer is sandwiched between dielectric layers, and the dielectric layer sandwiching the light-emitting layer is sandwiched between electrodes, and its light-emitting mechanism is local-type luminescence using inner-shell electron transitions of metal ions. Note that an organic EL element is used here for illustration as the light-emitting element.

[0248] In order to extract light emission, at least one of a pair of electrodes of the light-emitting element is made transparent. A transistor and a light-emitting element are formed on a substrate. As the light-emitting element, a top-emission structure that emits light from the surface on the side opposite to the substrate; a bottom-emission structure that emits light from the surface on the substrate side; and a double-sided emission structure that emits light from both surfaces can be adopted.

[0249] Figure 18B is an example of a light-emitting display device (also referred to as an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513 used as the display element is electrically connected to the transistor 4010 provided in the display unit 215. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of extracting light from the light-emitting element 4513, etc.

[0250] The partition wall 4510 is formed of an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030, and to form the side surface of the opening as an inclined surface having a continuous curvature.

[0251] The light-emitting layer 4511 can be composed of one layer or a stack of multiple layers.

[0252] The light-emitting color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, etc. according to the material constituting the light-emitting layer 4511.

[0253] As a method for realizing color display, there are the following methods: a method of combining a light-emitting element 4513 that emits white light and a coloring layer; and a method of arranging light-emitting elements 4513 with different light-emitting colors for each pixel. The productivity of the former method is higher than that of the latter method. On the other hand, in the latter method, since the light-emitting layer 4511 needs to be formed for each pixel, its productivity is lower than that of the former method. However, in the latter method, light-emitting colors with higher color purity than those of the former method can be obtained. By providing the light-emitting element 4513 with a microcavity structure in the latter method, the color purity can be further improved.

[0254] The light-emitting layer 4511 may also contain inorganic compounds such as quantum dots. For example, by using quantum dots for the light-emitting layer, they can also be used as light-emitting materials.

[0255] To prevent the intrusion of oxygen, hydrogen, moisture, carbon dioxide, etc. into the light-emitting element 4513, a protective layer may also be formed on the second electrode layer 4031 and the partition wall 4510. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), etc. can be formed. In addition, a filler 4514 is provided and sealed in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005. Thus, in order not to be exposed to external gases, it is preferable to use a highly airtight and low-degassing protective film (adhesive film, ultraviolet curable resin film, etc.), covering material for encapsulation (enclosure).

[0256] As the filler 4514, in addition to inert gases such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can also be used. For example, PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene-vinyl acetate) etc. can be used. The filler 4514 may also contain a desiccant.

[0257] As the sealant 4005, a glass material such as glass powder or a curable resin that cures at room temperature such as a two-component mixed resin, a photocurable resin, a thermosetting resin, etc. can be used. The sealant 4005 may also contain a desiccant.

[0258] In addition, as needed, optical films such as a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. may be appropriately provided on the light-emitting surface of the light-emitting element. In addition, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed, which is a treatment for reducing reflected glare by diffusing reflected light using irregularities on the surface.

[0259] By making the light-emitting element have a microcavity structure, light with high color purity can be extracted. In addition, by combining the microcavity structure and the color filter, reflection glare can be prevented, and the visibility of the image can be improved.

[0260] Regarding the first electrode layer and the second electrode layer (also referred to as the pixel electrode layer, common electrode layer, counter electrode layer, etc.) to which a voltage is applied to the display element, it is sufficient to select its light transmissivity and reflectivity according to the direction of the extracted light, the place where the electrode layer is provided, and the pattern structure of the electrode layer.

[0261] As the first electrode layer 4030 and the second electrode layer 4031, a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0262] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or their alloys or nitrides.

[0263] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers or their derivatives composed of two or more of aniline, pyrrole, and thiophene can be cited.

[0264] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably composed of a non-linear element.

[0265] Note that, as Figure 19 shown, a stacked structure in which a transistor and a capacitor include an overlapping region in the height direction can also be adopted. For example, by arranging the transistors 4011 and 4022 that constitute the drive circuit in an overlapping manner, a display device with a narrow bezel can be realized. In addition, by arranging the transistors 4010, 4023, the capacitor 4020, etc. that constitute the pixel circuit in such a way as to partially include an overlapping region, the aperture ratio and resolution can be improved. In addition, in Figure 19 shows an example of applying the stacked structure to the Figure 18A shown liquid crystal display device, but it can also be applied to the Figure 18B shown EL display device.

[0266] In addition, in the pixel circuit, a transparent conductive film having high light transmittance to visible light is used as the electrode and the wiring, which can improve the light transmittance in the pixel, and thus can substantially increase the aperture ratio. In addition, since the semiconductor layer also has light transmittance when using an OS transistor, the aperture ratio is further increased. This is also effective when a stacked structure is not adopted for transistors and the like.

[0267] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0268] (Embodiment 3)

[0269] In this embodiment, an example of a transistor that can be used instead of each transistor shown in the above embodiment will be described with reference to the drawings.

[0270] The display device according to one aspect of the present invention can be manufactured using various types of transistors such as bottom-gate transistors or top-gate transistors. Therefore, it is possible to easily correspond to the replacement of the semiconductor layer material or the transistor structure used in the existing production line.

[0271] <Bottom-gate transistor>

[0272] Figure 20A1 A cross-sectional view in the channel length direction of a channel protection type transistor 810, which is one of the bottom-gate transistors, is shown. In Figure 20A1 , the transistor 810 is formed on the substrate 771. In addition, the transistor 810 includes an electrode 746 on the substrate 771 with an insulating layer 772 interposed therebetween. In addition, a semiconductor layer 742 is included on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0273] In addition, an insulating layer 741 is included on the channel formation region of the semiconductor layer 742. In addition, an electrode 744a and an electrode 744b are included on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can be used as one of the source electrode and the drain electrode. The electrode 744b can be used as the other of the source electrode and the drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741.

[0274] The insulating layer 741 can be used as a channel protection layer. By providing the insulating layer 741 on the channel formation region, it is possible to prevent the semiconductor layer 742 from being exposed when forming the electrode 744a and the electrode 744b. Thereby, it is possible to prevent the channel formation region of the semiconductor layer 742 from being etched when forming the electrode 744a and the electrode 744b. According to one aspect of the present invention, a transistor with good electrical characteristics can be achieved.

[0275] In addition, the transistor 810 includes an insulating layer 728 over the electrode 744 a , the electrode 744 b , and the insulating layer 741 , and includes an insulating layer 729 over the insulating layer 728 .

[0276] When an oxide semiconductor is used for the semiconductor layer 742, a material that can remove oxygen from a portion of the semiconductor layer 742 to generate oxygen vacancies is preferably used for at least the portion of the electrode 744a and the electrode 744b that is in contact with the semiconductor layer 742. The carrier concentration in the region where the oxygen vacancies are generated in the semiconductor layer 742 increases, and the region is converted to n-type to become an n-type region (n + When an oxide semiconductor is used for the semiconductor layer 742, an example of a material that can remove oxygen from the semiconductor layer 742 to generate an oxygen vacancy may include tungsten, titanium, or the like.

[0277] By forming the source region and the drain region in the semiconductor layer 742, the contact resistance between the electrode 744a and the electrode 744b and the semiconductor layer 742 can be reduced. Therefore, the electrical characteristics of the transistor such as field effect mobility and threshold voltage can be improved.

[0278] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of a transistor.

[0279] The insulating layer 729 is preferably formed using a material having a function of preventing impurities from being diffused into the transistor from the outside or reducing diffusion of impurities. Alternatively, the insulating layer 729 may be omitted as necessary.

[0280] Figure 20A2 The transistor 811 shown in the figure is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0281] Generally speaking, the back gate electrode is formed using a conductive layer and is arranged in a manner that the channel forming region of the semiconductor layer is clamped by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0282] Both the electrode 746 and the electrode 723 can be used as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can all be used as gate insulating layers. Additionally, the electrode 723 can be disposed between the insulating layer 728 and the insulating layer 729.

[0283] Note that when one of the electrode 746 and the electrode 723 is referred to as the "gate electrode", the other is referred to as the "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as the "gate electrode", the electrode 746 is referred to as the "back gate electrode". Additionally, when the electrode 723 is used as the "gate electrode", the transistor 811 is a type of top-gate transistor. Furthermore, sometimes one of the electrode 746 and the electrode 723 is referred to as the "first gate electrode", and sometimes the other is referred to as the "second gate electrode".

[0284] By disposing the electrode 746 and the electrode 723 with the semiconductor layer 742 therebetween and setting the potentials of the electrode 746 and the electrode 723 to be the same, the region through which carriers flow in the semiconductor layer 742 expands more in the film thickness direction, so the amount of carrier movement increases. As a result, the on-state current of the transistor 811 increases, and the field-effect mobility also increases.

[0285] Therefore, the transistor 811 is a transistor having a large on-state current relative to the occupied area. That is, the occupied area of the transistor 811 can be reduced relative to the required on-state current. According to one aspect of the present invention, the occupied area of the transistor can be reduced. Therefore, according to one aspect of the present invention, a semiconductor device with high integration can be realized.

[0286] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they have the function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). Additionally, when the back gate electrode is formed larger than the semiconductor layer to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0287] In addition, by forming the back gate electrode using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Thereby, photo-degradation of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as threshold voltage drift of the transistor can be prevented.

[0288] According to one aspect of the present invention, a transistor with good reliability can be realized. Additionally, a semiconductor device with good reliability can be realized.

[0289] Figure 20B1 Shown in relation to Figure 20A1A cross-sectional view of a channel length direction of a channel protection transistor 820 having a different structure. The transistor 820 has a structure substantially the same as that of the transistor 810, except that the insulating layer 741 covers the end of the semiconductor layer 742. In the opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. In addition, in the other openings formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0290] Figure 20B2 The transistor 821 shown is different from the transistor 820 in that an electrode 723 which can be used as a back gate electrode is included on the insulating layer 729 .

[0291] By providing the insulating layer 741, exposure of the semiconductor layer 742 generated when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, the semiconductor layer 742 can be prevented from being thinned when the electrode 744a and the electrode 744b are formed.

[0292] In addition, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 of the transistor 820 and the transistor 821 are longer than those of the transistor 810 and the transistor 811. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with good electrical characteristics can be provided.

[0293] Figure 20C1 A cross-sectional view in the channel length direction of a channel-etched transistor 825, which is one of the bottom-gate transistors, is shown. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Therefore, a portion of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0294] Figure 20C2 The transistor 826 shown is different from the transistor 825 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729 .

[0295] Figure 21A1 , Figure 21A2 , Figure 21B1 , Figure 21B2 , Figure 21C1 and Figure 21C2A cross-sectional view in the channel width direction of transistors 810, 811, 820, 821, 825, and 826 is shown.

[0296] In Figure 21B2 and Figure 21C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0297] In the channel width direction, the lengths of the gate electrode and the back gate electrode are larger than that of the semiconductor layer 742, and the semiconductor layer 742 is entirely covered by the gate electrode or the back gate electrode with the insulating layers 726, 741, 728, and 729 interposed therebetween.

[0298] By adopting this structure, the semiconductor layer 742 included in the transistor can be electrostatically surrounded by the electric fields of the gate electrode and the back gate electrode.

[0299] A device structure of a transistor that electrostatically surrounds the semiconductor layer 742 forming a channel formation region by using the electric fields of the gate electrode and the back gate electrode, such as transistor 821 or transistor 826, can be referred to as a Surrounded channel (S-channel) structure.

[0300] By adopting the S-channel structure, an electric field for causing channel formation can be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and the back gate electrode. Thereby, the current driving ability of the transistor is improved, and thus higher on-state current characteristics can be obtained. Further, since the on-state current can be increased, the transistor can be miniaturized. In addition, by adopting the S-channel structure, the mechanical strength of the transistor can be improved.

[0301] <Top-gate transistor>

[0302] Figure 22A1 The illustrated transistor 842 is one of the top-gate transistors. The electrodes 744a and 744b are electrically connected to the semiconductor layer 742 through openings formed in the insulating layers 728 and 729.

[0303] In addition, a portion of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the impurity 755 is introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, thereby forming an impurity region in the semiconductor layer 742 in a self-aligned manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which the impurity 755 is introduced through the insulating layer 726 is lower than that of the region into which the impurity 755 is not introduced through the insulating layer 726. An LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0304] Figure 22A2 The transistor 843 shown is different from the transistor 842 in that it includes an electrode 723. The transistor 843 includes an electrode 723 formed on a substrate 771. The electrode 723 overlaps a region of the semiconductor layer 742 via an insulating layer 772. The electrode 723 can be used as a back gate electrode.

[0305] In addition, if Figure 22B1 The transistor 844 and Figure 22B2 As in the transistor 845 shown in FIG. 8 , the insulating layer 726 in the region not overlapping with the electrode 746 may be completely removed. Figure 22C1 The transistor 846 and Figure 22C2 As in the transistor 847 shown in the figure, the insulating layer 726 does not need to be removed.

[0306] In transistors 842 to 847, after forming electrode 746, impurity 755 may be introduced into semiconductor layer 742 using electrode 746 as a mask, thereby forming an impurity region in semiconductor layer 742 in a self-aligned manner. According to one embodiment of the present invention, a transistor with good electrical characteristics can be realized. In addition, according to one embodiment of the present invention, a semiconductor device with high integration can be realized.

[0307] Figure 23A1 , Figure 23A2 , Figure 23B1 , Figure 23B2 , Figure 23C1 and Figure 23C2 A cross-sectional view of transistors 842 , 843 , 844 , 845 , 846 , and 847 in the channel width direction is shown.

[0308] The transistor 843, the transistor 845, and the transistor 847 have the above-mentioned S-channel structure. However, the present invention is not limited to this, and the transistor 843, the transistor 845, and the transistor 847 may not have the S-channel structure.

[0309] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0310] (Embodiment 4)

[0311] Examples of electronic devices that can use a display device according to one aspect of the present invention include display devices, personal computers, image storage devices and image reproduction devices having a recording medium, mobile phones, game machines including portable game machines, portable data terminals, e-book readers, imaging devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. Figures 24A to 24F Specific examples of these electronic devices are shown.

[0312] Figure 24A This is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a speaker 967, a display unit 965, operation keys 966, a zoom button 968, a lens 969, etc. By using a display device according to one aspect of the present invention for the display unit 965, various images can be displayed.

[0313] Figure 24B This is a digital signage, which includes a large display unit 922. For example, it can be installed on the side of a pillar 921. By using a display device according to one aspect of the present invention for the display unit 922, a high-quality display can be performed.

[0314] Figure 24C This is a mobile phone, which includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations such as making a call or inputting text can be performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be used in a bent manner as shown in the figure. By using a display device according to one aspect of the present invention for the display unit 952, various images can be displayed.

[0315] Figure 24D This is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Data can be input or output by using the touch screen function of the display unit 912. By using a display device according to one aspect of the present invention for the display unit 912, various images can be displayed.

[0316] Figure 24EIt is a television set, which includes a housing 971, a display unit 973, operation keys 974, speakers 975, communication connection terminals 976, a photoelectric sensor 977, etc. The display unit 973 is provided with a touch sensor and can perform input operations. By using the display device according to one embodiment of the present invention for the display unit 973, various images can be displayed.

[0317] Figure 24F It is an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, a sensor 904, etc. The display unit 902 and the display unit 903 are composed of a single display panel and are flexible. In addition, the housing 901 is also flexible, so that the information processing terminal can be folded and used as shown in the attached drawings, and the information processing terminal can be used in a flat shape like a tablet terminal. The sensor 904 can detect the shape of the housing 901. For example, when the housing is bent, the display of the display unit 902 and the display unit 903 can be switched. By using the display device according to one embodiment of the present invention for the display unit 902 and the display unit 903, various images can be displayed.

[0318] This embodiment can be implemented by appropriately combining with the structures described in other embodiments, etc.

[0319] [Reference Signs]

[0320] 10: Pixel circuit, 10B: Sub-pixel circuit, 10G: Sub-pixel circuit, 10R: Sub-pixel circuit, 11: Pixel circuit, 13: Row driver, 14: Column driver, 15: Circuit, 16: Selection circuit, 17: Pixel array, 20: Shift register, 21: Buffer circuit, 22: Shift register, 23: Buffer circuit, 24: Sensor, 25: Circuit, 26B: Electrode, 26G: Electrode, 26R: Electrode, 31: Pixel, 31B: Sub-pixel, 31G: Sub-pixel, 31R: Sub-pixel, 101a: Transistor, 101b: Transistor, 103a: Transistor, 103b: Transistor, 104a: Capacitor, 104b: Capacitor, 110a: Circuit block, 110b: Circuit block, 111: Transistor, 112: Transistor, 113: Capacitor, 114: EL element, 115: Transistor, 116: Capacitor, 116a: Capacitor, 116b: Capacitor, 117: Liquid crystal element, 117a: Liquid crystal element, 117b: Liquid crystal element, 118: Transistor, 119: Transistor, 120: Circuit, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 128: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 132: Wiring, 133: Wiring, 134: Wiring, 215: Display unit, 221a: Scan line driving circuit, 231a: Signal line driving circuit, 232a: Signal line driving circuit, 241a: Common line driving circuit, 723: Electrode, 726: Insulating layer, 728: Insulating layer, 729: Insulating layer, 741: Insulating layer, 742: Semiconductor layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Insulating layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Display unit, 903: Display unit, 904: Sensor, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Column, 922: Display unit, 951: Housing, 952: Display unit, 953: Operation button, 954: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display unit, 966: Operation key, 967: Speaker, 968: Zoom button, 969: Lens, 971: Housing, 973: Display unit, 974: Operation key, 975: Speaker, 976: Communication connection terminal, 977: Optical sensor, 4001: Substrate, 4005: Sealant, 4006: Substrate,4008: Liquid crystal layer, 4010: Transistor, 4011: Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropic conductive layer, 4020: Capacitor, 4021: Electrode, 4030: Electrode layer, 4031: Electrode layer, 4032: Insulating layer, 4033: Insulating layer, 4035: Spacer, 4041: Printed circuit board, 4042: Integrated circuit, 4102: Insulating layer, 4103: Insulating layer, 4104: Insulating layer, 4110: Insulating layer, 4111: Insulating layer, 4112: Insulating layer, 4131: Coloring layer, 4132: Light-shielding layer, 4133: Insulating layer, 4200: Input device, 4210: Touch screen, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate, 4272b: FPC, 4273b: IC, 4510: Partition wall, 4511: Light-emitting layer, 4513: Light-emitting element, 4514: Filler.

Claims

1. A display device, comprising: a first pixel circuit; a second pixel circuit; a first wiring; a second wiring; a third wiring; a fourth wiring; a fifth wiring; a sixth wiring; and a seventh wiring, wherein, the first pixel circuit includes a first transistor, a second transistor, a first capacitor, and a first circuit block, the second pixel circuit includes a third transistor, a fourth transistor, a second capacitor, and a second circuit block, one of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor, the other electrode of the first capacitor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the second transistor is electrically connected to the first circuit block, one of the source and drain of the third transistor is electrically connected to one electrode of the second capacitor, the other electrode of the second capacitor is electrically connected to one of the source and drain of the fourth transistor, one of the source and drain of the fourth transistor is electrically connected to the second circuit block, the gates of the second transistor and the fourth transistor are electrically connected to the first wiring, the gate of the first transistor is electrically connected to the second wiring, the gate of the third transistor is electrically connected to the third wiring, the other of the source and drain of the second transistor is electrically connected to the fourth wiring, the other of the source and drain of the first transistor and the other of the source and drain of the third transistor are electrically connected to the fifth wiring, the other of the source and drain of the fourth transistor is electrically connected to the sixth wiring, the first circuit block includes a third capacitor and a first display element, the second circuit block includes a fourth capacitor and a second display element, one electrode of the first display element is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to the other electrode of the first capacitor, one electrode of the second display element is electrically connected to one electrode of the fourth capacitor, one electrode of the fourth capacitor is electrically connected to the other electrode of the second capacitor, and, the other electrode of the third capacitor and the other electrode of the fourth capacitor are electrically connected to the seventh wiring.

2. The display device according to claim 1, wherein the first circuit block includes a fifth transistor, the third capacitor, and a first liquid crystal element as the first display element, the second circuit block includes a sixth transistor, the fourth capacitor, and a second liquid crystal element as the second display element, one electrode of the first liquid crystal element is electrically connected to one electrode of the third capacitor, one electrode of the third capacitor is electrically connected to one of the source and drain of the fifth transistor, the other of the source and drain of the fifth transistor is electrically connected to the other electrode of the first capacitor, one electrode of the second liquid crystal element is electrically connected to one electrode of the fourth capacitor, one electrode of the fourth capacitor is electrically connected to one of the source and drain of the sixth transistor, And the other of the source and the drain of the sixth transistor is electrically connected to the other electrode of the second capacitor.

3. The display device according to claim 1, wherein the second transistor includes a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M, where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

4. An electronic device including the display device according to claim 1 and a camera.

Images