Computing circuits, chips and computing devices

Abstract

The present disclosure relates to an operation circuit, a chip and a computing device. An operation circuit is disclosed, comprising: a first plurality of registers, configured to form a plurality of stages, so that digital signals are sequentially transmitted along each stage of registers in the first plurality of registers; a plurality of combinational logic modules, wherein each stage of registers is coupled to a next stage of registers through a corresponding combinational logic module; a second plurality of registers, comprising a plurality of sub-sections corresponding to each combinational logic module, wherein each combinational logic module comprises a first sub-module, a second sub-module and a third sub-module, the second sub-module comprises an adder, the first sub-module and the third sub-module do not comprise an adder, and the first sub-module is coupled to the output of the first stage register and the input of the corresponding sub-section of the second plurality of registers, the second sub-module is coupled to the output of the corresponding sub-section and the input of the next stage register, and the third sub-module is coupled to the output of the first stage register and the input of the next stage register.

Description

Technical Field

[0001] The present disclosure relates to an operation circuit, a chip including the operation circuit, and a computing device including the chip. Background Art

[0002] Chip size, chip operating speed and chip power consumption are three crucial factors that determine chip performance. Among them, chip size determines chip cost, chip operating speed determines operating speed (i.e. computing power), and chip power consumption determines power consumption (i.e. cost). In practical applications, the most important performance indicator is the power consumption per unit computing power, i.e. the power consumption to computing power ratio.

[0003] Figure 1 The prior art operation circuit 100 is shown. The operation circuit 100 uses a pipeline structure to implement the SHA-256 algorithm.

[0004] like Figure 1 As shown, the operation circuit 100 includes a plurality of registers, which are configured to form a plurality of stages 111-1, 111-2, ..., 111-N, wherein the first stage register 111-1 includes registers 111-1a, 111-1b, ..., 111-1h, the second stage register 111-2 includes registers 111-2a, 111-2b, ..., 111-2h, the Nth stage register 111-N includes registers 111-Na, 111-Nb, ..., 111-Nh, etc. Digital signals are sequentially transmitted along the various stages of registers 111-1, 111-2, ..., 111-N.

[0005] The operation circuit 100 further includes a plurality of combinational logic modules 120 - 1 , 120 - 2 , ... Each level of register is coupled to the next level of register through a corresponding combinational logic module.

[0006] Each combinational logic module 120-1, 120-2, ... includes a first submodule 121-1, 121-2, ..., a second submodule 122-1, 122-2, ... and a third submodule 123-1, 123-2, ..., wherein the second submodule includes an adder, while the first submodule and the third submodule do not include an adder. Figure 1 In the embodiment, the second submodule 122 - 1 , 122 - 2 , . . . includes two adders 131 - 1 , 131 - 2 , . . . and 132 - 1 , 132 - 2 , . . .

[0007] like Figure 1As shown, in the first combinational logic module 120-1, the first submodule 121-1 is coupled to the output terminal of the first-level register 111-1 and the input terminal of the second submodule 122-1 including adders 131-1 and 132-1, the second submodule 122-1 (and the adders 131-1 and 132-1 therein) is coupled to the output terminal of the first submodule 121-1 and the input terminal of the second-level register 111-2, and the third submodule 123-1 is coupled to the output terminal of the first-level register 111-1 and the input terminal of the second-level register 111-2.

[0008] The output ends of the eight registers 111-1a, 111-1b, 111-1c, 111-1d, 111-1e, 111-1f, 111-1g, and 111-1h in the first-stage register 111-1 are all coupled to the input ends of the first submodule 121-1 and the third submodule 123-1 in the corresponding first combinational logic module 120-1.

[0009] The input ends of two registers 111-2a and 111-2e in the second-level register 111-2 are coupled to the output end of the second sub-module 122-1 in the corresponding first combinational logic module 120-1, and the other six registers 111-2b, 111-2c, 111-2d, 111-2f, 111-2g, and 111-2h are coupled to the output end of the third sub-module 123-1.

[0010] It should be noted that, for ease of understanding, Figure 1 The 8 registers in each level of registers (for example, the 8 registers 111-1a, 111-1b, 111-1c, 111-1d, 111-1e, 111-1f, 111-1g, 111-1h in the first level register 111-1) are numbered according to the SHA-256 algorithm. Figure 1 The arrangement order of some registers (eg, 111 - 1b to 111 - 1e) is appropriately adjusted.

[0011] However, this operation circuit 100 has certain defects. In the combinational logic module 120-1, the first submodule 121-1 including multiple combinational logics will cause glitches in the signal, and the adders 131-1 and 132-1 will cause the previously generated glitches in the signal to be transmitted to each bit, thereby further expanding the glitches in the signal. The glitches in the signal will cause invalid level flips, thereby generating unexpected additional power consumption. In other words, this will lead to a decrease in the power consumption and computing power ratio of the chip.

[0012] Figure 2Another operation circuit 200 of the prior art is shown. The operation circuit 200 also adopts a pipeline structure to implement the SHA-256 algorithm.

[0013] like Figure 2 As shown, the operation circuit 200 includes a plurality of registers, which are configured to form a plurality of stages 211-1, 211-2, ..., 211-M, wherein the first stage register 211-1 includes registers 211-1a, 211-1b, ..., 211-1h, the second stage register 211-2 includes registers 211-2a, 211-2b, ..., 211-2h, the Mth stage register 211-M includes registers 211-Ma, 211-Mb, ..., 211-Mh, etc. The digital signal is sequentially transmitted along the registers 211-1, 211-2, ..., 211-M at each stage.

[0014] The operation circuit 200 further includes a plurality of groups of combinational logic modules, each of which includes a first submodule 221 - 1 , a second submodule 222 - 2 and a third submodule 223 - 2 .

[0015] In each group of combinational logic modules, the second submodule 222-2 includes an adder, while the first submodule 221-1 and the third submodule 223-2 do not include an adder. Figure 2 In the embodiment, the second submodule 222-2 includes two adders 231-2 and 232-2.

[0016] like Figure 2 As shown, the first-level register 211-1 is coupled to the second-level register 211-2 through the first submodule 221-1 in the first group of combinational logic modules, and the second-level register 211-2 is coupled to the third-level register 211-3 through the second submodule 222-2 and the third submodule 223-2 in the first group of combinational logic modules.

[0017] The input end of the first sub-module 221-1 in the first group of combinational logic modules is coupled to the output ends of the eight registers 211-1a, 211-1b, 211-1c, 211-1d, 211-1e, 211-1f, 211-1g, and 211-1h in the first-level register 211-1, and the output end is coupled to the input ends of the eight registers 211-2a, 211-2b, 211-2c, 211-2d, 211-2e, 211-2f, 211-2g, and 211-2h in the second-level register 211-2.

[0018] The input end of the second submodule 222-2 in the first group of combinational logic modules is coupled to the output ends of two registers 211-2a, 211-2e in the second-level register 211-2, and the output end is coupled to the input ends of two registers 211-3a, 211-3e in the third-level register 211-3.

[0019] The input end of the third sub-module 223-2 in the first group of combinational logic modules is coupled to the output ends of the eight registers 211-2a, 211-2b, 211-2c, 211-2d, 211-2e, 211-2f, 211-2g, and 211-2h in the second-level register 211-2, and the output end is coupled to the input ends of the other six registers 211-3b, 211-3c, 211-3d, 211-3f, 211-3g, and 211-3h in the third-level register 211-3.

[0020] Figure 2 The M in the operation circuit 200 is Figure 1 In the operation circuit 100 of FIG. 1 , N indicates the number of stages of registers, that is, the number of stages of pipelines. For example, if the operation circuit 200 adopts a structure corresponding to the operation circuit 100, then M=2N.

[0021] In the operation circuit 200, the corresponding first-level register 211-2 inserted between the first submodule 221-1 and the second submodule 222-2 in each group of combinational logic modules can remove the burrs in the signal before the signal enters the adder 231-2, 232-2 in the second submodule 222-2, so that the burrs generated in the first submodule 221-1 including multiple combinational logics will not be further transmitted and amplified by the adder 231-2, 232-2. This reduces the power consumption of the chip and improves the power consumption and computing power ratio.

[0022] However, the number of registers required in the operation circuit 200 is twice that of the operation circuit 100, and the corresponding manufacturing cost is also twice that of the operation circuit 100. This leads to a significant increase in the manufacturing cost of the chip.

[0023] Therefore, it is expected to remove burrs and improve the power consumption and computing power ratio of the chip at a lower manufacturing cost, and thus an improved computing circuit is needed. Summary of the invention

[0024] According to one aspect of the present disclosure, there is provided an operation circuit, comprising: a first plurality of registers, configured to form a plurality of stages, so that a digital signal is transmitted in sequence along each stage of registers in the first plurality of registers; a plurality of combinational logic modules, wherein each stage of registers in the first plurality of registers is coupled to a next stage of registers through a corresponding combinational logic module; a second plurality of registers, wherein the second plurality of registers comprises a plurality of sub-portions corresponding to each combinational logic module, wherein each combinational logic module comprises a first sub-module, a second sub-module and a third sub-module, the second sub-module comprises at least one adder, the first sub-module and the third sub-module do not comprise an adder, and the first sub-module is coupled to an output terminal of a first-stage register in the first plurality of registers and an input terminal of a corresponding sub-portion of the second plurality of registers, the second sub-module is coupled to an output terminal of a corresponding sub-portion of the second plurality of registers and an input terminal of a next stage of register in the first plurality of registers, and the third sub-module is coupled to an output terminal of a first-stage register in the first plurality of registers and an input terminal of a next stage of register.

[0025] According to another aspect of the present disclosure, a chip is provided, which includes the computing circuit as described above.

[0026] According to yet another aspect of the present disclosure, a computing device is provided, which includes the chip as described above.

[0027] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0029] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0030] Figure 1 A conventional operation circuit is shown.

[0031] Figure 2 Another operation circuit in the prior art is shown.

[0032] Figure 3 A schematic diagram of an operation circuit according to one or more exemplary embodiments of the present disclosure is shown.

[0033] Figure 4A and Figure 4B An operation circuit and a corresponding clock according to the first embodiment of the present disclosure are respectively shown.

[0034] Figure 5Aand Figure 5B An operation circuit and a corresponding clock according to a second embodiment of the present disclosure are respectively shown.

[0035] Fig. 6A and Figure 6B An operation circuit and a corresponding clock according to a third embodiment of the present disclosure are respectively shown.

[0036] Fig. 7A and Figure 7B An operation circuit and a corresponding clock according to a fourth embodiment of the present disclosure are respectively shown.

[0037] Note that in the embodiments described below, sometimes the same reference numerals are used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In some cases, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0038] For ease of understanding, the position, size, range, etc. of each structure shown in the drawings and the like may not represent the actual position, size, range, etc. Therefore, the present disclosure is not limited to the position, size, range, etc. disclosed in the drawings and the like. DETAILED DESCRIPTION

[0039] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0040] The following description of at least one exemplary embodiment is in fact merely illustrative and is in no way intended to limit the present disclosure and its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will appreciate that they merely illustrate exemplary ways of the present disclosure that can be implemented, rather than exhaustive ways. In addition, the drawings need not be drawn to scale, and some features may be enlarged to illustrate the details of specific components.

[0041] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.

[0042] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0043] Figure 3FIG. 3 is a schematic diagram of an operation circuit 300 according to one or more exemplary embodiments of the present disclosure. The operation circuit 300 adopts a pipeline structure to implement the SHA-256 algorithm.

[0044] like Figure 3 As shown, the operation circuit 300 includes a first plurality of registers, a second plurality of registers, and a plurality of combinational logic modules.

[0045] The first plurality of registers are configured to form a plurality of stages 311 - 1 , 311 - 2 , . . . , 311 -N, and the digital signal is sequentially transmitted along each stage of the registers 311 - 1 , 311 - 2 , . . . , 311 -N.

[0046] exist Figure 3 In the illustrated embodiment, the first level register 311-1 includes registers 311-1a, 311-1b, ..., 311-1h, the second level register 311-2 includes registers 311-2a, 311-2b, ..., 311-2h, the Nth level register 311-N includes registers 311-Na, 311-Nb, ..., 311-Nh, and so on.

[0047] It should be understood by those skilled in the art that the number of registers in each level of registers is not limited to Figure 3 The embodiment shown in the figure can appropriately determine the number of registers in each level of registers according to the requirements of the chip and the algorithm.

[0048] It should be noted that, for ease of understanding, Figure 3 The 8 registers in each level of registers (for example, the 8 registers 311-1a, 311-1b, 311-1c, 311-1d, 311-1e, 311-1f, 311-1g, 311-1h in the first level register 311-1) are numbered according to the SHA-256 algorithm. Figure 3 The arrangement order of some registers (eg, 311 - 1 b to 311 - 1 e) is appropriately adjusted.

[0049] like Figure 3 As shown, each level of registers is coupled to the next level of registers through corresponding combinational logic modules 320 - 1 , 320 - 2 , ... For example, the first level register 311 - 1 is coupled to the second level register 311 - 2 through the first combinational logic module 320 - 1 .

[0050] Each combinational logic module 320-1, 320-2, ... includes a first submodule 321-1, 321-2, ..., a second submodule 322-1, 322-2, ... and a third submodule 323-1, 323-2, ..., wherein the second submodule 322-1, 322-2, ... includes an adder, while the first submodule 321-1, 321-2, ... and the third submodule 323-1, 323-2, ... do not include an adder.

[0051] exist Figure 3 In the illustrated embodiment, the second submodule 322-1 of the first combinatorial logic module 320-1 includes adders 331-1, 332-1, the second submodule 322-2 of the second combinatorial logic module 320-2 includes adders 331-2, 332-2, and so on.

[0052] Those skilled in the art should understand that the number of adders in the second submodule of each combinational logic module is not limited to Figure 3 The embodiment shown in the figure can appropriately determine the number of adders in the second submodule of each combinational logic module according to the requirements of the algorithm.

[0053] The second plurality of registers includes a plurality of sub-sections 312-1, 312-2, ... corresponding to each of the combinational logic modules 320-1, 320-2, .... Figure 3 In the illustrated embodiment, a first subsection 312-1 of the second plurality of registers includes registers 312-1a, 312-1b, 312-1c, 312-1d, and a second subsection 312-2 includes registers 312-2a, 312-2b, 312-2c, 312-2d, and so on.

[0054] like Figure 3 As shown, in the first combinational logic module 320-1, the first submodule 321-1 is coupled to the output of the first-level register 311-1 and the input of the first subsection 312-1 of the second plurality of registers, the second submodule 322-1 (and the adders 331-1, 332-1 therein) is coupled to the output of the first subsection 312-1 of the second plurality of registers and the input of the second-level register 311-2, and the third submodule 323-1 is coupled to the output of the first-level register 311-1 and the input of the second-level register 311-2.

[0055] It should be understood by those skilled in the art that the number and configuration of registers in each subsection of the second plurality of registers is not limited to Figure 3 In a preferred embodiment, the number and configuration of registers in each sub-portion of the second plurality of registers can be appropriately determined according to the number of adders in the second sub-module of each combinatorial logic module.

[0056] In a preferred embodiment, the input of each adder in the second submodule of each combinatorial logic module is coupled to the output of two registers in the corresponding subsection of the second plurality of registers. Figure 3 In the illustrated embodiment, the first adder 331-1 in the second submodule 322-1 of the first combinatorial logic module 320-1 is coupled to the registers 312-1a and 312-1b in the first subsection 312-1 of the second plurality of registers, and the second adder 332-1 is coupled to the registers 312-1c and 312-1d. More specifically, in a preferred embodiment, the sum input of the adder 331-1 can be coupled to the register 312-1a, the carry input can be coupled to the register 312-1b, and the sum input of the adder 332-1 can be coupled to the register 312-1c, and the carry input can be coupled to the register 312-1d.

[0057] exist Figure 3 In the illustrated embodiment, in the second-level register 311-2, the input ends of a portion of the registers 311-2a, 311-2e are coupled to the output end of the second sub-module 322-1 in the corresponding first combinational logic module 320-1, while the input ends of the other registers 311-2b, 311-2c, 311-2d, 311-2f, 311-2g, 311-2h are coupled to the output end of the third sub-module 323-1.

[0058] In a preferred embodiment, for the second submodule in each combinational logic module, the output end of each adder therein is respectively coupled to a register in the corresponding next-level register. Figure 3 In the illustrated embodiment, output terminals of two adders 331 - 1 and 332 - 1 in the second submodule 322 - 1 in the first combinatorial logic module 320 - 1 are respectively coupled to two registers 311 - 2 a and 311 - 2 e in the second-stage register 311 - 2 .

[0059] In the operation circuit 300, the signal output by the first submodule of each combinational logic module is transmitted to the corresponding adder of the second submodule via the corresponding subpart of the second plurality of registers. Thus, the burrs in the signal generated by the first submodule including multiple combinational logics are removed at the corresponding subpart of the second plurality of registers, and then the burred signal is transmitted to the adder in the second submodule. This can effectively filter the burrs in the signal, reduce the additional power consumption caused by the burrs, and thus improve the power consumption and computing power ratio of the chip.

[0060] In addition, compared with the operation circuit 200 in the prior art, the number of registers added in the operation circuit 300 is greatly reduced, which greatly reduces the manufacturing cost of the operation circuit 300, thereby achieving substantially the same glitch filtering effect at a lower manufacturing cost.

[0061] The clock for each of the first and second pluralities of registers may be appropriately set according to the needs of the operational circuitry and the algorithm.

[0062] The frequency of the clock used for each register in the first plurality of registers and the second plurality of registers may be the same. In a preferred embodiment, the duty cycle of the clock used for each register in the first plurality of registers and the second plurality of registers is also the same.

[0063] In a preferred embodiment, the clock for the first plurality of registers and the clock for the second plurality of registers may be generated by the same clock, or may be generated by each other. For example, the clock for the second plurality of registers may be generated by phase shifting, inverting, etc., of the clock for the first plurality of registers, or vice versa.

[0064] For each register in the first plurality of registers and the second plurality of registers, when the register is triggered, the signal at its input terminal should have been stable and can be passed back by the register. However, the operation in the combinational logic module requires a certain calculation delay, and the operation of the register also requires a certain register delay (for example, Ck2q delay when the register is a latch). For example, the calculation delay of each combinational logic module is on the order of hundreds to thousands of picoseconds. The period, frequency and duty cycle of the clock for each register can be determined based on the calculation delay of the combinational logic module and its submodules, so that the clock is set to properly trigger the register while ensuring that the signal at the register input terminal is stable.

[0065] The period of the clock used for each register should be greater than or equal to the delay required for the signal to be transmitted between the two-stage registers. Generally speaking, in the operation circuit 300, the calculation delay of the third submodule of the combinational logic module is much smaller than the calculation delay of the first submodule and the second submodule, and the register delay of the second plurality of registers is much smaller than the calculation delay of the first submodule and the second submodule. Therefore, the delay required for the signal to be transmitted between the two-stage registers is substantially equal to the calculation delay of each combinational logic module, and substantially equal to the sum of the calculation delays of the first submodule and the second submodule.

[0066] Therefore, the period and frequency of the clock for each register can be determined according to the calculation delay of the combinatorial logic module, that is, according to the sum of the calculation delays of the first submodule and the second submodule of the combinatorial logic module. In a preferred embodiment, the period of the clock for each register can be substantially equal to the sum of the calculation delays of the first submodule and the second submodule of the combinatorial logic module.

[0067] In a further preferred embodiment, the duty cycle of the clock for each register may be determined according to the ratio of the computational delays of the first submodule and the second submodule of each combinatorial logic module. The duty cycle of the clock for each register may be substantially equal to the ratio of the computational delays of the first submodule and the second submodule of each combinatorial logic module, or substantially equal to the inverse of the ratio.

[0068] It should be noted that the expression "substantially equal" herein means that the two are roughly equal, but not necessarily strictly and precisely equal. Those skilled in the art should understand that this is in line with technical principles and engineering practices. For example, the two may differ by about 5% or about 10%. In some contexts, the two may differ by about 15% or about 20%.

[0069] In particular, the period and duty cycle of the clock for the first plurality of registers and the second plurality of registers can be set as above, so that when the combinational logic operation in the first submodule is completed, the level of the clock for the second plurality of registers is flipped to trigger the second plurality of registers. The second plurality of registers can be implemented as edge-triggered registers or level-triggered registers. In the case where the second plurality of registers are edge-triggered registers (e.g., D-type flip-flops), the corresponding edge (rising edge or falling edge) of the clock triggers the second plurality of registers. In the case where the second plurality of registers are level-triggered registers (e.g., latches), the level of the clock is flipped to a corresponding level (high level or low level) so that the second plurality of registers enter an active state (e.g., a penetration state of a latch).

[0070] The implementation of the combinatorial logic module can be adjusted to adjust the calculation delay of the combinatorial logic module and its submodules. More specifically, the implementation of the first submodule and the second submodule of each combinatorial logic module can be adjusted to adjust the duration and / or ratio of its calculation delay.

[0071] In a preferred embodiment, the first submodule and the second submodule of each combinational logic module can be implemented so that the sum of their calculation delays is minimized, and the period of the clock used for each register can be correspondingly set to be substantially equal to the sum of the calculation delays of the first submodule and the second submodule, and the duty cycle is set to be substantially equal to the ratio of the calculation delays of the first submodule and the second submodule or its inverse. This makes it possible to minimize the period of the clock used for each register, thereby increasing the clock frequency, and thus increasing the computing power consumption ratio of the chip.

[0072] In another preferred embodiment, the first submodule and the second submodule of each combinational logic module can be implemented so that their calculation delays are substantially equal, and the period of the clock used for each register can be correspondingly set to be substantially equal to the sum of the calculation delays of the first submodule and the second submodule, and the duty cycle is set to be substantially equal to 1:1. In another preferred embodiment, the first submodule and the second submodule of each combinational logic module can be implemented so that the larger calculation delay of the two calculation delays is minimized, and the period of the clock used for each register can be correspondingly set to be substantially equal to twice the larger calculation delay, and the duty cycle is set to be substantially equal to 1:1. This is conducive to easily obtaining the clock and reducing the requirements for the accuracy of the clock duty cycle, thereby helping to ensure the stability of chip performance.

[0073] Figure 4A The operation circuit 400 according to the first embodiment of the present disclosure is shown. Similar to the operation circuit 300, the operation circuit 400 includes a first plurality of registers, a second plurality of registers, and a plurality of combinational logic modules.

[0074] exist Figure 4A In the first embodiment shown, the first plurality of registers are implemented by D-type flip-flops and the second plurality of registers are implemented by latches.

[0075] The first plurality of registers are configured to form a plurality of stages 411-1, 411-2, ..., and the digital signal is sequentially transmitted along each stage of the registers 411-1, 411-2, .... Figure 4A In the illustrated embodiment, the first level register 411 - 1 includes registers 411 - 1 a , 411 - 1 b , . . . , 411 - 1 h , and the second level register 411 - 2 includes registers 411 - 2 a , 411 - 2 b , . . . , 411 - 2 h , and so on.

[0076] The second plurality of registers includes a plurality of subdivisions 412-1. Figure 4A In the illustrated embodiment, the first sub-portion 412 - 1 of the second plurality of registers includes registers 412 - 1 a , 412 - 1 b , 412 - 1 c , and 412 - 1 d .

[0077] Each combinational logic module includes a first submodule 421-1, a second submodule 422-1 and a third submodule 423-1, wherein the second submodule 422-1 includes adders 431-1, 432-1, while the first submodule 421-1 and the third submodule 423-1 do not include adders.

[0078] Figure 4B Shown with Figure 4A The operation circuit 400 of the first embodiment shown corresponds to a first clock CLK401 for a first plurality of registers and a second clock CLK402 for a second plurality of registers.

[0079] exist Figure 4B In the preferred embodiment shown, the clock for each register in the first plurality of registers is the same, and the clock for each register in the second plurality of registers is also the same. However, this does not necessarily mean that the clock for each register in the first plurality of registers is derived from the same clock, nor does it necessarily mean that the clock for each register in the second plurality of registers is derived from the same clock. On the contrary, they can be derived from different clocks.

[0080] In one example, the first plurality of registers are rising edge triggered D-type flip-flops, and the second plurality of registers are high level triggered latches. Figure 4B The first clock CLK401 and the second clock CLK402 are schematically shown in FIG.

[0081] The following takes the first-stage register 411 - 1 , the first sub-portion 412 - 1 of the second plurality of registers, and the first combinational logic module as examples to exemplarily describe the operation of the operation circuit 400 driven by the first clock CLK401 and the second clock CLK402 .

[0082] At a rising edge of the first clock CLK401, the first plurality of registers are triggered, and the first-stage register 411-1 transmits the signal to the first submodule 421-1 and the third submodule 423-1. In the first submodule 421-1, the signal undergoes a variety of combinational logic operations and is then transmitted to the input end of the first subsection 412-1 of the second plurality of registers. During this period, the second clock CLK402 is at a low level, so that the second plurality of registers is in an inactive state, i.e., a blocking state. At this time, the first subsection 412-1 of the second plurality of registers will not transmit the signal from the first submodule 421-1 to the second submodule 422-1.

[0083] Afterwards, when the second clock CLK402 is converted from a low level to a high level, the second plurality of registers enters an active state, i.e., a penetration state. Thus, the first subsection 412-1 of the second plurality of registers transmits the signal from the first submodule 421-1 to the second submodule 422-1. In the second submodule 422-1, the signal is added by adders 431-1 and 432-1, and then transmitted to the input end of the second-stage register 411-2 in the first plurality of registers.

[0084] Afterwards, at the next rising edge of the first clock CLK401, the first plurality of registers are triggered again, and the second-stage register 411-2 transmits the signal to the second combinational logic module (not shown). At this time, the second clock CLK402 is at a low level, so that the second plurality of registers are inactive.

[0085] The first clock CLK401 and the second clock CLK402 are set so that, for each cycle of the first clock CLK401 and the second clock CLK402 , at a rising edge of the first clock CLK401 , the second clock CLK402 is at a low level.

[0086] The first clock CLK401 and the second clock CLK402 can be set so that for each clock cycle, the time from the rising edge of the first clock CLK401 to the second clock CLK402 from the low level to the high level is greater than or equal to the calculation delay of the first submodule of each combinational logic module. This ensures that when the combinational logic operation in the first submodule is not completed, the second plurality of registers is in an inactive state. That is, when each subsection 412-1 of the second plurality of registers enters the active state, the data at its input end (i.e., the output end of the corresponding first submodule 421-1) is already stable and can be passed to the second submodule 422-1 for further operation.

[0087] exist Figure 4B In the preferred embodiment shown, the first clock CLK401 and the second clock CLK402 have the same frequency, a phase difference of 180 degrees, and a duty cycle of 1: 1. Such a first clock CLK401 and a second clock CLK402 can be easily obtained. For example, the second clock CLK402 can be obtained by inverting or shifting the first clock CLK401 by 180 degrees.

[0088] Those skilled in the art should understand that in the case where the first plurality of registers are falling edge triggered D-type flip-flops and / or the second plurality of registers are low level triggered latches, the first clock CLK401 and the second clock CLK402 may be adjusted accordingly.

[0089] Figure 5AAn operation circuit 500 according to a second embodiment of the present disclosure is shown. Similar to the operation circuit 300, the operation circuit 500 includes a first plurality of registers, a second plurality of registers, and a plurality of combinational logic modules.

[0090] exist Figure 5A In the second embodiment shown, both the first plurality of registers and the second plurality of registers are implemented by D-type flip-flops, and their triggering edges are different.

[0091] The first plurality of registers are configured to form a plurality of stages 511-1, 511-2, ..., and the digital signal is sequentially transmitted along each stage of the registers 511-1, 511-2, .... Figure 5A In the illustrated embodiment, the first level register 511 - 1 includes registers 511 - 1 a , 511 - 1 b , . . . , 511 - 1 h , and the second level register 511 - 2 includes registers 511 - 2 a , 511 - 2 b , . . . , 511 - 2 h , and so on.

[0092] The second plurality of registers includes a plurality of subdivisions 512-1. Figure 5A In the illustrated embodiment, the first sub-portion 512 - 1 of the second plurality of registers includes registers 512 - 1 a , 512 - 1 b , 512 - 1 c , and 512 - 1 d .

[0093] Each combinational logic module includes a first submodule 521-1, a second submodule 522-1 and a third submodule 523-1, wherein the second submodule 522-1 includes adders 531-1, 532-1, while the first submodule 521-1 and the third submodule 523-1 do not include adders.

[0094] Figure 5B Shown with Figure 5A The arithmetic circuit 500 of the second embodiment shown corresponds to a first clock CLK501 for the first plurality of registers and a second clock CLK502 for the second plurality of registers. Similarly, the clock for each register in the first plurality of registers and the clock for each register in the second plurality of registers do not necessarily originate from the same clock.

[0095] In one example, the first plurality of registers are rising edge triggered D type flip-flops, and the second plurality of registers are falling edge triggered D type flip-flops. Figure 5B The first clock CLK501 and the second clock CLK502 are schematically shown in FIG.

[0096] The following takes the first-stage register 511 - 1 , the first sub-portion 512 - 1 of the second plurality of registers, and the first combinational logic module as examples to exemplarily describe the operation of the operation circuit 500 driven by the first clock CLK501 and the second clock CLK502 .

[0097] At a rising edge of the first clock CLK501 , the first plurality of registers are triggered, and the first stage register 511 - 1 transmits the signal to the first submodule 521 - 1 , and then to the input end of the first subsection 512 - 1 of the second plurality of registers.

[0098] Afterwards, at a falling edge of the second clock CLK502, the second plurality of registers are triggered, and the first subsection 512-1 of the second plurality of registers transmits the signal from the first submodule 521-1 to the second submodule 522-1, and further to the input end of the second stage register 511-2 in the first plurality of registers.

[0099] Afterwards, at the next rising edge of the first clock CLK501 , the first plurality of registers are triggered again, and the second-stage register 511 - 2 transmits the signal to the second combinational logic module (not shown).

[0100] The first clock CLK501 and the second clock CLK502 may be set so that for each cycle of the first clock CLK501 and the second clock CLK502, the duration of the low level may be greater than or equal to the calculation delay of the first submodule of each combinational logic module. For example, for the first clock CLK501 and the second clock CLK502 with a duty cycle of 1:1, their half cycle may be greater than or equal to the calculation delay of the first submodule of each combinational logic module.

[0101] exist Figure 5B In the preferred embodiment shown, the first clock CLK501 and the second clock CLK502 are the same, and the duty ratio is 1: 1. This can further simplify the implementation of the first clock CLK501 and the second clock CLK502.

[0102] It should be noted that the first clock CLK501 and the second clock CLK502 being the same does not necessarily mean that the first clock CLK501 for the first plurality of registers and the second clock CLK502 for the second plurality of registers are derived from the same clock. On the contrary, they may be derived from different clocks.

[0103] Those skilled in the art should understand that in the case where the first plurality of registers are falling edge triggered D type flip-flops and the second plurality of registers are rising edge triggered D type flip-flops, the first clock CLK501 and the second clock CLK502 may be adjusted accordingly.

[0104] Fig. 6A An operation circuit 600 according to a third embodiment of the present disclosure is shown. Similar to the operation circuit 300, the operation circuit 600 includes a first plurality of registers, a second plurality of registers, and a plurality of combinational logic modules.

[0105] exist Fig. 6A In the third embodiment shown, both the first plurality of registers and the second plurality of registers are implemented by D-type flip-flops, and their triggering edges are the same.

[0106] The first plurality of registers are configured to form a plurality of stages 611-1, 611-2, ..., and the digital signal is sequentially transmitted along each stage of the registers 611-1, 611-2, .... Fig. 6A In the illustrated embodiment, the first level register 611 - 1 includes registers 611 - 1 a , 611 - 1 b , . . . , 611 - 1 h , and the second level register 611 - 2 includes registers 611 - 2 a , 611 - 2 b , . . . , 611 - 2 h , and so on.

[0107] The second plurality of registers includes a plurality of subdivisions 612-1. Fig. 6A In the illustrated embodiment, the first sub-portion 612 - 1 of the second plurality of registers includes registers 612 - 1 a , 612 - 1 b , 612 - 1 c , and 612 - 1 d .

[0108] Each combinational logic module includes a first submodule 621-1, a second submodule 622-1 and a third submodule 623-1, wherein the second submodule 622-1 includes adders 631-1, 632-1, while the first submodule 621-1 and the third submodule 623-1 do not include adders.

[0109] Figure 6B Shown with Fig. 6A The arithmetic circuit 600 of the third embodiment shown corresponds to a first clock CLK601 for the first plurality of registers and a second clock CLK602 for the second plurality of registers. Similarly, the clock for each register in the first plurality of registers and the clock for each register in the second plurality of registers do not necessarily originate from the same clock.

[0110] In one example, the first plurality of registers and the second plurality of registers are both rising edge triggered D-type flip-flops. Figure 6B The first clock CLK601 and the second clock CLK602 are schematically shown in FIG.

[0111] The following takes the first-stage register 611 - 1 , the first sub-portion 612 - 1 of the second plurality of registers, and the first combinational logic module as examples to exemplarily describe the operation of the operation circuit 600 driven by the first clock CLK601 and the second clock CLK602 .

[0112] At a rising edge of the first clock CLK601, the first plurality of registers are triggered, and the first stage register 611-1 transmits the signal to the first submodule 621-1, and then to the input end of the first subsection 612-1 of the second plurality of registers.

[0113] Afterwards, at the rising edge of the second clock CLK602, the second plurality of registers are triggered, and the first subsection 612-1 of the second plurality of registers transmits the signal from the first submodule 621-1 to the second submodule 622-1, and further to the input end of the second stage register 611-2 in the first plurality of registers.

[0114] Afterwards, at the next rising edge of the first clock CLK601 , the first plurality of registers are triggered again, and the second-stage register 611 - 2 transfers the signal to the second combinational logic module (not shown).

[0115] The first clock CLK601 and the second clock CLK602 may be set so that for each cycle of the first clock CLK601 and the second clock CLK602 , the time from the rising edge of the first clock CLK601 to the rising edge of the second clock CLK602 is greater than or equal to the calculation delay of the first submodule of each combinational logic module.

[0116] exist Figure 6B In the preferred embodiment shown, the first clock CLK601 and the second clock CLK602 have the same frequency, a phase difference of 180 degrees, and a duty cycle of 1:1.

[0117] Those skilled in the art should understand that in the case where both the first plurality of registers and the second plurality of registers are falling-edge-triggered D-type flip-flops, the first clock CLK601 and the second clock CLK602 may be adjusted accordingly.

[0118] Fig. 7A An operation circuit 700 according to a fourth embodiment of the present disclosure is shown. Similar to the operation circuit 300, the operation circuit 700 includes a first plurality of registers, a second plurality of registers, and a plurality of combinational logic modules.

[0119] exist Fig. 7A In the fourth embodiment shown, both the first plurality of registers and the second plurality of registers are implemented by D-type flip-flops, and their triggering edges are the same.

[0120] The first plurality of registers are configured to form a plurality of stages 711-1, 711-2, ..., and the digital signal is sequentially transmitted along each stage of the registers 711-1, 711-2, .... Fig. 7A In the illustrated embodiment, the first level register 711 - 1 includes registers 711 - 1 a , 711 - 1 b , . . . , 711 - 1 h , and the second level register 711 - 2 includes registers 711 - 2 a , 711 - 2 b , . . . , 711 - 2 h , and so on.

[0121] The second plurality of registers includes a plurality of subdivisions 712-1. Fig. 7A In the illustrated embodiment, the first sub-portion 712 - 1 of the second plurality of registers includes registers 712 - 1 a , 712 - 1 b , 712 - 1 c , and 712 - 1 d .

[0122] Each combinational logic module includes a first submodule 721-1, a second submodule 722-1 and a third submodule 723-1, wherein the second submodule 722-1 includes adders 731-1, 732-1, while the first submodule 721-1 and the third submodule 723-1 do not include adders.

[0123] Figure 7B Shown with Fig. 7A The operation circuit 700 of the fourth embodiment shown corresponds to a first clock CLK701 for a register in the first plurality of registers coupled to the output end of the second sub-module, a second clock CLK702 for the second plurality of registers, and a third clock CLK703 for a register in the first plurality of registers coupled to the output end of the third sub-module, wherein the third clock CLK703 is the same as the second clock CLK702.

[0124] For example, the first clock CLK701 is a clock for registers 711-1a, 711-2a, ..., 711-1e, 711-2e, ..., and the third clock CLK703 is a clock for registers 711-1b, 711-2b, ..., 711-1c, 711-2c, ..., 711-1h, 711-2h, ...

[0125] Similarly, the third clock CLK703 being the same as the second clock CLK702 does not necessarily mean that the third clock CLK703 for the registers of the first plurality of registers coupled to the output terminal of the third submodule and the second clock CLK702 for the second plurality of registers are derived from the same clock. On the contrary, they may be derived from different clocks. In addition, the clock for each register of the first plurality of registers coupled to the output terminal of the second submodule, the clock for each register of the second plurality of registers, and the clock for each register of the first plurality of registers coupled to the output terminal of the third submodule are not necessarily derived from the same clock.

[0126] In one example, the first plurality of registers and the second plurality of registers are both rising edge triggered D-type flip-flops. Figure 7B Schematically shows a first clock CLK701, a second clock CLK702 and a third clock CLK703.

[0127] The following takes the first-level register 711-1, the second-level register 711-2, the first sub-part 712-1 of the second plurality of registers and the first combinational logic module as examples to exemplarily describe the operation of the operation circuit 700 driven by the first clock CLK701, the second clock CLK702 and the third clock CLK703.

[0128] At a rising edge of the third clock CLK703, a portion of the registers 711-1b, 711-1c, ..., 711-1h in the first-stage register 711-1 is triggered to transmit signals to the input terminals of the first submodule 721-1 and the third submodule 723-1.

[0129] Afterwards, at the rising edge of the first clock CLK701, another part of the registers 711-1a and 711-1e in the first-stage register 711-1 are triggered to pass the signal to the input end of the first submodule 721-1 and the third submodule 723-1. Thus, the signals from all the registers 711-1a, 711-1b, ..., 711-1h in the first-stage register 711-1 are passed to the input end of the first submodule 721-1 and the third submodule 723-1. Furthermore, the signal from the first-stage register 711-1 at the input end of the first submodule 721-1 is passed to the input end of the first subsection 712-1 of the second plurality of registers through the first submodule 721-1. Furthermore, the signal from the first-stage register 711 - 1 at the input end of the third submodule 723 - 1 is transmitted to the input ends of a portion of the registers 711 - 2 b, 711 - 2 c, ..., 711 - 2 h in the second-stage register 711 - 2 through the third submodule 723 - 1 .

[0130] Afterwards, at the rising edge of the second clock CLK702, the second plurality of registers are triggered, so that the first sub-portion 712-1 of the second plurality of registers passes the signal from the first sub-module 721-1 to the second sub-module 722-1, and then to the input end of another part of the registers 711-2a and 711-2e in the second-level register 711-2.

[0131] At this time, at the next rising edge of the third clock CLK703, a part of the registers 711-2b, 711-2c, ..., 711-2h in the second-level registers are triggered to transmit signals to the first submodule and the third submodule (not shown) in the corresponding second combinational logic module.

[0132] The first clock CLK701 , the second clock CLK702 , and the third clock CLK703 may be set so that for each clock cycle, the time from the rising edge of the first clock CLK701 to the rising edge of the second clock CLK702 is greater than or equal to the calculation delay of the first submodule of each combinatorial logic module.

[0133] exist Figure 7B In the preferred embodiment shown, the second clock CLK702 and the third clock CLK703 are the same, while the first clock CLK701 and the second clock CLK702 have the same frequency and a phase difference of 180 degrees. In this preferred embodiment, the duty ratio of the first clock CLK701, the second clock CLK702 and the third clock CLK703 is 1:1. Those skilled in the art should understand that the first clock CLK701, the second clock CLK702 and the third clock CLK703 can also be appropriately set in other ways.

[0134] Those skilled in the art should understand that the first plurality of registers and the second plurality of registers can be appropriately implemented as other types of registers (for example, the first plurality of registers and the second plurality of registers are both falling edge triggered D type flip-flops). In such a case, the first clock CLK701, the second clock CLK702 and the third clock CLK703 can be adjusted accordingly.

[0135] The operation circuit according to the present disclosure may be implemented in various appropriate ways, such as software, hardware, a combination of software and hardware, etc. In one implementation, a chip may include the operation circuit as described above, and the chip may also be included in a computing device.

[0136] The words "front", "rear", "top", "bottom", "above", "below", etc., if present, in the specification and claims are used for descriptive purposes and are not necessarily used to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances, such that the embodiments of the disclosure described herein, for example, are capable of operation in other orientations than those illustrated or otherwise described herein.

[0137] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be exactly copied. Any implementation described as an example herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the present disclosure is not limited by any expressed or implied theory given in the above technical field, background technology, summary of the invention, or detailed description.

[0138] As used herein, the term "substantially" is intended to include any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0139] In addition, the foregoing description may have referred to elements or nodes or features that are "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connection" means that one element / node / feature is directly connected (or directly communicates) with another element / node / feature electrically, mechanically, logically or otherwise. Similarly, unless otherwise expressly stated, "coupling" means that one element / node / feature can be mechanically, electrically, logically or otherwise connected to another element / node / feature in a direct or indirect manner to allow interaction, even if the two features may not be directly connected. In other words, "coupling" is intended to include direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0140] In addition, the terms "first", "second" and the like may also be used herein for reference purposes only, and thus are not intended to be limiting. For example, the terms "first", "second" and other such numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0141] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0142] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0143] Those skilled in the art will appreciate that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed in additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of specific operations, and the order of operations may be changed in other various embodiments. However, other modifications, variations, and replacements are equally possible. Therefore, this specification and accompanying drawings should be considered illustrative, not restrictive.

[0144] Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. It should also be understood by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A computing circuit, characterized in that: The operation circuit comprises: a first plurality of registers configured to form a plurality of stages such that the digital signal is sequentially transmitted along each stage of the first plurality of registers; a plurality of combinational logic modules, wherein each level of registers in the first plurality of registers is coupled to a next level of registers through a corresponding combinational logic module; a second plurality of registers, the second plurality of registers comprising a plurality of sub-divisions corresponding to each combinatorial logic module, Each combinational logic module includes a first submodule, a second submodule and a third submodule, the second submodule includes at least one adder, the first submodule and the third submodule do not include an adder, and The first submodule is coupled to the output end of a first-level register among the first plurality of registers and the input end of a corresponding sub-part of the second plurality of registers, the second submodule is coupled to the output end of a corresponding sub-part of the second plurality of registers and the input end of a next-level register among the first plurality of registers, and the third submodule is coupled to the output end of a first-level register among the first plurality of registers and the input end of a next-level register.

2. The operation circuit according to claim 1, characterized in that: An input terminal of each adder of the at least one adder of the second sub-module of each combinatorial logic module is coupled to two registers of the second plurality of registers.

3. The operation circuit according to claim 1, characterized in that: The frequency and duty cycle of the clock used for each of the first plurality of registers and the second plurality of registers are the same.

4. The operation circuit according to claim 3, characterized in that: The frequency of the clock is determined according to the calculation delay of the combinational logic module.

5. The operation circuit according to claim 4, characterized in that: The duty cycle of the clock is determined according to a ratio of calculation delays of the first submodule and the second submodule of each combinatorial logic module.

6. The operation circuit according to claim 5, characterized in that: The first submodule and the second submodule of each combinatorial logic module are implemented so that the sum of their calculation delays is minimized.

7. The operation circuit according to claim 5, characterized in that: The first submodule and the second submodule of each combinatorial logic module are implemented such that their calculation delays are substantially equal, and the duty cycle of the clock is 1:

1.

8. The operation circuit according to any one of claims 1 to 7, characterized in that: The first plurality of registers are implemented by D-type flip-flops, and the second plurality of registers are implemented by latches.

9. The operation circuit according to claim 8, characterized in that: A first clock for the first plurality of registers and a second clock for the second plurality of registers are configured such that for each cycle of the first clock and the second clock, at a triggering edge of the first clock that triggers the first plurality of registers, the second clock is at an inactive level that causes the second plurality of registers to be inactive.

10. The operation circuit according to claim 9, characterized in that: For each cycle of the first clock and the second clock, the time from the triggering edge of the first clock to the time when the second clock switches from the inactive level to the active level that makes the second plurality of registers active is greater than or equal to the calculation delay of the first sub-module of each combinational logic module.

11. The operation circuit according to any one of claims 1 to 7, characterized in that: The first plurality of registers and the second plurality of registers are both implemented by D-type flip-flops.

12. The operation circuit according to claim 11, characterized in that: The trigger edges of the first plurality of registers and the second plurality of registers are different, and a first clock for the first plurality of registers is the same as a second clock for the second plurality of registers.

13. The operation circuit according to claim 12, characterized in that: The duty ratio of the first clock and the second clock is 1:1, and a half period thereof is greater than or equal to a calculation delay of the first submodule of each combinational logic module.

14. The operation circuit according to claim 11, characterized in that: The triggering edges of the first plurality of registers and the second plurality of registers are the same.

15. The operation circuit according to claim 14, characterized in that: For each cycle of a first clock for the first plurality of registers and a second clock for the second plurality of registers, a time from a triggering edge of the first clock that triggers the first plurality of registers to a triggering edge of the second clock that triggers the second plurality of registers is greater than or equal to a computational delay of the first sub-module of each combinational logic module.

16. The operation circuit according to claim 15, characterized in that: The first clock and the second clock have the same frequency and duty cycle, and a phase difference of 180 degrees.

17. The operation circuit according to claim 11, characterized in that: The trigger edges of the first plurality of registers and the second plurality of registers are the same, and a first clock for a register of the first plurality of registers coupled to an output terminal of the second submodule is different from a second clock for the second plurality of registers, and a third clock for a register of the first plurality of registers coupled to an output terminal of a third submodule is the same as the second clock.

18. The operation circuit according to claim 17, characterized in that: The first clock and the second clock have the same frequency and duty cycle, and a phase difference of 180 degrees.

19. A chip, characterized in that: The chip comprises the operation circuit according to any one of claims 1-18.

20. A computing device, characterized in that: The computing device comprises the chip according to claim 19.

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