A novel heterojunction battery and its preparation method

Abstract

The present invention discloses a novel heterojunction battery, comprising: a silicon layer substrate, a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first doping layer, a first TCO layer and a first metal grid line which are sequentially arranged on the front surface of the first intrinsic amorphous silicon layer; the first doping layer includes a heavily doped layer and a lightly doped layer, and the heavily doped layer and the lightly doped layer are alternately arranged on the front surface of the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer, and the lightly doped layer includes a lightly doped n-type amorphous silicon layer and a first silicon nitride layer arranged on the lightly doped n-type amorphous silicon layer; and a second doping layer, a second TCO layer and a second metal grid line which are sequentially arranged on the back surface of the second intrinsic amorphous silicon layer; the second doping layer is a doped p-type amorphous silicon layer. Therefore, the heterojunction structure battery prepared by adopting the structure of the present invention can not only improve the performance of the heterojunction battery, but also greatly reduce the manufacturing cost of the heterojunction battery.

Description

Technical Field

[0001] The present invention belongs to the field of solar cell manufacturing, and relates to a novel heterojunction cell and a preparation method thereof. Background Art

[0002] The essence of the rapid development of the photovoltaic industrial chain in recent years is technology-driven cost reduction and efficiency improvement. At present, the single-crystal trend has been established, the efficiency improvement progress of p-type cells has slowed down, and n-type cells have great potential for efficiency improvement. Looking ahead, we believe that the most anticipated change in the photovoltaic industry lies in the shift from p-type cells to n-type cells in the cell segment. Among them, heterojunction cells have become the next big trend in the industry due to their high efficiency and large cost reduction potential. Heterojunction solar cells combine the advantages of crystalline silicon cells and thin-film cells, and have the advantages of simple structure, good temperature characteristics, and bifacial power generation. They are one of the hot directions of high-conversion-efficiency silicon-based solar cells. In 1989, Sanyo in Japan initiated the development of heterojunction cells. Since 2011, China has carried out preliminary explorations on heterojunction cells, and enterprises such as Shangpeng, Saiang, and Guodian have introduced imported equipment for attempts. From 2015 to 2018, enterprises such as Jineng, Zhongzhi, Jushi, Hanergy, and Tongwei have successively established mass production pilot lines, but due to cost factors, they have not been mass-produced on a large scale.

[0003] A heterojunction solar cell uses an n-type monocrystalline silicon wafer as a substrate. On the front surface of the n-type silicon wafer that has been textured and cleaned, an intrinsic amorphous silicon thin film and an n-type amorphous silicon layer are sequentially deposited to form a front surface field. On the back surface, an intrinsic amorphous silicon thin film and a p-type amorphous silicon layer are sequentially deposited to form a p-n heterojunction. On both sides of the doped amorphous silicon thin film, a transparent conductive oxide thin film (TCO) is deposited again. Finally, metal electrodes are formed on the top layers on both sides through screen printing to form a heterojunction solar cell with a symmetric structure. Heterojunction solar cells maintain the core advantage of high efficiency due to the large bandgap width of the heterostructure, but there are still some technical difficulties that need to be overcome at present, such as light absorption loss of the window layer material, grid line contact loss, and high cost.

[0004] To solve the above problems, the present invention provides a novel heterojunction cell. In the cell, the double-sided doped amorphous silicon layer adopts a selective doping method, and the amorphous silicon is divided into a contact region (locally heavily doped) and a passivation region according to functions, and a silicon nitride layer and a TCO lamination method are adopted. The heterojunction solar cell prepared by this structure can not only improve the performance of the heterojunction solar cell, but also greatly reduce the manufacturing cost of the heterojunction cell, and has a profound market development prospect. Summary of the Invention

[0005] In view of this, the present invention provides a novel heterojunction cell and a preparation method thereof. The cell prepared by the present invention can not only improve the performance of the heterojunction cell, but also greatly reduce the manufacturing cost of the heterojunction cell.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A novel heterojunction cell, comprising: a silicon layer substrate, a first intrinsic amorphous silicon layer disposed on the front surface of the silicon layer substrate, and a second intrinsic amorphous silicon layer disposed on the back surface of the silicon layer substrate, characterized in that it further comprises:

[0008] A first doping layer, a first TCO layer, and a first metal grid line sequentially disposed on the front surface of the first intrinsic amorphous silicon layer;

[0009] The first doping layer includes a lightly doped layer, and the lightly doped layer includes a lightly doped n-type amorphous silicon layer;

[0010] And a second doping layer, a second TCO layer, and a second metal grid line sequentially disposed on the back surface of the second intrinsic amorphous silicon layer;

[0011] The second doping layer includes a doped p-type amorphous silicon layer.

[0012] Preferably, the first doping layer further comprises: a heavily doped layer; the heavily doped layer and the lightly doped layer are alternately disposed on the front surface of the first intrinsic amorphous silicon layer and are both in contact with the first intrinsic amorphous silicon layer; and the heavily doped layer is a heavily doped n-type amorphous silicon layer;

[0013] The lightly doped layer further comprises: a first silicon nitride layer, and the first silicon nitride layer is disposed on the front surface of the lightly doped n-type amorphous silicon layer.

[0014] In the present invention, the doping layer is partitioned into a contact region and a passivation region according to functions. Since n-type amorphous silicon has a field passivation effect, local heavy doping is adopted in the contact region to reduce the series resistance generated when contacting the metal grid line and improve the FF. The passivation region adopts light doping to form a front surface field and enhance the passivation effect; the number of the heavily doped layer and the lightly doped layer can be set according to actual needs, and the heavily doped layer is at least 1.

[0015] Preferably, the second doping layer further comprises: a second silicon nitride layer, and the doped p-type amorphous silicon layer and the second silicon nitride layer are alternately disposed on the back surface of the second intrinsic amorphous silicon layer and are both in contact with the second intrinsic amorphous silicon layer.

[0016] The p-type amorphous silicon will affect the relative positions of the Fermi level and the bandgap center due to boron doping, increasing the defect density and thus reducing the minority carrier lifetime. Therefore, only local doping is performed in the contact region on the p surface, and no doping is performed in the rest, which can not only ensure a better passivation effect but also ensure the contact resistance in the metal region, making the Uoc and FF reach the maximum balance. The number of the doped p-type amorphous silicon layer and the second silicon nitride layer can be set according to the actual situation, and the doped p-type amorphous silicon layer is at least 1.

[0017] The novel heterojunction battery structure proposed in the present invention includes but is not limited to the above-mentioned structure. The front side of the battery structure can be an n-side or a p-side; the heterojunction structure can include only an n-side or a p-side; in the battery structure, the silicon nitride layer can be designed as a stacked film for optical matching.

[0018] Preferably, the thickness of the lightly doped n-type amorphous silicon layer is 5-10 nm, and the doping concentration is ≤3%; the thickness of the heavily doped n-type amorphous silicon layer is 5-10 nm, each width is 20-100 μm, and the doping concentration is 4-10%.

[0019] Preferably, the thickness of the doped p-type amorphous silicon layer is 8-10 nm, each width is 20-100 μm, and the doping concentration is 3-10%.

[0020] Preferably, the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 5-10 nm; the thicknesses of the first TCO layer and the second TCO layer are both 10-50 nm.

[0021] Preferably, the thicknesses of the first silicon nitride layer and the second silicon nitride layer are both 40-70 nm, and the refractive index is 2.1-2.6.

[0022] Using the silicon nitride layer as the window material to replace a part of the thickness of the TCO layer and designing a layered stacked film structure can not only reduce the optical loss, but also greatly reduce the cost of the TCO material, optimize the efficiency and at the same time greatly reduce the production cost of the heterojunction battery.

[0023] Preferably, the position of the first metal grid line corresponds to that of the heavily doped layer.

[0024] Preferably, the position of the second metal grid line corresponds to that of the doped p-type amorphous silicon layer.

[0025] Preferably, the silicon layer substrate is an n-type single crystal silicon wafer.

[0026] The preparation method of a novel heterojunction battery described above includes the following steps:

[0027] S1: Texturing and cleaning the silicon layer substrate to form a double-sided textured surface structure;

[0028] S2: Depositing the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer on the front and back sides of the silicon layer substrate respectively; and depositing a lightly doped n-type amorphous silicon layer on the front of the first intrinsic amorphous layer;

[0029] S3: Depositing a first silicon nitride layer on the front of the lightly doped n-type amorphous silicon layer;

[0030] S4: Use a masking method to etch the first silicon nitride layer that has completed step S3 with a 3-10% HF solution in a partitioned manner. After etching and removing the first silicon nitride layer in the area without masking protection, remove the masking glue with a 1-5% KOH solution, and deposit a heavily doped n-type amorphous silicon layer on the etched area;

[0031] S5: Deposit a first TCO layer on the front of the lightly doped n-type amorphous silicon layer that has completed step S2, or deposit a first TCO layer on the front of the heavily doped n-type amorphous silicon layer and the first silicon nitride layer that have completed step S4;

[0032] S6: Deposit a second silicon nitride layer or a doped p-type amorphous silicon layer on the back of the second intrinsic amorphous silicon layer that has completed step S5;

[0033] S7: Use a masking method to etch the back of the second silicon nitride layer that has completed step S6 with a 3-10% HF solution in a partitioned manner. After etching and removing the second silicon nitride layer in the area without masking protection, remove the masking glue with a 1-5% KOH solution, and deposit a doped p-type amorphous silicon layer on the etched area;

[0034] S8: Deposit a second TCO layer on the back of the doped p-type amorphous silicon layer that has completed step S6, or deposit a second TCO layer on the back of the doped p-type amorphous silicon layer and the second silicon nitride layer that have completed step S7;

[0035] S9: Perform metal grid line printing on the front of the first TCO layer and the back of the second TCO layer that have completed step S8, and thus obtain the novel heterojunction battery.

[0036] During the preparation process, HF will not etch the positive lightly doped n-type amorphous silicon layer and the second intrinsic amorphous silicon, but the masking glue needs to be removed with KOH. During the process of removing the masking glue with KOH, the n-type lightly doped amorphous silicon and the p-side intrinsic amorphous silicon will be removed. Therefore, the heavily doped layer only includes the heavily doped n-type amorphous silicon layer.

[0037] Compared with the prior art, the present invention has the following beneficial effects: After adopting the structure of the present invention, the double-sided doped amorphous silicon layer of the battery adopts a selective doping method, and the amorphous silicon is divided into a contact region (locally heavily doped) and a passivation region according to functions. Through process regulation, the passivation region has better passivation performance, and the contact region can reduce the gate line contact resistance due to heavy doping; The TCO adopts a silicon nitride and TCO laminated structure. A silicon nitride thin film with a certain thickness is first deposited on the doped amorphous silicon thin film, and then the TCO layer is deposited, which can improve optical absorption. And since the silicon nitride material replaces a certain thickness of the TCO, the production cost of the heterojunction battery can be greatly reduced. Therefore, the heterojunction battery prepared by adopting the structure of the present invention can not only improve the performance of the heterojunction battery, but also greatly reduce the manufacturing cost of the heterojunction battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0039] Figure 1 It is a schematic structural diagram of a novel heterojunction battery of the present invention;

[0040] Figure 2 It is a schematic structural diagram of a novel heterojunction battery in Embodiment 4 of the present invention;

[0041] Figure 3 It is a schematic structural diagram of a novel heterojunction battery in Embodiment 5 of the present invention;

[0042] Figure 4 It is a schematic structural diagram of a heterojunction battery of the comparative example of the present invention.

[0043] Among them, in the figure:

[0044] 1. First metal gate line; 2. First TCO layer; 3. First silicon nitride layer; 4. Heavily doped n-type amorphous silicon layer; 5. Lightly doped n-type amorphous silicon layer; 6. First intrinsic amorphous silicon layer; 7. Silicon layer substrate; 8. Second intrinsic amorphous silicon layer; 9. Doped p-type amorphous silicon layer; 10. Second silicon nitride layer; 11. Second TCO layer; 12. Second metal gate line. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0045] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Apparently, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0046] As Figure 2 , a novel heterojunction battery includes: a silicon layer substrate 7, a first intrinsic amorphous silicon layer 6 disposed on the front surface of the silicon layer substrate 7, and a second intrinsic amorphous silicon layer 8 disposed on the back surface of the silicon layer substrate 7. It further includes:

[0047] A first doping layer, a first TCO layer 2, and a first metal grid line 1 sequentially disposed on the front surface of the first intrinsic amorphous silicon layer 6; the first doping layer includes a heavily doped layer and a lightly doped layer, the heavily doped layer and the lightly doped layer are alternately disposed on the front surface of the first intrinsic amorphous silicon layer 6 and are both in contact with the first intrinsic amorphous silicon layer; the heavily doped layer is a heavily doped n-type amorphous silicon layer 4, and the lightly doped layer includes a lightly doped n-type amorphous silicon layer 5 and a first silicon nitride layer 3 disposed on the front surface of the lightly doped n-type amorphous silicon layer;

[0048] And a second doping layer, a second TCO layer 11, and a second metal grid line 12 sequentially disposed on the back surface of the second intrinsic amorphous silicon layer 8; the second doping layer is a doped p-type amorphous silicon layer 9.

[0049] Further, there is another embodiment, as Figure 3 , the first doping layer is only the lightly doped n-type amorphous silicon layer 5, the second doping layer includes a doped p-type amorphous silicon layer 9 and a second silicon nitride layer 10, the doped p-type amorphous silicon layer 9 and the second silicon nitride layer 10 are alternately disposed on the back surface of the second intrinsic amorphous silicon layer 8 and are both in contact with the second intrinsic amorphous silicon layer 8.

[0050] Further, there is another embodiment, as Figure 1 , the first doping layer includes a heavily doped layer and a lightly doped layer, and the second doping layer includes a doped p-type amorphous silicon layer 9 and a second silicon nitride layer 10.

[0051] Further, the position of the first metal grid line 1 corresponds to that of the heavily doped layer, and the position of the second metal grid line 12 corresponds to that of the doped p-type amorphous silicon layer 9.

[0052] Embodiment 1

[0053] As Figure 1 , the preparation process steps of a novel heterojunction battery are as follows:

[0054] S1 Texturize and clean the N-type monocrystalline silicon wafer, texturize the wafer and form a clean surface, and the size of the textured surface is 3 μm;

[0055] S2 uses a PECVD device to deposit an amorphous silicon thin film on the previous silicon wafer. On the front side, a first intrinsic amorphous silicon layer (thickness 5 nm) and a lightly doped n-type amorphous silicon layer (thickness 5 nm, doping concentration 1%) are deposited in sequence; on the back side, a second intrinsic amorphous silicon layer (thickness 5 nm) is deposited.

[0056] S3 uses a PECVD device to deposit a first silicon nitride layer on the front side of the lightly doped n-type amorphous silicon layer completed in step S2, with a deposition thickness of 40 nm; a second silicon nitride layer is deposited on the back side of the second intrinsic amorphous silicon layer, with a deposition thickness of 40 nm.

[0057] S4 uses a mask paste (implemented by screen printing) to selectively partition the first silicon carbide layer completed in step S3, and uses an HF solution (concentration 3%) to etch the first silicon carbide layer in a partitioned manner. The partitioned etching area is 20 μm. After etching and removing the first silicon nitride layer in the area without mask protection, a KOH solution (concentration 2%) is used to remove the mask glue, and a heavily doped n-type amorphous silicon layer is deposited on the etched area; then a first TCO layer is deposited on the front side of the first silicon carbide layer and the heavily doped n-type amorphous silicon layer, with a thickness of 10 nm.

[0058] S5 uses a mask paste (implemented by screen printing) to selectively partition the second silicon carbide layer completed in step S4, and uses an HF solution (concentration 3%) to etch the silicon wafer in a partitioned manner. The partitioned etching area is 20 μm. After etching and removing the second silicon nitride layer in the area without mask protection, a KOH solution (concentration 2%) is used to remove the mask glue, and a doped p-type amorphous silicon layer (thickness 8 nm, doping concentration 3%) is deposited on the etched area; then a second TCO layer is deposited on the back side of the second silicon nitride layer and the doped p-type amorphous silicon layer, with a thickness of 10 nm.

[0059] S6 performs metal grid line printing on the front side of the first TCO layer and the back side of the second TCO layer completed in step S5, and a new type of heterojunction battery is obtained.

[0060] Example 2

[0061] A new type of heterojunction battery, the preparation process steps are as follows:

[0062] S1 performs texturing cleaning on the N-type monocrystalline silicon wafer, textures the silicon wafer and forms a clean surface, and the texture size is 3 μm.

[0063] S2 uses a PECVD device to deposit an amorphous silicon thin film on the previous silicon wafer. On the front side, a first intrinsic amorphous silicon layer (thickness 10 nm) and a lightly doped n-type amorphous silicon layer (thickness 10 nm, doping concentration 3%) are deposited in sequence; on the back side, a second intrinsic amorphous silicon layer (thickness 10 nm) is deposited.

[0064] S3 uses a PECVD device to deposit a first silicon nitride layer on the front side of the lightly doped n-type amorphous silicon layer with a deposition thickness of 70 nm; and deposits a second silicon nitride layer on the back side of the second intrinsic amorphous silicon layer with a deposition thickness of 70 nm.

[0065] S4 Selectively partitions the first silicon carbide layer completed in step S3 using a mask paste (implemented by screen printing), and uses an HF solution (concentration 10%) to etch the first silicon carbide layer in partitions. The partition etching area is 100 μm. After etching and removing the first silicon nitride layer in the area without mask protection, use a KOH solution (concentration 2%) to remove the mask glue, and deposit a heavily doped n-type amorphous silicon layer on the etched area; then deposit a first TCO layer with a thickness of 50 nm on the front side of the first silicon carbide layer and the heavily doped n-type amorphous silicon layer.

[0066] S5 Selectively partitions the second silicon carbide layer completed in step S4 using a mask paste (implemented by screen printing), and uses an HF solution (concentration 10%) to etch the silicon wafer in partitions. The partition etching area is 100 μm. After etching and removing the second silicon nitride layer in the area without mask protection, use a KOH solution (concentration 2%) to remove the mask glue, and deposit a doped p-type amorphous silicon layer (thickness 10 nm, doping concentration 10%) on the etched area; then deposit a second TCO layer with a thickness of 50 nm on the back side of the second silicon nitride layer and the doped p-type amorphous silicon layer.

[0067] S6 Perform metal grid line printing on the front side of the first TCO layer and the back side of the second TCO layer completed in step S5, and a new type of heterojunction battery is obtained.

[0068] Example 3

[0069] A new type of heterojunction battery, the preparation process steps are as follows:

[0070] S1 Perform texturing cleaning on the N-type monocrystalline silicon wafer, texture the silicon wafer and form a clean surface, and the texture size is 3 μm.

[0071] S2 Use a PECVD device to deposit amorphous silicon thin films on the previous silicon wafer. On the front side, deposit a first intrinsic amorphous silicon layer (thickness 8 nm) and a lightly doped n-type amorphous silicon layer (thickness 8 nm, doping concentration 2%) in sequence; deposit a second intrinsic amorphous silicon layer (thickness 8 nm) on the back side.

[0072] S3 Use a PECVD device to deposit a first silicon nitride layer on the front side of the lightly doped n-type amorphous silicon layer completed in step S2 with a deposition thickness of 70 nm; deposit a second silicon nitride layer on the back side of the second intrinsic amorphous silicon layer with a deposition thickness of 70 nm.

[0073] S4 uses a mask paste (implemented by screen printing) to selectively partition the first silicon carbide layer that has completed step S3, and uses an HF solution (concentration 5%) to perform partition etching on the silicon wafer. The partition etching area is 50 μm. After etching and removing the first silicon nitride layer in the area without mask protection, use a KOH solution (concentration 2%) to remove the mask glue, and deposit a heavily doped n-type amorphous silicon layer on the etched area; then deposit a first TCO layer on the front sides of the first silicon carbide layer and the heavily doped n-type amorphous silicon layer, with a thickness of 30 nm;

[0074] S5 uses a mask paste (implemented by screen printing) to selectively partition the second silicon carbide layer that has completed step S4, and uses an HF solution (concentration 5%) to perform partition etching on the silicon wafer. The partition etching area is 50 μm. After etching and removing the second silicon nitride layer in the area without mask protection, use a KOH solution (concentration 2%) to remove the mask glue, and deposit a doped p-type amorphous silicon layer (thickness 10 nm, doping concentration 5%) on the etched area; then deposit a second TCO layer on the back sides of the second silicon nitride layer and the doped p-type amorphous silicon layer, with a thickness of 30 nm;

[0075] S6 performs metal grid line printing on the front side of the first TCO layer and the second TCO layer that have completed step S5 respectively, to obtain a new type of heterojunction battery, and conduct electrical performance tests. The results are shown in Table 1.

[0076] Example 4

[0077] A heterojunction battery with a patented technology structure on the front side (such as Figure 2 ), and the preparation process steps are as follows:

[0078] S1 performs texturing and cleaning on the N-type monocrystalline silicon wafer, textures the silicon wafer and forms a clean surface, and the texture size is 3 μm;

[0079] S2 uses a PECVD device to deposit amorphous silicon thin films on the previous silicon wafer. On the front side, deposit a first intrinsic amorphous silicon layer (thickness 8 nm) and a lightly doped n-type amorphous silicon layer (thickness 8 nm, doping concentration 2%) in sequence; on the back side, deposit a second intrinsic amorphous silicon layer (thickness 8 nm) and a doped p-type amorphous silicon layer (thickness 10 nm, doping concentration 5%) in sequence;

[0080] S3 uses a PECVD device to deposit a first silicon nitride layer on the front side of the lightly doped n-type amorphous silicon layer that has completed step S2, with a deposition thickness of 70 nm;

[0081] S4 uses an RPD device to deposit a second TCO layer on the back side of the doped p-type amorphous silicon layer that has completed step S3, with a deposition thickness of 100 nm;

[0082] S5 uses a mask paste (implemented by screen printing) to selectively partition the first silicon carbide layer, and uses an HF solution (concentration 5%) to etch the partition of the first silicon carbide layer. The partition etching area is 50 μm; and the etched area is heavily doped with n-type amorphous silicon (thickness 10 mm, doping concentration 4%), and the front sides of the first silicon carbide layer and the heavily doped n-type amorphous silicon layer are deposited with the first TCO layer, with a deposition thickness of 30 nm;

[0083] S6 uses screen printing to print metal grid lines on the front side of the first TCO layer and the back side of the second TCO layer that have completed step S5 (the front grid line printing position is the heavily doped n-type amorphous silicon area). After drying and curing, electrical performance tests are carried out, and the results are shown in Table 1.

[0084] Example 5

[0085] A heterojunction back-contact cell using a patented technology structure (such as Figure 3 ), and the preparation process steps are as follows:

[0086] S1 Textures and cleans the N-type monocrystalline silicon wafer to texture the wafer and form a clean surface, with the texture size of 3 μm;

[0087] S2 Uses a PECVD device to deposit an amorphous silicon thin film on the silicon wafer. The first intrinsic amorphous silicon layer (thickness 8 nm) and the lightly doped n-type amorphous silicon layer (thickness 8 nm, doping concentration 2%) are sequentially deposited on the front side; the second intrinsic amorphous silicon layer (thickness 8 nm) is deposited on the back side;

[0088] S3 Uses a PECVD device to deposit the second silicon carbide layer on the back side of the second intrinsic amorphous silicon layer, with a deposition thickness of 70 nm;

[0089] S4 Uses an RPD device to deposit the first TCO layer on the front side of the lightly doped n-type amorphous silicon layer, with a deposition thickness of 100 nm;

[0090] S5 uses a mask paste (implemented by screen printing) to selectively partition the back side of the second silicon carbide layer, and uses an HF solution (concentration 5%) to etch the partition of the second silicon carbide layer. The partition etching area is 50 μm, and the etched area is doped with p-type amorphous silicon (thickness 10 mm, doping concentration 5%). Then, an RPD device is used to deposit the second TCO layer on the back sides of the doped p-type amorphous silicon and the second silicon carbide layer, with a deposition thickness of 30 nm;

[0091] S6 uses screen printing to print metal grid lines on the front side of the first TCO layer and the back side of the second TCO layer (the back grid line printing position is the p-type doped amorphous silicon area). After drying and curing, electrical performance tests are carried out, and the results are shown in Table 1.

[0092] Comparative Example

[0093] It is a conventional heterojunction structure battery, and the preparation process steps are as follows:

[0094] S1 Texturize and clean the N-type monocrystalline silicon wafer to texture the wafer and form a clean surface, with the texture size of 3 μm;

[0095] S2 Use PECVD equipment to deposit amorphous silicon thin films on the previous silicon wafer. On the front side, deposit the first intrinsic amorphous silicon layer (thickness 8 nm) and the lightly doped n-type amorphous silicon layer (thickness 8 nm, doping concentration 2%) in sequence; on the back side, deposit the second intrinsic amorphous silicon layer (thickness 8 nm) and the p-type doped amorphous silicon layer (thickness 10 nm, doping concentration 5%) in sequence;

[0096] S3 Use RPD equipment to deposit the first TCO layer on the front side of the lightly doped n-type amorphous silicon layer with a deposition thickness of 100 nm, and deposit the second TCO layer on the back side of the p-type doped amorphous silicon layer with a deposition thickness of 30 nm;

[0097] S4 Use screen printing to print metal grid lines on the front side of the first TCO layer and the back side of the second TCO layer, and perform electrical performance tests after drying and curing. The results are shown in Table 1.

[0098] Table 1 Battery test performance results

[0099] Grouping Eta Uoc Isc FF TCO Cost Reduction Comparative Example 0.00 0.000 0.000 0.0 0 Example 4 0.16 0.000 0.020 0.40 -30％ Example 5 0.22 0.002 0.006 0.50 -30％ Example 3 0.29 0.002 0.002 0.20 -60％

[0100] As can be seen from the above, the comparative example is used as the BL standard. Compared with the comparative example, the efficiency of Example 4 is increased by 0.16%. The main reason is that the patented technology structure is adopted on the front side, and the amorphous silicon metal contact area is heavily doped, effectively improving the FF of the battery; and the silicon nitride and TCO laminated film method is adopted on the front side to improve the light utilization rate, thereby improving the Isc of the battery. And due to the introduction of the SiNx layer, the consumption of TCO materials is reduced, and the TCO cost is reduced by 30% compared with Example 1. Compared with the comparative example, the efficiency of Example 5 is increased by 0.22%. The main reason is that the patented technology structure is adopted on the back side, and the p-type amorphous silicon is only doped in the metal contact area without affecting the passivation effect, which can effectively improve the Uoc and FF of the battery; and due to the introduction of the SiNx layer on the back side, the consumption of TCO materials is reduced, and the TCO cost is reduced by 30% compared with Example 1; Example 3 combines Example 4 and Example 5 first, and the efficiency is increased by 0.29% compared with the comparative example, and the TCO cost is directly reduced by 60%.

[0101] In this specification, each embodiment is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same and similar parts among the embodiments, reference can be made to each other.

[0102] The foregoing description of the disclosed embodiments enables those skilled in the art to practice or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A novel heterojunction battery, characterized in that, it comprises: a silicon layer substrate, a first intrinsic amorphous silicon layer disposed on the front surface of the silicon layer substrate, and a second intrinsic amorphous silicon layer disposed on the back surface of the silicon layer substrate, and further comprises: a first doping layer, a first TCO layer, and a first metal grid line sequentially disposed on the front surface of the first intrinsic amorphous silicon layer; the first doping layer comprises a lightly doped layer, and the lightly doped layer comprises a lightly doped n-type amorphous silicon layer; and a second doping layer, a second TCO layer, and a second metal grid line sequentially disposed on the back surface of the second intrinsic amorphous silicon layer; the second doping layer comprises a doped p-type amorphous silicon layer; the first doping layer further comprises: a heavily doped layer; the heavily doped layer and the lightly doped layer are alternately disposed on the front surface of the first intrinsic amorphous silicon layer, and both are in contact with the first intrinsic amorphous silicon layer; and the heavily doped layer is a heavily doped n-type amorphous silicon layer; the lightly doped layer further comprises: a first silicon nitride layer, and the first silicon nitride layer is disposed on the front surface of the lightly doped n-type amorphous silicon layer; the second doping layer further comprises: a second silicon nitride layer, the doped p-type amorphous silicon layer and the second silicon nitride layer are alternately disposed on the back surface of the second intrinsic amorphous silicon layer, and both are in contact with the second intrinsic amorphous silicon layer.

2. A novel heterojunction battery according to claim 1, characterized in that, the thickness of the lightly doped n-type amorphous silicon layer is 5 - 10 nm, and the doping concentration is ≤ 3%; the thickness of the heavily doped n-type amorphous silicon layer is 5 - 10 nm, each width is 20 - 100 μm, and the doping concentration is 4 - 10%.

3. A novel heterojunction battery according to claim 1, characterized in that, the thickness of the doped p-type amorphous silicon layer is 8 - 10 nm, each width is 20 - 100 μm, and the doping concentration is 3 - 10%.

4. A novel heterojunction battery according to any one of claims 1 - 3, characterized in that, the thicknesses of the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are both 5 - 10 nm; the thicknesses of the first TCO layer and the second TCO layer are both 10 - 50 nm.

5. A novel heterojunction battery according to claim 1, characterized in that, the thicknesses of the first silicon nitride layer and the second silicon nitride layer are both 40 - 70 nm, and the refractive index is 2.1 - 2.

6.

6. A novel heterojunction battery according to claim 1, characterized in that, the position of the first metal grid line corresponds to that of the heavily doped layer.

7. A novel heterojunction battery according to claim 1, characterized in that, the position of the second metal grid line corresponds to that of the doped p-type amorphous silicon layer.

8. A preparation method of a novel heterojunction battery, characterized in that, it comprises the following steps: S1: Texturing and cleaning the silicon layer substrate to form a double-sided textured surface structure; S2: Depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front and back surfaces of the silicon layer substrate respectively; and depositing a lightly doped n-type amorphous silicon layer on the front surface of the first intrinsic amorphous silicon layer; S3: Depositing a first silicon nitride layer on the front surface of the lightly doped n-type amorphous silicon layer; S4: Use a masking method to etch the first silicon nitride layer that has completed step S3 with a 3-10% HF solution in zones. After etching and removing the first silicon nitride layer in the unmasked protected areas, remove the masking glue with a 1-5% KOH solution, and deposit a heavily doped n-type amorphous silicon layer on the etched areas; S5: Deposit a first TCO layer on the front of the lightly doped n-type amorphous silicon layer that has completed step S2, or deposit a first TCO layer on the front of the heavily doped n-type amorphous silicon layer and the first silicon nitride layer that have completed step S4; S6: Deposit a second silicon nitride layer or a doped p-type amorphous silicon layer on the back of the second intrinsic amorphous silicon layer that has completed step S5; S7: Use a masking method to etch the back of the second silicon nitride layer that has completed step S6 with a 3-10% HF solution in zones. After etching and removing the second silicon nitride layer in the unmasked protected areas, remove the masking glue with a 1-5% KOH solution, and deposit a doped p-type amorphous silicon layer on the etched areas; S8: Deposit a second TCO layer on the back of the doped p-type amorphous silicon layer that has completed step S6, or deposit a second TCO layer on the back of the doped p-type amorphous silicon layer and the second silicon nitride layer that have completed step S7; S9: Perform metal grid line printing on the front of the first TCO layer and the back of the second TCO layer that have completed step S8, and thus obtain the novel heterojunction battery.

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