Flush cache lines from shared memory pages to memory.

Abstract

The processing system (100) flushes cache lines (308, 309) from the cache (302) that share the same memory page (147) as the cache line (304) identified for eviction. The cache controller (175) of the processing system identifies the cache line as scheduled for eviction. In response, the cache controller identifies additional “dirty sacrifice” cache lines (cache lines that have been modified at the cache but not yet written back to memory) associated with the same memory page and writes each of the identified cache lines to the same memory page in memory (105). By writing each of the dirty sacrifice cache lines associated with the memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

Description

Background Technology

[0001] Processing systems often utilize memory hierarchies to support data storage for the system's processing nodes. A memory hierarchy comprises multiple tiers of cache accessible to one or more processor cores of a node, and main memory for storing all data that can be manipulated by program instructions executed at the processor cores. To improve processing efficiency, processing systems can implement memory management schemes, in which the system moves data to different tiers of the memory hierarchy according to the scheme. For example, under some memory management schemes, the system moves data most recently accessed by a processor core to a tier of the memory hierarchy closer to that core, allowing for relatively fast access to that data in the future. Furthermore, the memory management scheme controls how to replace data at which tier of the memory hierarchy when new data is received, and how and when data is copied between tiers of the memory hierarchy. However, conventional memory management schemes can inefficiently perform these data replacement and transfer operations, consuming excessive amounts of system resources. Attached Figure Description

[0002] This disclosure can be better understood by referring to the accompanying drawings, which will make its many features and advantages readily apparent to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0003] Figure 1 This is a block diagram of a processing system according to some implementation schemes, the processing system flushing cache lines that share the same memory pages as the cache lines being evicted.

[0004] Figure 2 It is based on some implementation plans. Figure 1 A block diagram of the cache hierarchy used in the processing system.

[0005] Figure 3 This illustrates some implementation schemes. Figure 1 A block diagram of the processing system flushing instances of cache lines that share the same memory pages as the cache line being evicted.

[0006] Figure 4 This is a flowchart illustrating a method, according to some embodiments, for flushing cache lines that share the same memory pages as the cache line being evicted.

[0007] Figure 5 This is a flowchart illustrating a method for storing cache lines that share the same memory pages at the same index in the cache, according to some implementation schemes. Detailed Implementation

[0008] Figures 1 to 5 This paper illustrates a technique for improving memory management efficiency at a processing system by flushing cache lines that share the same memory page as the cache lines identified for eviction. The processing system's cache controller identifies cache lines as scheduled for eviction. In response, the cache controller identifies additional "dirty sacrifice" cache lines (cache lines that have been modified at the cache but not yet written back to memory) associated with the same memory page and writes each identified cache line to the same memory page. By writing each dirty sacrifice cache line associated with a memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

[0009] For example, one benchmark for processing efficiency is "write locality," which at least in part refers to how often a processing system performs sequential write operations or write operations that are relatively close in time to the same memory page. Specifically, because preparing memory pages for write operations consumes system resources, increasing write locality reduces the number of times memory pages need to be prepared, and thus reduces system resource consumption. Conventional cache controllers only write cache lines to memory when a cache line is selected for eviction by a replacement policy. Those cache lines often come from memory pages different from other recently evicted cache lines. Using the techniques described herein, the cache controller flushes cache lines that share the same memory pages as the cache line being evicted, thereby increasing write locality and improving processing efficiency.

[0010] Figure 1This is a block diagram of a processing system 100 according to some embodiments. The processing system 100 is generally configured to execute a set of instructions (e.g., computer programs or application programs) on behalf of an electronic device. Therefore, the processing system can be incorporated into any of many electronic devices such as desktop or laptop computers, servers, tablets, smartphones, game consoles, etc. To support the execution of the instruction set, the processing system 100 includes or can access memory 105 or other storage components implemented using non-transitory computer-readable media such as dynamic random access memory (DRAM). However, the DRAM memory (DRAM) 105 can also be implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. The processing system 100 also includes a bus 110 to support communication between entities implemented in the processing system 100, such as DRAM 105. DRAM 105 is divided into a set of logical segments, referred to herein as pages (e.g., memory page 147). In some implementations, each memory page shares common addressing or other access circuitry, making multiple sequential accesses to the same memory page less resource-intensive than sequential accesses to different memory pages. As further described herein, processing system 100 implements a memory management scheme to encourage sequential access to the same memory pages, thereby saving system resources and improving processing efficiency.

[0011] Processing system 100 includes a graphics processing unit (GPU) 115 configured to render images for presentation on display 120. For example, GPU 115 may render objects to produce pixel values ​​provided to display 120, which uses these pixel values ​​to display an image representing the rendered object. Some embodiments of GPU 115 are used for general-purpose computing. In the illustrated embodiment, GPU 115 implements multiple processing elements 116, 117, 118 (collectively referred to herein as "processing elements 116 to 118") configured to execute instructions simultaneously or in parallel. In the illustrated embodiment, GPU 115 communicates with DRAM 105 via bus 110. However, some embodiments of GPU 115 communicate with DRAM 105 via a direct connection or via other buses, bridges, switches, routers, etc. GPU 115 executes instructions stored in DRAM 105, and GPU 115 stores information such as the results of instruction execution in DRAM 105. For example, DRAM 105 may store a copy 125 of instructions from program code to be executed by GPU 115. GPU 115 includes a scheduler 130 configured to schedule instructions for execution by processing elements 116 to 118.

[0012] GPU 115 also implements a cache hierarchy 135, which includes one or more levels of caches used to cache instructions or data for relatively low latency access by processing elements 116 to 118. The cache hierarchy 135 includes multiple individual caches and corresponding cache locations (cache lines), as shown in... Figure 2 The GPU 115 also includes a cache controller 139 for controlling data movement between levels of the cache hierarchy 135 and between the cache hierarchy 135 and the DRAM 105, as further described below.

[0013] The processing system 100 also includes a central processing unit (CPU) 140 implementing multiple processing elements 141, 142, and 143, collectively referred to herein as "processing elements 141 to 143". Processing elements 141 to 143 are configured to execute instructions simultaneously or in parallel. For example, processing elements 141 to 143 are configured to execute multiple threads simultaneously or in parallel. The CPU 140 includes a scheduler 150 configured to schedule instructions for execution by processing elements 141 to 143. The CPU 140 is connected to a bus 110 and thus communicates with the GPU 115 and DRAM 105 via the bus 110. The CPU 140 executes instructions such as program code 145 stored in the DRAM 105, and the CPU 140 also stores information such as the results of executing instructions in the DRAM 105.

[0014] CPU 140 implements a cache hierarchy 155, which includes one or more levels of cache for caching instructions or data for relatively low latency access by processing elements 141 to 143. While cache hierarchy 155 is depicted external to processing elements 141 to 143, some implementations of processing elements 141 to 143 incorporate corresponding caches interconnected to cache hierarchy 155. Details of cache hierarchy 155 are described below with respect to... Figure 2 To describe in more detail.

[0015] CPU 140 also includes a cache controller 175 for receiving and sending first and subsequent cache lines into and out of cache hierarchy 155, data movement between levels in cache hierarchy 155, and data movement between cache hierarchy 155 and DRAM 105. The operation of cache controller 175 is described in further detail below. It should be understood that cache controller 139 performs similar operations relative to cache hierarchy 135.

[0016] The cache controller 175 implements a specified memory management scheme for the cache hierarchy 155 and DRAM 105 by managing various aspects of the corresponding cache entries. For example, during instruction execution, processing elements 141 to 143 generate operations called memory access operations to retrieve or modify data from or modify the cache hierarchy 155. Examples of memory access operations include write operations to write data to a memory location and read operations to read data from a memory location. Each memory location corresponds to a different memory address, and each memory access operation includes a memory address targeted by the memory access operation. The cache controller 175 receives memory access operations from processing elements 141 to 143 and performs the memory access operation by providing data to processing elements 141 to 143 in the case of a read operation or by modifying data at one or more entries (called cache lines) in the cache hierarchy 155 in the case of a write operation.

[0017] During memory access operations, cache controller 175 moves data between different levels of cache hierarchy 155 and between cache hierarchy 155 and DRAM 105 based on a specified memory management scheme. For example, in some embodiments, cache controller 175 improves memory access efficiency by moving recently accessed data (i.e., data most recently targeted by a memory access operation) to a higher level of cache hierarchy 155, such that the data is "closer" to processing elements 141 to 143 in cache hierarchy 155 and can therefore be accessed by processing elements 141 to 143 more quickly. In some embodiments, cache controller 175 speculatively transfers data between levels of the memory hierarchy based at least in part on patterns detected in memory access operations generated by processing elements 141 to 143. Furthermore, cache controller 175 manages data transfer between cache hierarchy 155 and DRAM 105. For example, in response to determining that data targeted by a memory operation is not stored at a cache line of the cache hierarchy 155, the cache controller 175 transfers the data targeted by the memory operation from DRAM 105 to one or more cache lines of the cache hierarchy 155.

[0018] The cache controller 175 is also configured to maintain data consistency between different levels of the cache hierarchy 155 and between the cache hierarchy 155 and DRAM 105. Specifically, when data is modified at a cache line of the cache hierarchy 155, as further described below, the cache controller ensures that the modified data is stored at other cache lines of the cache hierarchy 155 and at the entry in DRAM 105 corresponding to the memory address of the modified data before it can be accessed by another processing element, processor core, processing unit, etc.

[0019] To manage data transfer between levels of the cache hierarchy 155 and maintain data consistency, the cache controller 175 maintains consistency status information for each cache line of the cache hierarchy 155. The consistency status information of a cache line indicates whether the cache line stores valid data and is therefore unsuitable for replacement by data associated with a different memory address, or stores invalid data and is therefore suitable for replacement by data associated with a different memory address. Furthermore, for cache lines with a valid status, the consistency status information indicates whether the data at the cache line is in a modified state—that is, 1) whether the data at the cache line has been modified from its original state when it was stored at the cache line, and 2) whether the modified data at the cache line has not yet been copied to a lower level of the cache hierarchy 155 or DRAM 105. In some embodiments, the consistency status information indicates additional consistency aspects, such as whether the data stored at the cache line is exclusively accessible by the CPU or shared with other processing units.

[0020] To transfer data between levels of the cache hierarchy 155 and maintain data consistency, the cache controller 175 performs at least two types of operations, referred to herein as eviction operations and flush operations. Specifically, the cache controller 175 performs an eviction operation to remove valid data from a cache line in response to, for example, determining that received data will be stored at the cache line, based on a memory management scheme implemented by the cache controller 175. To perform an eviction operation on a cache line, the cache controller 175 determines whether the cache line is in a modified state. If not, the cache controller 175 sets the state of the cache line to an invalid state. If the cache line is in a modified state, the cache controller 175 copies the contents of the cache line to one or more of the lower levels of the cache hierarchy 155 and DRAM 105.

[0021] Cache controller 175 performs a flush operation to maintain data consistency between different levels of cache hierarchy 155. To perform a flush operation, cache controller 175 identifies one or more cache lines at a given level of cache hierarchy 155 as being in a valid or modified state, and copies the contents of the modified cache line to one or more lower levels of the cache hierarchy. Conversely, in the case of an eviction operation, cache controller 175 keeps the identified cache lines in a valid state. In some embodiments, cache controller 175 performs the flush operation periodically or in response to one or more specified conditions (such as the execution of a specific instruction, a change in the executing thread, etc.) identified at CPU 140.

[0022] In some implementations, in response to evicting a cache line, the cache controller 175 performs a flush operation on the cache line associated with the same DRAM 105 page as the evicted cache line. Specifically, in response to identifying a cache line for eviction, the cache controller 175 identifies other cache lines at the same level of the cache hierarchy 155, which are assigned to the same memory address as the identified cache line for eviction. The cache controller then writes the evicted cache line and the additional identified cache lines to DRAM 105 via multiple write operations to the same memory page, thus improving processor efficiency. Furthermore, in some implementations, the CPU 140 sets the flushed cache line to a clean (i.e., unmodified) state.

[0023] Figure 2 Is with Figure 1 A block diagram of cache hierarchy 200 corresponding to one of cache hierarchy structures 135 and 155. Cache hierarchy 200 caches information, such as instructions or data for processing elements 201, 202, 203, and 204, collectively referred to herein as "processing elements 201 to 204". Processing elements 201 to 204 are used to implement, for example... Figure 1 Some embodiments of the processing elements 116 to 118 and 141 to 143 shown.

[0024] The cache hierarchy 200 includes three levels of cache: a first level comprising L1 caches 211, 212, 213, and 214 (collectively referred to herein as "L1 caches 211 to 214"); a second level comprising L2 caches 215 and 220; and a third level comprising L3 cache 225. However, some implementations of the cache hierarchy 200 include more or fewer cache levels. While L1 caches 211 to 214 are depicted as separate hardware structures interconnected to the corresponding processing elements 201 to 204, some implementations of L1 caches 211 to 214 are incorporated into the hardware structures implementing processing elements 201 to 204. Each level of cache contains multiple separate cache lines (e.g., cache lines 230 to 237).

[0025] L1 caches 211 to 214 are used to cache information for access by corresponding processing elements 201 to 204, and are dedicated caches for each processing element. For example, L1 cache 211 is configured to cache information for processing element 201. Processing element 201 can therefore issue a memory access request to L1 cache 211. If the memory access request is hit in L1 cache 211, the requested information is returned. If the memory access request is not hit in L1 cache 211 (i.e., the requested data does not exist), the memory access request is forwarded to the next lower cache level (i.e., L2 cache 215).

[0026] Processing elements 201 to 204 are grouped into subsets 227 and 229, and subsets 227 and 229 are associated with corresponding L2 caches 215 and 220. L2 caches 215 and 220 are therefore shared caches configured to cache information for processing elements 201 to 204 used by subsets 227 and 229. For example, L2 cache 215 caches information for processing elements 201 and 202. As discussed above, if one of the processing elements 201 and 202 issues a memory access request that is not hit in the corresponding L1 caches 211 and 212, the memory access request is forwarded to L2 cache 215. If the memory access request is hit in L2 cache 215, the requested information is returned to the requesting processing element 201 or 202. If a memory access request is not hit in L2 cache 215, L2 cache 215 forwards the memory access request to the next higher level of the cache (e.g., L3 cache 225).

[0027] L3 cache 225 is configured as a shared cache for processing elements 201 to 204. Memory access requests from processing elements 201 to 204 that are missed in L2 caches 215 and 220 are forwarded to L3 cache 225. If the memory access request hits in L3 cache 225, the requested information is returned to the request processing elements 201 to 204. If the memory access request misses in L3 cache 225, L3 cache 225 forwards the memory access request to DRAM 105. The cache hierarchy 200 also includes cache index 170 and... Figure 1 The cache controller 175.

[0028] Figure 3 This is a block diagram illustrating an example 300 of a cache line that shares the same memory page as the cache line being evicted, according to some embodiments. Example 300 shows a cache 302 corresponding to a level of cache hierarchy 155 and includes multiple cache lines 304 to 311. Each of cache lines 304 to 311 is allocated by CPU 140 to a page of DRAM 105. For example, cache line 304 stores data allocated to a memory address corresponding to a given DRAM page designated PG 1, while cache line 305 stores data allocated to a different DRAM page designated PG 2.

[0029] In response to the identification of cache line 304 for eviction, cache controller 175 performs a search of cache 302 to locate cache lines in a modified state (sometimes referred to as "dirty" cache lines) associated with the same memory page—i.e., DRAM PG 1—and in a modified state. Therefore, in example 300, cache controller 175 identifies cache lines 308 and 309. Cache controller 175 then writes each of cache lines 304, 308, and 309 to DRAM 105, invalidating cache line 304. Furthermore, cache controller 175 sets cache lines 308 and 309 to an unmodified state and keeps each of cache lines 308 and 309 in a valid state. Thus, cache controller 175 flushes the data associated with the same memory page as the cache line 304 being evicted, thereby improving write locality of the processing system 100.

[0030] Figure 4 This is a flowchart illustrating a method 400 for improving write locality in a processing system according to some implementation schemes. (Compared to...) Figure 1Method 400 is described using an exemplary implementation at processing system 100. Method 400 begins at block 402, where cache controller 175 identifies a cache line for eviction from cache hierarchy 155 to DRAM 105 in response to, for example, receiving data designated for storage at a cache line. At block 404, cache controller 175 searches the cache for a modified (i.e., dirty) cache line associated with the same memory page in DRAM. At block 406, cache controller 175 writes both the cache line identified for eviction at block 402 and the dirty cache line identified at block 404 to the corresponding memory page in DRAM 105. At block 408, cache controller 175 invalidates the evicted cache line, thereby indicating that the cache line is ready to store incoming data. At block 410, cache controller 175 sets the dirty cache line identified at block 404 to an unmodified (i.e., clean) state, but keeps the cache line in an active state to indicate that the cache line cannot be used to store data associated with different memory addresses.

[0031] In some implementations, the cache controller 175 can further improve memory management by storing data associated with the same memory page at the cache line associated with the same index. By storing data in this manner, it is possible to... Figure 4 Method 400 quickly and efficiently flushes data to the same memory page. An exemplary method 500, according to some embodiments, stores cache lines sharing the same memory page at the same index in the cache. Relative to... Figure 1 The method 500 is described using an exemplary implementation at the processing system 100. At block 502, cache controller 175 receives data to be stored in the cache of cache hierarchy 155. At block 504, cache controller 175 identifies a memory page of DRAM 105 for the memory address of the received data. At block 506, cache controller 175 identifies an index of the cache corresponding to the memory page identified at block 504. At block 508, cache controller 175 stores the received data at the cache line of the identified index.

[0032] In some implementations, the above-described devices and techniques are used in systems including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips) (such as those described above). Figures 1 to 5The processing system 100 described is implemented. Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used for the design and fabrication of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representing one or more IC devices to perform at least a portion of a process for designing or modifying a manufacturing system to fabricate said circuits. This code may include instructions, data, or a combination of instructions and data. Software instructions representing design or fabrication tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or fabrication of the IC device may be stored in and accessed from the same or different computer-readable storage media.

[0033] Computer-readable storage media can include any non-transitory storage media or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media can include, but are not limited to, optical media (e.g., compact optical discs (CDs), digital versatile optical discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tapes, or magnetic hard disks), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or microelectromechanical systems (MEMS) based storage media. Computer-readable storage media can be embedded in a computing system (e.g., system RAM or ROM), fixedly attached to a computing system (e.g., magnetic hard disks), removably attached to a computing system (e.g., optical discs or USB-based flash memory), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage devices (NAS)).

[0034] In some implementations, certain aspects of the above-described techniques may be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer-readable storage medium. The software may include instructions and certain data that, when executed by one or more processors, instruct the one or more processors to perform one or more aspects of the above-described techniques. The non-transitory computer-readable storage medium may include, for example, disk or optical disk storage devices, solid-state storage devices (such as flash memory), caches, random access memory (RAM), or other non-volatile memory devices. The executable instructions stored on the non-transitory computer-readable storage medium may be in the form of source code, assembly language code, object code, or other instruction formats that are interpreted or executable by one or more processors.

[0035] Please note that not all activities or elements described in the general description above are required, and a particular activity or device may not be necessary. Furthermore, one or more further activities or elements may be performed in addition to those described. The order in which the activities are listed is not necessarily the order in which they are performed. Additionally, the concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and variations can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are intended to be included within the scope of this disclosure.

[0036] The benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, the aforementioned benefits, advantages, solutions to problems, and any features that may cause any benefit, advantage, or solution to appear or become more significant should not be construed as key, essential, or necessary features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways readily apparent to those skilled in the art who have benefited from the teachings herein. There are no limitations on the details of the constructions or designs shown herein, except as described in the appended claims. Therefore, it is apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A method for improving write locality in a processing system, comprising: The processor identifies a first cache line from the cache for eviction, the first cache line storing first data associated with a memory page; as well as In response to the identification of the first cache line used for eviction: Search the cache to find other cache lines that store data associated with the memory page and have multiple indices, including the first index; In response to searching the cache, a second cache line storing second data associated with the memory page is identified; as well as In response to the identification of the second cache line, the first data and the second data are written to the memory page. The first index in the plurality of indexes of the cache refers to the first and second cache lines, and The first data and the second data are stored based on the first index.

2. The method of claim 1, further comprising: In response to writing the second data to the memory page, the second cache line is set to a clean state at the cache.

3. The method of claim 2, further comprising: In response to setting the second cache line to the clean state, the second cache line is kept in an active state at the cache.

4. The method of claim 3, further comprising: In response to writing the first data to the memory page, the first cache line is set to an invalid state at the cache.

5. The method of claim 1, further comprising: The second data is received at the cache before the first data for eviction is identified; as well as In response to receiving the second data, and in response to recognizing that both the first data and the second data are stored at the memory page, the second data is stored in the second cache line, wherein the second index of the plurality of indices refers to the third cache line, and wherein the third cache line stores the third data associated with the second memory page, which is different from the memory page associated with the first and second cache lines.

6. The method of claim 5, further comprising: In response to identifying the first cache line for eviction, a search is performed on the cache line associated with the first index to locate the data associated with the memory page.

7. The method of claim 1, further comprising: In response to searching the cache: Identify the third cache line associated with the memory page; as well as In response to the identification of the third cache line, the data of the third cache line is written to the memory page.

8. The method of claim 1, wherein the first cache line and the second cache line have addresses separated by addresses of a plurality of other cache lines of the cache.

9. A method for improving write locality in a processing system, comprising: In response to the identification of a first cache line for eviction from the cache, the first cache line storing first data associated with a first memory page: Identify, at the cache, a first plurality of cache lines storing data corresponding to the first memory page; as well as The cache lines are flushed by writing the data stored in each of the first plurality of cache lines to memory.

10. The method of claim 9, wherein rinsing further comprises: Each of the first plurality of cache lines is kept in an active state at the cache location.

11. The method of claim 9, further comprising: In response to identifying the first cache line for eviction, the first cache line is invalidated at the cache.

12. The method of claim 9, wherein identifying the first plurality of cache lines comprises: Identify the index of the cache associated with the first cache line; as well as Search the cache to find the first plurality of cache lines associated with the index.

13. The method of claim 9, further comprising: In response to identifying a second cache line for evicting from the cache, wherein the second cache line stores second data associated with a second memory page, the second memory page being different from the first memory page: A second plurality of cache lines are identified at the cache location, storing data corresponding to the second memory page; as well as The second plurality of cache lines are flushed from the cache by writing the data stored at each of the second plurality of cache lines to the second memory.

14. The method of claim 13, wherein the first plurality of cache lines and the second plurality of cache lines are associated with different indices of the cache.

15. A processor comprising: A cache configured to store first data on a first cache line and second data on a second cache line, wherein the first data and the second data are associated with memory pages, and the first cache line and the second cache line are associated with a first index among a plurality of indices of the cache, wherein, based on the associated first index among the plurality of indices, the first data is stored at the first cache line and the second data is stored at the second cache line; and The cache controller is configured to: Identify the first cache line used for eviction; In response to identifying the first cache line, the cache is searched to find data that is associated with the memory page and the first index; In response to searching the cache, the second cache line is identified; as well as In response to the identification of the second cache line, the first data and the second data are written to the memory page.

16. The processor of claim 15, wherein in response to writing the second data to the memory page, the cache controller is configured to set the second cache line to a clean state at the cache.

17. The processor of claim 16, wherein In response to setting the second cache line to the clean state, the cache controller is configured to maintain the second cache line in an active state at the cache.

18. The processor of claim 15, wherein The cache controller is configured to: The second data is received at the cache before the first data for eviction is identified; and In response to receiving the second data and in response to recognizing that both the first data and the second data are stored at the memory page, the second data is stored at the second cache line.

19. The processor of claim 18, wherein In response to identifying the first cache line for eviction, the cache controller is configured to search the cache line pointed to by the first index to find data associated with the memory page.

20. The processor of claim 15, wherein In response to the cache controller searching the cache, the cache controller is configured to: Identify the third cache line associated with the memory page; and In response to the identification of the third cache line, the third data of the third cache line is written to the memory page.

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