Semiconductor device

Abstract

A semiconductor device having good electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. An island-shaped insulating layer containing an oxide is provided in contact with a bottom surface of a semiconductor layer containing a metal oxide exhibiting semiconductor characteristics. The insulating layer containing an oxide is provided in contact with a portion that is a channel formation region of the semiconductor layer, and is not provided in a portion that is a low-resistance region.

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a display device. One aspect of the present invention relates to a method of manufacturing a semiconductor device or a display device.

[0002] Note that one aspect of the present invention is not limited to the technical fields described above. Examples of technical fields encompassing one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, methods for driving these devices, and methods for manufacturing these devices. A semiconductor device refers to any device capable of operating by utilizing the characteristics of semiconductors. Background Technology

[0003] Oxide semiconductors using metal oxides have attracted attention as semiconductor materials that can be used in transistors. For example, Patent Document 1 discloses a semiconductor device in which multiple oxide semiconductor layers are stacked, wherein the oxide semiconductor layer used as a channel contains indium and gallium, and the proportion of indium is higher than that of gallium, thereby improving the field-effect mobility (sometimes simply referred to as mobility or μFE).

[0004] Since metal oxides, which can be used as semiconductor layers, can be formed using methods such as sputtering, they can be used as semiconductor layers for transistors in large display devices. Furthermore, because a portion of the production equipment used for transistors using polycrystalline silicon or amorphous silicon can be modified and utilized, equipment investment can be reduced. Moreover, compared to transistors using amorphous silicon, transistors using metal oxides have higher field-effect mobility, thus enabling high-performance display devices with driving circuitry.

[0005] Furthermore, Patent Document 2 discloses a thin-film transistor using an oxide semiconductor film, wherein the source and drain regions include low-resistance regions comprising at least one of aluminum, boron, gallium, indium, titanium, silicon, germanium, tin, and lead as dopants.

[0006] [Preliminary Technology Documents]

[0007] [Patent Literature]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2014-7399

[0009] [Patent Document 2] Japanese Patent Application Publication No. 2011-228622 Summary of the Invention

[0010] The technical problem that the invention aims to solve

[0011] One objective of this invention is to provide a semiconductor device with good electrical characteristics. Another objective of this invention is to provide a semiconductor device with stable electrical characteristics. Yet another objective of this invention is to provide a semiconductor device with high reliability.

[0012] Note that the description of these objectives does not preclude the existence of other objectives. Also note that one embodiment of the invention does not necessarily require achieving all of the above objectives. Furthermore, objectives other than those described above can be extracted from the description in the specification, drawings, claims, etc.

[0013] means of solving technical problems

[0014] One aspect of the present invention is a semiconductor device comprising a first insulating layer, a second insulating layer, a third insulating layer, a semiconductor layer, and a first conductive layer. The second insulating layer is located on the first insulating layer and has an island-like shape. The semiconductor layer has portions contacting the top surface of the second insulating layer and portions contacting the top surface of the first insulating layer, and also has an island-like shape. The third insulating layer and the first conductive layer are sequentially stacked on the semiconductor layer. The second insulating layer is disposed at least in the region where the first conductive layer and the semiconductor layer overlap. Furthermore, the semiconductor layer extends outward beyond a pair of ends of the second insulating layer in the channel length direction and is located inside the pair of ends of the second insulating layer in the channel width direction. Additionally, the semiconductor layer comprises a metal oxide, the first insulating layer comprises a metal oxide or a nitride, and the second and third insulating layers comprise oxides.

[0015] Furthermore, in the above structure, a second conductive layer and a third conductive layer are preferably included. Preferably, the second conductive layer and the third conductive layer are disposed separately from each other, sandwiching a second insulating layer, and each contacts the semiconductor layer in a region where the second insulating layer is not disposed.

[0016] Furthermore, in the above structure, a fourth insulating layer is preferably included. Preferably, the fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer, having a portion that contacts a portion of the top surface of the semiconductor layer in an area where the second insulating layer is not provided, and a portion that contacts the first insulating layer on the outer side of the end of the semiconductor layer. Furthermore, the fourth insulating layer preferably comprises a metal oxide or a nitride.

[0017] Furthermore, in the above structure, the fourth insulating layer preferably comprises silicon nitride or aluminum nitride.

[0018] Furthermore, in the above structure, the first insulating layer preferably comprises silicon nitride or aluminum oxide.

[0019] Furthermore, in the above structure, a fourth conductive layer is preferably included below the first insulating layer. In this case, the fourth conductive layer preferably has a region that completely overlaps with the semiconductor layer, the first conductive layer, and the second insulating layer.

[0020] Furthermore, in the above structure, it is preferable to include a fifth insulating layer in the region where the second and fourth conductive layers overlap, where there is no semiconductor layer. In this case, the fifth insulating layer is preferably located on the same surface as the second insulating layer and contains the same material as the second insulating layer.

[0021] Furthermore, in the above structure, a metal oxide layer is preferably included between the third insulating layer and the first conductive layer. In this case, the metal oxide layer and the semiconductor layer preferably contain the same metal element. Additionally, the metal oxide layer preferably contains aluminum or hafnium.

[0022] Invention Effects

[0023] According to one aspect of the present invention, a semiconductor device with good electrical characteristics can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device with stable electrical characteristics can be provided. Additionally, according to one aspect of the present invention, a display device with high reliability can be provided.

[0024] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the invention does not necessarily require all of the aforementioned effects. Additionally, effects other than those described above can be extracted from the description in the specification, drawings, claims, etc. Attached Figure Description

[0025] [Figure 1] Example of a transistor structure.

[0026] [Figure 2] Example of a transistor structure.

[0027] [Figure 3] Example of a transistor structure.

[0028] [Figure 4] Example of a transistor structure.

[0029] [ Figure 5 Example of pixel structure.

[0030] [Figure 6] A diagram illustrating the manufacturing process of a transistor.

[0031] [Figure 7] A diagram illustrating the manufacturing process of a transistor.

[0032] [Figure 8] A diagram illustrating the manufacturing process of a transistor.

[0033] [Figure 9] Top view of the display device.

[0034] [ Figure 10 Cross-sectional view of the display device.

[0035] [ Figure 11 Cross-sectional view of the display device.

[0036] [ Figure 12 Cross-sectional view of the display device.

[0037] [Figure 13] Block diagram and circuit diagram of the display device.

[0038] [Figure 14] Circuit diagram of the display device.

[0039] [Figure 15] shows an example of the structure of the display module.

[0040] [Figure 16] Example of the structure of an electronic device.

[0041] [Figure 17] Example of the structure of an electronic device.

[0042] [Figure 18] Example of the structure of an electronic device.

[0043] [Figure 19] Electrical characteristics of a transistor according to an embodiment. Detailed Implementation

[0044] The embodiments will now be described with reference to the accompanying drawings. However, the embodiments can be implemented in many different ways, and those skilled in the art will readily understand that the methods and details can be varied in many ways without departing from the spirit and scope of the invention. Therefore, the invention should not be construed as being limited to the contents described in the embodiments shown below.

[0045] In the accompanying drawings described in this specification, the size of the structures, the thickness of the layers, or the area are sometimes exaggerated for clarity.

[0046] The ordinal numbers “first,” “second,” “third,” etc., used in this specification are added to avoid confusion of the constituent elements, not to limit the quantity.

[0047] In this specification, for convenience, terms such as "upper" and "lower" are used to indicate the arrangement and to illustrate the positional relationships of the constituent elements with reference to the accompanying drawings. Furthermore, the positional relationships of the constituent elements may be appropriately changed depending on the direction in which each structure is described. Therefore, the use of terms not limited to those described in the specification may be substituted as appropriate.

[0048] Furthermore, in this specification and other documents, when using transistors with different polarities or when the current direction changes during circuit operation, the functions of the source and drain of the transistor are sometimes interchanged. Therefore, the "source" and "drain" can be interchanged.

[0049] In this specification, "electrical connection" includes connections made via "elements that have a certain electrical function." Here, "elements that have a certain electrical function" are not particularly limited as long as they can transmit and receive electrical signals between the connected objects. For example, "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0050] Furthermore, in this specification and other materials, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be changed to "conductive film." Also, for example, "insulating layer" may sometimes be changed to "insulating film."

[0051] Furthermore, in this specification and other documents, unless otherwise specified, off-state current refers to the drain current when the transistor is in the off state (also known as the non-conducting state or the blocked state). Unless otherwise specified, in an n-channel transistor, the off state refers to the state where the gate-source voltage Vgs is lower than the threshold voltage Vth (in a p-channel transistor, Vgs is higher than Vth).

[0052] In this specification and the like, a display panel, as used in one type of display device, refers to a panel capable of displaying (outputting) images, etc., on a display surface. Therefore, a display panel is one type of output device.

[0053] Furthermore, in this specification and the like, a structure in which connectors such as FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) are mounted on the substrate of a display panel, or a structure in which ICs (integrated circuits) are directly mounted on the substrate in the form of COG (Chip On Glass), is sometimes referred to as a display panel module or display module, or simply a display panel, etc.

[0054] Note that, as described in this specification, the touch panel of one type of display device has the following functions: displaying images on the display surface; and functioning as a touch sensor to detect when a detected object such as a finger or stylus touches, presses, or approaches the display surface. Therefore, the touch panel is one type of input / output device.

[0055] A touch panel can also be referred to as a display panel (or display device) with a touch sensor, or a display panel (or display device) with touch sensor functionality. A touch panel may also include a display panel and a touch sensor panel. Alternatively, it may have a structure in which a touch sensor is located inside or on the surface of the display panel.

[0056] Furthermore, in this specification and other documents, the structure on which a connector or IC is mounted on the substrate of the touch panel is sometimes referred to as a touch panel module, display module, or simply touch panel, etc.

[0057] (Implementation Method 1)

[0058] In this embodiment, a semiconductor device, a display device, and a method for manufacturing the same according to one aspect of the present invention will be described.

[0059] One aspect of the present invention is a transistor comprising a semiconductor layer forming a channel on a formed surface, a gate insulating layer (also referred to as a third insulating layer) on the semiconductor layer, and a gate electrode on the gate insulating layer. The semiconductor layer preferably comprises a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting semiconductor properties.

[0060] The top surface shapes of the gate electrode and the gate insulating layer are preferably substantially the same. In other words, the gate electrode and the gate insulating layer are preferably processed to have continuous side surfaces. For example, they can be formed by continuously processing the insulating film that forms the gate insulating layer and the conductive film that forms the gate electrode using the same etching mask. Alternatively, the gate insulating layer can be formed by processing the insulating film using the previously processed gate electrode as a hard mask.

[0061] Additionally, the semiconductor layer has a channel forming region that forms a channel, and a pair of low-resistance regions that serve as source and drain regions. The channel forming region is the region in the semiconductor layer that overlaps with the gate electrode. The pair of low-resistance regions are regions that are positioned to sandwich the channel forming region and have a lower resistance than the channel forming region.

[0062] Note that in this specification, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source and drain regions with the shortest distance. That is, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in the on state. Furthermore, the channel width direction refers to the direction orthogonal to the channel length direction. In addition, depending on the structure and shape of the transistor, the channel length direction and channel width direction are sometimes not limited to one direction.

[0063] Here, it is preferable to provide an island-shaped insulating layer (also called a second insulating layer) containing oxide in contact with the bottom surface of the semiconductor layer. By providing the second insulating layer containing oxide in contact with the semiconductor layer, oxygen that is released due to heating can be effectively supplied to the semiconductor layer to fill oxygen vacancies in the semiconductor layer.

[0064] Furthermore, the second insulating layer containing oxide is preferably disposed in contact with the portion of the channel formation region that forms the semiconductor layer, rather than in the portion that forms the low-resistance region. Thus, the low-resistance region contains more oxygen vacancies than the channel formation region, making it easier to generate charge carriers and achieving a low-resistance region more effectively.

[0065] An insulating layer containing nitride (also called a fourth insulating layer) is provided in such a way that it is in surface contact with the low-resistance region of the semiconductor layer. By providing the insulating layer containing nitride in contact with the semiconductor layer, the conductivity of the low-resistance region can be further improved. Furthermore, it is preferable to perform heat treatment while the insulating layer containing nitride is provided in contact with the semiconductor layer, as this further promotes low resistance.

[0066] The fourth insulating layer is preferably provided in a manner that covers the first conductive layer. This allows the fourth insulating layer to be formed in a way that it does not contact the portion of the semiconductor layer where the first conductive layer is located, i.e., the channel formation region, but only the portion outside the channel formation region. As a result, a low-resistance region with self-aligned low resistance can be formed.

[0067] As nitrides, silicon nitride, gallium nitride, or aluminum nitride are particularly preferred. For example, when using silicon nitride, hydrogen-containing silicon nitride is more preferred. Silicon nitride has a barrier effect against hydrogen or oxygen, thus preventing both hydrogen diffusion from the outside into the semiconductor layer and oxygen detachment from the semiconductor layer to the outside, enabling the realization of highly reliable transistors.

[0068] When using metal nitrides, aluminum is particularly preferred. For example, regarding aluminum nitride films formed by reactive sputtering using aluminum as the sputtering target and a nitrogen-containing gas as the deposition gas, by appropriately controlling the nitrogen gas flow rate ratio relative to the total flow rate of the deposition gas, a film with both extremely high insulation and extremely high barrier properties against hydrogen or oxygen can be formed. Therefore, by providing an insulating film containing such a metal nitride in contact with the semiconductor layer, not only can the resistance of the semiconductor layer be reduced, but oxygen can also be effectively prevented from detaching from the semiconductor layer and hydrogen can diffuse into the semiconductor layer.

[0069] When aluminum nitride is used as the metal nitride, the thickness of the insulating layer containing the aluminum nitride is preferably 5 nm or more. Even such a thin film can simultaneously possess the functions of high barrier properties against hydrogen and oxygen and low resistivity of the semiconductor layer. Furthermore, there is no limitation on the thickness of the insulating layer, but considering productivity, it is preferably 500 nm or less, more preferably 200 nm or less, and even more preferably 50 nm or less.

[0070] As described above, one aspect of the present invention employs a structure in which the second insulating layer has an island-like shape. Furthermore, it is preferable to provide an insulating layer (also referred to as a first insulating layer) that has high barrier properties against water, hydrogen, and oxygen beneath the second insulating layer. The first insulating layer can be a metal oxide or the aforementioned nitride. As a metal oxide, materials containing high barrier properties against hydrogen and oxygen, such as aluminum oxide or hafnium oxide, are particularly preferred.

[0071] Furthermore, a structure is preferably adopted in which the first insulating layer and the fourth insulating layer are in contact on the outside of the island-shaped semiconductor layer and the island-shaped second insulating layer. In other words, a structure is preferably adopted in which the semiconductor layer and the second insulating layer are surrounded (sealed) by the first insulating layer and the fourth insulating layer. As a result, the release of oxygen from the second insulating layer to the outside can be effectively suppressed, and most of the oxygen can be supplied to the portion that becomes the channel formation region of the semiconductor layer.

[0072] By adopting the above structure, semiconductor devices with good electrical characteristics and high reliability can be realized.

[0073] The following description, with reference to the accompanying drawings, illustrates more specific examples.

[0074] [Structure Example 1]

[0075] Figure 1A This is a top view of transistor 100. Figure 1B Equivalent to along Figure 1A The cross-sectional view shown is the dotted-dash line A1-A2. Figure 1C Equivalent to along Figure 1A The cross-sectional view shown is the dotted-dash line B1-B2. Figure 1A In the diagram, some components of transistor 100 (such as the gate insulating layer) are omitted. Additionally, sometimes the direction of the dashed line A1-A2 corresponds to the channel length direction, and the direction of the dashed line B1-B2 corresponds to the channel width direction. Furthermore, in the subsequent top view of the transistor, [the text abruptly ends here]. Figure 1A Similarly, a portion of the constituent elements is omitted.

[0076] A transistor 100 is disposed on a substrate 102 and includes an insulating layer 103, an insulating layer 104, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, an insulating layer 116, and an insulating layer 118. The insulating layer 104 is disposed on the insulating layer 103, and the semiconductor layer 108 is disposed in contact with the top surfaces of the insulating layers 103 and 104. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are sequentially stacked, each covering a portion of the semiconductor layer 108. The insulating layer 116 is disposed to cover the top and side surfaces of the insulating layer 104, the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the top and side surfaces of the conductive layer 112. The insulating layer 118 is disposed to cover the insulating layer 116.

[0077] A portion of the conductive layer 112 is used as a gate electrode. A portion of the insulating layer 110 is used as a gate insulating layer. The transistor 100 is a so-called top-gate transistor in which a gate electrode is disposed on the semiconductor layer 108.

[0078] Semiconductor layer 108 preferably comprises metal oxide.

[0079] For example, semiconductor layer 108 preferably comprises indium, M (M is selected from one or more of gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. In particular, M is preferably aluminum, gallium, yttrium, or tin.

[0080] In particular, as the semiconductor layer 108, an oxide containing indium, gallium and zinc is preferably used.

[0081] The semiconductor layer 108 can also be a stacked structure with layers of different compositions, different crystallinity, or different impurity concentrations.

[0082] Semiconductor layer 108 includes a region overlapping conductive layer 112 and a low-resistance region 108n sandwiching the region. Region 108n is in contact with insulating layer 116. The region of semiconductor layer 108 overlapping conductive layer 112 is used as a channel formation region of transistor 100. On the other hand, region 108n is used as a source region or drain region of transistor 100.

[0083] In addition, such as Figure 1A and Figure 1B As shown, transistor 100 may also include conductive layers 120a and 120b on insulating layer 118. Conductive layers 120a and 120b are used as source electrodes or drain electrodes. Conductive layers 120a and 120b are electrically connected to region 108n through openings 141a and 141b respectively provided in insulating layers 118 and 116.

[0084] In addition, the top surfaces of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 are generally identical in shape.

[0085] In this specification, "generally consistent top surface shape" means that at least a portion of the outline of each layer in the stack overlaps. For example, it means that part or all of the upper and lower layers are processed through the same mask pattern. However, there are actually cases where the outlines do not overlap, such as when the upper layer is inside or outside the lower layer, and in these cases, it can also be said that the "top surface shape is generally consistent".

[0086] The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 serves as a barrier film to prevent oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side. Furthermore, the metal oxide layer 114 also serves as a barrier film to prevent hydrogen or water contained in the conductive layer 112 from diffusing to the insulating layer 110 side. The metal oxide layer 114 can be, for example, made of a material that is at least less permeable to oxygen and hydrogen than the insulating layer 110.

[0087] By utilizing the metal oxide layer 114, even if a material that readily absorbs oxygen, such as aluminum or copper, is used in the conductive layer 112, oxygen diffusion from the insulating layer 110 to the conductive layer 112 can be prevented. Furthermore, even if the conductive layer 112 contains hydrogen, the supply of hydrogen from the conductive layer 112 through the insulating layer 110 to the semiconductor layer 108 can be suppressed. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0088] The metal oxide layer 114 can be made of either an insulating or conductive material. When the metal oxide layer 114 is insulating, it is used as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 is conductive, it is used as part of the gate electrode.

[0089] In particular, as the metal oxide layer 114, an insulating material with a higher dielectric constant than silicon oxide is preferably used. In particular, an alumina film, a hafnium oxide film, or a hafnium aluminate film is preferably used.

[0090] Furthermore, the metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when forming an alumina film using a sputtering apparatus, oxygen can be appropriately added to the insulating layer 110 or the semiconductor layer 108 by forming the alumina film in an atmosphere containing oxygen gas. In addition, the film density can be increased when forming an alumina film using a sputtering apparatus, so this is preferred.

[0091] Alternatively, the oxide semiconductor material that can be used in the semiconductor layer 108 can be used as the metal oxide layer 114. In this case, since the equipment can be shared by using a metal oxide film formed using the same sputtering target as the semiconductor layer 108, it is preferable.

[0092] Furthermore, when both the semiconductor layer 108 and the metal oxide layer 114 use metal oxide materials containing indium and gallium, it is preferable to use a material with a higher gallium content (content ratio) than the semiconductor layer 108 to improve oxygen barrier properties. In this case, by using a material with a higher indium content than the metal oxide layer 114 in the semiconductor layer 108, the field-effect mobility of the transistor 100 can be improved.

[0093] The insulating layer 116 may be an insulating film containing nitrides. For example, nitrides of semiconductor materials such as silicon nitride and gallium nitride, or metal nitrides such as aluminum nitride, may be used. The insulating film containing metal nitrides preferably contains at least one of the metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium, as well as nitrogen. Films containing aluminum and nitrogen are particularly preferred because the insulation is extremely high at this time.

[0094] When using aluminum nitride film as the insulating layer 116, it is preferable to use a film whose composition satisfies AlN x (x is a real number greater than 0 and less than 2, preferably a real number greater than 0.5 and less than 1.5) film. Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation of heat generated when driving the transistor 100.

[0095] Alternatively, as the insulating layer 116, aluminum titanium nitride film, titanium nitride film, etc. can be used.

[0096] Region 108n is part of semiconductor layer 108 and has a lower resistance than the channel formation region.

[0097] Here, when using an indium-containing metal oxide film as the semiconductor layer 108, regions where indium oxide is deposited or regions with high indium concentrations sometimes form near the interface on the insulating layer 116 side of region 108n. This can sometimes be observed using analytical techniques such as X-ray photoelectron spectroscopy (XPS).

[0098] Furthermore, region 108n can also be described as a region with a higher carrier concentration, a higher oxygen vacancy density, or an n-type region compared to the channel formation region.

[0099] Furthermore, the insulating layers 104 and 110, which are in contact with the channel formation region of the semiconductor layer 108, are preferably made of oxide films. For example, oxide films such as silicon oxide films, silicon oxynitride films, and aluminum oxide films can be used. As a result, oxygen detached from the insulating layer 104 or insulating layer 110 is supplied to the channel formation region of the semiconductor layer 108 through heat treatment or the like in the manufacturing process of the transistor 100, thereby reducing oxygen vacancies in the semiconductor layer 108.

[0100] As the insulating layer 103 disposed on the lower side (substrate 102 side) of the insulating layer 104, it is preferable to use an insulating film that does not easily diffuse oxygen and hydrogen. In particular, metal oxide films such as alumina films, hafnium oxide films or hafnium aluminate films, or nitrogen-containing insulating films such as aluminum nitride, aluminum oxynitride, silicon nitride, and silicon oxynitride can be used.

[0101] Alumina films, hafnium oxide films, and hafnium aluminate films exhibit extremely high barrier properties even when thin. Therefore, their thickness can be 0.5 nm or more and 50 nm or less, preferably 1 nm or more and 40 nm or less, and more preferably 2 nm or more and 30 nm or less. In particular, alumina films have high barrier properties against hydrogen and the like, thus achieving sufficient effect even with extremely thin thicknesses (e.g., 0.5 nm or more and 1.5 nm or less). Furthermore, they can be formed using deposition methods such as sputtering or atomic layer deposition (ALD).

[0102] Here, both the semiconductor layer 108 and the insulating layer 104 are processed into island shapes. Figure 1A In the image, the outline of the insulating layer 104 is shown in dashed lines.

[0103] The end of the insulating layer 104 in the channel length direction is located inside the end of the semiconductor layer 108. On the other hand, the end in the channel width direction is located outside the end of the semiconductor layer 108. In other words, it can be said that the semiconductor layer 108 extends outward beyond the pair of ends of the insulating layer 104 in the channel length direction and is located inside the pair of ends of the insulating layer 104 in the channel width direction.

[0104] An insulating layer 104 is provided in a manner that overlaps with the channel forming region of the semiconductor layer 108. Furthermore, regions 108n of the semiconductor layer 108 have areas that do not overlap with the insulating layer 104. Preferably, the insulating layer 104 is not provided at least in the portions of region 108n that contact the conductive layer 120a and those that contact the conductive layer 120b.

[0105] In addition, such as Figure 1B and Figure 1C As shown, in the region outside the semiconductor layer 108 and the insulating layer 104, the insulating layer 103 and the insulating layer 116 are in contact. Therefore, a structure in which the semiconductor layer 108 and the insulating layer 104 are sealed by the insulating layer 103 and the insulating layer 116 can be realized. Due to this structure, the diffusion of hydrogen from the outside into the semiconductor layer 108 and the insulating layer 104 of the transistor 100, as well as the diffusion of oxygen from the semiconductor layer 108 and the insulating layer 104 to the outside, can be effectively suppressed.

[0106] Furthermore, insulating layer 118 sometimes contains hydrogen; however, insulating layers 104 and 110, which are in contact with semiconductor layer 108 and include oxide films, are insulating layers 116 and therefore do not contact insulating layer 118. Thus, even when insulating layer 118 contains hydrogen, it is effectively prevented that the hydrogen from diffusing through insulating layers 104 and 110 to semiconductor layer 108 due to heat or other factors applied during the manufacturing process of transistor 100.

[0107] Here, the semiconductor layer 108 and the oxygen vacancies that may be formed in the semiconductor layer 108 will be explained.

[0108] Oxygen vacancies formed in semiconductor layer 108 can affect transistor characteristics and cause problems. For example, when oxygen vacancies are formed in semiconductor layer 108, they can sometimes bond with hydrogen to become carrier supply sources. When carrier supply sources are generated in semiconductor layer 108, the electrical characteristics of transistor 100 change, typically resulting in a shift in the threshold voltage. Therefore, fewer oxygen vacancies in semiconductor layer 108 are preferable.

[0109] Therefore, in one aspect of the present invention, the insulating film near the semiconductor layer 108, specifically the insulating layer 110 above the semiconductor layer 108 and the insulating layer 104 below the semiconductor layer 108, comprises an oxide film. By moving oxygen from the insulating layer 104 and the insulating layer 110 to the semiconductor layer 108 using heating or the like in the manufacturing process, oxygen vacancies in the semiconductor layer 108 can be reduced.

[0110] Furthermore, the semiconductor layer 108 preferably includes regions where the atomic ratio of In is greater than the atomic ratio of M. The higher the atomic ratio of In, the higher the field-effect mobility of the transistor.

[0111] In metal oxides containing In, Ga, and Zn, the bonding force between In and oxygen is weaker than that between Ga and oxygen. Therefore, when the number of In atoms is relatively large, oxygen vacancies tend to form in the metal oxide film. Furthermore, the same tendency exists when the metal element shown in M ​​above is used instead of Ga. When there are many oxygen vacancies in the metal oxide film, the electrical characteristics and reliability of the transistor decrease.

[0112] However, in one aspect of the present invention, an extremely large amount of oxygen can be supplied to the semiconductor layer 108 comprising metal oxide, thereby allowing the use of metal oxide materials with a high atomic ratio of In. Therefore, transistors with extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0113] For example, metal oxides in which the atomic number of In is 1.5 times, 2 times, 3 times, 3.5 times, or 4 times that of M can be appropriately used.

[0114] In particular, the atomic ratio of In, M, and Zn in the semiconductor layer 108 is preferably In:M:Zn = 5:1:6 or close to thereafter (when In is 5, this includes cases where M is 0.5 or more but less than 1.5, and Zn is 5 or more but less than 7). Furthermore, the atomic ratio of In, M, and Zn is preferably In:M:Zn = 4:2:3 or close to thereafter. Additionally, in the composition of the semiconductor layer 108, the atomic ratio of In, M, and Zn can also be approximately equal. That is, the semiconductor layer 108 can contain materials with an atomic ratio of In, M, and Zn of In:M:Zn = 1:1:1 or close to thereafter.

[0115] For example, by using the aforementioned high field-effect mobility transistors in a gate driver to generate gate signals, a display device with a narrow bezel width (also known as a narrow bezel) can be provided. Furthermore, by using the aforementioned high field-effect mobility transistors in a source driver (especially a demultiplexer connected to the output terminal of a shift register included in the source driver), a display device with fewer wiring connections to the display device can be provided.

[0116] Note that even when the semiconductor layer 108 includes regions where the atomic ratio of In is greater than that of M, the field-effect mobility may sometimes decrease when the crystallinity of the semiconductor layer 108 is high. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD) or transmission electron microscopy (TEM).

[0117] Here, impurities such as hydrogen or moisture mixed into the semiconductor layer 108 cause problems by affecting the transistor characteristics. Therefore, the less impurities such as hydrogen or moisture in the semiconductor layer 108, the better. It is preferable to use a metal oxide film with low impurity concentration and low defect state density to manufacture transistors with good electrical characteristics. By making the impurity concentration low and the defect state density low (making oxygen vacancies less), the carrier density in the film can be reduced. Transistors using this metal oxide film as the semiconductor layer rarely have the electrical characteristic of negative threshold voltage (also known as normally-on characteristic). In addition, transistors using this metal oxide film have the characteristic of extremely low off-state current.

[0118] In addition, the semiconductor layer 108 can also have a stacked structure of two or more layers.

[0119] For example, a semiconductor layer 108 formed by stacking two or more metal oxide films of different compositions can be used. For example, when using In-Ga-Zn oxide, it is preferable to stack two or more films formed using sputtering targets with an In:M:Zn atomic ratio of In:M:Zn = 5:1:6, In:M:Zn = 4:2:3, In:M:Zn = 1:1:1, In:M:Zn = 2:2:1, In:M:Zn = 1:3:4, In:M:Zn = 1:3:2 or close to thereof.

[0120] Alternatively, a semiconductor layer 108 can be formed by stacking two or more metal oxide films with different crystallinity. In this case, it is preferable to use the same oxide target material to continuously form the metal oxide film under different deposition conditions in a manner that does not expose it to the atmosphere.

[0121] For example, the oxygen flow rate during the formation of the first metal oxide film is set to be smaller than the oxygen flow rate during the formation of the second metal oxide film. Alternatively, conditions are adopted in which no oxygen is introduced during the formation of the first metal oxide film. This allows for efficient oxygen supply during the formation of the second metal oxide film. Furthermore, the first metal oxide film may have lower crystallinity and higher conductivity than the second metal oxide film. On the other hand, by making the crystallinity of the second metal oxide film disposed on the upper part higher than that of the first metal oxide film, damage caused during the processing of the semiconductor layer 108 or the formation of the insulating layer 110 can be suppressed.

[0122] More specifically, the oxygen flow rate during the formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and less than 30%, more preferably 0% or more and less than 20%, and typically 10%. The oxygen flow rate during the formation of the second metal oxide film is 50% or more and less than 100%, preferably 60% or more and less than 100%, more preferably 80% or more and less than 100%, and even more preferably 90% or more and less than 100%, and typically 100%. Furthermore, although the pressure, temperature, power, and other conditions during the formation of the first and second metal oxide films can be different, it is preferable to keep the conditions other than the oxygen flow rate the same, as this can shorten the time required for the film formation process.

[0123] By adopting the above structure, a transistor 100 with good electrical characteristics and high reliability can be realized.

[0124] The above is an explanation of structural example 1.

[0125] [Structure Example 2]

[0126] The following describes a transistor structure example whose structure differs from that of example 1 described above. Sometimes, descriptions of parts that overlap with those in example 1 are omitted. Furthermore, in the accompanying drawings shown below, parts having the same function as those in the example above are depicted using the same shading lines, and sometimes reference numerals are not added.

[0127] Figure 2A This is a top view of transistor 100A. Figure 2B It is a cross-sectional view along the channel length of transistor 100A. Figure 2C This is a cross-sectional view of the channel width of transistor 100A.

[0128] The main difference between transistor 100A and structure example 1 is that a conductive layer 106 is included between substrate 102 and insulating layer 103. The conductive layer 106 has a region that overlaps with semiconductor layer 108 and conductive layer 112 through insulating layer 104 and insulating layer 103.

[0129] In transistor 100A, conductive layer 106 functions as a first gate electrode (also known as a bottom gate electrode), and conductive layer 112 functions as a second gate electrode (also known as a top gate electrode). Furthermore, a portion of insulating layer 103 and insulating layer 104 are used as a first gate insulating layer, and a portion of insulating layer 110 is used as a second gate insulating layer.

[0130] The portion of the semiconductor layer 108 that overlaps with at least one of the conductive layers 112 and 106 is used as a channel forming region. Hereinafter, for ease of explanation, the portion of the semiconductor layer 108 that overlaps with the conductive layer 112 is sometimes referred to as the channel forming region, but in practice, the channel is sometimes also formed in the portion that does not overlap with the conductive layer 112 but overlaps with the conductive layer 106 (including the portion of region 108n).

[0131] In addition, such as Figure 2C As shown, the conductive layer 106 can be electrically connected to the conductive layer 112 through openings 142 provided in the metal oxide layer 114, the insulating layer 110, and the insulating layer 103. Therefore, the same potential can be supplied to the conductive layer 106 and the conductive layer 112.

[0132] As conductive layer 106, the same material as conductive layer 112, conductive layer 120a, or conductive layer 120b can be used. In particular, it is preferred to use a material containing copper for conductive layer 106, as this can reduce wiring resistance.

[0133] In addition, such as Figure 2A and Figure 2C As shown, preferably, the conductive layer 112 and conductive layer 106 protrude to the outer side of the end of the semiconductor layer 108 in the channel width direction. At this time, as... Figure 2CAs shown, conductive layers 112 and 106 cover the entire channel width direction of semiconductor layer 108 through insulating layers 110 and 104.

[0134] By employing the above structure, an electric field generated by a pair of gate electrodes can be used to surround the semiconductor layer 108. In this case, it is particularly preferable to supply the conductive layer 106 and the conductive layer 112 with the same potential. This allows for the effective application of an electric field to induce a channel in the semiconductor layer 108, thereby increasing the on-state current of the transistor 100A. Therefore, miniaturization of the transistor 100A can be achieved.

[0135] Alternatively, conductive layer 112 may not be connected to conductive layer 106. In this case, a fixed potential can be supplied to one of the pair of gate electrodes, and a signal for driving transistor 100A can be supplied to the other. In this case, the threshold voltage when driving transistor 100A with the other electrode can be controlled by utilizing the potential supplied to one electrode.

[0136] Transistor 100A is an example in which insulating layer 104 is disposed inside conductive layer 106. That is, it is manufactured in such a way that, in the channel length direction of transistor 100A, the end of insulating layer 104 is located inside the end of conductive layer 106, and in the channel width direction, the end of insulating layer 104 is located inside the end of conductive layer 106.

[0137] In addition, such as Figure 2A As shown, an insulating layer 104a is provided at the intersection of conductive layer 106 and conductive layer 120a, and at the intersection of conductive layer 106 and conductive layer 120b.

[0138] Figure 2B The intersection of conductive layer 120b and conductive layer 106 is shown. Insulating layer 104a is an insulating layer located on the same surface as insulating layer 104 and containing the same material as insulating layer 104. For example, insulating layer 104a can be formed by processing the same insulating film as insulating layer 104. By distributing insulating layer 104a at the intersection of conductive layer 120b and conductive layer 106, the parasitic capacitance between conductive layer 120b and conductive layer 106 can be reduced.

[0139] Note that this example describes the placement of an insulating layer 104a at the intersection of conductive layer 106 and conductive layer 120a or conductive layer 120b, but it is not limited to this. For example, by placing an insulating layer 104a at the intersection of conductive layer 112 (or wiring obtained by processing a conductive film identical to conductive layer 112) or wiring obtained by processing a semiconductor film identical to semiconductor layer 108 with conductive layer 106, parasitic capacitance can be reduced in the same way as described above.

[0140] The above is an explanation of structural example 2.

[0141] [Example of variation]

[0142] The following describes a variation of structural example 2.

[0143] [Example of variation 1]

[0144] Figure 3A , Figure 3B and Figure 3C The transistor 100B shown is an example of a case where the insulating layer 104 is processed using the same photomask as the conductive layer 112.

[0145] When viewed from above, the outlines of the insulating layer 104 and the conductive layer 112 are roughly the same. However, depending on the processing conditions of the insulating layer 104 or the conductive layer 112, sometimes the outline of the insulating layer 104 is located inside the outline of the conductive layer 112, or sometimes the outline of the insulating layer 104 is located outside the outline of the conductive layer 112.

[0146] Thus, by sharing the photomask used in the processing of insulating layer 104 and conductive layer 112, manufacturing costs can be reduced.

[0147] Note that this illustration shows the conductive layer 112 having an island shape and a portion of the conductive layer 106 being used for wiring; however, a layout pattern where the conductive layer 106 has an island shape and a portion of the conductive layer 112 is used for wiring is also possible. In this case, the insulating layer 104 can be fabricated using the same photomask as the conductive layer 106.

[0148] [Variation Example 2]

[0149] Figure 4A The cross section shown in the width direction of the channel is... Figure 2C The main difference lies in the length of the channel width of the insulating layer 104.

[0150] exist Figure 4A The following situation is shown: the end of the insulating layer 104 in the channel width direction is located outside the end of the conductive layer 112 in the channel width direction, and inside the end of the conductive layer 106 in the channel width direction.

[0151] In addition, conductive layer 112 and conductive layer 106 are electrically connected through openings 142 formed in metal oxide layer 114, insulating layer 110, insulating layer 104 and insulating layer 103.

[0152] [Example 3]

[0153] Figure 4BFor example, the end of the insulating layer 104 in the channel width direction is located inside the end of the conductive layer 112 in the channel width direction and the end of the conductive layer 106 in the channel width direction, and the insulating layer 104 is located in the portion forming the opening 142.

[0154] [Example 4]

[0155] Figure 4C For example, the end of the insulating layer 104 in the channel width direction is located outside the end of the conductive layer 112 in the channel width direction and the end of the conductive layer 106 in the channel width direction.

[0156] The above is an explanation of the variation examples.

[0157] [Application Examples]

[0158] The following describes an example of using the aforementioned transistors as pixels in a display device.

[0159] Figure 5 This is a top view schematic of a display device in which multiple sub-pixels are configured in a matrix. Each sub-pixel includes at least one transistor 100 and a conductive layer 131 electrically connected to the transistor 100 and used as a pixel electrode. Note that a simplified sub-pixel structure is shown here; other transistors or capacitors may be appropriately provided depending on the display element used for the sub-pixel.

[0160] exist Figure 5 In this configuration, conductive layer 112 is used as a gate line (also known as a scan line), conductive layer 120a is used as a source line (also known as a signal line or video signal line), and conductive layer 120b is used as wiring to electrically connect transistor 100 and conductive layer 131.

[0161] exist Figure 5 In this configuration, an insulating layer 104 with an island-like shape is provided for each transistor. The insulating layer 104 is configured to include the channel forming region of the semiconductor layer 108 of the transistor 100 and is not provided at the connection portions (openings 141a and 141b) between the conductive layer 120a and the conductive layer 120b and the semiconductor layer 108.

[0162] In addition, Figure 5 An insulating layer 104a is provided at the intersection of conductive layer 112 and conductive layer 120a.

[0163] The transistor of one embodiment of the present invention can be used not only in display devices but also in various circuits or devices. For example, it can be suitably used in various circuits such as arithmetic circuits, storage circuits, driving circuits, and interface circuits installed in IC chips in electronic devices, or in display devices using liquid crystal elements or organic EL elements, and in driving circuits in various sensing devices.

[0164] The above are examples of applications.

[0165] [Components of a Semiconductor Device]

[0166] The constituent elements of the semiconductor device of this embodiment will be described in detail below.

[0167] [Substrate]

[0168] While there are no particular restrictions on the material of the substrate 102, it must at least possess heat resistance capable of withstanding subsequent heat treatments. For example, single-crystal or polycrystalline semiconductor substrates made of silicon or silicon carbide, compound semiconductor substrates such as silicon-germanium, SOI substrates, glass substrates, ceramic substrates, quartz substrates, sapphire substrates, etc., can be used as substrate 102. Alternatively, substrates on which semiconductor elements are disposed may also be used as substrate 102.

[0169] Furthermore, a flexible substrate can be used as substrate 102, and transistors such as 100 can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between substrate 102 and transistors such as 100. A release layer can be used when a part or all of a semiconductor device is fabricated on the release layer, and then it is separated from substrate 102 and transferred to another substrate. In this case, transistors such as 100 can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0170] [Insulation layer 104]

[0171] The insulating layer 104 can be formed using methods such as sputtering, CVD, evaporation, and pulsed laser deposition (PLD). The insulating layer 104 can be formed, for example, as a single layer or a stack of oxide or nitride insulating films. Note that, to improve the interface characteristics between the insulating layer 104 and the semiconductor layer 108, the region of the insulating layer 104 in contact with the semiconductor layer 108 is preferably formed using an oxide insulating film. Furthermore, the insulating layer 104 is preferably a film that releases oxygen upon heating.

[0172] The insulating layer 104 may be made of silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide, and may be provided in a stacked or single layer configuration.

[0173] Furthermore, when a film other than an oxide film, such as a silicon nitride film, is used on the side of the insulating layer 104 that contacts the semiconductor layer 108, it is preferable to pre-treat the surface that contacts the semiconductor layer 108, such as by oxygen plasma treatment, to oxidize the surface or the vicinity of the surface.

[0174] [Conductive film]

[0175] The conductive layers 112 and 106 used as gate electrodes, the conductive layer 120a used as source electrodes, and the conductive layer 120b used as drain electrodes can be formed using metal elements selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, and cobalt, or alloys composed of the above metal elements, or alloys combining the above metal elements.

[0176] Furthermore, as conductive layers 112, 106, 120a, and 120b, oxide conductors or metal oxide films such as In-Sn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide, and In-Ga-Zn oxide can be used.

[0177] Here, we will explain oxide conductors (OC). For example, by forming oxygen vacancies in a metal oxide with semiconductor properties and adding hydrogen to these oxygen vacancies, a donor level is formed near the conduction band. Thus, the conductivity of the metal oxide increases, making it a conductor; the metal oxide that becomes a conductor can also be called an oxide conductor.

[0178] Furthermore, the conductive layer 112, etc., can also be a stacked structure of a conductive film containing the aforementioned oxide conductor (metal oxide) or a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced. In this case, it is preferable to use a conductive film containing an oxide conductor on the side that contacts the insulating layer used as the gate insulating film.

[0179] Furthermore, conductive layers 112, 106, 120a, and 120b preferably comprise one or more of the metal elements selected from titanium, tungsten, tantalum, and molybdenum. In particular, a tantalum nitride film is preferred. This tantalum nitride film is conductive and has high barrier properties against copper, oxygen, or hydrogen, and releases little hydrogen from itself, thus making it suitable as a conductive film in contact with or near the semiconductor layer 108.

[0180] [Insulation layer 110]

[0181] The insulating layer 110, used as the gate insulating film of transistor 100, etc., can be formed using PECVD, sputtering, or the like. The insulating layer 110 can be one or more insulating layers selected from silicon oxide film, silicon oxynitride film, silicon oxynitride film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film, and neodymium oxide film. The insulating layer 110 can be a two-layer stacked structure or a three-layer or more stacked structure.

[0182] Furthermore, the insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region having an oxygen content exceeding the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, by forming the insulating layer 110 in an oxygen atmosphere, subjecting the formed insulating layer 110 to heat treatment, plasma treatment, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere, oxygen can be supplied to the insulating layer 110.

[0183] As the insulating layer 110, materials such as hafnium oxide, which have a higher relative permittivity than silicon oxide or silicon oxynitride, can also be used. This allows for an increase in the thickness of the insulating layer 110 to suppress leakage current caused by tunneling current. In particular, crystalline hafnium oxide is preferred because its relative permittivity is higher than that of amorphous hafnium oxide.

[0184] [Semiconductor layer]

[0185] When the semiconductor layer 108 is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the sputtering target used to form the In-M-Zn oxide is greater than or equal to the atomic ratio of M. Examples of such atomic ratios of metal elements in the sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, and In:M:Zn = 5:2:5.

[0186] Furthermore, a sputtering target containing polycrystalline oxide is preferably used, thereby facilitating the formation of a crystalline semiconductor layer 108. Note that the atomic ratio of the formed semiconductor layer 108 varies within ±40% of the atomic ratio of the metal elements in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the formed semiconductor layer 108 may sometimes be In:Ga:Zn = 4:2:3 [atomic ratio] or close to it.

[0187] When the atomic number ratio is recorded as In:Ga:Zn = 4:2:3 or similar, it includes the following cases: when the atomic number ratio of In is 4, the atomic number ratio of Ga is 1 or more and 3 or less, and the atomic number ratio of Zn is 2 or more and 4 or less. Furthermore, when the atomic number ratio is recorded as In:Ga:Zn = 5:1:6 or similar, it includes the following cases: when the atomic number ratio of In is 5, the atomic number ratio of Ga is greater than 0.1 and less than 2, and the atomic number ratio of Zn is 5 or more and less than 7. Furthermore, when the atomic number ratio is recorded as In:Ga:Zn = 1:1:1 or similar, it includes the following cases: when the atomic number ratio of In is 1, the atomic number ratio of Ga is greater than 0.1 and less than 2, and the atomic number ratio of Zn is greater than 0.1 and less than 2.

[0188] Furthermore, the bandgap of the semiconductor layer 108 is 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide with a wider bandgap than silicon, the off-state current of the transistor can be reduced.

[0189] Furthermore, the semiconductor layer 108 preferably has a non-single-crystal structure. Non-single-crystal structures include, for example, CAAC structures, polycrystalline structures, microcrystalline structures, or amorphous structures, as described later. Among non-single-crystal structures, amorphous structures have the highest defect state density, while CAAC structures have the lowest defect state density.

[0190] The following is an explanation of CAAC (c-axis aligned crystal). CAAC represents an example of a crystal structure.

[0191] CAAC structure refers to a crystalline structure including thin films containing multiple nanocrystals (crystalline regions with a maximum diameter of less than 10 nm), characterized by the following features: the c-axis of each nanocrystal is oriented in a specific direction, while its a-axis and b-axis are not oriented, and the nanocrystals are continuously connected without forming grain boundaries. In particular, in thin films with CAAC structure, the c-axis of each nanocrystal is easily oriented in the thickness direction of the film, the normal direction of the formed surface, or the normal direction of the film surface.

[0192] CAAC-OS (Oxide Semiconductor) is a highly crystalline oxide semiconductor. No distinct grain boundaries are observed in CAAC-OS, thus reducing the likelihood of decreased electron mobility due to grain boundaries. Furthermore, the crystallinity of oxide semiconductors can sometimes decrease due to the incorporation of impurities or the formation of defects; therefore, CAAC-OS can be considered an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Consequently, oxide semiconductors containing CAAC-OS exhibit stable physical properties. Therefore, oxide semiconductors containing CAAC-OS possess high heat resistance and high reliability.

[0193] In crystallography, the c-axis is generally considered the most special of the three axes (a-axis, b-axis, and c-axis) that constitute the unit lattice. In particular, in crystals with layered structures, the two axes parallel to the planes of the layers are generally the a-axis and b-axis, and the axis intersecting the layers is the c-axis. A typical example of such layered crystals is graphite, classified as a hexagonal crystal, where the a-axis and b-axis of the unit lattice are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane. For example, InGaZnO4, with its layered YbFe2O4-type crystal structure, can be classified as a hexagonal crystal, where the a-axis and b-axis of the unit lattice are parallel to the planes of the layers, and the c-axis is orthogonal to the layers (i.e., the a-axis and b-axis).

[0194] An example of the crystal structure of a metal oxide will be illustrated. Note that an example will be a metal oxide formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]). Metal oxides formed by sputtering using the above target at a substrate temperature of 100°C or higher and 130°C or lower tend to have either an nc (nano crystal) structure or a CAAC structure, or a mixture thereof. Metal oxides formed by sputtering at a substrate temperature of room temperature (RT) tend to have an nc crystal structure. Note that room temperature (RT) here includes the temperature at which the substrate is not intentionally heated.

[0195] [Example of manufacturing method]

[0196] The following describes an example of a method for manufacturing a transistor according to one aspect of the present invention. Here, the transistor 100A shown in the above-described structural example 2 will be used as an example for description.

[0197] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD), and atomic layer deposition (ALD). CVD methods include plasma-enhanced chemical vapor deposition (PECVD) and thermal CVD. Furthermore, metal-organic chemical vapor deposition (MOCVD) is one type of thermal CVD method.

[0198] In addition, thin films (insulating films, semiconductor films, conductive films, etc.) constituting semiconductor devices can be formed using methods such as spin coating, dip coating, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor knife coating, slot coating, roller coating, curtain coating, and doctor blade coating.

[0199] Furthermore, when processing thin films constituting semiconductor devices, photolithography and other methods can be used. Besides the methods mentioned above, nanoimprinting, sandblasting, and lift-off methods can also be used to process thin films. Additionally, island-shaped thin films can be directly formed using film deposition methods that utilize metal masks or similar masking techniques.

[0200] Photolithography typically involves two methods. One method involves forming a resist mask on the thin film to be processed, processing the film through etching, and then removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development to process the film into the desired shape.

[0201] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365nm), g-line (wavelength 436nm), h-line (wavelength 405nm), or a mixture of these. Additionally, ultraviolet light, KrF lasers, or ArF lasers can also be used. Furthermore, immersion lithography can also be employed. Extreme ultraviolet (EUV) light or X-rays can also be used as the light for exposure. Electron beams can also be used instead of the light used for exposure. When using EUV light, X-rays, or electron beams, extremely fine processing can be performed, making them preferred. Furthermore, when exposure is performed by scanning with a beam such as an electron beam, a photomask is not required.

[0202] As a method for etching thin films, dry etching, wet etching, and sandblasting can be used.

[0203] In the figures shown in Figures 6 to 8, cross-sections in the channel length direction and the channel width direction of each stage of the manufacturing process of transistor 100A are shown side by side.

[0204] [Formation of conductive layer 106]

[0205] A conductive film is formed on the substrate 102, and then etched to obtain a conductive layer 106 used as a gate electrode (see reference). Figure 6A ).

[0206] [Formation of insulating layer 103 and insulating layer 104]

[0207] Next, an insulating layer 103 and an insulating film 104f are stacked to cover the substrate 102 and the conductive layer 106. Figure 6B The insulating layer 103 and the insulating film 104f can each be formed using PECVD, ALD, sputtering, or other methods.

[0208] For example, insulating layer 103 can be formed using ALD, PECVD or sputtering, and insulating film 104f can be formed using PECVD or sputtering.

[0209] Next, a portion of the insulating film 104f is removed by etching, and it is processed into island shapes to form insulating layer 104 and insulating layer 104a. Figure 6C ).

[0210] [Formation of semiconductor layer 108]

[0211] Next, a metal oxide film is formed on insulating layer 104 and insulating layer 103, and then processed to form semiconductor layer 108. Figure 7A ).

[0212] The metal oxide film is preferably formed by sputtering using a metal oxide target.

[0213] Furthermore, when forming a metal oxide film, an inert gas (e.g., helium, argon, xenon, etc.) can be mixed in addition to oxygen gas. The higher the proportion of oxygen gas in the overall deposition gas during metal oxide film formation (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, thereby enabling high-reliability transistors. Conversely, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, thereby obtaining transistors with high on-state current.

[0214] Furthermore, as for the deposition conditions of the metal oxide film, the substrate temperature can be above room temperature and below 200°C, preferably above room temperature and below 140°C. For example, the deposition temperature is preferably above room temperature and below 140°C because this can improve productivity. In addition, by forming the metal oxide film at room temperature or without intentional heating, crystallinity can be reduced.

[0215] Furthermore, it is preferable to perform a treatment to remove water, hydrogen, organic matter, etc., adhering to the surface of the insulating layer 104, or to supply oxygen to the insulating layer 104 before forming the metal oxide film. For example, heating treatment can be performed at a temperature of 70°C or higher and 200°C or lower under a reduced pressure atmosphere. Alternatively, plasma treatment in an oxygen-containing atmosphere can be performed. In addition, by performing plasma treatment in an atmosphere containing N2O gas, organic matter on the surface of the insulating layer 104 can be suitably removed. After performing this treatment, it is preferable to continuously form the metal oxide film while keeping the surface of the insulating layer 104 from exposure to the atmosphere.

[0216] When processing metal oxide films, one or both wet etching and dry etching methods can be used. In this case, sometimes a portion of the insulating layer 104 that does not overlap with the semiconductor layer 108 is etched and thinned.

[0217] Alternatively, a heat treatment to remove hydrogen or water from the metal oxide film or semiconductor layer 108 may be performed after the metal oxide film is formed or after the metal oxide film is processed into a semiconductor layer 108. Typically, the heat treatment temperature is above 150°C and below the strain point of the substrate, above 250°C and below 450°C, or above 300°C and below 450°C.

[0218] The heating process can be performed in an atmosphere containing rare gases or nitrogen. Alternatively, it can be performed in such an atmosphere followed by heating in an atmosphere containing oxygen. Furthermore, the atmosphere for the aforementioned heating process preferably does not contain hydrogen, water, or the like. This heating process can be performed using an electric furnace, an RTA (Regenerative Thermal Absorption) device, or the like. By using an RTA device, the heating process time can be shortened.

[0219] [Formation of insulating film 110f and metal oxide film 114f]

[0220] Next, an insulating film 110f, which becomes an insulating layer 110, and a metal oxide film 114f, which becomes a metal oxide layer 114, are stacked to cover the insulating layer 103, the insulating layer 104, and the semiconductor layer 108.

[0221] As the insulating film 110f, it is preferably formed, for example, using a plasma-enhanced chemical vapor deposition apparatus (also known as a PECVD apparatus or a plasma CVD apparatus) as an oxide film such as a silicon oxide film or a silicon oxynitride film. Alternatively, the insulating film 110f can be formed using a microwave-based PECVD method.

[0222] The metal oxide film 114f is preferably formed, for example, in an oxygen-containing atmosphere. In particular, it is preferably formed by sputtering in an oxygen-containing atmosphere. This allows oxygen to be supplied to the insulating film 110f during the formation of the metal oxide film 114f.

[0223] The above description can be used when forming a metal oxide film 114f using a sputtering method with an oxide target containing a metal oxide, similar to the semiconductor layer 108 described above.

[0224] For example, oxygen is preferably used as the deposition gas in the formation conditions of the metal oxide film 114f, and the metal oxide film is formed by reactive sputtering using a metal target. When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.

[0225] When forming the metal oxide film 114f, the higher the ratio of oxygen flow rate to the total flow rate of the deposition gas introduced into the deposition chamber of the deposition apparatus (oxygen flow ratio) or the higher the oxygen partial pressure in the deposition chamber, the greater the amount of oxygen supplied to the insulating film 110f. The oxygen flow ratio or oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% ​​or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow ratio to 100% so that the oxygen partial pressure is as close as possible to 100%.

[0226] Thus, by forming the metal oxide film 114f using sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110f while preventing oxygen from escaping from the insulating film 110f during its formation. As a result, a large amount of oxygen can be confined within the insulating film 110f. Furthermore, a greater amount of oxygen can be supplied to the semiconductor layer 108 through subsequent heat treatment. Consequently, oxygen vacancies in the semiconductor layer 108 can be reduced, enabling the realization of a highly reliable transistor.

[0227] Next, after forming the metal oxide film 114f, an opening reaching the conductive layer 106 is formed by etching the metal oxide film 114f, the insulating film 110f, (insulating layer 104), and a portion of the insulating layer 103. This allows the subsequently formed conductive layer 112 to be electrically connected to the conductive layer 106 through this opening.

[0228] Figure 7B This is equivalent to a cross-sectional diagram of this stage.

[0229] [Formation of conductive layer 112, metal oxide layer 114 and insulating layer 110]

[0230] Next, a conductive film, which becomes the conductive layer 112, is formed on the metal oxide film 114f. This conductive film is preferably formed by sputtering using a sputtering target made of metal or alloy.

[0231] Next, a portion of the conductive film, the metal oxide film 114f, and the insulating film 110f are etched. Figure 7CPreferably, the same resist mask is used to process the conductive film, the metal oxide film 114f, and the insulating film 110f. Alternatively, the metal oxide film 114f and the insulating film 110f can be etched using the etched conductive layer 112 as a hard mask.

[0232] Thus, an island-shaped conductive layer 112, a metal oxide layer 114, and an insulating layer 110 with roughly the same top surface shape can be formed.

[0233] When etching the conductive film, metal oxide film 114f and insulating film 110f, sometimes semiconductor layers 108 and other materials not covered by insulating layer 110 are also etched, and their thickness is reduced.

[0234] [Formation of insulating layer 116]

[0235] Next, an insulating layer 116 is formed to cover the insulating layer 104, the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the conductive layer 112. Furthermore, at this time, a region where the insulating layer 103 and the insulating layer 116 contact is formed on the outer side of the ends of the semiconductor layer 108 and the insulating layer 104. Figure 8A ).

[0236] The insulating layer 116 is preferably formed by reactive sputtering using a sputtering target containing the aforementioned metal elements and a mixture of nitrogen gas as the deposition gas and a rare gas as the dilution gas. Therefore, the film quality of the insulating layer 116 can be easily controlled by controlling the flow rate ratio of the deposition gas.

[0237] For example, when an aluminum nitride film formed by reactive sputtering using an aluminum target is used as the insulating layer 116, the flow rate of nitrogen gas relative to the total flow rate of the deposition gas is 30% or more and 100% or less, preferably 40% or more and 100% or less, and more preferably 50% or more and 100% or less.

[0238] For example, when silicon nitride is used as the insulating layer 116, it is preferable to form the insulating layer 116 using a PECVD method that employs a mixture of silicon-containing gases such as silane and nitrogen-containing gases such as ammonia or nitrous oxide as the deposition gas. In this case, it is preferable that the deposited silicon nitride contains hydrogen. As a result, hydrogen diffuses from the insulating layer 116 into the semiconductor layer 108, making it easy to reduce the resistance of a portion of the semiconductor layer 108.

[0239] When forming the insulating layer 116, a low-resistance region 108n is formed at and near the interface of the semiconductor layer 108 that contacts the insulating layer 116.

[0240] [First heat treatment]

[0241] Next, a heat treatment is preferably performed. By heat treatment, the low resistance of the low resistance region 108n of the semiconductor layer 108 can be promoted.

[0242] The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. Higher heat treatment temperatures are better, and the temperature can be determined based on the heat resistance of the substrate 102, conductive layer 106, conductive layer 112, etc. For example, the heat treatment temperature can be 120°C or higher and 500°C or lower, preferably 150°C or higher and 450°C or lower, more preferably 200°C or higher and 400°C or lower, and even more preferably 250°C or higher and 400°C or lower. For example, when the heat treatment temperature is set to around 350°C, semiconductor devices can be manufactured with high yield using production equipment for large glass substrates.

[0243] Note that the heat treatment can be performed at any time after the formation of the insulating layer 116. Furthermore, the above-described heat treatment can also be used as another type of heat treatment.

[0244] For example, through heat treatment, oxygen in the semiconductor layer 108 is extracted to one side of the insulating layer 116, creating oxygen vacancies. These oxygen vacancies bond with hydrogen contained in the semiconductor layer 108 or hydrogen supplied from the insulating layer 116, increasing the carrier concentration and potentially making the portion in contact with the insulating layer 116 have lower resistance.

[0245] Alternatively, through heat treatment, the metal elements contained in the semiconductor layer 108 may diffuse towards the interface with the insulating layer 116, forming a region with a high concentration of the metal element. As a result, the portion of the semiconductor layer 108 in contact with the insulating layer 116 is made less resistive. For example, when an indium-containing metal oxide film is used for the semiconductor layer 108, a region with a high indium concentration is sometimes observed near the interface between the semiconductor layer 108 and the insulating layer 116.

[0246] The region 108n, which has been reduced in resistance through the aforementioned combined effect, becomes an extremely stable low-resistance region. The region 108n formed in the above manner has the following characteristics: even if, for example, oxygen supply treatment is performed in a subsequent process, its resistance is not easily increased again.

[0247] [Formation of insulating layer 118]

[0248] Next, an insulating layer 118 is formed in such a way as to cover the insulating layer 116. The insulating layer 118 can be formed, for example, using the PECVD method.

[0249] [Formation of openings 141a and 141b]

[0250] Next, by partially etching the insulating layers 118 and 116, openings 141a and 141b reaching region 108n are formed.

[0251] [Formation of conductive layers 120a and 120b]

[0252] Next, a conductive film is formed on the insulating layer 118 to cover openings 141a and 141b, and the conductive film is processed into the desired shape to form conductive layers 120a and 120b. Figure 8B ).

[0253] Through the above process, transistor 100A can be manufactured.

[0254] Note that when using the transistor 100 illustrated in structural example 1, the forming process of the conductive layer 106 and the forming process of the opening 142 in the above manufacturing method example can be omitted.

[0255] The above are examples illustrating manufacturing methods.

[0256] At least a portion of the structural examples, manufacturing method examples, and corresponding drawings shown in this embodiment can be implemented in appropriate combinations with other structural examples, manufacturing method examples, or drawings.

[0257] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0258] (Implementation Method 2)

[0259] In this embodiment, an example of a display device having the transistors illustrated in the above embodiment will be described.

[0260] [Structure Example]

[0261] Figure 9A A top view of the display device 700 is shown. The display device 700 includes a first substrate 701 and a second substrate 705 bonded together using a sealant 712. In the area sealed by the first substrate 701, the second substrate 705, and the sealant 712, a pixel portion 702, a source driving circuit portion 704, and a gate driving circuit portion 706 are disposed on the first substrate 701. The pixel portion 702 is provided with a plurality of display elements.

[0262] Furthermore, an FPC terminal portion 708, which connects to an FPC 716 (Flexible printed circuit), is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Various signals are provided to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 via the FPC terminal portion 708 and signal lines 710 using the FPC 716.

[0263] Multiple gate drive circuit sections 706 can be provided. Furthermore, the gate drive circuit section 706 and the source drive circuit section 704 can be separately formed on a semiconductor substrate or the like, or they can be packaged as an IC chip. This IC chip can be mounted on the first substrate 701 or mounted to the FPC 716.

[0264] The transistors included in the pixel section 702, the source drive circuit section 704, and the gate drive circuit section 706 can be transistors of a semiconductor device according to one aspect of the present invention.

[0265] Examples of display elements provided in the pixel unit 702 include liquid crystal elements and light-emitting elements. As liquid crystal elements, transmissive liquid crystal elements, reflective liquid crystal elements, and transflective liquid crystal elements can be used. Furthermore, examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), QLEDs (Quantum-dot LEDs), and semiconductor lasers. Additionally, display elements using shutter-based or light-interference-based MEMS (Micro Electro Mechanical Systems) elements, or those employing microencapsulation, electrophoresis, electrowetting, or electronic powder fluid (registered trademark) methods, can be used.

[0266] Figure 9B The display device 700A shown is a display device that can be used with electronic devices that have large screens. For example, the display device 700A can be used with television devices, monitor devices, personal computers (including laptops or desktops), tablet terminals, digital signage, etc.

[0267] The display device 700A includes multiple source driver ICs 721 and a pair of gate driver circuits 722.

[0268] Multiple source driver ICs 721 are mounted onto FPC 723. Furthermore, one terminal of each FPC 723 is connected to a first substrate 701, and another terminal is connected to a printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be positioned on the back of the pixel section 702 and mounted in the electronic device, thereby reducing the space required to mount the electronic device.

[0269] On the other hand, the gate drive circuit section 722 is formed on the first substrate 701. As a result, an electronic device with a narrow bezel can be realized.

[0270] By adopting the above structure, large and high-definition display devices can be realized. For example, it can be applied to display devices with a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. In addition, it can realize display devices with extremely high resolutions such as 4K2K and 8K4K.

[0271] [Example of cross-sectional structure]

[0272] The following reference Figures 10 to 12 The structure of liquid crystal elements and EL elements used as display elements is explained. Figures 10 to 12 They are respectively along Figure 9A The cross-sectional view of the dotted-dash line QR is shown. Figure 10 and Figure 11 It is a structure that uses liquid crystal elements as display elements. Figure 12 It is a structure that uses EL components.

[0273] [Description of the same parts of the display device]

[0274] Figures 10 to 12 The display device 700 shown includes a lead-in wiring section 711, a pixel section 702, a source drive circuit section 704, and an FPC terminal section 708. The lead-in wiring section 711 includes signal lines 710. The pixel section 702 includes transistors 750 and capacitors 790. The source drive circuit section 704 includes transistors 752.

[0275] The transistors shown in Embodiment 1 can be used as transistors 750 and 752.

[0276] The transistor used in this embodiment comprises a highly purified oxide semiconductor film in which the formation of oxygen vacancies is suppressed. This transistor can have a low off-state current. Therefore, the hold time of electrical signals such as image signals can be extended, and the write interval of image signals can be extended when the power is on. Therefore, the refresh frequency can be reduced, thereby achieving a power reduction effect.

[0277] Furthermore, the transistors used in this embodiment exhibit high field-effect mobility, enabling high-speed driving. For example, by using such high-speed driving transistors in a display device, both the switching transistors for the pixel section and the driving transistors for the driving circuit section can be formed on the same substrate. In other words, since a separate semiconductor device formed from silicon wafers or the like is not required for the driving circuit, the number of components in the display device can be reduced. Moreover, by using high-speed driving transistors also in the pixel section, high-quality images can be provided.

[0278] The capacitor 790 includes a lower electrode formed by processing a film identical to the semiconductor layer included in the transistor 750 and having low resistance, and an upper electrode formed by processing a conductive film identical to the source electrode or drain electrode. Furthermore, an insulating film covering both layers of the transistor 750 is disposed between the lower electrode and the upper electrode. In other words, the capacitor 790 has a laminated structure in which an insulating film serving as a dielectric film is sandwiched between a pair of electrodes.

[0279] In addition, a planarization insulating film 770 is provided on transistors 750, 752 and capacitor 790.

[0280] Furthermore, the transistor 750 included in the pixel section 702 and the transistor 752 included in the source drive circuit section 704 can use transistors with different structures. For example, one can use a top-gate transistor and the other uses a bottom-gate transistor. Alternatively, the source drive circuit section 704 can also be referred to as a gate drive section.

[0281] The signal line 710 and the source and drain electrodes of transistors 750 and 752 are formed from the same conductive film. Here, it is preferable to use a low-resistance material such as a material containing copper, which can reduce signal delay caused by wiring resistance, thereby enabling large-screen display.

[0282] The FPC terminal section 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. Here, the connection electrode 760 and the source and drain electrodes of transistors 750 and 752 are formed of the same conductive film.

[0283] The first substrate 701 and the second substrate 705 can be flexible substrates such as glass substrates or plastic substrates.

[0284] In addition, a light-shielding film 738, a coloring film 736, and an insulating film 734 in contact with them are provided on one side of the second substrate 705.

[0285] [Example of the structure of a display device using liquid crystal elements]

[0286] Figure 10 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776 between the conductive films 772 and 774. The conductive film 774 is disposed on one side of the second substrate 705 and serves as a common electrode. Furthermore, the conductive film 772 is electrically connected to the source or drain electrode included in the transistor 750. The conductive film 772 is formed on a planarization insulating film 770 and serves as a pixel electrode.

[0287] The conductive film 772 can be made of a material that is transparent to visible light or a material that is reflective. For example, a transparent material can be an oxide material containing In, Zn, Sn, etc. For example, a reflective material can be a material containing Al, Ag, etc.

[0288] When a reflective material is used as the conductive film 772, the display device 700 is a reflective liquid crystal display device. On the other hand, when a light-transmitting material is used as the conductive film 772, the display device 700 is a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizer is provided on the viewing side. In the case of a transmissive liquid crystal display device, a pair of polarizers are provided to sandwich the liquid crystal element.

[0289] Figure 11 The display device 700 shown illustrates an example of a liquid crystal element 775 using a lateral electric field method (e.g., FFS mode). A conductive film 774 serving as a common electrode is disposed on the conductive film 772, separated by an insulating film 773. The orientation state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive film 772 and the conductive film 774.

[0290] In addition, although Figure 10 and Figure 11 Although not illustrated, a structure in which an alignment film is in contact with the liquid crystal layer 776 can also be used. Furthermore, optical components (optical substrates) such as polarizing components, phase difference components, and anti-reflection components, as well as light sources such as backlighting and sidelighting, can be appropriately provided.

[0291] The liquid crystal layer 776 can be made of thermotropic liquid crystals, low-molecular-weight liquid crystals, high-molecular-weight liquid crystals, high-molecular-weight dispersed liquid crystals, high-molecular-weight network liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc. Furthermore, when using a lateral electric field, a blue-phase liquid crystal that does not require an alignment film can also be used.

[0292] In addition, the modes of liquid crystal elements can include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated Birefringence) mode, ECB (Electrically Controlled Birefringence) mode, guest-host mode, etc.

[0293] [Display devices using light-emitting elements]

[0294] Figure 12 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 772, an EL layer 786, and a conductive film 788. The EL layer 786 has an inorganic compound such as an organic compound or quantum dots.

[0295] Examples of materials that can be used in organic compounds include fluorescent or phosphorescent materials. Furthermore, examples of materials that can be used in quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell quantum dot materials, and nucleated quantum dot materials.

[0296] Figure 12 The display device 700 shown has an insulating film 730 covering a portion of the conductive film 772 on a planarized insulating film 770. Here, the light-emitting element 782 is a top-emitting type light-emitting element that includes a light-transmitting conductive film 788. Alternatively, the light-emitting element 782 may also employ a bottom-emitting structure that emits light from the conductive film 772 side or a double-sided emitting structure that emits light from both the conductive film 772 side and the conductive film 788 side.

[0297] Furthermore, the coloring film 736 is disposed at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is disposed at a position overlapping with the insulating film 730 in the winding wiring section 711 and the source drive circuit section 704. Furthermore, the coloring film 736 and the light-shielding film 738 are covered by the insulating film 734. Furthermore, the space between the light-emitting element 782 and the insulating film 734 is filled by the sealing film 732. Additionally, when the EL layer 786 is formed as an island in each pixel or as a strip in each pixel column—that is, when the EL layer 786 is formed by separate coating—a structure without the coloring film 736 can also be used.

[0298] [Example of a structure for incorporating an input device in a display device]

[0299] In addition, it is also possible to Figures 10 to 12 The display device 700 shown is equipped with an input device. Examples of such an input device include, for instance, a touch sensor.

[0300] For example, various methods can be used as sensors, such as electrostatic capacitive, resistive film, surface acoustic wave, infrared, optical, and piezoresistive. Furthermore, two or more of these methods can be combined.

[0301] In addition, the touch panel has the following structures: a so-called In-Cell type touch panel in which the input device is formed on the inside of a pair of substrates; a so-called On-Cell type touch panel in which the input device is formed on the display device 700; a so-called Out-Cell type touch panel in which the input device is attached to the display device 700; etc.

[0302] The structural examples shown in this embodiment and at least a portion of the corresponding drawings can be implemented in appropriate combinations with other structural examples or drawings.

[0303] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0304] (Implementation Method 3)

[0305] In this embodiment, a display device including a semiconductor device according to one aspect of the present invention will be described with reference to FIG13.

[0306] Figure 13A The display device shown includes a pixel unit 502, a driving circuit unit 504, a protection circuit 506, and a terminal unit 507. Note that a structure without the protection circuit 506 may also be used.

[0307] A transistor according to one aspect of the present invention can be used for the transistors included in the pixel section 502 or the driving circuit section 504. Furthermore, a transistor according to one aspect of the present invention can also be used for the protection circuit 506.

[0308] The pixel unit 502 includes multiple pixel circuits 501 that drive multiple display elements configured in X rows and Y columns (X and Y are independent natural numbers of 2 or more).

[0309] The drive circuit section 504 includes drive circuits for a gate driver 504a that outputs scan signals to gate lines GL_1 to GL_X, and a source driver 504b that supplies data signals to data lines DL_1 to DL_Y. The gate driver 504a can be configured with at least a shift register. Furthermore, the source driver 504b can be configured, for example, with multiple analog switches. Alternatively, the source driver 504b can also be configured with a shift register.

[0310] Terminal section 507 refers to the section provided with terminals for inputting power, control signals, and image signals to the display device from external circuitry.

[0311] The protection circuit 506 is a circuit that keeps the wire connected to it in a conductive state with other wires when the wire to which it is connected is supplied with a potential outside a certain range. Figure 13AThe protection circuit 506 shown is connected to various wiring connections, such as the scan line GL between the gate driver 504a and the pixel circuit 501, or the data line DL between the source driver 504b and the pixel circuit 501.

[0312] In addition, a structure in which the gate driver 504a and the source driver 504b are each disposed on the same substrate as the pixel portion 502 can be used, or a structure in which another substrate (e.g., a driving circuit board formed using a single crystal semiconductor film or a polycrystalline semiconductor film) on which the gate driving circuit or the source driving circuit is formed can be mounted on the substrate by COG or TAB (Tape Automated Bonding) can be used.

[0313] also, Figure 13A The multiple pixel circuits 501 shown can, for example, be employed with... Figure 13B and Figure 13C The structure shown.

[0314] Figure 13B The pixel circuit 501 shown includes a liquid crystal element 570, a transistor 550, and a capacitor 560. Furthermore, the pixel circuit 501 is connected to data lines DL_n, scan lines GL_m, and a potential supply line VL.

[0315] The potential of one electrode of a pair of electrodes in the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the data being written. Alternatively, a common potential can be supplied to one electrode of a pair of electrodes in the liquid crystal element 570 of each of the multiple pixel circuits 501. Furthermore, a different potential can be supplied to one electrode of a pair of electrodes in the liquid crystal element 570 of each row of pixel circuits 501.

[0316] also, Figure 13C The pixel circuit 501 shown includes transistors 552 and 554, capacitor 562, and light-emitting element 572. Furthermore, the pixel circuit 501 is connected to data line DL_n, scan line GL_m, potential supply line VL_a, and power supply line VL_b.

[0317] Furthermore, a high power supply potential VDD is applied to one of the potential supply lines VL_a and VL_b, and a low power supply potential VSS is applied to the other. Based on the potential applied to the gate of transistor 554, the current flowing through the light-emitting element 572 is controlled, thereby controlling the luminous intensity from the light-emitting element 572.

[0318] The structural examples shown in this embodiment and at least a portion of the corresponding drawings can be implemented in appropriate combinations with other structural examples or drawings.

[0319] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0320] (Implementation Method 4)

[0321] The pixel circuit having a memory for correcting the grayscale displayed by the pixels and the display device having the pixel circuit will be described below. The transistor illustrated in Embodiment 1 can be used in the pixel circuit illustrated below.

[0322] [Circuit Structure]

[0323] Figure 14A A circuit diagram of pixel circuit 400 is shown. Pixel circuit 400 includes transistor M1, transistor M2, capacitor C1, and circuit 401. Furthermore, pixel circuit 400 is connected to wiring S1, wiring S2, wiring G1, and wiring G2.

[0324] The gate of transistor M1 is connected to wiring G1, one of its source and drain is connected to wiring S1, and the other of its source and drain is connected to one electrode of capacitor C1. The gate of transistor M2 is connected to wiring G2, one of its source and drain is connected to wiring S2, and the other of its source and drain is connected to the other electrode of capacitor C1 and circuit 401.

[0325] Circuit 401 includes at least one display element. The display element can be a wide variety of components, typically including light-emitting elements such as organic EL elements or LED elements, liquid crystal elements or MEMS (Micro Electro Mechanical Systems) elements, etc.

[0326] The node connecting transistor M1 and capacitor C1 is denoted as N1, and the node connecting transistor M2 and circuit 401 is denoted as N2.

[0327] The pixel circuit 400 maintains the potential of node N1 by turning transistor M1 off. Similarly, it maintains the potential of node N2 by turning transistor M2 off. Furthermore, when a predetermined potential is written to node N1 via transistor M1 with transistor M2 off, the potential of node N2 changes in response to the change in the potential of node N1 due to the capacitive coupling through capacitor C1.

[0328] Here, one or both of transistors M1 and M2 can be an oxide semiconductor transistor as illustrated in Embodiment 1. Because this transistor has extremely low off-state current, the potentials of nodes N1 and N2 can be maintained for a long time. Alternatively, when the potential maintenance period of each node is short (specifically, when the frame rate is 30Hz or higher, etc.), a semiconductor transistor such as silicon can also be used.

[0329] [Driver Method Example]

[0330] Next, refer to Figure 14B An example illustrating the operation of the pixel circuit 400 is provided. Figure 14B This is a timing diagram of the operation of pixel circuit 400. Note that, for ease of explanation, the effects of various resistors such as wiring resistors, parasitic capacitances of transistors or wiring, and threshold voltages of transistors are not considered here.

[0331] exist Figure 14B In the work shown, a frame period is divided into period T1 and period T2. Period T1 is the period for writing potential to node N2, and period T2 is the period for writing potential to node N1.

[0332] [Period T1]

[0333] During period T1, a potential that turns the transistor on is supplied to both wiring G1 and wiring G2. Additionally, a fixed potential V is supplied to wiring S1. ref Provides a first data potential V to wiring S2 w .

[0334] Node N1 is supplied with potential V from wiring S1 via transistor M1. ref Additionally, node N2 is supplied with a first data potential V through transistor M2. w Therefore, capacitor C1 becomes a capacitor that maintains the potential difference V. w -V ref The state.

[0335] [Date T2]

[0336] Next, during period T2, wiring G1 is supplied with a potential that turns transistor M1 on, and wiring G2 is supplied with a potential that turns transistor M2 off. Wiring S1 is supplied with the second data potential V. data Alternatively, a predetermined constant potential can be provided to wiring S2 or it can be made to float.

[0337] Node N1 is supplied with a second data potential V through transistor M1. data At this time, due to capacitive coupling through capacitor C1, the corresponding second data potential V... dataThe potential of node N2 changes by a value of dV. That is, circuit 401 is input with the sum of the first data potential Vw and the potential dV. Note that although... Figure 14B The diagram shows dV as a positive value, but it can also be negative. That is, the potential V... data It can also be compared to the potential V ref Low.

[0338] Here, the potential dV is primarily determined by the capacitance of capacitor C1 and the capacitance of circuit 401. When the capacitance of capacitor C1 is sufficiently greater than the capacitance of circuit 401, the potential dV becomes close to the second data potential V. data The potential.

[0339] As described above, since the pixel circuit 400 can combine two data signals to generate a potential supplied to the circuit 401 including the display element, grayscale correction can be performed within the pixel circuit 400.

[0340] Furthermore, the pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. For example, when using a light-emitting element, high dynamic range (HDR) display can be achieved. Additionally, when using a liquid crystal element, overdrive can be implemented.

[0341] [Application Examples]

[0342] [Examples of using liquid crystal components]

[0343] Figure 14C The pixel circuit 400LC shown includes circuit 401LC. Circuit 401LC includes a liquid crystal element LC and a capacitor C2.

[0344] One electrode of the liquid crystal element LC is connected to node N2 and one electrode of capacitor C2, and the other electrode is connected to the supplied potential V. com2 The wiring connection. The other electrode of capacitor C2 is connected to the supplied potential V. com1 Wiring connections.

[0345] Capacitor C2 is used as a storage capacitor. Alternatively, capacitor C2 can be omitted when it is not needed.

[0346] Since the pixel circuit 400LC can provide a high voltage to the liquid crystal element LC, high-speed display can be achieved, for example, through overdrive, and liquid crystal materials with high driving voltage can be used. Furthermore, by providing a correction signal to wiring S1 or wiring S2, grayscale correction can be performed based on factors such as operating temperature or the degradation state of the liquid crystal element LC.

[0347] [Example of using light-emitting elements]

[0348] Figure 14D The pixel circuit 400EL shown includes circuit 401EL. Circuit 401EL includes a light-emitting element EL, a transistor M3, and a capacitor C2.

[0349] The gate of transistor M3 is connected to node N2 and one electrode of capacitor C2. One of its source and drain terminals is connected to the wiring at the supplied potential VH, and the other of its source and drain terminals is connected to one electrode of the light-emitting element EL. The other electrode of capacitor C2 is connected to the supplied potential VH. com The wiring connection. The other electrode of the light-emitting element EL is connected to the supplied potential V. L Wiring connections.

[0350] Transistor M3 controls the current supplied to the light-emitting element EL. Capacitor C2 serves as a storage capacitor. Capacitor C2 can be omitted if not needed.

[0351] Furthermore, although the structure shown here has the anode side of the light-emitting element EL connected to the transistor M3, a structure with the cathode side connected to the transistor M3 can also be used. When using the structure with the cathode side connected to the transistor M3, the potential V can be appropriately changed. H With potential V L The value of .

[0352] In the pixel circuit 400EL, a large current can flow through the light-emitting element EL by applying a high potential to the gate of transistor M3, thus enabling HDR display and other functions. Furthermore, by providing a correction signal to wiring S1 or wiring S2, deviations in the electrical characteristics of transistor M3 and the light-emitting element EL can be corrected.

[0353] In addition, not limited to Figure 14C and Figure 14D The circuit shown can also be constructed using additional transistors or capacitors.

[0354] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0355] (Implementation Method 5)

[0356] In this embodiment, a display module that can be manufactured using one method of the present invention will be described.

[0357] Figure 15A The display module 6000 shown includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011, located between an upper cover 6001 and a lower cover 6002.

[0358] For example, a display device manufactured using one method of the present invention can be used as display device 6006. By utilizing display device 6006, a display module with extremely low power consumption can be realized.

[0359] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape or size according to the size of the display device 6006.

[0360] The display device 6006 can also function as a touch panel.

[0361] The frame 6009 has the functions of protecting the display device 6006, blocking electromagnetic waves generated by the operation of the printed circuit board 6010, and serving as a heat sink.

[0362] The printed circuit board 6010 has a power supply circuit, as well as signal processing circuits for outputting video signals and clock signals, battery control circuits, etc.

[0363] Figure 15B This is a cross-sectional schematic diagram of a display module 6000 equipped with an optical touch sensor.

[0364] The display module 6000 includes a light-emitting part 6015 and a light-receiving part 6016 disposed on a printed circuit board 6010. In addition, a pair of light guides (light guide 6017a and light guide 6017b) are disposed in the area surrounded by the upper cover 6001 and the lower cover 6002.

[0365] The display device 6006 overlaps with the printed circuit board 6010 and the battery 6011 through the frame 6009. The display device 6006 and the frame 6009 are fixed to the light guide portion 6017a and the light guide portion 6017b.

[0366] The light 6018 emitted from the light-emitting unit 6015 passes through the light guide unit 6017a, the top of the display device 6006, and the light guide unit 6017b to reach the light-receiving unit 6016. For example, when the light 6018 is blocked by a detection object such as a finger or stylus, touch operation can be detected.

[0367] For example, multiple light-emitting units 6015 are arranged along two adjacent sides of the display device 6006. Multiple light-receiving units 6016 are arranged opposite to the light-emitting units 6015. Thus, information about the position of the touch operation can be obtained.

[0368] The light-emitting part 6015 can be a light source such as an LED element, and in particular, a light source that emits infrared light is preferred. The light-receiving part 6016 can be a photoelectric element that receives the light emitted by the light-emitting part 6015 and converts it into an electrical signal. A photodiode capable of receiving infrared light is preferred.

[0369] By using light guides 6017a and 6017b that allow light 6018 to pass through, the light-emitting part 6015 and the light-receiving part 6016 can be positioned on the lower side of the display device 6006, thus suppressing external light from reaching the light-receiving part 6016 and causing malfunctions of the touch sensor. In particular, when using a resin that absorbs visible light and transmits infrared light, malfunctions of the touch sensor can be suppressed even more effectively.

[0370] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0371] (Implementation Method 6)

[0372] In this embodiment, an electronic device having a display device manufactured using one method of the present invention will be described.

[0373] The electronic devices illustrated below are electronic devices that incorporate a display device according to one aspect of the present invention in their display units, and therefore are electronic devices that achieve high resolution. Furthermore, electronic devices that simultaneously achieve high definition and a large screen can also be implemented.

[0374] In one aspect of the present invention, the display unit of an electronic device may display images with resolutions of full HD, 4K2K, 8K4K, 16K8K, or higher.

[0375] As electronic devices, in addition to television sets, laptop computers, monitors, digital signage, pinball machines, and game consoles, which have relatively large screens, examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices.

[0376] An electronic device using one aspect of the present invention can be assembled along a plane or curved surface such as the inner or outer wall of a house or building, the interior or exterior decoration of a car, etc.

[0377] Figure 16A This is an exterior view of the camera 8000 equipped with a viewfinder 8100.

[0378] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. In addition, the camera 8000 is equipped with a detachable lens 8006.

[0379] In camera 8000, the lens 8006 and the housing can also be formed as one unit.

[0380] The camera 8000 can take an image by pressing the shutter button 8004 or by touching the display 8002, which serves as a touch panel.

[0381] The housing 8001 includes an insert with electrodes, which can be connected to the viewfinder 8100 and to a flash unit, etc.

[0382] The viewfinder 8100 includes a housing 8101, a display unit 8102, and buttons 8103, etc.

[0383] The housing 8101 is mounted to the camera 8000 via an inserter that fits into the camera 8000. The viewfinder 8100 can display images received from the camera 8000, etc., on the display unit 8102.

[0384] Button 8103 is used as a power button, etc.

[0385] One embodiment of the display device of the present invention can be used in the display unit 8002 of a camera 8000 and the display unit 8102 of a viewfinder 8100. Alternatively, a viewfinder may be built into the camera 8000.

[0386] Figure 16B This is an image of the 8200 head-mounted display.

[0387] The head-mounted display 8200 includes a mounting section 8201, a lens 8202, a main body 8203, a display section 8204, and a cable 8205. Furthermore, a battery 8206 is built into the mounting section 8201.

[0388] Power is supplied from battery 8206 to main body 8203 via cable 8205. Main body 8203 includes a wireless receiver and can display received image information on display unit 8204. Furthermore, main body 8203 includes a camera, thereby allowing input methods using the user's eye movements and eyelid movements.

[0389] Furthermore, multiple electrodes can be provided at the user-contacted location of the mounting unit 8201 to detect the current flowing through the electrodes in response to the user's eye movements, thereby enabling the function of recognizing the user's gaze. Additionally, it can also have the function of monitoring the user's pulse based on the current flowing through the electrodes. The mounting unit 8201 can incorporate various sensors such as temperature sensors, pressure sensors, and acceleration sensors, and may also have the function of displaying the user's biometric information on the display unit 8204 or changing the image displayed on the display unit 8204 in sync with the user's head movements.

[0390] The display device according to one aspect of the present invention can be used in the display unit 8204.

[0391] Figure 16C , Figure 16D and Figure 16EThis is an external view of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a strap-shaped fixing tool 8304, and a pair of lenses 8305.

[0392] The user can see the display on the display unit 8302 through the lens 8305. A curved configuration of the display unit 8302 is preferred because it provides a high degree of realism. Furthermore, by viewing different images displayed on different areas of the display unit 8302 through the lens 8305, three-dimensional displays utilizing parallax are possible. Moreover, one embodiment of the invention is not limited to a structure with only one display unit 8302; two display units 8302 can also be provided, with one display unit for each of the user's eyes.

[0393] A display device according to one aspect of the present invention can be used in the display unit 8302. Because the display device including the semiconductor device according to one aspect of the present invention has extremely high resolution, even if... Figure 16E Using the 8305 lens for magnification in that way allows for the display of more realistic images without the user seeing the pixels.

[0394] Figures 17A to 17G The electronic device shown includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, a sensor 9007 (which has the function of measuring the following factors: force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation), a microphone 9008, etc.

[0395] Figures 17A to 17G The electronic device shown has various functions. For example, it may have the following functions: displaying various information (still images, moving images, text images, etc.) on a display unit; a touch panel function; displaying a calendar, date, or time; controlling processing using various software (programs); wireless communication function; and processing by reading programs or data stored in a storage medium; etc. Note that the functions of the electronic device are not limited to the above functions, but can have various functions. The electronic device may include multiple display units. In addition, a camera or the like may be installed in the electronic device to give it the following functions: capturing still images or moving images and storing the captured images in a storage medium (external storage medium or storage medium built into the camera); displaying the captured images on a display unit; etc.

[0396] The following is a detailed explanation. Figures 17A to 17G The electronic device shown.

[0397] Figure 17A This is a perspective view showing the television unit 9100. A large display unit 9001, for example, 50 inches or larger or 100 inches or larger, can be assembled into the television unit 9100.

[0398] Figure 17B This is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used, for example, as a smartphone. The portable information terminal 9101 may also be equipped with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Furthermore, the portable information terminal 9101 can display text or image information on multiple surfaces. Figure 17B An example showing three icons 9050 is illustrated. Alternatively, information 9051, represented by a dashed rectangle, can be displayed on another surface of the display unit 9001. Examples of information 9051 include notifications of received emails, SNS notifications, or phone calls; the title or sender's name of the email or SNS notification; the date; the time; remaining battery level; and the antenna signal strength. Alternatively, icons 9050 can be displayed in the same location where information 9051 is displayed.

[0399] Figure 17C This is a perspective view showing a portable information terminal 9102. The portable information terminal 9102 has the function of displaying information on three or more surfaces of the display unit 9001. Here, examples are shown where information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053, which is displayed in a position visible from above the portable information terminal 9102, even when the portable information terminal 9102 is placed in a jacket pocket. The user can check this display without taking the portable information terminal 9102 out of their pocket, thereby determining, for example, whether to answer a phone call.

[0400] Figure 17D This is a perspective view showing a watch-type portable information terminal 9200. The portable information terminal 9200 can be used, for example, as a smartwatch. Furthermore, the display surface of the display unit 9001 is curved, allowing for display on the curved surface. For example, the portable information terminal 9200 can make hands-free calls by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006, which allows for data exchange with other information terminals or charging. Furthermore, charging can also be performed using wireless power.

[0401] Figure 17E , Figure 17F and Figure 17G This is a perspective view showing the foldable portable information terminal 9201. Furthermore, Figure 17E This is a 3D view of the portable information terminal 9201 in its unfolded state. Figure 17G This is a 3D view of the portable information terminal 9201 in a folded state, and Figure 17F It is a portable information terminal 9201 for use from Figure 17E and Figure 17G A three-dimensional view of a state transitioning from one state to another. The portable information terminal 9201 is highly portable in its folded state and offers excellent visibility in its unfolded state due to its large, seamlessly integrated display area. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.

[0402] Figure 18A An example of a television device is shown. The display unit 7500 of the television device 7100 is assembled in a housing 7101. The structure in which the housing 7101 is supported by a bracket 7103 is shown here.

[0403] It can be operated using the operating switch provided in the housing 7101 or the separately provided remote control 7111. Figure 18A The operation of the television device 7100 shown is illustrated. Alternatively, a touch panel can be applied to the display unit 7500, allowing operation of the television device 7100 via touch display unit 7500. The remote control 7111 may also include both operation buttons and a display unit.

[0404] In addition, the television device 7100 may also include a television broadcast receiver or a communication device for connecting to a communication network.

[0405] Figure 18B A notebook computer 7200 is shown. The notebook computer 7200 includes a casing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is assembled in the casing 7211.

[0406] Figure 18C and Figure 18D This shows an example of digital signage.

[0407] Figure 18C The digital sign 7300 shown includes a housing 7301, a display unit 7500, and a speaker 7303. It may also include LEDs, operation keys (including a power switch or operation switch), connection terminals, various sensors, and a microphone.

[0408] also, Figure 18DA digital sign 7400 is shown mounted on a cylindrical column 7401. The digital sign 7400 includes a display section 7500 disposed along the curved surface of the column 7401.

[0409] The larger the display unit 7500, the more information it can provide at once, and the easier it is to attract attention, thereby improving the effectiveness of advertising.

[0410] A touch panel is preferably used in the display unit 7500, allowing users to operate it. Therefore, it can be used not only for advertising but also to provide users with information they need, such as route or traffic information, and directions to commercial facilities.

[0411] like Figure 18C and Figure 18D As shown, digital signage 7300 or digital signage 7400 is preferably linked to an information terminal device 7311, such as a smartphone carried by the user, via wireless communication. For example, advertising information displayed on display unit 7500 can be displayed on the screen of information terminal device 7311, and the display on display unit 7500 can be switched by operating information terminal device 7311.

[0412] Furthermore, the game can be executed on the digital signage 7300 or 7400 using the information terminal device 7311 as the operating unit (controller). This allows multiple users to participate in the game simultaneously and enjoy the experience.

[0413] One aspect of the display device of the present invention can be applied to Figures 18A to 18D The display unit 7500 shown is shown.

[0414] Although the electronic device of this embodiment has a structure with a display unit, an embodiment of the present invention can also be used in an electronic device without a display unit.

[0415] At least a portion of this embodiment can be implemented in combination with other embodiments described in this specification.

[0416] [Example]

[0417] In this embodiment, a transistor of one aspect of the present invention is manufactured, and its electrical characteristics are evaluated.

[0418] [Sample manufacturing]

[0419] The structure of the manufactured transistor can be referenced from the transistor 100B illustrated in Embodiment 1 and FIG. 3. Additionally, for comparison, a transistor was also manufactured without processing the oxide film corresponding to the insulating layer 104.

[0420] As the first gate electrode, a tungsten film with a thickness of approximately 100 nm is used, which is formed on a glass substrate by sputtering.

[0421] As the first gate insulating layer, a silicon nitride film with a thickness of approximately 400 nm and a silicon oxynitride film with a thickness of approximately 50 nm are formed by plasma CVD. Furthermore, the silicon oxynitride film is processed using the same photomask as the subsequent second gate electrode.

[0422] As the semiconductor layer, a metal oxide film with a thickness of approximately 40 nm is used, deposited by sputtering using an In-Ga-Zn oxide target.

[0423] As the second gate insulating layer, a silicon oxynitride film with a thickness of approximately 150 nm is used, deposited by plasma CVD. Additionally, openings leading to the first gate electrode are formed in both the second and first gate insulating layers.

[0424] As the second gate electrode, a metal oxide film is deposited by sputtering using the same In-Ga-Zn oxide target used in the formation of the semiconductor layer.

[0425] The second gate electrode and the second gate insulating layer are processed using the same mask, exposing portions of the source and drain regions that form the semiconductor layer. Furthermore, a structure is adopted in which the second gate electrode and the first gate electrode are electrically connected through the aforementioned opening.

[0426] As a protective insulating layer, a layer consisting of a hydrogen-containing silicon nitride film with a thickness of approximately 100 nm and an oxynitride film with a thickness of approximately 300 nm, each formed by plasma CVD, is used. Furthermore, an opening leading to the semiconductor layer is formed within the protective insulating layer.

[0427] As the source and drain electrodes, a stacked structure consisting of a titanium film with a thickness of approximately 50 nm, an aluminum film with a thickness of approximately 400 nm, and a titanium film with a thickness of approximately 100 nm, each formed by sputtering, is used. Additionally, an acrylic resin film is formed as a protective film on the source and drain electrodes.

[0428] Through the above processes, sample A, comprising a transistor formed on a glass substrate, is manufactured. Additionally, a comparative sample is similarly manufactured without processing the silicon oxynitride film of the aforementioned gate insulating layer.

[0429] [Id-Vg characteristics of a transistor]

[0430] The Id-Vg characteristics of the manufactured sample A and the comparative sample were measured. The transistor dimensions used for the measurements were approximately 3 μm in channel length and 3 μm in channel width. Furthermore, 20 measurements were taken.

[0431] As a measurement condition for the Id-Vg characteristic of the transistor, the voltages applied to the first and second gate electrodes (hereinafter also referred to as gate voltage (Vg)) vary from -15V to +20V in increments of 0.25V. Furthermore, the voltage applied to the source electrode (hereinafter also referred to as source voltage (Vs)) is set to 0V (comm), and the voltage applied to the drain electrode (hereinafter also referred to as drain voltage (Vd)) is set to 0.1V and 10V, respectively.

[0432] Figure 19A The Id-Vg characteristics of the reference sample are shown. Figure 19B The Id-Vg characteristics of sample A are shown.

[0433] like Figure 19A and Figure 19B As shown, although the characteristic fluctuations in sample A are slightly larger, sample A exhibits higher current-voltage characteristics than the comparison sample, indicating that it has good transistor characteristics.

[0434] Based on the above results, it can be confirmed that by processing the oxide layer located on the lower side of the semiconductor layer in contact with the channel formation region but not with the source and drain regions, the high resistance of the source and drain regions is suppressed, and high current-voltage characteristics can be achieved.

[0435] [Symbol Explanation]

[0436] 100, 100A, 100B: Transistors; 102: Substrate; 103, 104, 104a, 110, 116, 118: Insulating layers; 104f, 110f: Insulating films; 106, 112, 120a, 120b, 131: Conductive layers; 108: Semiconductor layers; 108n: Regions; 114: Metal oxide layers; 114f: Metal oxide films; 141a, 141b, 142: Openings.

Claims

1. A semiconductor device, comprising: First insulating layer; Second insulating layer; Third insulating layer; Semiconductor layer; First conductive layer; Second conductive layer; Third conductive layer; The fourth conductive layer is located below the first insulating layer; Fourth insulating layer; The fifth insulating layer is located in the region where the first insulating layer and the fourth conductive layer overlap, in the region where the semiconductor layer is not disposed. The second insulating layer is located on the first insulating layer and has an island-like shape. The semiconductor layer has a portion that contacts the top surface of the second insulating layer and a portion that contacts the top surface of the first insulating layer, and has an island-like shape. The third insulating layer and the first conductive layer are sequentially stacked on the semiconductor layer. The second insulating layer is disposed at least in the region where the first conductive layer and the semiconductor layer overlap. The semiconductor layer extends outward beyond a pair of ends of the second insulating layer along the channel length direction. The semiconductor layer is located inside a pair of ends of the second insulating layer in the channel width direction. The third insulating layer contacts the side surface of the second insulating layer in the direction of the channel width. The second conductive layer and the third conductive layer are separated from each other, and the second insulating layer is sandwiched between the second conductive layer and the third conductive layer. The second conductive layer and the third conductive layer each contact the semiconductor layer in the area where the second insulating layer is not disposed. The fourth conductive layer has a region that overlaps with the semiconductor layer, the first conductive layer, and the second insulating layer. The semiconductor layer comprises a metal oxide. The first insulating layer comprises a metal oxide or a nitride. The second insulating layer and the third insulating layer comprise oxides. The fourth insulating layer covers the second insulating layer, the semiconductor layer, the third insulating layer, and the first conductive layer. The fourth insulating layer has a portion that contacts a portion of the top surface of the semiconductor layer in an area where the second insulating layer is not disposed, and a portion that contacts the first insulating layer on the outer side of the end of the semiconductor layer. The fourth insulating layer comprises a metal oxide or a nitride. Furthermore, the fifth insulating layer is located on the same surface as the second insulating layer and contains the same material as the second insulating layer.

2. The semiconductor device according to claim 1, The fourth insulating layer comprises silicon nitride or aluminum nitride.

3. The semiconductor device according to claim 1, The first insulating layer comprises silicon nitride or aluminum oxide.

4. The semiconductor device according to claim 1, A metal oxide layer is further included between the third insulating layer and the first conductive layer. Furthermore, the metal oxide layer and the semiconductor layer contain the same metal element.

5. The semiconductor device according to claim 1, A metal oxide layer is further included between the third insulating layer and the first conductive layer. Furthermore, the metal oxide layer contains aluminum or hafnium.

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