Data processing method and device, computer device and storage medium

Abstract

The application relates to a data processing method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining a target task, obtaining more than one data set corresponding to the target task in parallel, determining an instruction stream corresponding to the target task, the instruction stream comprising more than one target instruction triggering sequence determination, triggering various target instructions in the triggering sequence in a loop, and taking each data set in the more than one data set as a triggering object in sequence when each target instruction is triggered, until an operation result corresponding to the target task is obtained by executing the triggered target instructions. The method can improve the data processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, computer equipment, and storage medium. Background Technology

[0002] With the development of computer technology, machine learning technology has emerged. Various machine learning models based on this technology can improve model accuracy through extensive computation, and in practical applications, they can be used to deploy rich online services. Machine learning models typically include multiple operators; if the computation time of each operator is too long, it will lead to slow service response. For example, in the natural language processing domain, the BERT model (Bidirectional Encoder Representation from Transformers, a general pre-trained language representation model) can be used to deploy rich online services. In such scenarios, people often use graphics processing units (GPUs) to parallelize the BERT service computation process to improve online response speed and reduce service latency. Softmax (normalization) is an important operator in the BERT model; if this operator takes too long to run on the GPU, it will lead to low efficiency in the overall inference task of BERT.

[0003] In traditional approaches, to improve the efficiency of batch processing large amounts of data, the data to be processed is often divided into the smallest processing units, and several of these units are grouped into batches for parallel processing. However, when processing a single smallest unit, if multiple instructions need to be issued and the operands of different instructions are dependent, subsequent instructions must wait for the preceding instructions to finish executing, easily causing instruction issuance stuttering. This results in a very high overall processing time for multiple smallest units, leading to low efficiency in batch processing of large amounts of data. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, and storage medium that can improve the processing efficiency when batch processing large amounts of data, in order to address the above-mentioned technical problems.

[0005] A data processing method, the method comprising:

[0006] Obtain the target task, and simultaneously obtain more than one dataset corresponding to the target task;

[0007] Determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order;

[0008] Various target instructions are triggered cyclically in the order of triggering, and each dataset in the more than one dataset is used as the trigger object when each target instruction is triggered, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0009] A data processing apparatus, the apparatus comprising:

[0010] The acquisition module is used to acquire the target task and acquire more than one dataset corresponding to the target task in parallel.

[0011] A determination module is used to determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order.

[0012] The instruction triggering module is used to cyclically trigger various target instructions according to the triggering order, and when triggering each target instruction, it sequentially takes each dataset in the more than one dataset as the trigger object until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0013] A computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program performing the following steps:

[0014] Obtain the target task, and simultaneously obtain more than one dataset corresponding to the target task;

[0015] Determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order;

[0016] Various target instructions are triggered cyclically in the order of triggering, and each dataset in the more than one dataset is used as the trigger object when each target instruction is triggered, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0017] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0018] Obtain the target task, and simultaneously obtain more than one dataset corresponding to the target task;

[0019] Determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order;

[0020] Various target instructions are triggered cyclically in the order of triggering, and each dataset in the more than one dataset is used as the trigger object when each target instruction is triggered, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0021] The aforementioned data processing method, apparatus, computer equipment, and storage medium, in scenarios requiring the processing of large amounts of data, acquire multiple datasets corresponding to a target task in parallel and determine an instruction stream corresponding to the target task. This instruction stream includes multiple target instructions with a determined triggering order. Furthermore, when processing multiple datasets, various target instructions can be triggered cyclically according to the triggering order. When triggering each target instruction, each dataset in the multiple datasets is sequentially used as the trigger object until the executed target instructions produce the operation result corresponding to the target task. Thus, in one cyclic triggering process, by alternately triggering the same type of target instructions based on different datasets, and then alternately triggering another type of target instruction based on different datasets, until each target instruction in the instruction stream is triggered sequentially, a pipelined issuance of instructions is achieved. This increases instruction-level parallelism to adjust the parallel granularity of the target task, rather than executing the target task corresponding to a single dataset only once, thus balancing resource utilization and parallel efficiency. For the entire dataset, the parallel alternating processing method significantly improves data processing efficiency. Attached Figure Description

[0022] Figure 1 This is a diagram illustrating the application environment of a data processing method in one embodiment.

[0023] Figure 2 This is a flowchart illustrating a data processing method in one embodiment;

[0024] Figure 3 This is a schematic diagram illustrating the principle of a graphics processor performing parallel partitioning of a target task in one embodiment;

[0025] Figure 4 This is a schematic diagram comparing the command issuance code segment in the conventional method with the command issuance code segment in this application in another embodiment;

[0026] Figure 5 This is a flowchart illustrating the steps in one embodiment of cyclically triggering various target instructions in a triggering order, and when triggering each target instruction, sequentially using each dataset in more than one dataset as the triggering object, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0027] Figure 6This is a design overview diagram of an online service system using the Transformer inference engine in one embodiment.

[0028] Figure 7(A) is a schematic diagram of the execution principle of the Softmax operator in a traditional scheme in one embodiment;

[0029] Figure 7(B) is a schematic diagram of the execution principle of the Softmax operator in this application in one embodiment;

[0030] Figure 8(A) is a schematic diagram comparing the performance of Softmax calculation implemented by this application on a processor in one embodiment with that of Softmax calculation in a conventional scheme;

[0031] Figure 8(B) is a schematic diagram showing the performance acceleration of Softmax calculation implemented by this application on a processor in one embodiment compared with Softmax calculation in the conventional scheme;

[0032] Figure 8(C) is a schematic diagram comparing the performance of Softmax calculation implemented by this application on another processor in one embodiment with that of Softmax calculation in a conventional scheme;

[0033] Figure 8(D) is a schematic diagram showing the performance acceleration of Softmax computation implemented by this application on another processor in one embodiment compared with Softmax computation in the conventional scheme;

[0034] Figure 9 This is a structural block diagram of a data processing device in one embodiment;

[0035] Figure 10 This is a structural block diagram of a data processing device in one embodiment;

[0036] Figure 11 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0038] The data processing method provided in this application can be applied to, for example... Figure 1In the application environment shown, user terminal 110 communicates with computer device 120 via a network. A user can initiate a service request through user terminal 110. Computer device 120 generates more than one computing task based on the service request, including a target task. Computer device 120 can acquire the target task, acquire more than one dataset corresponding to the target task in parallel; determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order; cyclically trigger various target instructions according to the triggering order, and when triggering each target instruction, sequentially using each dataset in the more than one dataset as the trigger object, until the triggered target instructions are executed to obtain the operation result corresponding to the target task. Computer device 120 can determine the service processing result corresponding to the service request based on each operation result and feed the service processing result back to user terminal 110.

[0039] The user terminal 110 can be, but is not limited to, various personal computers, laptops, smartphones, tablets, and portable wearable devices. The computer equipment 120 can be a terminal or a server, and the server can be a standalone server or a server cluster consisting of multiple servers.

[0040] It should be noted that the computer device 120 can deploy machine learning models with different functions, enabling the deployment of various types of online services. For example, the computer device can use machine learning models with natural language processing (NLP) capabilities (such as the BERT model) to provide chatbot services, search services, or reading comprehension services. The computer device can also use machine learning models with image processing capabilities (such as semantic segmentation models or image classification models) to provide image classification services, object recognition services, or monitoring and analysis services. Different machine learning models involve multiple operators when providing services, such as Softmax (normalization operator), MatMut (a linear transformation operator), AddBias LayerNorm (a regularization operator), AddBiasActGeLU (an activation function operator), AddBias Transpose (an operator for calculating the transpose matrix), and Lookup Table (an operator for creating a lookup table).

[0041] The normalization operation maps some inputs to real numbers between 0 and 1, and normalization guarantees that the sum is 1, satisfying a probability distribution. The formula is as follows: Where, x j This represents the j-th element in a one-dimensional array. This means that each element in the one-dimensional array is subjected to exp(x)i The sum after the operation. The denominator performs a summation operation on the elements of |x|, which is a reduction operation. In machine learning, reduction operations often operate on a multi-dimensional tensor, thus it can be seen as a batch processing version of the above formula. Merging the high dimensions of the input matrix can be considered as a two-dimensional matrix (high dim, leading dim), also called a two-dimensional matrix (high dimension, low dimension). Therefore, when a reduction operation is needed on an array of length (leading dim), a total of high dim reduction operations need to be performed, which means batch reduction operations are required. When the target task is a reduction task, the data processing method mentioned in this application embodiment can be used to perform batch reduction operations on a large amount of data to be processed, which can greatly improve processing efficiency. Of course, the target task can also be other computational tasks that require batch processing, which is related to the specific application scenario, and this application embodiment does not limit this.

[0042] It should also be noted that the data processing methods mentioned in the embodiments of this application mainly target machine learning models implemented through artificial intelligence technology, which need to perform more than one computational task during operation. This includes the target tasks mentioned in the embodiments of this application. Artificial intelligence (AI) is the theory, method, technology, and application system that uses digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to obtain optimal results. In other words, artificial intelligence is a comprehensive technology in computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. Artificial intelligence studies the design principles and implementation methods of various intelligent machines, enabling them to have perception, reasoning, and decision-making functions.

[0043] Artificial intelligence (AI) is a comprehensive discipline encompassing a wide range of fields, including both hardware and software technologies. Fundamental AI technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, big data processing, operating / interactive systems, and mechatronics. AI software technologies primarily include computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0044] It is understood that the data processing methods in the various embodiments of this application specifically involve machine learning technology in artificial intelligence. Machine learning (ML) is a multidisciplinary field involving probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory, and many other disciplines. It specifically studies how computers can simulate or implement human learning behavior to acquire new knowledge or skills and reorganize existing knowledge structures to continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental way to endow computers with intelligence; its applications span all areas of artificial intelligence. Machine learning and deep learning typically include techniques such as artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and instructional learning.

[0045] The solutions provided in this application relate to machine learning technology in artificial intelligence, and are described in detail through the following embodiments:

[0046] In one embodiment, such as Figure 2 As shown, a data processing method is provided, which can be applied to... Figure 1 Taking computer device 120 as an example, the following steps are included:

[0047] Step S202: Obtain the target task and obtain more than one dataset corresponding to the target task in parallel.

[0048] The target task is the computational task to be performed, which can specifically be a reduction task. The dataset is a collection of data, where each data point can be considered an element; the dataset can also be called a set of elements. In one embodiment, the data in the dataset can specifically be ordered data, such as a one-dimensional array.

[0049] Specifically, the computer device can receive a service request sent by a user terminal and generate a series of computing tasks based on the service request. One of the computing tasks can be a target task, which can be a reduction task. The computer device can acquire the data to be processed corresponding to the target task and decompose the data to be processed into data blocks, and each data block can consist of multiple datasets. The computer device can acquire a preset number of datasets in parallel at one time, and then execute the data processing method mentioned in the embodiments of this application on these preset number of datasets to obtain the operation results corresponding to each dataset. The preset number is greater than one.

[0050] It is understood that this series of computational tasks can be dependent, meaning they have a fixed execution order. For example, once one computational task completes and obtains its result, subsequent computational tasks can execute based on that result. Of course, different computational tasks can also be executed in parallel without any dependency between them, and this application does not limit this.

[0051] In one embodiment, each of the more than one datasets can specifically be a dataset composed of raw data that has not yet undergone the target task. Each of the more than one datasets can also be a dataset composed of data that has already undergone the target task but needs to be executed again. In this case, the dataset is composed of intermediate operation results obtained after the target task has been executed. This embodiment of the application does not limit this.

[0052] In one embodiment, before acquiring more than one dataset corresponding to the target task in parallel, the data processing method further includes a data segmentation step, which specifically includes: acquiring the input matrix to be processed corresponding to the target task; segmenting the input matrix into more than one data block along the high-dimensional direction according to a preset segmentation size; dividing the data block into at least one first data group; the first data group includes a preset number of datasets, the preset number being greater than one.

[0053] The input matrix represents the source data for the target task to be executed, or it can be considered the data to be processed, which is the sum of all datasets for the target task. Specifically, the input matrix can be the feature vector matrix obtained by the machine learning model during processing. This input matrix can be viewed as a two-dimensional matrix (high dim, leading dim), where each one-dimensional array of length leading dim constitutes the dataset mentioned in the embodiments of this application. For the input matrix, there are high dim such datasets.

[0054] Specifically, the computer device can acquire the input matrix to be processed corresponding to the target task. Then, according to a preset partitioning size (e.g., blk_size), the input matrix is ​​divided into several data blocks along the high-dimension direction. This allows the computer device to perform parallel computation on multiple data blocks, balancing resource consumption and processing efficiency. When processing each data block, the computer device can divide that data block into at least one first data group. Each first data group includes a preset number of datasets, where the preset number is greater than one. In other words, the computer device can construct a first data group from the preset number of datasets and process this data group simultaneously in parallel. For example, when the preset number is two, the computer device can perform reduction processing on two datasets in parallel at the same time.

[0055] It is understood that, given sufficient hardware resources, a computer device can process each data block in parallel. Of course, the computer device can also process one data block before processing another; this embodiment of the application does not limit this.

[0056] It should be noted that in online server scenarios with rich machine learning models, due to the large amount of data processing, a large number of computations can be supported by deploying computing devices equipped with graphics processing units (GPUs). By parallelizing a large number of computational tasks, online response speed can be improved and service latency can be reduced. Mapping such batch task operations to the parallel architecture of GPUs for computation requires special techniques. Based on this, various embodiments of this application propose an optimization method for efficient batch task processing on GPUs to accelerate the computation process. The core idea lies in exploiting the high-dimensional parallel computing capabilities of the input matrix.

[0057] In one embodiment, reference Figure 3 , Figure 3 This is a schematic diagram illustrating the principle of a graphics processor performing parallel partitioning of a target task in one embodiment. For example... Figure 3As shown, a computer device can allocate a block of data to a thread block for processing. A thread block comprises several threads, each processing one or more elements. Each thread within the thread block corresponding to a data block is hardware-scheduled to run on a streaming multiprocessor (SM) of the GPU. Within an SM are numerous streaming processes (SPs), each running one thread from the thread block. Threads within a thread block are scheduled in units of warps. A warp is the most basic level of parallelism in a GPU; an SP within an SM is divided into several warps, each containing 32 threads. These 32 threads work together, executing the same instructions.

[0058] In one embodiment, for each data block, the computer device can allocate a corresponding thread block. The computer device can divide the data block into at least one first data group, and execute the target task as a whole for each first data group. That is, the computer device can allocate a corresponding thread bundle for each first data group, wherein one element from each dataset in the first data group is stored in a thread register in the corresponding thread bundle and invoked by the corresponding thread. In this way, the computer device can process the data block by sequentially executing the target operation corresponding to the target task on each first data group. Thus, when processing each data block, instead of processing only one dataset at a time, the data processing efficiency is greatly improved by adjusting the task parallel granularity to balance the utilization of the GPU stream processor and the parallel efficiency.

[0059] In the above embodiments, dividing the input matrix into more than one data block allows a large computational load to be broken down into smaller computational loads that can be processed in batches. Furthermore, adjusting the parallel granularity of the task when processing each data block balances resource utilization and parallel efficiency, thereby significantly improving overall data processing efficiency.

[0060] Step S204: Determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order.

[0061] Instruction streams are sequences of instructions that a computer program needs to execute. The instruction streams mentioned in this application include more than one type of target instruction with a determined triggering order. After a target instruction is triggered, the computer device executes the target operation corresponding to that target instruction. Different types of target instructions correspond to different target operations. For example, when the target task is a reduction task, the corresponding instruction stream includes shuffling instructions and summing instructions, and the target operation corresponding to the target instruction may specifically include shuffling operations and summing operations.

[0062] This can be understood as follows: each target instruction in the instruction stream is an instruction related to the target task. Different types of target instructions, when triggered and executed, can achieve the execution of the target task. For example, when the target task is a summation task, the target instructions in the corresponding instruction stream could specifically be shuffling instructions and summation instructions. When the target task is a maximum value task, the corresponding target instructions could specifically include shuffling instructions and maximum value instructions. When the target task is a variance calculation task, the corresponding target instructions could specifically include shuffling instructions, multiplication instructions, summation instructions, and instructions for division, etc. It is understood that the target instructions included in the instruction stream are related to the specific target task, and this application embodiment does not limit this.

[0063] Specifically, after determining a target task, a computer device can determine the instruction stream required to execute that target task. This instruction stream includes more than one type of target instructions with a predetermined triggering order. The predetermined triggering order means that the execution order of each target instruction among the more than one type of target instructions is fixed. For example, when the instruction stream includes a first instruction and a second instruction, the first instruction must be executed before the second instruction; that is, the second instruction can only be executed after the first instruction has been executed.

[0064] In one embodiment, there are dependencies between different types of target instructions. For example, when the target task is a reduction task, the corresponding instruction stream includes a shuffle instruction (SHFL instruction) and a summation instruction (FADD instruction). The destination operand of the SHFL instruction and the source operand of the FADD instruction are the same, therefore these two instructions are dependent. That is, the computer device can only issue the corresponding FADD instruction based on the target operand after issuing and executing the SHFL instruction to obtain the target operand.

[0065] In one embodiment, the instruction stream includes a first instruction and a second instruction, the first instruction being triggered before the second instruction; the triggering object of the second instruction also includes first target operation data obtained by executing the first instruction, wherein the execution time of the first instruction is more than one time period.

[0066] Specifically, the instruction stream includes a first instruction and a second instruction, with the first instruction being triggered before the second instruction. The triggering object of the second instruction also includes the first target operation data obtained by executing the first instruction, wherein the execution time of the first instruction is more than one time cycle.

[0067] In one embodiment, the target task includes a reduction task, with the corresponding first instruction being a shuffle instruction (SHFL instruction) and the second instruction being a summation instruction (FADD instruction). During each instruction stream cycle, the computer device first issues an SHFL instruction, then performs the corresponding shuffle operation to obtain the corresponding first destination operation data. This first destination operation data is then used as the source operation data for the FADD instruction, which is then issued and executed.

[0068] In the above embodiments, the instruction stream includes a first instruction and a second instruction. The issuance of the first instruction and the second instruction is dependent on each other; that is, the first instruction is triggered before the second instruction, and the triggering object of the second instruction also includes the first target operation data obtained by executing the first instruction. In this way, through the dependency relationship between different instructions, the entire instruction stream can work together to assist in the execution of the target task.

[0069] Step S206: Circularly trigger various target instructions in the triggering order, and when triggering each target instruction, take each dataset in more than one dataset as the trigger object in turn, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0070] Specifically, the computer device can cyclically trigger various target instructions in a triggering order, and when triggering each target instruction, it sequentially uses each dataset in the more than one dataset as the trigger object. In other words, the computer device will alternately trigger the target instructions corresponding to each dataset in the more than one dataset, and then execute the corresponding target operation until the execution of each triggered target instruction obtains the operation result corresponding to the target task, at which point it stops transmitting target instructions.

[0071] In one embodiment, the dataset includes a first instruction and a second instruction. For a dataset, when a computer device triggers a target instruction that takes each element in the dataset as the trigger object, the first target operation data obtained after the first instruction, which is triggered first in the triggering order, is also used as the trigger object for the second instruction, which is triggered later in the triggering order.

[0072] In one embodiment, taking two datasets (more than one dataset) as an example, the triggering method of the target instruction is described as follows: The computer device can allocate corresponding thread bundles to the two datasets and configure two sets of registers for each thread bundle to store the two datasets respectively. For ease of description, the two datasets can be referred to as the first dataset and the second dataset. One element (referred to as the first element) in the first dataset is assigned to a thread in the corresponding thread bundle, and one element (referred to as the second element) in the second dataset is also assigned to that thread. The computer device can store the first element and the second element in the corresponding first register and second register respectively. Thus, in one loop of triggering, each thread in the thread bundle can use one element from the first dataset as the trigger object to trigger the first instruction, then use one element from the second dataset as the trigger object to trigger the first instruction, then use another element from the first dataset as the trigger object to trigger the second instruction, and so on. Each time a thread triggers the target instruction, each thread can read the trigger object from the corresponding register and execute the corresponding triggering operation based on the trigger object. This process continues until the triggered target instructions are executed and the operation results corresponding to each dataset are obtained. These operation results also correspond to the target task.

[0073] In one embodiment, the code for triggering the target instruction in a single loop is as follows:

[0074] SHFL.XOR,R4,R3,0X10,0X1F / / (First instruction 1) / /

[0075] SHFL.XOR,R6,R5,0X10,0X1F / / (First instruction 2) / /

[0076] FADD R3,R3,R4 / / (Second instruction 1) / /

[0077] FADD R5,R5,R6 / / (Second instruction 2) / /

[0078] In this instruction snippet, Instruction 1 and Instruction 2 are target instructions for the first dataset; Instruction 1 and Instruction 2 are target instructions for the second dataset. As can be seen from the above instruction snippet, the target register R3 of the SHLF instruction for the first dataset only becomes the source operand of FADD after two cycles. One cycle in between allows for the issuance of an additional SHFL instruction for the second dataset, increasing instruction-level parallelism, reducing instruction issue stuttering caused by operand dependencies, and enabling pipelined instruction issuance.

[0079] The following example illustrates how the instruction triggering method described in this application improves processing efficiency: FADD can only be executed two cycles after SHLF. In the traditional method, issuing two sets of instruction streams requires six cycles, such as: 1SHLF; 2--; 3FADD; 4SHLF; 5--; 6FADD. However, in this application embodiment, it only requires four cycles, such as: 1SHLF; 2SHLF; 2FADD; 3FADD. This significantly improves instruction issuance efficiency, thereby improving the processing efficiency for more than one dataset. This efficiency improvement is particularly pronounced when processing large datasets.

[0080] In one embodiment, when triggering each target instruction, sequentially using each dataset from more than one dataset as the trigger object specifically includes: in each loop triggering process, when triggering the first instruction, sequentially using each dataset from more than one dataset as the trigger object, and obtaining first target operation data corresponding to each dataset by executing the first instruction; when triggering the second instruction, sequentially using the first target operation data corresponding to each dataset and the corresponding dataset as the trigger object, and obtaining second target operation data corresponding to each dataset by executing the second instruction, wherein the second target operation data is used to update the corresponding dataset.

[0081] Specifically, in each loop triggering process, when the computer device triggers the first instruction, it can sequentially use each dataset from more than one dataset as the trigger object, and obtain the first objective operation data corresponding to each dataset by executing the first instruction. Then, when triggering the second instruction, the computer device can sequentially use the first objective operation data corresponding to each dataset and the corresponding dataset as the trigger object, and obtain the second objective operation data corresponding to each dataset by executing the second instruction, and then update the corresponding dataset using the second objective operation data. In this way, in the next loop triggering process, the next round of triggering can be based on the second objective operation data obtained in the previous loop, and so on, continuously triggering and updating, until the operation result corresponding to each dataset is obtained.

[0082] In one embodiment, the instruction stream includes shuffling instructions and summing instructions. The computer device can trigger the shuffling and summing instructions corresponding to each dataset in a cross-processing manner until the datasets are processed in parallel to obtain the reduction result corresponding to the reduction task. For each dataset, the computer device can obtain data from a register through the thread corresponding to that dataset, trigger the shuffling instruction and execute the shuffling operation, and then trigger and execute the summing instruction on the first destination operation data of the shuffling operation and the data in the register corresponding to that thread to obtain the second destination operation data, and replace the original data in the register with the second destination operation data. In this way, the shuffling and summing operations are executed cyclically until the sum of all data in the dataset is obtained, which is the reduction result corresponding to that dataset.

[0083] refer to Figure 4 , Figure 4 This is a schematic diagram comparing the instruction issuance code segment in the conventional method with the instruction issuance code segment in this application in one embodiment. Figure 4 The left side shows a code snippet for issuing commands in the traditional method, from... Figure 4 As can be seen on the left, in the traditional scheme, only one dataset is processed at a time. Therefore, the destination operand R3 of each SHFL instruction is the source operand R3 of the next instruction FADD. This means FADD must wait for SHFL to complete before it can be issued, resulting in very low instruction execution efficiency. However, the reference... Figure 4 In the instruction issuance code snippet in the embodiment of this application on the right, the destination operand R3 of the SHLF instruction is used as the source operand of FADD only after two cycles. In the cycle between them, an additional SHFL instruction can be issued, which increases instruction-level parallelism.

[0084] In the above embodiments, by adjusting the parallel granularity of tasks, target instructions for other datasets can be issued during the waiting period for issuing different types of target instructions to one dataset. This balances resource utilization and greatly improves the parallel efficiency of instruction issuance.

[0085] In one embodiment, the computer device can acquire a target task and determine the instruction stream corresponding to the target task. This instruction stream includes more than one type of target instruction with a determined triggering order. The computer device can then acquire more than one dataset corresponding to the target task in parallel and allocate corresponding thread blocks to these datasets. One element from each dataset is assigned to a thread within a thread block. In this way, the computer device can cyclically trigger various target instructions according to the triggering order through each thread in the thread block. When triggering each target instruction, each dataset in the more than one dataset is used as the trigger object in sequence until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0086] In one embodiment, the data processing methods mentioned in the embodiments of this application are implemented by running on a graphics processing unit (GPU), and the target task mentioned in the embodiments of this application can specifically be a reduction task. This reduction task can specifically be an operator in a machine learning model. That is, when a computer device performs specific business processing through this machine learning model, a reduction operation is performed during the processing. Therefore, by using the data processing methods mentioned in the embodiments of this application to perform the corresponding reduction operation, processing efficiency can be greatly improved. Specifically, the machine learning model, when applied to the field of natural language processing, can be a language representation model, such as the BERT model.

[0087] The aforementioned data processing method, in scenarios requiring the processing of large amounts of data, acquires multiple datasets corresponding to the target task in parallel and determines the instruction stream corresponding to the target task. This instruction stream includes multiple target instructions with a predetermined triggering order. Then, when processing multiple datasets, various target instructions can be triggered cyclically according to the triggering order. When triggering each target instruction, each dataset in the multiple datasets is used as the trigger object in turn, until the triggered target instructions are executed and the operation result corresponding to the target task is obtained. In this way, during a single cyclic triggering process, by alternately triggering the same type of target instructions based on different datasets, and then alternately triggering another type of target instruction based on different datasets, until each target instruction in the instruction stream is triggered sequentially, a pipelined issuance of instructions is achieved. This increases instruction-level parallelism to adjust the parallel granularity of the target task, rather than executing the target task corresponding to a single dataset only once, thus balancing resource utilization and parallel efficiency. For the entire dataset, the parallel alternating processing method significantly improves data processing efficiency.

[0088] In one embodiment, performing a target operation on more than one dataset is a two-phase process. The following details how these two phases are implemented. (References) Figure 5 Step S206, which involves cyclically triggering various target instructions in the triggering order, and when triggering each target instruction, sequentially using each dataset from more than one dataset as the trigger object, until the triggered target instructions are executed to obtain the operation result corresponding to the target task, specifically includes the following steps:

[0089] Step S502: Divide each dataset into more than one set of data subsets, and take one of the data subsets in each dataset as the second data set.

[0090] In one embodiment, the computer device may divide each dataset into more than one set of data subsets, wherein each data subset includes a predetermined number of elements. The computer device may then select one data subset from each dataset as a second data set.

[0091] For example, there may be more than one dataset, including a first dataset and a second dataset. Each dataset contains 64 elements, and a computer device can consider 32 elements from each dataset as a subset. That is, the first dataset contains two first subsets; the second dataset contains two second subsets. The computer device can then combine one of the first subsets and one of the second subsets into a single second dataset, meaning there can be two second datasets.

[0092] Step S504: Assign a corresponding thread bundle to each of the second data groups.

[0093] Specifically, the computer device may allocate a corresponding thread bundle to each of the second data groups. Each thread in the thread bundle corresponds to a preset number of registers, and each of the preset number of registers is used to store one of the elements in a subset of the data.

[0094] For example, when the second data set includes a first data subset and a second data subset, and each data subset includes 32 elements, the computer device can allocate a thread bundle for the second data set, wherein each thread bundle corresponds to two registers, and the two registers in each thread bundle are used to store one element from the first data subset and one element from the second data subset, respectively.

[0095] In one embodiment, the step of dividing each dataset into more than one set of data subsets and obtaining one data subset from each dataset as a second data group specifically includes: determining the number of threads corresponding to a thread bundle, and dividing each dataset into more than one set of data subsets based on the number of threads; obtaining one data subset from each dataset as a second data group. The step of assigning a corresponding thread bundle to each data group specifically includes: obtaining the same number of thread bundles as the second data group, and assigning each second data group to one of the thread bundles.

[0096] The number of threads refers to the number of threads included in a thread bundle. For example, if a thread bundle contains 32 threads, then the corresponding number of threads is 32. Specifically, the computer device can determine the number of threads corresponding to a thread bundle and, based on this number, divide each dataset into more than one subset of data. That is, every 32 elements in the dataset constitutes a subset. Elements that, when divided to the last few elements, are also grouped into a subset. Then, the computer device can obtain one subset of data from each dataset as a second data group. The computer device then obtains the same number of thread bundles as the second data groups and assigns each second data group to one of the thread bundles.

[0097] In the above embodiments, the computer device can divide each dataset into more than one set of data subsets according to the number of threads corresponding to the thread bundle. In this way, one data subset in each dataset can be assigned to a thread bundle for processing, which facilitates triggering each target instruction in the instruction stream according to the thread bundle.

[0098] Step S506: For each thread bundle, various target instructions are triggered cyclically in the triggering order. When each target instruction is triggered, each data subset in the second data group corresponding to the thread bundle is taken as the trigger object in turn, until the intermediate operation results corresponding to each data subset in the corresponding second data group are obtained by executing the triggered target instructions through the thread bundle.

[0099] Specifically, each thread in the thread bundle cyclically triggers various target instructions in the order of triggering. When each target instruction is triggered, each thread takes each data subset in the second data group corresponding to the thread bundle as the trigger object in turn, until the intermediate operation results corresponding to each data subset in the corresponding second data group are obtained by executing the triggered target instructions through the thread bundle.

[0100] In one embodiment, the instruction stream includes a first instruction and a second instruction. For each thread bundle, during each loop triggering process, when a thread in that bundle triggers the first instruction, it can sequentially use one element from each data subset in the second data group as the trigger object, and obtain the first destination operation data corresponding to each data subset by executing the operation corresponding to the first instruction. Then, when triggering the second instruction, the computer device can sequentially use the first destination operation data corresponding to each data subset and another element from the corresponding data subset as the trigger object, and obtain the second destination operation data corresponding to each data subset by executing the operation corresponding to the second instruction, and then update the corresponding data subset using each second destination operation data. In this way, in the next loop triggering process, the next round of triggering can be based on the second destination operation data obtained in the current loop, and so on, triggering and updating continuously until the intermediate operation results corresponding to each data subset are obtained.

[0101] In one embodiment, each thread bundle may select a representative thread to store the intermediate operation results corresponding to each data subset in the corresponding second data group to the corresponding shared location. In one embodiment, after each Warp selects a representative thread to write to the shared memory, it needs to perform a synchronization operation __syncthreads(), and all threads in the thread bundle must wait for each other to have reached the synchronization operation before continuing execution.

[0102] In one embodiment, the computer device may store the intermediate operation results stored in each shared location into the register corresponding to the thread bundle of the second stage. The thread bundle of the second stage may determine the operation result corresponding to each dataset based on the intermediate operation results stored in each register corresponding to each subset of data.

[0103] Step S508: Based on the intermediate operation results corresponding to each data subset in the second data group corresponding to each thread bundle, determine the operation results corresponding to each dataset.

[0104] Specifically, the computer device can execute the target operation corresponding to the target task again based on the intermediate operation results corresponding to each data subset in the second data group corresponding to each thread bundle, and obtain the operation results corresponding to each dataset respectively.

[0105] In one embodiment, for each dataset, the computer device can obtain intermediate operation results corresponding to each subset of data in the dataset, and based on each intermediate operation result, cyclically trigger various target instructions in a triggering order, and execute the target operation corresponding to each target instruction after triggering the target instruction, until the operation result corresponding to the dataset is obtained. In this way, the computer device can obtain the operation result corresponding to each dataset.

[0106] In one embodiment, step S508, which is the step of determining the operation result corresponding to each dataset based on the intermediate operation result corresponding to each data subset in the second data group corresponding to each thread bundle, specifically includes: constructing an intermediate array corresponding to the corresponding dataset from the intermediate operation results corresponding to each data subset in each dataset; cyclically triggering various target instructions in the triggering order, and when triggering each target instruction, sequentially using each intermediate array in more than one intermediate array as the trigger object, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0107] Specifically, the computer device can construct an intermediate array corresponding to each subset of data in each dataset, based on the intermediate operation results of each subset. Thus, after one round of target operations corresponding to the target task, each subset of data in each dataset can obtain a corresponding intermediate operation result, and these intermediate operation results can form a one-dimensional intermediate array. That is, for a predetermined number of datasets, a predetermined number of intermediate arrays will be generated. Furthermore, the computer device can perform a second-stage target operation on these predetermined number of intermediate arrays to obtain the corresponding operation results. Specifically, the computer device can allocate corresponding thread bundles to these predetermined number of intermediate arrays, and then, through the allocated thread bundles, cyclically trigger various target instructions according to the triggering order. When triggering each target instruction, each intermediate array in more than one intermediate array is used as the trigger object in turn, until the triggered target instructions are executed and the operation result corresponding to the target task is obtained.

[0108] The following example, using the target task as the reduction task and the corresponding target operation as the reduction operation, illustrates the two-stage process: For each subset of data in each dataset, the computer device can use the `warpAllReduceSum` function to perform a reduction summation operation on the elements stored in the 32 threads within a warp, obtaining intermediate operation results corresponding to a subset of data. The computer device can then write the intermediate operation results corresponding to each subset of data to their respective shared memory. The computer device can then write the intermediate operation results from each shared memory to a warp register, and finally run the `warpAllReduceSum` function again to obtain the reduction result for the entire dataset.

[0109] In the above embodiments, when processing more than one dataset in parallel, the target task can be completed by executing a two-stage loop to trigger the target instruction in the instruction stream and perform the corresponding target operation. This balances resource utilization and parallel efficiency.

[0110] In one embodiment, the computer device may also use other methods to fuse the intermediate operation results corresponding to each data subset in a dataset to obtain the operation result corresponding to the dataset. For example, the computer device may directly perform summation or multiplication operations on the intermediate operation results corresponding to each data subset in a dataset to obtain the operation result corresponding to the target task. This application embodiment does not limit this approach.

[0111] In one embodiment, during the second phase of WarpReduce, the thread bundle used to process the results of each intermediate operation, after obtaining the operation result corresponding to each dataset, can store each operation result to a specified shared location, which may specifically be shared memory. After writing to the shared memory, the thread bundle needs to perform a synchronization operation before continuing to execute subsequent tasks.

[0112] In the above embodiments, when processing more than one dataset in parallel, each dataset can be split into data subsets for processing, and then the intermediate operation results corresponding to each data subset can be merged to obtain the operation result corresponding to the target task. By adjusting the parallel granularity of data processing, both data processing efficiency and resource utilization can be taken into account.

[0113] In one embodiment, the data processing method further includes a branch judgment step, which specifically includes: when the number of elements in the data subset is less than the number of threads in the thread bundle, determining the valid and invalid threads in the thread bundle; the valid thread is the thread that has been assigned elements to be processed; the invalid thread is the thread that has not been assigned elements to be processed; wherein, the elements to be processed are the elements in each data subset in the second data group. Step 506, that is, for each thread bundle, various target instructions are triggered cyclically in the triggering order, and when each target instruction is triggered, each data subset in the second data group corresponding to the thread bundle is used as the trigger object in turn, until the intermediate operation results corresponding to each data subset in the corresponding second data group are obtained by executing the triggered target instructions through the thread bundle, including: for each thread bundle, various target instructions are triggered cyclically in the triggering order, and when a valid thread in the thread bundle triggers each target instruction, the corresponding assigned elements to be processed are used as the trigger object to implement the triggering of the target instruction; when an invalid thread in the thread bundle triggers each target instruction, a preset value is used as the corresponding trigger object to implement the triggering of the target instruction.

[0114] The preset value is a value that does not affect the operation result. For example, when the target task is maximum value reduction, this preset value is the smallest number that a computer device can represent; when the target task is summation reduction, this preset value is zero. Specifically, since each thread runs in units of thread bundles, if the number of elements in a certain subset of data is less than the number of threads in a thread bundle, the threads allocated to that subset of data will be padded to form a thread bundle. For example, when performing a WarpReduce operation on each dataset, since WarpReduce is performed in units of 32 threads, the size of the thread block corresponding to that dataset needs to be padded to be aligned to 32. That is, threads with fewer than 32 threads will be padded to 32. For example, by adjusting (blk, leading dim) to (blk, (leading dim+31) / 32*32) to make it an integer multiple of 32. The padded threads can be called invalid threads, that is, threads outside the boundary. In other words, threads that have been assigned pending elements in a thread bundle are considered valid threads, while threads that have not been assigned pending elements in a thread bundle are considered invalid threads.

[0115] It's understandable that an invalid thread cannot obtain valid data from the registers during runtime; therefore, this boundary case requires branching. The thread within the Warp can pre-execute the judgment step. When the thread within the Warp is a valid thread, it directly triggers each target instruction based on the element stored in the corresponding register; when the thread within the Warp is an invalid thread, it directly uses a preset value that does not affect the reduction result as the trigger object to trigger the corresponding target instruction—that is, assigning a value of 0 during the reduction operation. This judgment step can be implemented using if and else statements, so the if and else instructions need to be executed once before the reduction operation.

[0116] In traditional methods, branch checks are performed before executing the target operation on a single dataset using a thread bundle. Therefore, executing the target operation on N datasets (where N is a positive integer greater than 1) requires N branch checks, which undoubtedly incurs significant resource overhead and processing time. However, the method described in this application adjusts the parallel granularity to more than one dataset, such as M datasets (where M is a positive integer greater than 1 and M is less than N). Before executing the target operation on M datasets using a thread bundle, branch checks are performed; therefore, executing the target operation on N datasets requires N / M branch checks. This significantly reduces resource consumption and processing time, improving processing efficiency.

[0117] In the above embodiments, since each thread runs in units of thread bundles, invalid threads in a thread bundle are not assigned any elements to be processed. Therefore, during the operation, they can be assigned a preset value that does not affect the reduction result. This ensures that invalid threads do not affect the intermediate operation results corresponding to the data subset during the operation.

[0118] In one embodiment, the data processing method further includes a synchronization waiting step, which specifically includes: storing the operation results corresponding to each dataset in more than one dataset to the corresponding shared location; maintaining a waiting state after performing the synchronization operation until the waiting end condition is met to enter the next target task execution process.

[0119] Specifically, satisfying the waiting stop condition means that all threads in the thread block participating in the target task have executed to the synchronization operation. Specifically, the computer device can store the operation results corresponding to each dataset in more than one dataset to their respective designated shared locations, which can be shared memory. After completing the write to shared memory, the graphics processor needs to perform a synchronization operation, namely the operation corresponding to the __syncthreads() instruction, until all other parallel processing threads have executed to the synchronization operation before proceeding to the next execution of the target task.

[0120] In the above embodiments, the processing progress of different threads can be coordinated through synchronization operations, so as to better control the execution of the target task.

[0121] In one embodiment, the target task includes a reduction task; the operation result includes a reduction result. The data processing method further includes a normalization step, which specifically includes: acquiring the reduction result corresponding to each of more than one dataset in parallel; for each dataset, performing a division operation between each element in the dataset and the reduction result corresponding to the corresponding dataset to obtain the normalized distribution result corresponding to the corresponding dataset.

[0122] Specifically, the computer device can acquire the reduction results corresponding to each of more than one dataset in parallel. Then, for each dataset, each element in the dataset is divided by the reduction result corresponding to the corresponding dataset to obtain the normalized result for each element. The normalized results corresponding to each element in the dataset constitute the normalized distribution result for the dataset.

[0123] In one embodiment, a computer device issues various target instructions from an instruction stream via a thread and executes corresponding operations to obtain a reduction result corresponding to each dataset. This reduction result can be... This means that the computer device stores the reduction results corresponding to each dataset in shared memory, which can be accessed by other threads after a synchronization operation, and a division is performed to obtain the normalized result. result.

[0124] In the above embodiments, for each dataset, the normalized distribution result corresponding to the dataset can be obtained by dividing each element in the dataset by the reduction result corresponding to the dataset.

[0125] In one embodiment, the data processing method is executed by a graphics processor deployed on a computer device, and the data processing method is applied to a language representation model; wherein the reduction task is a subtask of the normalization task, and the normalization task is one of the computational tasks in the language representation model.

[0126] Specifically, the data processing methods mentioned in the embodiments of this application are executed by a graphics processor deployed on a computer device, and these data processing methods are applied to a language representation model. When performing business processing, the language representation model needs to execute various computational tasks, one of which is a normalization task. The reduction task is a sub-task of the normalization task.

[0127] For example, computer devices can deploy BERT models to provide online services, and Softmax is an important operator in the BERT model, which includes a reduction task as a subtask during execution. If the Softmax operator takes too long to run on the GPU, it will lead to low efficiency in the overall inference task of BERT. However, the data processing methods provided in the embodiments of this application can efficiently execute the reduction task, thereby improving the computational efficiency of the Softmax operator, thus improving the business processing efficiency of BERT, increasing online response speed, and reducing service latency.

[0128] In a specific application scenario, deploying this BERT model can provide various online services, such as question-answering services, reading comprehension services, information retrieval services, chatbot services (Dialog System or Chatbot), text summarization extraction services, or sentence similarity comparison services. Users can trigger business requests corresponding to a certain service through their user terminals, such as information retrieval requests corresponding to the information retrieval service. The computer equipment can then perform corresponding business processing and provide feedback through the BERT model. During the business processing, the BERT model sometimes requires normalization. For example, the BERT model needs to normalize the feature vectors extracted during intermediate processing. In this case, the data processing methods mentioned in the embodiments of this application can be used to reduce the feature vectors before performing division to obtain the normalized result, allowing subsequent computational tasks to continue.

[0129] In the above embodiments, the computational tasks in the language representation model can be processed in parallel using a graphics processing unit (GPU). These computational tasks include a normalization task, which in turn includes a reduction task. By performing cross-parallel processing on batches of reduction tasks, the execution of reduction tasks can be achieved efficiently, thereby improving the computational efficiency of the Softmax operator. This, in turn, improves the business processing efficiency of the language representation model, thereby increasing the online response speed when providing online services through the language representation model and reducing service latency.

[0130] In one embodiment, before obtaining the target task, the data processing method further includes: obtaining a business request and generating more than one computational task based on the business request; the more than one computational task includes the target task. After the step of dividing each element in the dataset by the reduction result corresponding to the corresponding dataset to obtain the normalized distribution result for each dataset, the data processing method further includes: processing the computational tasks in subsequent stages based on the normalized distribution results corresponding to each dataset to obtain the business processing result corresponding to the business request; and responding to the business request by feeding back the business processing result.

[0131] Specifically, the computer device can receive a service request triggered by a user terminal and generate more than one computing task based on the service request, including a target task. It is understood that the service request may specifically be a search request, an image recognition request, or a data acquisition request, etc. Based on different online services, the user terminal can trigger different service requests, and this embodiment does not limit this. Furthermore, the computer device can generate more than one computing task based on the service request. This computing task may be a feature extraction task, a reduction task, a normalization task, or a classification task, etc., related to the specific service request, and this embodiment does not limit this.

[0132] Furthermore, for each first data set, the computer device can cyclically trigger various target instructions sequentially according to the order of instructions in the instruction stream. When triggering each target instruction, each dataset in the first data set is sequentially used as the trigger object until the triggered target instructions are executed and the reduction result corresponding to the reduction task is obtained. In this way, the computer device can obtain the reduction result corresponding to each dataset.

[0133] Furthermore, the computer device can acquire the reduction results corresponding to each dataset in the first data group in parallel. For each dataset, each element in the dataset is divided by the reduction result corresponding to the corresponding dataset to obtain the normalized distribution result for that dataset. Based on the normalized distribution results corresponding to each dataset, subsequent computational tasks are processed to obtain the business processing result corresponding to the business request. The computer device responds to the business request by providing the corresponding business processing result. For example, when the business request is a search request, the computer device can provide the search results to the user terminal. When the business request is a data retrieval request, the computer device can provide the corresponding target data to the user terminal.

[0134] In one embodiment, the computer device can obtain the normalized distribution results corresponding to each dataset in the input matrix. Then, based on the normalized distribution results corresponding to each dataset, the computer device can process subsequent computational tasks to obtain the business processing results corresponding to the business request, and feed them back to the user terminal.

[0135] For example, computer devices can provide question-answering services, reading comprehension services, information retrieval services, chatbot services (dialog systems or chatbots), text summarization services, or sentence similarity comparison services based on machine learning models (such as the BERT model). Users can trigger business requests corresponding to a certain service through their user terminals, such as information retrieval requests, which carry the search text. The computer device can then use the machine learning model to process candidate content in the database. Specifically, it can extract features from the candidate texts, normalize the extracted features, and then classify them to obtain the probability that each candidate text belongs to the target category. Based on these probabilities, the target text is then selected from the candidate texts and fed back to the user terminal.

[0136] In a specific application scenario, refer to Figure 6 , Figure 6 This is a design overview diagram of an online service system employing the Transformer inference engine in one embodiment. (See diagram for example.) Figure 6 As shown, the specific application service could be WeChat Reading, Tencent Xiaowei, WeChat Dialogue Open Platform, etc. To provide these application services, the computer equipment needs to be deployed with corresponding hardware architecture or platforms, such as Intel CPUs (central processing units), NVIDIA GPUs, and open-source container orchestration engines based on Kubernetes. Based on this hardware platform, operator operations can be provided, such as MatMut, Softmax, AddBiasActGeLU, AddBiasTranspose, and Lookup Table operators under the transformers / Bert Encoder architecture (a neural network model architecture). These operators can form corresponding frameworks, such as Pybind11 (a tool for calling C++ code from Python), Tensor Conversion, Memory Management, and Pretrain Model Loader. Correspondingly, these frameworks can provide interfaces for invocation, such as interfaces based on PyTorch (a machine learning library) and conda (a package management and environment management system). By calling these interfaces or deploying them, online application services can be provided, such as WeChat Reading, Tencent Xiaowei, or WeChat Dialogue Open Platform.

[0137] In the above embodiments, after obtaining the normalized distribution results corresponding to the corresponding datasets, the subsequent calculation tasks are processed based on the normalized distribution results corresponding to each dataset according to the received business request, so as to obtain the business processing results corresponding to the business request and provide feedback, which can reduce the delay of the upper-layer business response.

[0138] The following detailed comparison illustrates how the data processing methods mentioned in the various embodiments of this case improve data processing efficiency.

[0139] Taking the Softmax operator in neural network algorithms as an example, in a traditional NVIDIA solution, the parallel processing of Softmax computation typically works as follows: The computer divides the input matrix along its high-dimension dimension into several parts, each with a size of blk_size. Each data block is assigned to a thread block for processing. A thread block contains several threads, each processing one or more elements. The thread block containing the elements in the data block to be processed (blk_size, leading dim) is hardware-scheduled to run on a Single Module (SM) of the GPU. Within the SM, there are many Single Module (SP) units, each running one thread from the thread block. Threads within a thread block are scheduled in units of Warp, where Warp is the most basic parallel granularity of the GPU, with each Warp containing 32 threads. These 32 threads in a Warp work together, executing the same instructions.

[0140] The most challenging aspect is performing reduction operations on the leading dim, which requires communication and time synchronization of data within different SP registers of the GPU. Traditionally, this can be achieved using the blockReduce algorithm (a reduction processing algorithm), a two-stage process. As shown in Figure 7(A), which illustrates the execution principle of the Softmax operator in a traditional scheme in one embodiment, one arrow in Figure 7(A) represents a thread. An element from a dataset (i.e., a row of leading dim) can be stored in the register of one thread. 32 threads constitute a thread bundle; for example, the threads corresponding to registers 0-31 in Figure 7(A) constitute a thread bundle. In this scheme, the reduction and summation of the elements stored by the 32 threads within a warp can be directly achieved using the warpAllReduceSum function, and this result is first written to shared memory. Since NVIDIA GPUs limit the number of threads in a thread block to no more than 1024, the number of warps within a thread block also does not exceed 32. The computer can then write the shared memory data into a warp register, and then run the warpAllReduceSum function again to obtain the reduction result corresponding to this dataset. Note that after each warp selects a representative thread to write to shared memory, it needs to perform a __syncthreads() operation and wait until all threads in the thread block have arrived before continuing execution. The __syncthreads operation is very time-consuming, which contributes to the overall time-consuming process.

[0141] Now that we've solved the reduction operation `blockReduceSum` on each row of the two-dimensional matrix `(blk_size, leading dim)` containing `leading dim` elements, the solution for Softmax is to implement it using `blk_size` one-dimensional reduction operations, as shown in Figure 7(A). The box contains the `blockReduce` process, which reduces the elements stored in each thread's register. The final reduction result is stored in a register of a specific thread. Outside the box, the value of this register is stored in shared memory and can be accessed by other threads after a synchronization operation to perform a division to obtain the normalized result.

[0142] However, the normalization process mentioned above is not the most efficient and there is still much room for improvement.

[0143] For example, performing reduction operations through the warpAllReduceSum function is not efficient. The destination operand of the shuffle instruction (__shfl_xor_sync instruction) and the source operand of the summation instruction (fadd instruction) inside the loop are the same. Therefore, these two instructions are dependent on each other. After the shuffle instruction is issued, it must wait for the corresponding shuffle operation to complete and obtain the corresponding destination operand before the summation instruction can be issued. This will cause the instruction pipeline to be stuck and result in low instruction execution efficiency.

[0144] Secondly, since WarpReduce operates on a 32-thread basis, the thread block size needs to be padded to a multiple of 32. This means that registers for some threads outside the boundary (also known as invalid threads) will be empty. These threads do not participate in the computation, and during reduction, they are assigned a preset value that does not affect the reduction result. This necessitates branching in boundary cases, requiring each thread within the WarpReduce to execute both the if and else statements, which incurs significant overhead.

[0145] Finally, after each warp selects a representative thread to write to shared memory, a `__syncthreads()` operation is required, which incurs significant `thread_sync` overhead. With a loop length of `blk_size`, this requires 2 * `blk_size` thread synchronization operations using `__syncthread`, making the synchronization overhead considerable.

[0146] The data processing methods provided in the embodiments of this application can solve the problems in the traditional solutions and improve the computational efficiency of the Softmax operator in the GPU. Specifically, more than one dataset is processed in parallel during a single reduction operation. This involves dividing the blk_size independent blockReduceSum loops in the traditional solution into blocks, splitting one loop into two nested loops of size blk_size / K and size K, and unrolling the inner loop of length K. Referring to Figure 7(B), which illustrates the execution principle of the Softmax operator in this application, by allocating K times more shared memory and registers, K datasets can be processed in parallel at once. As shown in Figure 7(B), taking K=2 as an example, Figure 7(B) shows the execution flow of a K=2 loop block. The blockReduceSum_2Elem within the box simultaneously reduces two datasets (one dataset being a one-dimensional array). This approach has many advantages, such as improved computational efficiency within the blockReduce_2Elem function. This can reduce the number of `sync_threads` calls after writing to shared memory in the original `blockReduce` function by 50%. Simultaneously, it can improve the instruction execution efficiency within `warpReduce_2Elem`, reduce instruction issue stuttering caused by operand dependencies, and enable pipelined instruction issuance. (Reference) Figure 4 The instruction layout diagram of WarpReduce_2Elem shows that the target register R3 of the SHLF instruction is only used as the source operand of FADD after two cycles. One more SHFL instruction can be issued in the middle cycle, increasing instruction-level parallelism. Furthermore, computational efficiency is improved outside of blockReduce_2Elem. The overhead of the sync_thread_ operation at the bottom of Figure 7(B) is reduced. It also reduces branch decision overhead by a factor of K.

[0147] The data processing methods mentioned in the embodiments of this application are applied to accelerate the Softmax operator computation of BERT, resulting in significant performance improvements. The performance of Softmax was tested on two typical GPU architectures and compared with traditional solutions, such as the closed-source deep learning acceleration operator library cuDNNv7 and an open-source traditional method proposed by NVIDIA. We tested the inference computation throughput of sequences with lengths from 10 to 500 at batch sizes of 1 and 20. Figure 8(A) is a schematic diagram comparing the performance of Softmax computation implemented in this application on a processor in one embodiment with that of Softmax computation in a traditional solution. Figure 8(B) is a schematic diagram showing the performance acceleration results of Softmax computation implemented in this application on a processor in one embodiment compared to Softmax computation in a traditional solution. As shown in Figures 8(A) and 8(B), on a Tesla P40 (an inference workload processor), the Softmax computation method provided in the embodiments of this application achieves a speedup of 1.1x to 14x compared to the cuDNN method and a speedup of 1.1x to 4.1x compared to the NVIDIA method. Figure 8(C) is a performance comparison diagram of the Softmax calculation implemented by this application on another processor in one embodiment and the Softmax calculation in the conventional scheme. Figure 8(D) is a performance acceleration diagram of the Softmax calculation implemented by this application on another processor in one embodiment compared with the Softmax calculation in the conventional scheme. As shown in Figures 8(C) and 8(D), on the Tesla V100 (another inference workload), the Softmax calculation method provided by the various embodiments of this application has a speedup of 1.1x to 6x compared to cuDNN, and a speedup of 1.2x to 4.6x compared to NVIDIA's solution.

[0148] It should be understood that, although Figure 2 or Figure 5 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order in which these steps are executed; they can be performed in other orders. Furthermore, Figure 2 or Figure 5 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0149] In one embodiment, such as Figure 9 As shown, a data processing device 900 is provided. This device can be a software module, a hardware module, or a combination of both, integrated into a computer device. Specifically, the device includes: an acquisition module 901, a determination module 902, and an instruction triggering module 903, wherein:

[0150] The acquisition module 901 is used to acquire the target task and acquire more than one dataset corresponding to the target task in parallel. The determination module 902 is used to determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order. The instruction triggering module 903 is used to cyclically trigger various target instructions in the triggering order, and when triggering each target instruction, each dataset in the more than one dataset is used as the trigger object in turn, until the triggered target instructions are executed and the operation result corresponding to the target task is obtained.

[0151] In one embodiment, the data processing apparatus 900 further includes a partitioning module 904, wherein: the acquisition module 901 is further configured to acquire the input matrix to be processed corresponding to the target task. The partitioning module 904 is configured to partition the input matrix into more than one data block along the high-dimensional direction according to a preset partitioning size. The partitioning module 904 is further configured to divide the data block into at least one first data group; the first data group includes a preset number of datasets, the preset number being greater than one.

[0152] In one embodiment, the instruction stream includes a first instruction and a second instruction, with the first instruction triggered before the second instruction. The triggering object of the second instruction also includes first target operation data obtained by executing the first instruction, wherein the execution time of the first instruction is more than one time cycle. The instruction triggering module 903 is further configured to, in each loop triggering process, when triggering the first instruction, sequentially use each dataset in more than one dataset as the triggering object, and obtain first target operation data corresponding to each dataset by executing the first instruction; when triggering the second instruction, sequentially use the first target operation data corresponding to each dataset and the corresponding dataset as the triggering object, and obtain second target operation data corresponding to each dataset by executing the second instruction, wherein the second target operation data is used to update the corresponding dataset.

[0153] In one embodiment, the instruction triggering module 903 is further configured to divide each dataset into more than one set of data subsets, and obtain one data subset from each dataset as a second data group; allocate a corresponding thread bundle to each second data group; for each thread bundle, cyclically trigger various target instructions in the triggering order, and when triggering each target instruction, sequentially take each data subset in the second data group corresponding to the thread bundle as the trigger object, until the intermediate operation results corresponding to each data subset in the corresponding second data group are obtained by executing the triggered target instructions through the thread bundle; and determine the operation results corresponding to each dataset based on the intermediate operation results corresponding to each data subset in the second data group corresponding to each thread bundle.

[0154] In one embodiment, the instruction triggering module 903 is further configured to determine the number of threads corresponding to a thread bundle, and based on the number of threads, divide each dataset into more than one set of data subsets; and obtain one of the data subsets in each dataset as a second data group. The instruction triggering module is also configured to obtain the same number of thread bundles as the second data groups, and assign each second data group to one of the thread bundles.

[0155] In one embodiment, the instruction triggering module 903 is further configured to construct an intermediate array corresponding to the corresponding dataset by taking the intermediate operation results corresponding to each subset of data in each dataset; to trigger various target instructions in a cyclical manner according to the triggering order, and when triggering each target instruction, to take each intermediate array in more than one intermediate array as the triggering object in turn, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

[0156] In one embodiment, the determining module 902 is further configured to determine the valid threads and invalid threads in the thread bundle when the number of elements in the data subset is less than the number of threads in the thread bundle; the valid threads are threads that have been assigned elements to be processed; the invalid threads are threads that have not been assigned elements to be processed; wherein the elements to be processed are the elements in each data subset in the second data group.

[0157] The instruction triggering module 903 is also used to, for valid threads in the thread bundle, sequentially use elements in each data subset of the corresponding allocated second data group as trigger objects when triggering each target instruction; and for invalid threads in the thread bundle, use a preset value as the corresponding trigger object when triggering each target instruction.

[0158] In one embodiment, the data processing device 900 further includes a storage module 905 and an execution module 906, wherein: the storage module 905 is used to store the operation results corresponding to each dataset in more than one dataset to their respective shared locations. The execution module 906, after performing a synchronization operation, remains in a waiting state until the waiting termination condition is met, at which point it enters the next target task execution process.

[0159] In one embodiment, the target task includes a reduction task; the operation result includes a reduction result; the data processing device 900 further includes a normalization processing module 907, wherein the acquisition module 901 is further configured to acquire in parallel the reduction result corresponding to each of the more than one datasets. The normalization processing module 907 is configured to, for each dataset, perform a division operation between each element in the dataset and the reduction result corresponding to the corresponding dataset to obtain the normalized distribution result corresponding to the corresponding dataset.

[0160] refer to Figure 10 In one embodiment, the data processing device 900 further includes a business processing module 908 and a feedback module 909, wherein: the acquisition module 901 is further configured to acquire a business request and generate more than one computing task based on the business request; the more than one computing task includes a target task. The business processing module 908 is configured to process the computing tasks in subsequent stages based on the normalized distribution results corresponding to each dataset, and obtain a business processing result corresponding to the business request. The feedback module 909 is configured to respond to the business request and provide feedback on the business processing result.

[0161] In one embodiment, the data processing apparatus is executed by a graphics processor deployed on a computer device, and the data processing apparatus is applied to a language representation model; wherein the reduction task is a subtask of the normalization task, and the normalization task is one of the computational tasks in the language representation model.

[0162] The aforementioned data processing device, in scenarios requiring the processing of large amounts of data, acquires multiple datasets corresponding to a target task in parallel and determines an instruction stream corresponding to the target task. This instruction stream includes multiple target instructions with a determined triggering order. Furthermore, when processing multiple datasets, various target instructions can be triggered cyclically according to the triggering order. When triggering each target instruction, each dataset within the multiple datasets is used as the trigger object in turn, until the executed target instructions produce the operation result corresponding to the target task. Thus, in one cyclic triggering process, by alternately triggering the same type of target instructions based on different datasets, and then alternately triggering another type of target instruction based on different datasets, until each target instruction in the instruction stream is triggered sequentially, a pipelined issuance of instructions is achieved. This increases instruction-level parallelism to adjust the parallel granularity of the target task, rather than executing the target task corresponding to a single dataset only once, thus balancing resource utilization and parallel efficiency. For the entire dataset, the parallel alternating processing method significantly improves data processing efficiency.

[0163] Specific limitations regarding the data processing device can be found in the limitations regarding the data processing method described above, and will not be repeated here. Each module in the aforementioned data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0164] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 11 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. Specifically, the processor may be a graphics processing unit (GPU) providing computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data such as operation results. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a data processing method.

[0165] Those skilled in the art will understand that Figure 11The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0166] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0167] In one embodiment, a computer-readable storage medium is provided storing a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0168] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0169] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0170] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A data processing method, characterized in that, The method includes: Obtain the target task, and simultaneously obtain more than one dataset corresponding to the target task; Determine the instruction stream corresponding to the target task; the instruction stream includes more than one target instruction with a determined triggering order; the instruction stream includes a first instruction and a second instruction, wherein the first instruction is triggered before the second instruction; the execution time of the first instruction is more than one time period; Each dataset is divided into more than one subset of data, and one subset of data from each dataset is taken as the second subset of data; Each of the second data groups is assigned a corresponding thread bundle; For each thread bundle, various target instructions are triggered cyclically according to the triggering order. When the first instruction is triggered, each data subset in the second data group corresponding to the thread bundle is taken as the trigger object in turn, and one element in each data subset in the second data group is taken as the trigger object in turn. The first target operation data corresponding to each data subset is obtained by executing the operation corresponding to the first instruction. When the second instruction is triggered, the first target operation data corresponding to each data subset and another element in the corresponding data subset are taken as the trigger objects in turn. The second target operation data corresponding to each data subset is obtained by executing the operation corresponding to the second instruction in turn. The corresponding data subset is then updated with each second target operation data until the intermediate operation results corresponding to each data subset in the corresponding second data group are obtained by executing each triggered target instruction through the thread bundle. The intermediate operation results corresponding to each subset of data in each dataset are used to construct the intermediate array corresponding to the dataset. Various target instructions are triggered cyclically in the triggering order, and when each target instruction is triggered, each intermediate array in the more than one intermediate array is used as the trigger object in turn, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

2. The method according to claim 1, characterized in that, Before acquiring more than one dataset corresponding to the target task in parallel, the method further includes: Obtain the input matrix to be processed corresponding to the target task; The input matrix is ​​divided into more than one data block along the high-dimensional direction according to a preset partitioning size; The data block is divided into at least one first data group; the first data group includes a preset number of datasets, the preset number being greater than one.

3. The method according to claim 1, characterized in that, The step of dividing each dataset into more than one subset of data, and obtaining one subset of data from each dataset as a second data group, includes: Determine the number of threads corresponding to each thread bundle, and based on the number of threads, divide each dataset into more than one subset of data. Take one subset of data from each dataset as the second dataset; The method further includes: Obtain the same number of thread bundles as the second data group, and assign each of the second data groups to the respective thread bundles.

4. The method according to claim 1, characterized in that, The method further includes: When the number of elements in the data subset is less than the number of threads in the thread bundle, the valid threads and invalid threads in the thread bundle are determined; the valid threads are threads that have been assigned elements to be processed; the invalid threads are threads that have not been assigned elements to be processed; wherein, the elements to be processed are the elements in each data subset of the second data group; For a valid thread in the thread bundle, when each target instruction is triggered, each data subset in the correspondingly allocated second data group is used as the trigger object in sequence; For invalid threads in the thread bundle, a preset value is used as the corresponding trigger object when each target instruction is triggered.

5. The method according to claim 1, characterized in that, The method further includes: The operation results corresponding to each of the more than one datasets are stored in their respective shared locations. After performing the synchronization operation, it remains in a waiting state until the waiting end condition is met, at which point it enters the next target task execution process.

6. The method according to any one of claims 1 to 5, characterized in that, The target task includes a reduction task, and the operation result includes a reduction result; the method further includes: Obtain the reduction results corresponding to each of the more than one datasets in parallel; For each dataset, each element in the dataset is divided by the reduction result corresponding to the dataset to obtain the normalized distribution result corresponding to the dataset.

7. The method according to claim 6, characterized in that, Before acquiring the target task, the method further includes: Obtain a business request, and generate more than one computing task based on the business request; the more than one computing task includes a target task; For each dataset, after performing a division operation between each element in the dataset and the reduction result corresponding to the corresponding dataset to obtain the normalized distribution result for the corresponding dataset, the method further includes: Based on the normalized distribution results corresponding to each dataset, the subsequent stages of computation tasks are processed to obtain the business processing result corresponding to the business request. The business processing result is fed back in response to the business request.

8. The method according to claim 6, characterized in that, The method is executed by a graphics processor deployed on a computer device, and the method is applied to a language representation model; wherein the reduction task is a subtask of the normalization task, and the normalization task is one of the computational tasks in the language representation model.

9. A data processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire the target task and acquire more than one dataset corresponding to the target task in parallel. A determination module is used to determine the instruction stream corresponding to the target task; the instruction stream includes more than one type of target instruction with a determined triggering order; the instruction stream includes a first instruction and a second instruction, wherein the first instruction is triggered before the second instruction; the execution time of the first instruction is more than one time period; The partitioning module is used to divide each dataset into more than one set of data subsets and to take one of the data subsets from each dataset as the second set of data. The allocation module is used to allocate a corresponding thread bundle to each of the second data groups; The instruction triggering module is used to cyclically trigger various target instructions according to the triggering order for each thread bundle. When triggering the first instruction, it sequentially uses each data subset in the second data group corresponding to the thread bundle as the trigger object, and sequentially uses one element of each data subset in the second data group as the trigger object. By executing the operation corresponding to the first instruction, it obtains the first target operation data corresponding to each data subset. When triggering the second instruction, it sequentially uses the first target operation data corresponding to each data subset and another element of the corresponding data subset as the trigger object, and by executing the operation corresponding to the second instruction, it obtains the first target operation data corresponding to each data subset. Based on the second objective operation data corresponding to each subset, the corresponding data subset is updated through each second objective operation data until the thread bundle executes each triggered target instruction to obtain intermediate operation results corresponding to each data subset in the corresponding second data group; it is also used to construct an intermediate array corresponding to the corresponding dataset by using the intermediate operation results corresponding to each data subset in each dataset; it cyclically triggers various target instructions according to the triggering order, and when triggering each target instruction, each intermediate array in the more than one intermediate array is used as the trigger object in turn, until the triggered target instructions are executed to obtain the operation result corresponding to the target task.

10. The apparatus according to claim 9, characterized in that, The acquisition module is further configured to acquire the input matrix to be processed corresponding to the target task; the partitioning module is further configured to partition the input matrix into more than one data block along the high-dimensional direction according to a preset partitioning size; The data block is divided into at least one first data group; the first data group includes a preset number of datasets, the preset number being greater than one.

11. The apparatus according to claim 9, characterized in that, The partitioning module is also used to determine the number of threads corresponding to the thread bundle, and based on the number of threads, to divide each dataset into more than one set of data subsets; and to obtain one of the data subsets in each dataset as the second data group; The allocation module is also used to obtain the same number of thread bundles as the second data group, and allocate each of the second data groups to each of the thread bundles.

12. The apparatus according to claim 9, characterized in that, The determining module is further configured to determine the valid threads and invalid threads in the thread bundle when the number of elements in the data subset is less than the number of threads in the thread bundle; the valid threads are threads that have been assigned elements to be processed; the invalid threads are threads that have not been assigned elements to be processed; wherein, the elements to be processed are elements in each data subset of the second data group; The instruction triggering module is further configured to, for valid threads in the thread bundle, sequentially use each data subset in the correspondingly allocated second data group as the trigger object when triggering each target instruction; and for invalid threads in the thread bundle, use a preset value as the corresponding trigger object when triggering each target instruction.

13. The apparatus according to claim 9, characterized in that, The device further includes: The storage module is used to store the operation results corresponding to each of the more than one datasets to their respective shared locations. The execution module is used to perform synchronous operations and then remain in a waiting state until the waiting end condition is met, at which point it will enter the next target task execution process.

14. The apparatus according to any one of claims 9 to 13, characterized in that, The target task includes a reduction task, and the operation result includes a reduction result; the acquisition module is further configured to acquire in parallel the reduction result corresponding to each dataset in the more than one dataset; the device further includes: The normalization processing module is used to perform a division operation between each element in the dataset and the reduction result corresponding to the dataset for each dataset, so as to obtain the normalized distribution result corresponding to the dataset.

15. The apparatus according to claim 14, characterized in that, The acquisition module is also used to acquire business requests and generate more than one computing task based on the business requests; The more than one computational task includes the target task; The device further includes: The business processing module is used to process the subsequent computation tasks based on the normalized distribution results corresponding to each dataset, and to obtain the business processing result corresponding to the business request. The feedback module is used to respond to the business request and provide feedback on the business processing result.

16. The apparatus according to claim 14, characterized in that, The device is executed by a graphics processor deployed on a computer device, and the device is applied to a language representation model; wherein the reduction task is a subtask of the normalization task, and the normalization task is one of the computational tasks in the language representation model.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 8.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 8.

19. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the method of any one of claims 1 to 8.

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