A PWM modulation component of an H-bridge drive circuit

Abstract

The present invention provides a PWM modulation component of an H-bridge driving circuit, wherein the four switch tubes of the H-bridge driving circuit are all NMOS tubes, the gates of the switch tubes are respectively connected to the driving circuits, the input ends of the driving circuits are respectively connected to the signal output ends of the H-bridge driving signal generating circuits, the H-bridge driving signal generating circuits continuously output a conduction signal to the driving circuits corresponding to the upper tubes on one side, continuously output a cutoff signal to the driving circuits corresponding to the lower tubes on one side, and alternately output a cutoff and conduction signal to the driving circuits corresponding to the upper tubes and the lower tubes on the other side. In the modulation component of the present invention, since the upper tube on the first side is always in the conduction state, there is a large parasitic capacitance between its gate and the power supply voltage, which greatly reduces the storage capacitance of the boost circuit itself; and the upper tube on the first side is turned on, and the lower tube on the first side is turned off, so that the output end of the H-bridge driving circuit will not have a negative voltage, making the circuit work more reliable than before.

Description

Technical Field

[0001] The present invention relates to an H-bridge drive circuit, and particularly to a PWM modulation component of an H-bridge drive circuit. Background Art

[0002] Integrated H-bridge drive chips are widely used in brushless DC motors. In a traditional H-bridge drive circuit designed by integrated circuit technology, PMOS transistors are generally used for the upper transistors of the H-bridge, and NMOS transistors are generally used for the lower transistors of the H-bridge. Under the condition of equal breakdown voltage and area, the on-resistance of PMOS transistors is much larger than that of NMOS transistors. In applications where a large drive current is required and a small on-resistance is needed, using PMOS transistors as the upper transistors of the H-bridge requires a very large area to achieve a small on-resistance, resulting in a very high chip cost and difficult packaging. This leads to the situation that in applications with large current, generally H-bridges are implemented using discrete devices instead of being integrated into integrated circuits.

[0003] Such as Figure 1As shown in the figure, the upper transistors M1 and M2 of the H-bridge are changed from PMOS transistors to NMOS transistors, that is, the upper left transistor M1, the upper right transistor M2, the lower left transistor M3, and the lower right transistor M4 of the H-bridge are all NMOS transistors, which can effectively reduce the on-resistance of the H-bridge. In high-current applications, it is possible to integrate the H-bridge into an integrated circuit. However, there are several disadvantages in the design when the upper transistors M1 and M2 of the H-bridge use NMOS transistors. First, when the upper transistors of the H-bridge use NMOS transistors, a boost circuit 101 needs to be designed to generate an internal power supply higher than the power supply voltage to drive the upper transistors M1 and M2 of the H-bridge. In order to ensure the stability of the internal power supply voltage output by the boost circuit 101, the boost circuit 101 needs to have a large storage capacitor CAP (the storage capacitor is generally in the boost circuit, and the capacitor required by the prior art is very large. An external storage capacitor CAP is connected to the output port of the boost circuit 101 in the figure to represent the internally integrated storage capacitor). This storage capacitor CAP will greatly increase the output transistor area of the chip. Second, when the upper transistors M1 and M2 (NMOS transistors) of the H-bridge change from cutoff to conduction, the voltage of the gates of the upper transistors M1 and M2 increases from zero to the output voltage of the boost circuit 101. This process is a process of charging the gates of the upper transistors M1 and M2, and all the charges required for charging come from the boost circuit 101. This requires the boost circuit 101 to have a large enough current capacity. The larger the output transistor area of the upper transistors M1 and M2 of the H-bridge, the greater the current capacity requirement of the boost circuit 101, and the larger the chip area. Third, since the power supply for the gates of the upper transistors M1 and M2 is the output of the boost circuit 101, the turning on or off of the upper transistors M1 and M2 of the H-bridge itself will affect the boost circuit 101, which makes the design of the rising edge time and falling edge time of the H-bridge more difficult. In the application of a brushless DC motor, when the H-bridge drive circuit needs to perform pulse width modulation (PWM) speed regulation, due to the frequent turning on and off of the output transistors, the above three disadvantages will become more prominent. Therefore, although the on-resistance of NMOS transistors is much smaller than that of PMOS transistors, most of the upper transistors of the H-bridge in integrated circuits still use PMOS transistors.

[0004] In addition, as Figure 1As shown, according to the principle of the traditional PWM speed regulation method, the PWM modulation component of the traditional H-bridge drive circuit will generate a negative voltage at the H-bridge output. The negative voltage will cause the parasitic NPN transistor to turn on in the integrated circuit, affecting the normal operation of the chip. In the PWM modulation component of the H-bridge drive circuit, the upper left transistor M1 and the lower left transistor M3 are connected through the first output terminal DO, and the upper right transistor M2 and the lower right transistor M4 are connected through the second output terminal DOB. When the driving load is a DC brushless motor or a fan, the motor coil can be equivalent to an inductor. Taking the current from the first output terminal DO to the second output terminal DOB as an example. The gate of the upper right transistor M2 is always at a low level, and the gate of the lower right transistor M4 is always at a high level. The upper right transistor M2 is turned off and the lower right transistor M4 is turned on; when the gate of the upper left transistor M1 is at a high level, the gate of the lower left transistor M3 is at a low level, the upper left transistor M1 is turned on and the lower left transistor M3 is turned off. Thus, the first output terminal DO is pulled up to a high potential, and the second output terminal DOB is pulled down to a low potential. The current direction is as Figure 1 shown by the first path W1’ in, and the current flows from the power supply voltage terminal VCC through the upper left transistor M1, the load inductor L1, and the lower right transistor M4 to the ground to supply power to the load; when the gate of the upper left transistor M1 changes from a high level to a low level, the gate of the lower left transistor M3 is at a high level, the upper left transistor M1 is turned off and the lower left transistor M3 is turned on. The first output terminal DO is pulled down to a low level. At this time, the second output terminal DOB is still at a low level. The load inductor between the first output terminal DO and the second output terminal DOB is an energy supply element. The current direction is as Figure 1 shown by the second path W2’ in. At this time, the current on the inductor forms a loop through the lower right transistor M4, the ground, and the lower left transistor M3, and the current slowly decays, realizing the method of turning on the two lower transistors for freewheeling. However, since the device needs time to turn on, to prevent direct current, the lower left transistor M3 is turned on only after the upper left transistor M1 is turned off. During this switching period, the inductor current will briefly return to the load inductor L1 through the body diodes of the lower right transistor M4 and the lower left transistor M3, causing a negative voltage to appear at the first output terminal DO.

[0005] To solve the above three disadvantages of using NMOS transistors for the upper H-bridge transistors and the problem of negative voltage generated when the H-bridge performs PWM speed regulation, a new PWM modulation component for the H-bridge drive circuit needs to be designed. SUMMARY OF THE INVENTION

[0006] The object of the present invention is to provide a PWM modulation component for an H-bridge drive circuit to reduce the storage capacitor of the boost circuit, make the output terminal have no negative voltage, reduce the requirement for the boost circuit capacity, and facilitate the adjustment of the rising edge and falling edge of the output terminal.

[0007] To achieve the above object, the present invention provides a PWM modulation component for an H-bridge drive circuit, which includes an H-bridge drive circuit of a chip. The H-bridge drive circuit has a first output terminal and a second output terminal on both sides respectively. A load with a load inductor is provided between the first output terminal and the second output terminal. The four switching tubes of the H-bridge drive circuit include the upper tube and the lower tube on the first side and the upper tube and the lower tube on the second side. The four switching tubes are all NMOS tubes. The gates of the four switching tubes are respectively connected to four drive circuits. The input terminals of the four drive circuits are respectively connected to the four signal output terminals of an H-bridge drive signal generation circuit. The H-bridge drive signal generation circuit is configured to continuously output a conduction signal to the drive circuit corresponding to the upper tube on the first side, continuously output a cut-off signal to the drive circuit corresponding to the lower tube on the first side, and alternately output a cut-off signal and a conduction signal to the drive circuits corresponding to the upper tube and the lower tube on the second side. Whenever the signal output to the drive circuit corresponding to one of the upper tube and the lower tube on the second side switches to a cut-off signal and the corresponding switching tube is completely cut off, the signal output to the drive circuit corresponding to the other of the upper tube and the lower tube on the second side switches to a conduction signal so that the corresponding switching tube starts to conduct.

[0008] Each drive circuit includes a PMOS tube, a first resistor, a second resistor, and an NMOS tube connected in sequence. A drive circuit output terminal is provided between the first resistor and the second resistor. Each drive circuit is respectively connected to the gate of the corresponding switching tube through its drive circuit output terminal; the source of the PMOS tube of the drive circuit is the power supply terminal, and its drain is connected to the first resistor; the source of the NMOS tube is connected to the second resistor, and its drain is grounded. The gates of the PMOS tube and the NMOS tube of the drive circuit are short-circuited and provided with its input terminal.

[0009] A charging diode is provided between both the first output terminal and the second output terminal and the gate of the upper tube on the same side.

[0010] The drains of the upper tubes on the first side and the second side are both connected to the power supply voltage of a chip, and the sources of the lower tubes on the first side and the second side are both grounded.

[0011] The power supply terminals of the drive circuits corresponding to the upper tubes on the first side and the second side are both connected to the power supply voltage through a boost circuit, and the power supply terminals of the drive circuits corresponding to the lower tubes on the first side and the second side are both directly connected to the internal power supply of a chip.

[0012] On the other hand, the present invention provides a PWM modulation method for an H-bridge drive circuit, including:

[0013] S1: Provide a PWM modulation component for an H-bridge drive circuit. The PWM modulation component of the H-bridge drive circuit includes an H-bridge drive circuit of a chip. The H-bridge drive circuit has a first output terminal and a second output terminal on both sides respectively. A load with a load inductor is provided between the first output terminal and the second output terminal. The four switching tubes of the H-bridge drive circuit include the upper tube and the lower tube on the first side and the upper tube and the lower tube on the second side. The four switching tubes are all NMOS tubes. The gates of the four switching tubes are respectively connected to four drive circuits. The input terminals of the four drive circuits are respectively connected to the four signal output terminals of an H-bridge drive signal generation circuit;

[0014] S2: The H-bridge drive signal generation circuit continuously outputs a conduction signal to the drive circuit corresponding to the upper tube on the first side, continuously outputs a cut-off signal to the drive circuit corresponding to the lower tube on the first side, outputs a cut-off signal to the drive circuit corresponding to the upper tube on the second side, outputs a conduction signal to the drive circuit corresponding to the lower tube on the second side, and conducts for a period of time;

[0015] S3: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower tube on the second side is switched to a cut-off signal, so that the corresponding switching tube is cut off completely;

[0016] S4: When the corresponding switching tube is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper tube on the second side is switched to a conduction signal, so that the corresponding switching tube starts to conduct and conducts for a period of time;

[0017] S5: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper tube on the second side is switched to a cut-off signal, so that the corresponding switching tube is cut off completely;

[0018] S6: When the corresponding switching tube is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower tube on the second side is switched to a conduction signal, so that the corresponding switching tube starts to conduct and conducts for a period of time;

[0019] S7: Repeat steps S3 - S6.

[0020] Each drive circuit includes a PMOS tube, a first resistor, a second resistor, and an NMOS tube connected in sequence. A drive circuit output terminal is provided between the first resistor and the second resistor. Each drive circuit is respectively connected to the gate of the corresponding switching tube through its drive circuit output terminal; the source of the PMOS tube of the drive circuit is the power supply terminal, and its drain is connected to the first resistor; the source of the NMOS tube is connected to the second resistor, and its drain is grounded. The gates of the PMOS tube and the NMOS tube of the drive circuit are short-circuited and provided with its input terminal.

[0021] A charging diode is provided between each of the first output terminal and the second output terminal and the gate of the upper transistor on the same side.

[0022] The drains of the upper transistors on the first side and the second side are both connected to the power supply voltage of a chip, and the sources of the lower transistors on the first side and the second side are both grounded.

[0023] The power supply terminals of the drive circuits corresponding to the upper transistors on the first side and the second side are both connected to the power supply voltage through a boost circuit, and the power supply terminals of the drive circuits corresponding to the lower transistors on the first side and the second side are both directly connected to the internal power supply of a chip.

[0024] In the PWM modulation component of the H-bridge drive circuit of the present invention, since the upper transistor on the first side is always in the conducting state, there is a large parasitic capacitance between its gate and the power supply voltage, which can act as the storage capacitance of the boost circuit. Therefore, the storage capacitance required by the boost circuit can be greatly reduced, and the chip cost is reduced. Moreover, since the upper transistor on the first side is always conducting, the lower transistor on the first side is always cutoff, and the upper and lower transistors on the second side alternately cutoff and conduct, the output terminal of the H-bridge drive circuit will not have a negative voltage, making the circuit work more reliably than before. In addition, by using the upper transistor on the first side always conducting and the lower transistor on the second side for modulation, when switching, the voltage at the output terminal is charged to the power supply voltage by the energy of the inductor current, and the charging diode pre-charges the corresponding gate when the voltage at the output terminal is boosted, which greatly reduces the requirement for the current capacity of the boost circuit and reduces the design difficulty of the boost circuit. In addition, the PWM modulation component of the H-bridge drive circuit of the present invention uses the lower transistor for modulation. The rising and falling edge times of the output terminal of the H-bridge drive circuit are independent of the switching speed of the upper transistor, and thus independent of the current capacity of the boost circuit, but are related to the switching speed of the lower transistor, which is convenient for adjusting the rising and falling edges of the output terminal of the H-bridge drive circuit. Description of the Drawings

[0025] Figure 1 is a schematic diagram of a conventional PWM modulation H-bridge drive circuit component.

[0026] Figure 2 is a schematic diagram of the PWM modulation component of the H-bridge drive circuit according to an embodiment of the present invention.

[0027] Figure 3 is a specific implementation circuit diagram of the PWM modulation component of the H-bridge drive circuit according to an embodiment of the present invention.

[0028] Figure 4 is a signal diagram of the PWM modulation component of the H-bridge drive circuit according to an embodiment of the present invention.

[0029] Figure 5 is as Figure 4Simplified circuit diagram of the PWM modulation component of the H-bridge drive circuit shown at the first working moment. Detailed implementation mode

[0030] The following combines the accompanying drawings to give a preferred embodiment of the present invention and describes it in detail.

[0031] As Figures 2 - 3 Shown is the PWM modulation component of the H-bridge drive circuit according to an embodiment of the present invention, which includes the H-bridge drive circuit 200 of a chip. The four switching tubes of the H-bridge drive circuit 200 are all NMOS tubes, including the upper left tube M1 and the lower left tube M3 on the left side in the figure, and the upper right tube M2 and the lower right tube M4 on the right side. In this embodiment, the left side is used as the first side and the right side is used as the second side. The drains of the upper left tube M1 and the upper right tube M2 are both connected to the power supply voltage VCC of a chip, and the sources of the lower left tube M3 and the lower right tube M4 are both grounded. The H-bridge drive circuit 200 has a first output terminal DO on the left side (between the source of the upper left tube M1 and the drain of the lower left tube M3), and the H-bridge drive circuit 200 has a second output terminal DOB on the right side (between the source of the upper right tube M2 and the drain of the lower right tube M4), and a load (such as a motor coil) with a load inductor L1 is provided between the first output terminal DO and the second output terminal DOB.

[0032] Charging diodes VD1 and VD2 are provided between the first output terminal DO and the second output terminal DOB and the gates of the upper tubes on the same side. Among them, a first charging diode VD1 is provided between the first output terminal DO and the gate of the upper left tube M1, and a second charging diode VD2 is provided between the second output terminal DOB and the gate of the upper right tube M2, which are respectively set to charge the corresponding gates in advance when the voltages of the first output terminal DO and the second output terminal DOB are boosted.

[0033] The gates of the four switching tubes are respectively connected to four drive circuits 202, 203, 204, and 205, that is, the gates of the upper left tube M1, the upper right tube M2, the lower left tube M3, and the lower right tube M4 are respectively connected to the upper left tube drive circuit 202, the upper right tube drive circuit 203, the lower left tube drive circuit 204, and the lower right tube drive circuit 205. These drive circuits are set to charge or discharge the gates of the upper left tube M1, the upper right tube M2, the lower left tube M3, and the lower right tube M4 of the H-bridge drive circuit 200 to make them conductive or cut off.

[0034] The structures of the left-upper transistor driving circuit 202, the right-upper transistor driving circuit 203, the left-lower transistor driving circuit 204, and the right-lower transistor driving circuit 205 are exactly the same. Each driving circuit includes a PMOS transistor PM, a first resistor R1, a second resistor R2, and an NMOS transistor NM connected in sequence. A driving circuit output terminal is provided between the first resistor and the second resistor. Each of the driving circuits 202, 203, 204, 205 is connected to the gate of the corresponding switching transistor through its driving circuit output terminal. The source of the PMOS transistor PM of the driving circuits 202, 203, 204, 205 is the power supply terminal, and its drain is connected to the first resistor R1; the drain of the NMOS transistor NM is connected to the second resistor R2, and its source is grounded. The gates of the PMOS transistor PM and the NMOS transistor NM of the driving circuit are short-circuited and provided with its input terminal.

[0035] The power supply terminals of the driving circuits corresponding to the left-upper transistor M1 and the right-upper transistor M2 (i.e., the left-upper transistor driving circuit 202 and the right-upper transistor driving circuit 203) are both connected to the power supply voltage VCC through a boost circuit 201. The power supply terminals of the driving circuits corresponding to the left-lower transistor M3 and the right-lower transistor M4 (the left-lower transistor driving circuit 204 and the right-lower transistor driving circuit 205) are both directly connected to the internal power supply VDD of a chip, so as to supply power to the left-upper transistor driving circuit 202 and the right-upper transistor driving circuit 203 through the supply voltage VCP generated by the boost circuit 201, and provide driving voltage for the left-lower transistor driving circuit 204 and the right-lower transistor driving circuit 205 through the internal power supply VDD of the chip. The supply voltage VCP generated by the boost circuit is higher than the power supply voltage VCC of the chip. The left-upper transistor M1 and the right-upper transistor M2 are NMOS transistors. When the gate voltage of their upper transistors should be higher than the power supply voltage to conduct, so the boost voltage generates the voltage VCP to supply power to the left-upper transistor driving circuit 202 and the right-upper transistor driving circuit 203. The power supply voltage VCC of the chip is higher than the internal power supply VDD of the chip.

[0036] The input terminals of the four driving circuits 202, 203, 204, 205 are respectively connected to the four signal output terminals of an H-bridge driving signal generation circuit 206. The H-bridge driving signal generation circuit 206 has an input terminal and the four signal output terminals. Its input terminal is directly connected to the internal power supply VDD of the chip. Its four signal output terminals are respectively the left-upper signal output terminal Hctrl1 connected to the input terminal of the left-upper transistor driving circuit 202, the right-upper signal output terminal Hctrl2 connected to the input terminal of the right-upper transistor driving circuit 203, the left-lower signal output terminal Lctrl1 connected to the input terminal of the left-lower transistor driving circuit 204, and the right-lower signal output terminal Lctrl2 connected to the input terminal of the right-lower transistor driving circuit 205. The H-bridge driving signal generation circuit 206 generates control signals through the signal output terminals to control the working mode of the H-bridge driving circuit 200.

[0037] As Figure 4 shown in the example where current flows from the first output terminal DO to the second output terminal DOB, when the PWM modulation H-bridge driving circuit 200 is adopted, the signals generated by the four signal output terminals of the H-bridge driving signal generating circuit 206, and the signals A, B, C, and D generated by the corresponding upper left transistor driving circuit 202, upper right transistor driving circuit 203, lower left transistor driving circuit 204, and lower right transistor driving circuit 205. In this embodiment, since the first side is the left side and the second side is the right side, the H-bridge driving signal generating circuit 206 is arranged to continuously output a conduction signal to the driving circuit corresponding to the upper left transistor M1 through its upper left signal output terminal Hctrl1, continuously output a cut-off signal to the driving circuit corresponding to the lower left transistor M3 through its lower left signal output terminal Lctrl1, alternately output a cut-off signal and a conduction signal to the driving circuits corresponding to the upper right transistor M2 and the lower right transistor M4 through its upper right signal output terminal Hctrl2 and lower right signal output terminal Lctrl2, and whenever the signal output to one of the driving circuits corresponding to the upper right transistor M2 and the lower right transistor M4 is switched to a cut-off signal and the corresponding switching transistor is turned off, the signal output to the other driving circuit corresponding to the upper right transistor M2 and the lower right transistor M4 is switched to a conduction signal to make the corresponding switching transistor start to conduct. In this embodiment, the conduction signal is a low level and the cut-off signal is a high level. Correspondingly, the upper left transistor driving circuit 202 is arranged to continuously output a high level, the lower left transistor driving circuit 204 is arranged to continuously output a low level, and both the upper right transistor driving circuit 203 and the lower right transistor driving circuit 205 are arranged to alternately output a high level and a low level, and whenever one of the upper right transistor driving circuit 203 and the lower right transistor driving circuit 205 is switched to output a low level and the corresponding switching transistor is turned off, the other of the upper right transistor driving circuit 203 and the lower right transistor driving circuit 205 is switched to output a high level to make the corresponding switching transistor start to conduct, thus realizing PWM modulation. In this embodiment, at the first working moment, the signal output by the H-bridge driving signal generating circuit 206 to the driving circuit corresponding to the upper right transistor M2 through its upper right signal output terminal Hctrl2 is a cut-off signal, and the signal output to the driving circuit corresponding to the lower right transistor M4 through its lower right signal output terminal Lctrl2 is a conduction signal. At the second working moment, the signal output by the lower right signal output terminal Lctrl2 changes from a conduction signal to a cut-off signal, and then the signal output by the upper right signal output terminal Hctrl2 changes from a cut-off signal to a conduction signal.

[0038] The following combines Figures 2 - 5 to specifically describe the working principle of the PWM modulation component of the H-bridge driving circuit of the present invention.

[0039] When the H-bridge drive circuit 200 performs PWM modulation, taking the current direction from the first output terminal DO to the second output terminal DOB as an example, the 4 signal output terminals of the H-bridge drive signal generation circuit 206 generate signals as shown in Figure 4 below. The left-lower signal output terminal Lctrl1 continuously outputs a high level, causing the PMOS transistor PM in the left-lower transistor drive circuit 204 to be cut off and the NMOS transistor NM to be turned on. As a result, the signal C output by the left-lower transistor drive circuit 204 is pulled to the ground (a continuous low level) through its second resistor R2. Therefore, the left-lower transistor M3 is always cut off; the left-upper signal output terminal Hctrl1 continuously outputs a low level, causing the PMOS transistor PM in the left-upper transistor drive circuit 202 to be turned on and the NMOS transistor NM to be cut off. The supply voltage VCP generated by the boost circuit pulls the signal A generated by the left-upper transistor drive circuit 202 to the VCP level (a continuous high level) through the first resistor R1 of the left-upper transistor drive circuit 202. Therefore, the left-upper transistor M1 is always turned on, and the first output terminal DO is pulled to the power supply voltage.

[0040] When the right-upper signal output terminal Hctrl2 outputs a high level and the right-lower signal output terminal Lctrl2 outputs a low level, the PMOS transistor PM in the right-upper transistor drive circuit 203 is cut off and the NMOS transistor NM is turned on. The NMOS transistor NM in the right-upper transistor drive circuit 203 pulls the signal B generated by the right-upper transistor drive circuit 203 to the ground potential through its second resistor R2, which is a low level, and the right-upper transistor M2 is cut off; the PMOS transistor PM in the right-lower transistor drive circuit 205 is turned on and the NMOS transistor NM is cut off. The NMOS transistor NM in the right-lower transistor drive circuit 205 pulls the signal D generated by the right-lower transistor drive circuit 205 to the internal power supply voltage VDD through its first resistor R1, which is a high level, and the right-lower transistor M4 is turned on. The second output terminal DOB is pulled to the ground potential, and the H-bridge forms a path. The current direction is as shown in Figure 2 、 Figure 3 、 Figure 5 The first path W1 in the figure. The current flows from the power supply voltage VCC through the left-upper transistor M1, the load inductor L1, and the right-lower transistor M4 to the ground, and the load operates.

[0041] When the signal output by the right-lower signal output terminal Lctrl2 changes from a low level (conducting signal) to a high level (cut-off signal), the PMOS transistor PM in the right-lower transistor drive circuit 205 is cut off and the NMOS transistor NM is turned on, pulling the gate of the right-lower transistor M4 down through its second resistor. The simplified circuit is as shown in Figure 5As shown. Since the area of the H-bridge transistors is large, the gate-drain capacitance Cgd inside the lower-right transistor M4 is taken into account. When the gate voltage of the lower-right transistor M4 decreases, the current-carrying capacity of the lower-right transistor M4 decreases. However, due to the fact that the current in the load inductor L1 cannot change abruptly, the voltage at the second output terminal DOB will be boosted, causing a current to be generated across the gate-drain capacitance Cgd of the lower-right transistor M4 due to the voltage change. The current flows to ground through the second resistor R2 and the NMOS transistor NM in the lower-right transistor drive circuit 205, causing the voltage at the gate of the lower-right transistor M4 to drop and dynamically stabilize at a stable voltage Vb. At this time, the current path of the H-bridge is still 1. The voltage value of the stable voltage Vb is specifically determined by the current in the load inductor L1. The lower-right transistor M4 is still in the conducting state. At this time, the rising rate of the voltage at the second output terminal DOB is:

[0042]

[0043] Among them, is the conversion rate of the voltage at the second output terminal DOB, whose unit is usually V / S. Vb is the stable voltage at the gate of the lower-right transistor M4, and R24 is the resistance value of the second resistor R2 in the lower-right transistor drive circuit 205.

[0044] It can be seen from the above formula that the voltage at the second output terminal DOB is automatically boosted by the load inductor L1, and the rising time of the rising edge can be adjusted by the resistance value R24 of the second resistor R2 in the lower-right transistor drive circuit 205, and is no longer related to the current-carrying capacity of the boost circuit. The PWM modulation component of the H-bridge drive circuit of the present invention uses the lower transistor modulation. The rising and falling times of the rising and falling edges of the first output terminal DO and the second output terminal DOB of the H-bridge drive circuit are independent of the switching speed of the upper-left transistor M1 or the upper-right transistor M2, and thus are independent of the current-carrying capacity of the boost circuit, but are related to the switching speeds of the lower-left transistor M3 and the lower-right transistor M4 (in this embodiment, related to the switching speed of the lower-right transistor M4). The rising and falling times of the rising and falling edges of the first output terminal DO and the second output terminal DOB can be controlled by the lower-left transistor drive circuit 204 or the lower-right transistor drive circuit 205 (in this embodiment, the lower-right transistor drive circuit 205), which is convenient for adjusting the rising and falling edges of the output terminal of the H-bridge drive circuit, making the design more convenient.

[0045] When the voltage at the second output terminal DOB is boosted by the load inductor L1, it will keep rising until it is higher than the power supply voltage by a diode voltage drop. At this time, it will no longer rise, and the current will flow into the power supply voltage VCC through the body diode VD in the internal structure of the upper-right transistor M2. The body diode VD here is as Figure 5As shown, when the upper right transistor M2 is cut off and the voltage at its lower port is higher than that at its upper port, the current will flow through the diode. At this time, the voltage across the gate-drain capacitance Cgd of the lower right transistor M4 no longer changes and no current is generated. Therefore, the gate of the lower right transistor M4 is quickly pulled to ground through the second resistor R2 and the NMOS transistor NM in the lower right transistor drive circuit 205, and the lower right transistor M4 is cut off. The current of the inductor will flow back to the power supply voltage through the body diode VD of the upper right transistor M2, and the current path is as shown in Figure 5 the third path W3 in. It returns from the power supply voltage VCC, through the upper left transistor M1, the load inductor L1, and the body diode VD of the upper right transistor M2 to the power supply voltage VCC. Since a second charging diode VD2 is provided between the second output terminal DOB and the gate of the upper right transistor M2, when the voltage at the second output terminal DOB rises, the voltage at the gate of the upper right transistor M2 will also be charged to near the power supply voltage VCC by the second charging diode VD2. Therefore, for the PWM modulation component of the H-bridge drive circuit of the present invention, its H-bridge drive signal generation circuit drives the upper transistor on the first side to conduct through the drive circuit, cuts off the lower transistor on the first side, and cuts off and conducts the upper and lower transistors on the second side, so that negative voltages will not appear at the first output terminal DO and the second output terminal DOB of the H-bridge drive circuit, avoiding the generation of parasitic NPN transistors, reducing the difficulty of chip layout design, and at the same time avoiding affecting the normal operation of the circuit; since before the upper right transistor M2 starts to conduct, its gate has been charged to near the power supply voltage by the energy of the inductor current, and the charging diode pre-charges the corresponding gate when the voltage at the output terminal is boosted, this greatly reduces the requirement for the current capacity of the boost circuit 201 and reduces the design difficulty of the boost circuit 201.

[0046] As described above, when the lower right transistor M4 finishes being cut off, the signal output from the upper right signal output terminal Hctrl2 changes from high level to low level, and the upper right transistor drive circuit 203 switches to output a high level to make the corresponding upper right transistor M2 start to conduct. Since the second charging diode VD2 has charged the gate of the upper right transistor M2 to near the power supply voltage, when the VCP voltage generated by the boost circuit 201 charges the gate of the upper right transistor M2 through the PMOS transistor PM and the second resistor R2 in the upper right transistor drive circuit 203, the boost circuit 201 only needs to continue charging the gate to the VCP voltage on the basis that the gate is near the power supply voltage, which greatly reduces the requirement for the boost circuit. At this time, the upper right transistor M2 starts to conduct, and the current direction of the H-bridge is as shown in Figure 2 、 Figure 3 、 Figure 5 the second path W2 in. The current flows from the power supply voltage VCC through the upper left transistor M1, the load inductor L1, and the upper right transistor M2 back to the power supply voltage VCC to realize the freewheeling of the upper transistor.

[0047] In addition, since the upper left tube M1 of the present invention is always in the on state, there is a large parasitic capacitance between the gate of the upper left tube M1 and the power supply voltage VCC, which can act as a storage capacitor of the boost circuit 201. Therefore, the storage capacitor required by the boost circuit 201 can be greatly reduced, the area of ​​the storage capacitor in the boost circuit is reduced, and the chip cost is reduced.

[0048] In addition, in other embodiments, the principle of the current flowing from the second output terminal DOB to the first output terminal DO is the same as the principle described above, and two upper tubes are used for freewheeling, except that the first side becomes the right side and the second side becomes the left side. Specifically, the H-bridge drive signal generating circuit 206 continuously outputs a conduction signal (i.e., a low level) to the drive circuit corresponding to the right upper tube M2, continuously outputs a cutoff signal (i.e., a high level) to the drive circuit corresponding to the right lower tube M4, and alternately outputs a cutoff signal and a conduction signal to the drive circuits corresponding to the left upper tube M1 and the left lower tube M3, and whenever the signal output to the drive circuit corresponding to one of the left upper tube M1 and the left lower tube M3 is switched to a cutoff signal and the corresponding switch tube is cut off, the signal output to the other drive circuit corresponding to the left upper tube M1 and the left lower tube M3 is switched to a conduction signal so that the corresponding switch tube starts to turn on. When the PWM modulation component of the H-bridge drive circuit of the chip is used for PWM soft start, PWM soft switching and PWM speed regulation, using one side of the upper tube to be constantly turned on and the other side of the lower tube to perform PWM modulation all belong to the protection scope of the present invention.

[0049] Based on the PWM modulation component of the H-bridge drive circuit above, the PWM modulation method of the H-bridge drive circuit implemented includes the following steps:

[0050] Step S1: providing a PWM modulation component of an H-bridge driving circuit, wherein the PWM modulation component of the H-bridge driving circuit comprises an H-bridge driving circuit of a chip, wherein the H-bridge driving circuit has a first output terminal and a second output terminal on both sides, respectively, and a load having a load inductance is arranged between the first output terminal and the second output terminal, and wherein four switch tubes of the H-bridge driving circuit comprise an upper tube and a lower tube on the first side and an upper tube and a lower tube on the second side, wherein the four switch tubes are all NMOS tubes, and the gates of the four switch tubes are respectively connected to four driving circuits, and the input terminals of the four driving circuits are respectively connected to four signal output terminals of an H-bridge driving signal generating circuit;

[0051] Step S2: the H-bridge driving signal generating circuit continuously outputs a conduction signal to the driving circuit corresponding to the upper tube on the first side, continuously outputs a cutoff signal to the driving circuit corresponding to the lower tube on the first side, outputs a cutoff signal to the driving circuit corresponding to the upper tube on the second side, outputs a conduction signal to the driving circuit corresponding to the lower tube on the second side, and conducts for a period of time;

[0052] Step S3: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower transistor on the second side is switched to a cut-off signal, so that the corresponding switch transistor is cut off completely;

[0053] Step S4: When the corresponding switch transistor is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper transistor on the second side is switched to a conduction signal, so that the corresponding switch transistor starts to conduct and conducts for a period of time;

[0054] Step S5: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper transistor on the second side is switched to a cut-off signal, so that the corresponding switch transistor is cut off completely;

[0055] Step S6: When the corresponding switch transistor is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower transistor on the second side is switched to a conduction signal, so that the corresponding switch transistor starts to conduct and conducts for a period of time;

[0056] Step S7: Repeat the above steps S3 - S6.

[0057] The above is only the preferred embodiment of the present invention, and does not limit the scope of the present invention. Various changes can be made to the above embodiments of the present invention. That is, all simple, equivalent changes and modifications made according to the claims and the content of the specification of the present invention application fall within the scope of the claims of the present invention patent. What is not described in detail in the present invention is conventional content.

Claims

1. A PWM modulation method for an H-bridge drive circuit, characterized in that, Including: Step S1: Provide a PWM modulation component of an H-bridge drive circuit. The PWM modulation component of the H-bridge drive circuit includes an H-bridge drive circuit of a chip. The H-bridge drive circuit has a first output terminal and a second output terminal on both sides respectively. A load with a load inductor is provided between the first output terminal and the second output terminal. The four switching tubes of the H-bridge drive circuit include the upper tube and the lower tube on the first side and the upper tube and the lower tube on the second side. The four switching tubes are all NMOS tubes. The gates of the four switching tubes are respectively connected to four drive circuits. The input ends of the four drive circuits are respectively connected to the four signal output ends of an H-bridge drive signal generation circuit. Step S2: The H-bridge drive signal generation circuit continuously outputs a conduction signal to the drive circuit corresponding to the upper tube on the first side, continuously outputs a cut-off signal to the drive circuit corresponding to the lower tube on the first side, outputs a cut-off signal to the drive circuit corresponding to the upper tube on the second side, outputs a conduction signal to the drive circuit corresponding to the lower tube on the second side, and conducts for a period of time. Step S3: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower tube on the second side is switched to a cut-off signal, so that the corresponding switching tube is cut off completely. Step S4: When the corresponding switching tube is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper tube on the second side is switched to a conduction signal, so that the corresponding switching tube starts to conduct and conducts for a period of time. Step S5: The signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the upper tube on the second side is switched to a cut-off signal, so that the corresponding switching tube is cut off completely. Step S6: When the corresponding switching tube is cut off completely, the signal output by the H-bridge drive signal generation circuit to the drive circuit corresponding to the lower tube on the second side is switched to a conduction signal, so that the corresponding switching tube starts to conduct and conducts for a period of time. Step S7: Repeat Step S3 - Step S6.

2. The PWM modulation method of the H-bridge drive circuit according to claim 1, characterized in that, Each drive circuit includes a PMOS tube, a first resistor, a second resistor and an NMOS tube connected in sequence. A drive circuit output terminal is provided between the first resistor and the second resistor. Each drive circuit is respectively connected to the gate of the corresponding switching tube through its drive circuit output terminal. The source of the PMOS tube of the drive circuit is the power supply terminal, and its drain is connected to the first resistor. The drain of the NMOS tube is connected to the second resistor, and its source is grounded. The gates of the PMOS tube and the NMOS tube of the drive circuit are short-circuited and provided with its input end.

3. The PWM modulation method of the H-bridge drive circuit according to claim 2, wherein A charging diode is provided between both the first output terminal and the second output terminal and the gates of the upper tubes on the same side as them.

4. The PWM modulation method of the H-bridge drive circuit according to claim 2, characterized in that The drains of the upper tubes on the first side and the second side are both connected to the power supply voltage of a chip, and the sources of the lower tubes on the first side and the second side are both grounded.

5. The PWM modulation method of the H-bridge drive circuit according to claim 4, characterized in that, The power supply terminals of the drive circuits corresponding to the upper tubes on the first side and the second side are both connected to the power supply voltage through a boost circuit, and the power supply terminals of the drive circuits corresponding to the lower tubes on the first side and the second side are both directly connected to the internal power supply of a chip.

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