System and method for calibrating low power voltage mode transmitter driver impedance

Abstract

Embodiments of the present application relate to systems and methods for calibrating the impedance of a low-power voltage-mode transmitter driver. A low-power transmitter for transmitting a digital signal from an integrated chip is described herein. The transmitter includes a voltage-mode transmitter driver consisting of a plurality of driver slices, which includes an upper unit having a first resistor and a first transistor and a lower unit having a second resistor, a second transistor, and a third transistor. The calibration circuit drives the replica circuit to a desired impedance by adjusting a first gate voltage of a first transistor applied to a replica of the upper unit and adjusting a second gate voltage of a third transistor applied to a replica of the lower unit. The calibrated first gate voltage is applied to the first transistor and the second transistor of each of the plurality of driver slices, and the calibrated second gate voltage is applied to the third transistor of each of the plurality of driver slices.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure is also a continuation-in-part of commonly assigned and co-pending U.S. Application No. 16 / 264,411, filed on January 31, 2019, and claims the benefit of U.S. Patent No. 120, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to configurations of low power transmitter drivers, and in particular, to configurations for calibrating impedances of different cells at a low power voltage mode transmitter driver. Background Art

[0004] Voltage-mode transmitter drivers are often used for chip-to-chip connections in devices such as servers and routers. Voltage-mode transmitter drivers usually have two units, an upper unit with transistors and resistors, and a lower unit with transistors and resistors. The joint connecting the upper unit and the lower unit forms the output terminal of the voltage-mode transmitter driver.

[0005] High-speed chip-to-chip interconnect standards often require that the lower cell impedance and the upper cell impedance match a desired reference impedance to reduce reflections along the interconnect that degrade signal integrity. In other words, the power supply (V S ) and the output terminal, and the lower unit impedance between the output terminal and ground need to be equal to a certain reference impedance value. However, the transistors in the upper unit or the lower unit are usually composed of large-sized n-type transistors. The resistance of the transistor usually changes significantly due to different driving voltage levels, and may be quite unstable due to environmental factors such as temperature, humidity, vibration, etc. Therefore, the changing resistance of the n-type transistors in the upper unit and the lower unit usually leads to a mismatch between the upper unit impedance and the lower unit impedance, especially during different operating modes of the transistors. This mismatch usually causes excessive noise in the voltage-mode transmitter driver and produces unstable or even erroneous output at the output terminal of the voltage-mode transmitter driver. Summary of the invention

[0006] Embodiments described herein provide a low-power transmitter for transmitting digital signals from an integrated chip. The transmitter includes a voltage-mode transmitter driver composed of a plurality of driver slices, wherein each driver slice includes an upper unit and a lower unit. The upper unit includes a first resistor and a first transistor, wherein the upper unit is connected to a voltage source and an output of the voltage-mode transmitter driver. The lower unit includes a second resistor, a second transistor, and a third transistor, wherein the lower unit is connected to the output of the voltage-mode transmitter driver and ground. The transmitter also includes a replica circuit, which includes a replica of the upper unit and a replica of the lower unit. The calibration circuit of the transmitter is configured to drive the replica circuit to a desired impedance by adjusting the first gate voltage of the first transistor applied to the replica of the upper unit to be equal to the calibrated first gate voltage and adjusting the second gate voltage of the third transistor applied to the replica of the lower unit to be equal to the calibrated second gate voltage. The bias generator applies the calibrated first gate voltage to the first transistor and the second transistor of each driver slice in the plurality of driver slices, and applies the calibrated second gate voltage to the third transistor of each driver slice in the plurality of driver slices.

[0007] In some embodiments, the upper unit of each of the multiple driver slices is configured to generate an impedance that matches the impedance of the corresponding lower unit of each of the multiple driver slices in response to applying a calibrated first gate voltage to the first transistor and the second transistor of each of the multiple driver slices and applying a calibrated second gate voltage to the third transistor of each of the multiple driver slices.

[0008] In some embodiments, in response to applying a calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices and applying a calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the upper cells of the plurality of driver slices is equal to an impedance of the replica of the upper cells.

[0009] In some embodiments, in response to applying a calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices and applying a calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the lower cells of the plurality of driver slices is equal to an impedance of the replica of the lower cell.

[0010] In some embodiments, the copy of the upper cell further includes a copy of the first resistor and a copy of the first transistor, wherein the copy of the upper cell is connected to a voltage source and an output of the voltage-mode transmitter driver. The copy of the lower cell further includes a copy of the second resistor, a copy of the second transistor, and a copy of the third transistor, wherein the copy of the lower cell is connected to the output of the voltage-mode transmitter driver and ground.

[0011] In some embodiments, the calibration circuit also includes: a second lower unit, which includes a fourth transistor and a third resistor; and a constant current source configured to feed a constant current into the second lower unit to generate an output voltage; a comparator configured to compare the output voltage generated by the second lower unit with a first reference voltage and a second reference voltage; and a calibration logic control configured to adjust the impedance of the second lower unit to match the first predetermined impedance by adjusting the second gate voltage via a bias generator based on an output of the comparator.

[0012] In some embodiments, the bias generator is configured to decrease the second gate voltage in response to the calibration logic control receiving a high level output from the comparator indicating that the impedance of the second lower unit is low. In some embodiments, the bias generator is configured to increase the second gate voltage in response to the calibration logic control receiving a low level output from the comparator indicating that the impedance of the second lower unit is high.

[0013] In some embodiments, the calibration circuit is further configured to (i) maintain the second gate voltage at a voltage at which the impedance of the second lower unit matches the first predetermined impedance via the bias generator, (ii) adjust the first gate voltage to a voltage at which the impedance of the upper unit replica matches the second predetermined impedance via the bias generator, and (iii) calibrate the first gate voltage to a voltage at which the impedance of the replica of the upper unit matches the second predetermined impedance.

[0014] In some embodiments, the calibration circuit is further configured to (i) maintain a calibrated first gate voltage via a bias generator; (ii) adjust a second gate voltage via the bias generator so that the impedance of the replica of the lower unit matches a second predetermined impedance, and (iii) calibrate the second gate voltage to a voltage at which the impedance of the replica of the lower unit matches the second predetermined impedance.

[0015] In some embodiments, the bias generator is configured to supply a calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices and to supply a calibrated second gate voltage to the third transistor of each of the plurality of driver slices. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Other features of the present disclosure, its nature and various advantages will become apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, wherein like reference numerals refer to like parts throughout, and wherein:

[0017] Figure 1 is a block diagram illustrating a low power voltage mode transmitter driver using additional transistors with adjustable gate voltages applied thereto to calibrate the impedance of upper and lower cells according to some embodiments described herein;

[0018] Figure 2 is a diagram illustrating the operation of one embodiment described herein. Figure 1 The circuit shown is a logic flow diagram of the process of calibrating the impedance of a voltage mode transmitter.

[0019] Figure 3 is a circuit diagram illustrating a voltage-mode transmitter driver chip and a replica chip for calibrating impedance in a voltage-mode transmitter driver according to some embodiments described herein; and

[0020] Figure 4 A circuit diagram of a calibration circuit according to some embodiments of the present invention is illustrated, the calibration circuit being used to calibrate the impedance of the upper unit and the lower unit in the replica 201 to a desired impedance value; and

[0021] Figure 5a-5c is a logic flow diagram illustrating the operation of an embodiment according to the present invention. Figure 4 A process 500 for calibrating a circuit for impedance in a replica wafer 201 is shown.

[0022] Figure 6 is a system diagram of a low power transmitter according to one embodiment described herein. DETAILED DESCRIPTION

[0023] Considering the problem of impedance mismatch in voltage-mode transmitter drivers, systems and methods for independently calibrating the respective impedances of upper and lower units in low-power voltage-mode transmitter drivers are described herein. In some embodiments, the low-power voltage-mode transmitter driver can be used in technology systems such as servers and routers. These systems require high-speed, low-power, area-efficient chip-to-chip interconnects.

[0024] Figure 1 is a circuit diagram 100 illustrating a low power voltage mode transmitter driver that uses additional transistors with adjustable gate voltages applied thereto to calibrate the impedance of the upper and lower cells, and, Figure 2 is a diagram illustrating the operation of one embodiment described herein. Figure 1 The circuit 100 is shown as a logic flow diagram of a process for calibrating the impedance of a voltage mode transmitter. Figure 1 The circuit diagram 100 of FIG. 1 illustrates a low power voltage mode driver modeled as having an upper unit 102 and a lower unit 104. The upper unit 102 and the lower unit 104 can be used to provide different bits of a data stream. The upper unit 102 includes a transistor 106 and a resistor 108, one end of the resistor 108 being connected to the source of the transistor 106. The source of the transistor 106 is connected to a voltage source (V S). The other terminal of resistor 108 is connected to the output 118 of the voltage mode transmitter driver. In a conventional transmitter driver, the value of resistor 108 is selected to ensure that the output impedance measured at output terminal 118 matches the desired impedance. In such embodiments, the upper unit impedance can be measured as R(108)+1 / Gmn1(106), where Gmn1(106) is the transconductance of device 106. For example, in a conventional transmitter, when the desired impedance is 50 ohms, a suitable resistance value can be selected for resistor 108. The gate terminal of transistor 106 is connected to the output terminal of voltage driver 120. Voltage driver 120 has V IP The input voltage and adjustable drive voltage V DDR In an embodiment, the driving voltage V is adjusted DDR to change the output voltage from voltage driver 120 applied to the gate of transistor 106, thereby changing the resistance of transistor 106, which in turn changes the voltage at voltage source V S and the impedance of the upper unit 102 between the output terminal 118 .

[0025] Lower cell 104 includes resistor 112 having one terminal connected to output 118 and the other terminal connected to the drain of transistor 114. Transistor 114 is driven by voltage driver 110, which is similar to voltage driver 120 and has V IN The input voltage and the same adjustable drive voltage V DDR Similar to the upper unit, the impedance of the lower unit between the output terminal 118 and ground can be adjusted by adjusting the adjustable drive voltage VDDR to change.

[0026] The additional transistor 116 is connected to the source of the transistor 114. Specifically, the source terminal of the transistor 114 is connected to the drain terminal of the n-type transistor 116. The source terminal of the n-type transistor 116 is connected to ground.

[0027] The gate terminal of n-type transistor 116 is connected to an adjustable gate voltage (V G ). In addition to V DDR In addition, the gate voltage V G This changes the resistance of transistor 116, which in turn changes the impedance of the lower cell.

[0028] In some embodiments, transistor 116 may be a p-type transistor rather than a Figure 1 In such an embodiment, the other transistors 106 and 114 may also be p-type transistors instead of n-type transistors.

[0029] like Figure 1 The circuit 100 shown is as follows Figure 2At 212, the drain and source terminals of the transistor 106 of the upper cell 102 are connected to the voltage source V S and the output 118 of the voltage mode transmitter driver. At 214, the drain and source terminals of the transistor 114 of the lower unit 104 are connected to the output 118 of the voltage mode transmitter driver and to ground via the additional transistor 116, respectively. At 216, the adjustable gate voltage V G is applied to the gate of the additional transistor 116. At 218, the gate voltage V G The voltage level is such that the lower unit impedance between the output terminal 118 and the ground is connected to the voltage source V S and the upper unit impedance matching between the output terminal 118. By adjusting V G , the output impedance variation between the impedance of the upper unit 102 and the impedance of the lower unit 104 can be reduced.

[0030] Figure 3 is a circuit diagram illustrating a voltage-mode transmitter driver chip and a replica chip to calibrate impedance in a voltage-mode transmitter driver according to some embodiments described herein. Figure 3 As shown, Figure 1 Multiple identical copies (referred to as "slices") of the transmitter driver 100 are connected in parallel. Each driver slice includes an instance of an upper cell 102, a lower cell 104, and an additional transistor 116. The same voltage drivers 120 and 110 can be applied to the upper and lower cells in all driver slices.

[0031] The corresponding impedance of the upper unit or the lower unit can be set to match the desired reference value. For example, the desired impedance of the upper unit 102 of the low-power voltage mode transmitter driver is 50 ohms. Similarly, the desired impedance of the lower unit 104 of the low-power voltage mode transmitter driver is also 50 ohms, so as to match the desired upper unit impedance. In order to achieve a target impedance of 50 ohms for both the upper unit 102 and the lower unit 104, for example, when 20 driver slices are connected in parallel, each driver slice may need to be adjusted to have a corresponding upper unit impedance of 1K ohms. The net impedance of 20 driver slices connected in parallel can be measured using the following formula:

[0032]

[0033] Where Z is 1k ohm (per driver chip) and n is the Z that produces 50 ohms Net In some embodiments, to achieve different target impedances for the voltage-mode transmitter driver 100, each driver slice may be adjusted to present a different impedance value for a corresponding upper unit or lower unit impedance.

[0034] In order to achieve the desired impedance in the upper cell 102 and the lower cell 104 of the voltage mode transmitter driver, a replica chip 201 similar to the original driver chip is connected to the original parallel connected driver chips. By adjusting the replica chip to a value of 1k ohm, each of the 20 driver chips can be adjusted to an impedance of 1k ohm. This will eventually result in the impedance of the upper cell 102 and the lower cell 104 of the transmitter driver 100 being calibrated to the desired value of 50 ohms. The replica chip 201 includes a replica upper cell 202 and a replica lower cell 204. The replica upper cell 202 includes a transistor 206 that is a replica of the transistor 106 and a resistor 208 that is a replica of the resistor 108. The replica lower cell 204 includes a transistor 214 that is a replica of the transistor 114 and a resistor 212 that is a replica of the resistor 112, and a replica transistor 216 that is a replica of the transistor 116. All replica components are connected in a manner similar to the connection of the components in the driver 100. The driving voltage V DDR is applied to the gate terminals of transistors 206 and 214 .

[0035] Adjustable voltage V G and V DDR will be adjusted to calibrate the impedance of the replica upper cell 202 and the replica lower cell 204 to the desired value (1K ohm in this case). Since the replica slice is connected in parallel to the driver slice via connection 218, the adjustment voltage V G and V DDR The impedance in each original driver slice is calibrated in turn to achieve the desired value (1K ohms in this case). Figure 4-5c Aspects of the calibration replica 201 are further described.

[0036] Figure 4 FIG. 1 is a circuit diagram of a calibration circuit for calibrating the respective impedances of the upper and lower cells in the replica 201 to a desired impedance value according to some embodiments herein. In some embodiments, the respective impedances of the upper and lower cells 202 and 201 are calibrated independently of each other. The bias generator 302 controlled by the calibration logic 304 is used to adjust the independent voltage V G and V G1 , independent calibration of the impedance of the upper cell 202 and the lower cell 204 occurs. The calibration circuit 400 is arranged to adjust the replica 201. The gate terminal of the transistor 206 of the replica upper cell 202 of the replica 201 is connected to the switch box 318. The switch box 318 has a switch A, which, when closed, connects the gate terminal of the replica transistor 206 to V DDR210. Switch box 318 has another switch B, which connects the gate terminal of replica transistor 206 to ground when switch B is closed. Similarly, the gate terminal of transistor 214 of replica upper cell 202 of replica slice 201 is connected to switch box 316. Switch box 316 has switch A, which connects the gate terminal of transistor 214 to V when switch A is closed. DDR 210. Switch box 316 has another switch B that, when closed, connects the gate terminal of transistor 214 to ground. Replica transistor 216 is connected to V G 208.

[0037] Additionally, V DDR 210 is connected to the source terminal of transistor 320. The drain terminal of transistor 320 is connected to the power supply V S The gate terminal of transistor 320 is connected to bias generator 302, which in turn outputs a bias output voltage V G1 to be applied at the gate of transistor 320 and output V G 208 is applied to the gate of replica transistor 216. By adjusting V G1 , bias generator 302 indirectly changes V through transistor 320 DDR 210. The bias generator 302 is controlled by a calibration logic unit 304, which sends a signal to the bias generator to adjust the output voltage V G and V G1 (and indirectly adjust V DDR ), so that the replica upper unit 202 and the replica lower unit 204 of the replica sheet 201 both present the desired impedance value.

[0038] The calibration logic unit 304 receives two inputs: a clock and an output from a comparator 306. In addition to controlling the bias generator 302, the calibration logic unit 304 also controls the switch box 318, the switch box 316, the switch box 314, the switch 326, and the select bits of the multiplexer 308, as further described below. The comparator 306 compares the voltage level measured at the output terminal 328 with the reference voltage value retrieved from the multiplexer 308.

[0039] In order to adjust the impedance of the replica upper cell 202 independently of the impedance of the replica lower cell 204, a second lower cell 312 is added in parallel to the replica lower cell 204 in the calibration circuit 300. The lower cell 312 includes a transistor 322 and a resistor 324. The source terminal of the transistor 322 is grounded, and the drain terminal of the transistor 322 is connected to the resistor 324. The gate terminal of the transistor 322 is connected to the switch box 314. The switch box 314 has a switch A, which applies a voltage V to the transistor 322 when connected. G(Connected to bias generator 302 .) Additionally, switch box 314 has another switch 314B which, when connected, connects the gate terminal of transistor 322 to ground. Resistor 324 of lower cell 312 is connected to switch 326 which connects resistor 324 to current source 310 .

[0040] In order to calibrate the impedance of the replica upper cell 202, the replica lower cell 204, and the lower cell 312, a voltage level is measured at the output terminal 328. The voltage level measured at the output terminal 328 is compared with the reference voltage value at the comparator 306. Specifically, different reference voltage values ​​can be selected from the multiplexer 308 by the calibration logic 304. The calibration logic 304 provides a selection signal to the multiplexer 308 to cause the multiplexer 308 to output one of the available reference voltage values, for example, based on the calibration stage. Additionally, based on the output value of the comparator 306, the calibration logic unit 304 sends a signal to the bias generator 302 to adjust the output voltage V G and V G1 , or modify any one of switches 314, 316, 318 and 326. Figure 5a to Figure 5c The operation of the different components of circuit diagram 400 is further described.

[0041] In some embodiments, the impedance of the replica upper cell 202 is first calibrated and the impedance of the replica upper cell 202 is calibrated for V DDR 210 is fixed. Then, the voltage V G 208 is used to calibrate the impedance of the replica lower cell 204. To adjust the impedance of the replica upper cell 202, a lower cell 312 is deployed. The impedance of the lower cell 312 is controlled by a resistor 324 and a transistor 322. In some embodiments, to obtain a desired impedance of 1K ohms in the replica upper cell 202 and the replica lower cell 204 of the replica sheet 201, the impedance of the lower cell 312 is fixed at 3K ohms. The desired impedance value of 3k ohms for the lower cell 312 is selected based on the desired impedance values ​​for the upper cell 102 and the lower cell 104. In some embodiments, if the desired values ​​for the impedances of the upper cell 102 and the lower cell 104 are different from 50 ohms, the desired value for the impedance of the lower cell 312 may be different.

[0042] Figure 5a to Figure 5c is a logical flow diagram illustrating the operation of an embodiment according to the present invention. Figure 4 The circuit shown in process 500 is used to calibrate the impedance in replica wafer 201.

[0043] According to an example embodiment, the lower cell 312 is first calibrated so that the impedance of the lower cell 312 is set to a desired value (e.g., 3k ohms in this case). At the beginning of the impedance calibration of the lower cell 312, the calibration logic 304 sends a control signal to close switch B at 318, close switch B at 316, close switch 326, and close switch A at 314. At the same time, the calibration logic 304 sends a control signal to open switch A at 318, open switch A at 316, and open switch B at 314. By controlling the switches in this manner, transistors 206 and 214 are effectively removed from the circuit, and transistor 322 is connected to the current source 310. The calibration logic 304 selects REF1 as the reference voltage from the multiplexer 308 for the reference input to the comparator 306. The second input of the comparator 304 is the voltage measured at the output terminal 328.

[0044] Specifically, at 502, a constant current from a constant current source 310 is fed to the lower cell 312. This may produce a voltage across the lower cell 312 that may be measured at the output terminal 328.

[0045] At 504, the voltage level at the output terminal 328 is measured, and the measured voltage level is indicative of the impedance between the output terminal 328 and ground. Figure 4 As shown, the measured voltage level at output terminal 328 is fed into the negative terminal of comparator 306 .

[0046] At 506, an output is provided from the multiplexer 308, which is connected to a first reference voltage source providing a first reference voltage value REF1 and a second reference voltage source providing a second reference voltage value REF2. At 508, the calibration logic unit 304 sends a selection signal, thereby causing the multiplexer 308 to output one of the first reference voltage value REF1 and the second reference voltage value REF2. For example, to calibrate the impedance on the lower unit 312, the REF1 reference voltage is selected. In some embodiments, the reference voltage values ​​REF1 and REF2 are predefined based on the expected impedance of the upper unit 102 and the lower unit 104.

[0047] At 510, the comparator 306 compares the first voltage level detected at the output terminal 328 with the reference voltage value REF1 from the multiplexer 308. The output of the comparison indicates whether the voltage level at the output terminal 328 is greater than the reference voltage REF1, less than the reference voltage REF1, or substantially similar to the reference voltage REF1, which is sent to the calibration logic unit 304. As used herein, "substantially similar" means that two entities with tolerable differences are almost the same or equivalent due to limited measurement accuracy.

[0048] At 512 , the calibration logic unit 304 controls whether the output of the comparator 306 indicates that the voltage level at the output terminal 328 deviates from the first reference voltage value REF1 .

[0049] In response to determining that the output of comparator 306 indicates that the voltage level at output terminal 328 deviates from REF1, calibration logic unit 304 sends a signal to bias generator 302, causing bias generator 302 to adjust adjustable gate voltage V based on the sign of the output of comparator 306. G , until the updated output of the comparator 306 indicates that the updated voltage level at the output terminal 328 is substantially similar to the reference voltage value REF1.

[0050] For example, in some embodiments, a high positive output from comparator 306 means that the voltage at output terminal 328 is too low, and calibration logic unit 304 will command bias generator 302 to reduce V G voltage in order to increase the voltage measured on the lower cell 312. Similarly, if the output of comparator 306 is low, calibration logic 304 may command bias generator 302 to increase V G 208. In some embodiments, the output from multiplexer 308 may be connected to the negative terminal of comparator 306, while output terminal 328 may be connected to the positive terminal of comparator 306. In this case, the response of the calibration logic will also be opposite to the previous embodiment.

[0051] Finally, based on the signal from the calibration logic unit 304, the bias generator 302 is used to adjust V G The modification of V may make the voltage at 328 substantially similar to the REF1 voltage, or at least within a predetermined tolerable range of the REF1 voltage. G A slight increase or decrease in will flip the comparator output from high to low or from low to high. At this point, the calibration of the lower unit 312 to the desired impedance of 3K ohms is complete.

[0052] Once the voltage at output terminal 328 measured on lower cell 312 reaches the desired value (REF1), replica 201 is connected to lower cell 312 to be calibrated. Calibration of replica upper cell 202 is performed by connecting lower cell 312 to replica upper cell 202. Calibration logic 304 implements this configuration by closing switch A at 318, closing switch B at 316, and closing switch A at 314 and opening switch B at 318, opening switch A at 316, opening switch 326, and opening switch B at 314. Calibration logic 304 selects REF1 as the voltage reference from multiplexer 308. Voltage REF1 is fed to the positive input of comparator 306. Calibration logic 304 commands bias generator 302 to lock voltage V from the calibration configuration of lower cell 312. G The value of .

[0053] At 518, the replica upper cell 202 is connected to the lower cell 312. Based on the switch configuration selected by the calibration logic 304 as described above, the replica lower cell 204 and the current source 310 are removed from the calibration circuit 300. The replica upper cell 202 and the lower cell 312 are part of the calibration circuit 300. Once the replica upper cell 202 is connected to the lower cell 312, the voltage level is measured at the output terminal 328.

[0054] At 520 , the comparator 306 compares the voltage level detected at the output terminal 328 to the first reference voltage value REF1 .

[0055] At decision block 522, calibration logic 304 determines whether the output of comparator 306 indicates that the second voltage level at output terminal 328 deviates from first reference voltage value REF1. The output of the comparator is provided to calibration logic 304. Based on the result, calibration logic 304 controls the bias generator 302 to provide a voltage level at output terminal 328 that is different from first reference voltage value REF1. G1 208 supplies voltage to the calibration circuit 300 .

[0056] At 524, in response to determining that the output of the comparator 306 indicates that the voltage level at the output terminal 328 deviates from the first reference voltage value REF1, the calibration logic 304 sends a second signal to the bias generator 302, thereby causing the bias generator 302 to adjust the second adjustable gate voltage V based on the sign of the second output of the comparator 306. G1 , until the updated second voltage level of the comparator 306 indicates that the updated second voltage level at the output terminal is substantially similar to the first reference voltage value REF1.

[0057] At 526, in response to determining that the output of comparator 306 indicates that the first voltage level at output terminal 328 does not deviate from the first reference voltage value REF1, but is substantially similar to the first reference voltage value REF1, calibration logic 304 applies the adjusted second adjustable gate voltage V as the transistor driver voltage at the gate of transistor 106 and the gate of the second transistor 114. G1 .

[0058] As previously described during calibration of lower cell 312, calibration logic 304 controls bias generator 302 to adjust voltage V based on the result received from comparator 306. G1 To change V DDR During this process, the voltage V G The selected value is maintained during the calibration time of the lower cell 312. In some embodiments, when the output of comparator 306 is high, it means that the impedance of the replica upper cell 202 is too large, and the calibration logic will command bias generator 302 to increase V G1 voltage in order to increase V DDR 210, thereby reducing the impedance of the replica upper cell 202. On the other hand, if the output of the comparator is low, the calibration logic unit 304 will command the bias generator 302 to reduce the voltage V G1 , to reduce the voltage V DDR 210. This process is repeated until the voltage REF1 measured at 328 is within the tolerable range of the voltage.

[0059] It should be noted that once the voltage at output terminal 328 is substantially similar to REF1, according to Ohm's law (V=I×R), the impedance of replica upper cell 202 is 1K ohms. Calibration logic 304 switches the configuration of calibration circuit 300 to calibrate the impedance of replica lower cell 204 to 1K ohms.

[0060] Continuing to 530, the lower cell 204 is connected to the constant current source 310 while the calibration logic 304 sends control signals to close switch B at 318, close switch A at 316, close switch 326 and close switch B at 314 and open switch A at 318, open switch B at 314 and open switch A at 316. The calibration logic 304 selects REF2 at the multiplexer 308 as the reference voltage to be fed into the positive input of the comparator 306. The reference voltage is swapped from REF1 to REF2 because the expected impedance for the replica lower cell 204 is different than the expected impedance for the lower cell 312. According to this configuration of the calibration circuit 300, the replica upper cell 202 and the lower cell 312 are removed from the circuit. The replica lower cell 204 is connected to the current source 310. The current source 310 feeds a fixed amount of current into the replica lower cell 204 to produce a voltage across the replica lower cell 204 that can be measured at 328.

[0061] At 532, comparator 306 compares the voltage measured at output terminal 328 to the REF2 reference voltage received from multiplexer 308. Calibration logic 304 changes the select bit value of multiplexer 308 to select REF2 instead of REF1. The output of the comparison is fed to calibration logic 304.

[0062] At 534 , the calibration logic 304 determines whether the output of the comparator indicates that the voltage level at the output terminal 328 deviates from the second reference voltage value REF2 .

[0063] At 536, in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 deviates from the second reference voltage value REF2, the calibration logic 304 sends a signal to the bias generator 302, thereby causing the bias generator 302 to adjust the first adjustable gate voltage V based on the sign of the output of the comparator. G , until the updated output of comparator 306 indicates that the updated voltage level at output terminal 328 is substantially similar to the second reference voltage value REF2. The calibration logic is configured to command bias generator 302 to modify V G until the measured voltage at output terminal 328 is substantially similar to the REF2 voltage while maintaining V G1 In some embodiments, when the output of the comparator is high, the impedance of the replica lower cell 204 is too low, and the calibration logic 304 will command the bias generator 302 to reduce the voltage V G voltage in order to increase the impedance of the replica lower cell 204. Similarly, if the output of the comparator is low, the calibration logic 304 will command the bias generator 302 to increase the voltage V G When the impedance of the lower unit is adjusted to the desired range, the calibration of the replica is completed.

[0064] At 538, in response to determining that the output of the comparator indicates that the voltage level at the output terminal 328 has not deviated from the second reference voltage value REF2, the calibration process is complete. After adjusting the impedances of the lower cell 312, the replica of the replica upper cell 202, and the replica of the replica lower cell 204 to the desired values, the calibration process is complete. The calibrated V DDR and V G The gate voltages will be applied to transistors 106, 114 and 116 of the voltage mode transmitter driver 100 respectively.

[0065] Figure 6 1 shows a system diagram of a low power transmitter according to one embodiment described herein. Figure 6 As shown, the digital signal will be transmitted from one integrated chip (system on chip 602) to another integrated chip (system on chip 620) via a low-power physical layer transmitter 604. Specifically, as Figure 6 As shown, 80 bits of data are transmitted from SOC 602 to transmitter 604 for transmission to SOC 620.

[0066] The transmitter 604 includes a transmitter data multiplexer 606, a transmitter driver 608, a calibration logic 610, a bias generator 612, and a replica driver unit 614. The calibration logic 610 is configured to drive the replica driver unit 614 to a desired impedance via the bias generator 612. Specifically, the calibration logic 610 adjusts a first gate voltage (VG1) and a second gate voltage (VG) applied to the replica driver. Once the impedance of the replica driver unit 614 reaches the desired impedance (e.g., 1k ohms), the bias generator applies the calibrated first gate voltage VG1 and the calibrated second gate voltage VG to the transmitter driver 608 (e.g., the low power voltage mode transmitter driver 100).

[0067] As mentioned above Figure 5a to Figure 5c As discussed, the calibration logic 610 controls the bias generator 612 to set the first gate voltage VG1 and the second gate voltage VG to the calibrated first gate voltage and the calibrated second gate voltage, respectively. Once the calibrated first gate voltage VG1 and the calibrated second gate voltage VG are applied to the transmitter driver 608 (e.g., the first gate voltage VG1 is applied to the first transistor 106 of the upper cell 102 of each driver slice and to the second transistor 114 of the lower cell 104, and the second gate voltage VG is applied to the third transistor 116 of the lower cell 104, as shown in FIG. 1 ), the bias generator 612 controls the first gate voltage VG1 and the second gate voltage VG to be set to the calibrated first gate voltage and the calibrated second gate voltage, respectively. Figure 1 As shown), the impedance of the upper unit 102 and the lower unit 104 are matched.

[0068] In conventional transmitter designs, reflections are generated during transmission from the transmitter 604 to the SOC 620 due to the discontinuity of the impedance of the upper unit 102 and the lower unit 104. However, the transmitter design described herein provides matched impedance at the transmitter driver 608. Therefore, when the high-speed digital signal to be transmitted is converted into a low-swing analog high-speed signal, no reflections are generated, thereby improving the overall system performance. Before the transmitted low-swing analog high-speed signal is sent to the SOC 620, the transmitted low-swing analog high-speed signal is received at the physical layer of the receiver 618.

[0069] While operations are depicted in the drawings in a particular order, this should not be construed as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

[0070] The subject matter of this specification has been described in terms of certain aspects, but other aspects may be implemented and are within the scope of the appended claims. For example, the actions recited in the claims may be performed in a different order and still achieve the desired results. As an example, Figures 4 to 6 The processes depicted in the present disclosure do not necessarily require the particular order shown or sequential order to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous. Other variations are within the scope of the appended claims.

Claims

1. A low power transmitter for transmitting a digital signal from an integrated chip, the transmitter comprising: A voltage mode transmitter driver, comprising a plurality of driver slices, wherein each driver slice comprises an upper unit and a lower unit, wherein: The upper unit includes a first resistor and a first transistor, wherein the upper unit is connected to a voltage source and an output terminal of the voltage-mode transmitter driver; and the lower unit comprising a second resistor, a second transistor and a third transistor, wherein the lower unit is connected to the output terminal of the voltage-mode transmitter driver and ground; a replica circuit comprising a replica of the upper unit and a replica of the lower unit; a calibration circuit configured to drive the replica circuit to a desired impedance by adjusting a first gate voltage applied to the first transistor of the replica of the upper cell to be equal to a calibrated first gate voltage and adjusting a second gate voltage applied to the third transistor of the replica of the lower cell to be equal to a calibrated second gate voltage; and A bias generator is configured to receive the calibrated first gate voltage and the calibrated second gate voltage from the calibration circuit, and apply the calibrated first gate voltage to the first transistor and the second transistor of each driver slice in the plurality of driver slices, and apply the calibrated second gate voltage to the third transistor of each driver slice in the plurality of driver slices.

2. The low power transmitter according to claim 1, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the multiple driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the multiple driver slices, the upper unit of each of the multiple driver slices is configured to generate an impedance that matches the impedance of the corresponding lower unit of each of the multiple driver slices.

3. The low power transmitter according to claim 2, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the upper cells of the plurality of driver slices is equal to the impedance of the replica of the upper cell.

4. The low power transmitter according to claim 2, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the lower unit of the plurality of driver slices is equal to the impedance of the replica of the lower unit.

5. The low power transmitter according to claim 1, wherein: The copy of the upper unit also includes: a copy of the first resistor and a copy of the first transistor, wherein the copy of the upper cell is connected to the voltage source and the output of the voltage-mode transmitter driver; wherein the copy of the lower unit further comprises: a copy of the second resistor, a copy of the second transistor, and a copy of the third transistor, wherein the copy of the lower cell is connected to the output terminal of the voltage-mode transmitter driver and the ground.

6. The low power transmitter of claim 5, wherein the calibration circuit further comprises: a second lower unit including a fourth transistor and a third resistor; a constant current source configured to feed a constant current into the second lower unit to generate an output voltage; a comparator configured to compare the output voltage generated by the second lower unit with a first reference voltage and a second reference voltage; as well as A calibration logic control is configured to adjust the impedance of the second lower unit to match a first predetermined impedance by adjusting the second gate voltage via a bias generator based on an output of the comparator.

7. The low power transmitter of claim 6, wherein the bias generator is configured to reduce the second gate voltage in response to the calibration logic control receiving a high level output from the comparator indicating that the impedance of the second lower unit is low; and The bias generator is configured to increase the second gate voltage in response to the calibration logic control receiving a low level output from the comparator indicating that the impedance of the second lower unit is high.

8. The low power transmitter of claim 6, wherein the calibration circuit is further configured to: maintaining the second gate voltage at a voltage at which the impedance of the second lower unit matches the first predetermined impedance via the bias generator; adjusting, via the bias generator, the first gate voltage to a voltage at which an impedance of the replica of the upper cell matches a second predetermined impedance; and The first gate voltage is calibrated to a voltage at which the impedance of the replica of the upper cell matches the second predetermined impedance.

9. The low power transmitter of claim 8, wherein the calibration circuit is further configured to: maintaining the calibrated first gate voltage via the bias generator; adjusting, via the bias generator, the second gate voltage so that the impedance of the replica of the lower cell matches the second predetermined impedance; and The second gate voltage is calibrated to a voltage at which the impedance of the replica of the lower cell matches the second predetermined impedance.

10. The low power transmitter of claim 9, wherein the bias generator is configured to supply the calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices, and to supply the calibrated second gate voltage to the third transistor of each of the plurality of driver slices.

11. A method for transmitting a digital signal from an integrated chip via a low power transmitter, the low power transmitter comprising a plurality of driver chips, and a replica circuit, wherein each of the plurality of driver chips comprises an upper unit and a lower unit, and wherein the replica circuit comprises a replica of the upper unit and a replica of the lower unit, the method comprising: calibrating, via a calibration circuit of the low power transmitter, a first gate voltage and a second gate voltage by adjusting a first gate voltage applied to a first transistor of the replica circuit to be equal to a calibrated first gate voltage and adjusting a second gate voltage applied to a third transistor of the replica circuit to be equal to a calibrated second gate voltage; applying a calibrated first gate voltage to a first transistor of the upper unit of each driver slice of the plurality of driver slices; applying the calibrated first gate voltage to a second transistor of the lower unit of each driver slice of the plurality of driver slices; as well as A calibrated second gate voltage is applied to a third transistor of the lower unit of each of the plurality of driver slices.

12. The method according to claim 11, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the multiple driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the multiple driver slices, the upper unit of each of the multiple driver slices is configured to generate an impedance that matches the impedance of the corresponding lower unit of each of the multiple driver slices.

13. The method according to claim 12, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the upper cells of the plurality of driver slices is equal to the impedance of the replica of the upper cell.

14. The method according to claim 12, wherein: In response to applying the calibrated first gate voltage to the first transistor and the second transistor of each of the plurality of driver slices, and in response to applying the calibrated second gate voltage to the third transistor of each of the plurality of driver slices, a total impedance of the lower unit of the plurality of driver slices is equal to the impedance of the replica of the lower unit.

15. The method of claim 11, wherein calibrating the first gate voltage and the second gate voltage by driving the replica circuit of the low power transmitter to a desired impedance via the calibration circuit of the low power transmitter comprises: feeding a constant current into the second lower unit via a constant current source to generate an output voltage; comparing the output voltage generated by the second lower unit with a first reference voltage and a second reference voltage via a comparator; as well as Based on the output of the comparator, the impedance of the second lower unit is adjusted to match a first predetermined impedance through calibration logic control by adjusting the second gate voltage through a bias generator.

16. The method according to claim 15, further comprising: In response to the calibration logic control receiving a high level output from the comparator indicating that the impedance of the second lower unit is low, the second gate voltage is reduced via the bias generator.

17. The method according to claim 15, further comprising: In response to the calibration logic control receiving a low level output from the comparator indicating that the impedance of the second lower unit is high, the second gate voltage is increased via the bias generator.

18. The method according to claim 15, further comprising: maintaining the second gate voltage at a voltage at which the impedance of the second lower unit matches the first predetermined impedance via the bias generator; adjusting, via the bias generator, the first gate voltage to a voltage at which an impedance of the replica of the upper unit matches a second predetermined impedance; as well as The first gate voltage is calibrated to a voltage at which the impedance of the replica of the upper cell matches the second predetermined impedance.

19. The method according to claim 18, further comprising: maintaining the calibrated first gate voltage via the bias generator; adjusting the second gate voltage via the bias generator so that the impedance of the replica of the lower cell matches the second predetermined impedance; as well as The second gate voltage is calibrated to a voltage at which the impedance of the replica of the lower cell matches the second predetermined impedance.

20. The method according to claim 19, further comprising: The calibrated first gate voltage is supplied to the first transistor and the second transistor of each of the plurality of driver slices via the bias generator, and the calibrated second gate voltage is supplied to the third transistor of each of the plurality of driver slices.

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