Processor Architecture

Abstract

A processor (1) comprising a control unit (3) and a plurality of processing units (5), the plurality of processing units interacting with each other according to an operating architecture dynamically applied by the control unit from at least two of the following architectures and a combination of the following architectures: - Single Instruction Multiple Data (SIMD) streaming architecture, - Multiple Instruction Single Data (MISD) streaming architecture, - Multiple Instruction Multiple Data (MIMD) streaming architecture. The operating architecture is dynamically applied by the control unit according to: - Configuration functions contained in machine code, and / or - Data to be processed and current processing instructions received as input to the processor.

Description

Technical Field

[0001] The present invention belongs to the field of processors, and in particular to the field of intrinsic operation of processors. Background Art

[0002] Conventionally, a processor has an architecture defined in its design. The architecture is defined at least in part by the implementation of a machine instruction set (ISA, for "instruction set architecture") that the processor can execute. It is recognized that each known architecture can be classified into one of the following types (or categories) defined according to Fehling's taxonomy:

[0003] - Single Instruction Single Data or SI SD;

[0004] - Single Instruction Multiple Data or SIMD;

[0005] -Multiple Instruction Single Data or MI SD;

[0006] -Multiple Instruction Multiple Data or MI MD.

[0007] Each of these types of architectures has known advantages and disadvantages. The degree of parallelism between computations varies depending on the intended application. Selecting an architecture typically makes the processor on which it is implemented particularly efficient (fast) for certain computations and slower for other computations. The choice of processor type involves a trade-off in processor usage. Each processor type tends to be specialized for certain computations, to the detriment of other computations that are less efficient. Summary of the invention

[0008] The present invention improves this situation.

[0009] A processor is proposed, comprising a control unit and a plurality of processing units. The plurality of processing units interact with each other according to an operating architecture dynamically imposed by the control unit from at least two of the following architectures and combinations of the following architectures:

[0010] - Single Instruction Multiple Data (SIMD) streaming architecture,

[0011] -Multiple Instruction Single Data (MISD) streaming architecture,

[0012] -Multiple Instruction Multiple Data (MI MD) streaming architecture.

[0013] The operating architecture is dynamically imposed by the control unit based on:

[0014] - configuration functions contained in machine code, and / or

[0015] -The data to be processed and the current processing instructions received as input to the processor.

[0016] Such a processor allows for dynamic and contextual adaptation in its internal operation. When the calculations to be performed are independent of each other, the calculations can be processed in parallel (and therefore simultaneously) by different computing units. The processing of all calculations is accelerated. When the calculations to be performed are dependent on each other, parallel processing is not suitable. Recursive calculations are examples of calculations that are not suitable for parallel processing: in order to perform a calculation, the result of the previous calculation is required. One or more computing units must perform calculations sequentially, cycle by cycle. Such a processor is multi-purpose. Such a processor has an architecture that changes during the execution of calculations according to the calculation itself.

[0017] According to another aspect, a method for compiling source code implemented by a computing device is provided, the method comprising the following steps:

[0018] - receives source code as input,

[0019] -Search in source code:

[0020] - configuration data applying the operating architecture of the processor,

[0021] - a first portion of source code corresponding to data processing instructions comprising a concatenated sequence of elementary operations, and

[0022] - a second portion of the source code corresponding to data processing instructions comprising mutually independent elementary operations.

[0023] The method further comprises the following steps:

[0024] - Compile source code into machine code.

[0025] In case at least one configuration data imposing an operating architecture of the processor has been identified and / or in case at least one first portion of source code and at least one second portion of source code has been identified, the compiling comprises including a configuration function in the machine code. The configuration function is arranged to dynamically apply an architecture from at least two of the following architectures and a combination of the following architectures to the processor executing the machine code:

[0026] - Single Instruction Multiple Data (SIMD) streaming architecture,

[0027] -Multiple Instruction Single Data (MISD) streaming architecture,

[0028] -Multiple Instruction Multiple Data (MI MD) streaming architecture.

[0029] Optionally, the method for compiling source code further comprises: verifying compliance with a set of rules pre-established in the input processing instructions, and selecting configuration functions to be included in the machine code during compilation based on compliance with the rules.

[0030] According to another aspect, a method for managing a processor architecture implemented by a computing device is provided, the method comprising the following steps:

[0031] - receiving data to be processed and processing instructions as input to the processor, and

[0032] - dynamically applying an operating architecture to at least one processing unit of the processor according to the data to be processed and the received processing instructions, wherein the operating architecture is selected from at least two of the following architectures and a combination of the following architectures:

[0033] - Single Instruction Multiple Data (SIMD) streaming architecture,

[0034] -Multiple Instruction Single Data (MISD) streaming architecture,

[0035] -Multiple Instruction Multiple Data (MI MD) streaming architecture.

[0036] According to another aspect, a computer-readable non-transitory storage medium is provided, on which a compiled program including instructions for implementing the above method is stored. According to another aspect, a compiled computer program is proposed, including instructions for implementing the compiled method when the program is executed by a processor.

[0037] According to a further aspect, a non-transitory storage medium readable by a control unit of a processor is provided, on which a machine instruction set for implementing a method for managing an architecture such as defined herein is stored. According to a further aspect, a machine instruction set is provided, which, when executed by a control unit of a processor, is used to implement the architecture management method. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other features, details and advantages of the present invention will become apparent upon reading the following detailed description and analyzing the accompanying drawings, in which:

[0039] - Figure 1 Partially illustrating the architecture of a processor according to the present invention,

[0040] - Figure 2 shows the operating mode of the processor according to the present invention,

[0041] - Figure 3 shows the operating mode of the processor according to the present invention, and

[0042] - Figure 4 The operation details of the processor according to the present invention are shown. DETAILED DESCRIPTION

[0043] The drawings and the description hereinafter mainly contain elements of a certain nature. Therefore, they may not only serve to better understand the invention but also facilitate the definition of the invention where appropriate.

[0044] Figure 1 A processor 1 is shown, sometimes called a central processing unit or CPU. Processor 1 includes:

[0045] - control unit 3,

[0046] - a computing unit comprising a plurality of processing units 5,

[0047] - an input-output unit 7 or interface, and

[0048] - Memory unit 9.

[0049] As is known, the processor 1 receives data to be processed ("data") and processing instructions ("instructions") via the input-output unit 7. The data and instructions are stored in the memory unit 9. The memory unit 9 can be divided into several parts. For example, the memory unit 9 includes a data part (or "data pool") and an instruction part (or "instruction pool").

[0050] Each processing unit 5 performs calculations on data according to instructions taken from instructions stored in the memory unit 9. The control unit 3 imposes on each processing unit 5 the manner in which the elementary calculations should be performed (in particular, their order) and distributes the operations to be performed to each calculation component of the processing unit 5.

[0051] In the example described here, each processing unit 5 or PU includes several computing components: arithmetic and logic units or ALUs. Each processing unit 5 includes at least one ALU and at least one associated set of registers REG. In the following and according to the drawings, each processing unit 5 is numbered from PU 0 to PU N. Each ALU is numbered AB, where "A" identifies the processing unit PU A to which the ALU belongs, and "B" is the identifier of the ALU outside the other ALUs of the processing unit PU A.

[0052] The processor 1 comprises at least two ALUs divided into two processing units 5. For example, each processing unit 5 comprises a single ALU or multiple ALUs. Figures 1 to 3 In the example of , each processing unit 5 includes four ALUs numbered 0 to 3. When a processing unit 5 includes multiple ALUs, the processing unit 5 is called a multi-core.

[0053] Each ALU can perform:

[0054] - Arithmetic operations on integer data (addition, subtraction, multiplication, division, etc.);

[0055] - Arithmetic operations on floating-point data (addition, subtraction, multiplication, division, inversion, square root, logarithm, trigonometric functions, etc.);

[0056] -Logical operations (bin's complement AND, OR, XOR, etc.).

[0057] The processing unit 5 and the memory unit 9 interact according to one and / or another of the following three architectures:

[0058] - Single Instruction Multiple Data (SIMD) streaming architecture,

[0059] -Multiple Instruction Single Data (MISD) streaming architecture,

[0060] -Multiple Instruction Multiple Data (MI MD) streaming architecture.

[0061] Figure 2 An example of a SIMD architecture is shown in FIG. 1 . In this example, the processing units 5 interact according to the SIMD architecture. Data to be processed is copied (loaded) from the memory unit 9 to each of the sets of registers REG 0, REG 1, ..., REGN of the corresponding processing unit 5. The ALU performs the calculation. The result is written to the set of registers REG 0, REG 1, ..., REG N. Subsequently, the result is copied from the set of registers REG 0, REG 1, ..., REG N to the memory unit 9.

[0062] In this example, the processing units 5 do not exchange data directly with each other. The ALU of each processing unit 5 processes data and performs calculations independently from one processing unit 5 to another. The operation of the processor 1 is parallelized at the processing unit 5 level.

[0063] exist Figure 2 In the example of FIG. 5 , the interaction between the ALUs is not shown. Thus, although the processing units 5 interact with each other according to the SIMD architecture, as described below with respect to Figure 4 As described, the ALUs of the same processing unit interact with each other according to the SIMD architecture.

[0064] Figure 3An example of a MI SD architecture is shown in FIG. 1 . In this example, the processing units 5 interact according to the MI SD architecture. Data is copied (loaded) from the memory unit 9 to a set of registers of a single processing unit 5, here to a set of registers REG 0 of the processing unit PU 0. ALUs 0.0, 0.1, 0.2 and 0.3 perform calculations. The results are written to the set of registers REG 0. Subsequently, the results are copied from the set of registers REG 0 to a set of registers of another processing unit 5, here to a set of registers REG 1 of the processing unit PU 1. ALUs 1.0, 1.1, 1.2 and 1.3 in turn perform calculations and the results are written to the set of registers REG 1. These operations are reproduced in sequence by each of the processing units 5 until the results are written to the set of registers of the last processing unit 5, here to a set of registers REG N of the processing unit PU N. Subsequently, the results are copied from the last set of registers REG N to the memory unit 9.

[0065] In this example, processing units 5 directly exchange data with each other. The ALU of each processing unit 5 performs calculations on data, which are themselves the results of calculations implemented by other processing units 5. The operation of processor 1 is not parallelized at the processing unit 5 level. On the contrary, processing units 5 show serial or cascade operations. For example, this type of operation is suitable for so-called recursive calculations. The operations implemented by processing units 5 can be the same, but applied to different data each time. As a variant, instructions can also be different from each other and data can also be different from each other.

[0066] and Figure 2 As in the example, Figure 3 In the example of , the interaction between ALUs is not shown.

[0067] exist Figure 4 In the figure, the operations of two PUs are represented.

[0068] The processing unit PU X comprises four ALUs. The ALUs of the processing unit PU X interact with each other. Data is loaded from the set of registers REG X to each of the ALUs X.0, X.1, X.2, X.3 of the processing unit PU X. The ALU performs a calculation. The result is then written to the set of registers REG X.

[0069] The ALUs do not exchange data directly with each other.

[0070] exist Figure 4 In the example of , the architecture at the processing unit 5 level is not represented. Figure 2 and 3As described, the processing unit 5 may interact according to one and / or another of the SIMD, MISD and MIMD architectures. In other words, an instance of the PU X may interact with Figure 2 Examples and Figure 3 Instances of .

[0071] The control unit 3 can dynamically apply the operating architecture according to the data to be processed and the current instructions received as input to the processor 1. When the type of data and instructions to be processed can be inferred from the source code, this dynamic adaptation of the architecture can be implemented starting from the compilation phase, by adapting the machine instructions generated by the compiler according to the type of data and instructions to be processed. This adaptation can also be implemented at the processor level only when the processor executes conventional machine code, when this processor is programmed to implement a set of configuration instructions, which are a function of the data to be processed and the current instructions received.

[0072] An example of a computer code to perform a calculation is reproduced below. This code extracts instructions corresponding, for example, to a source code to be implemented by the processor 1 .

[0073] void processing()

[0074] {

[0075] matrix A(4,4);

[0076] matrix B(4,4);

[0077] matrix C(4,4);

[0078] C = A * B; / / (1)

[0079] C = C + B; / / (2)

[0080] matrix D(4,4);

[0081] D = inv(A); / / (3)

[0082] }

[0083] In an example, the processor includes four processing units PU, each of which includes four arithmetic and logic units ALU. In an example, matrix multiplication is processed first, and then matrix addition is processed. The compiler can process the matrix operation by decomposing it into basic operations. For each matrix operation, the basic operations that make up the matrix operation are independent of each other. In other words, the result of a basic operation is useless for implementing another basic operation. Therefore, the basic operations can be implemented in parallel with each other. Adding two matrices of 4×4 dimensions requires 16 basic operations (addition). This matrix addition, i.e., 16 basic operations, can be performed in a single cycle. Multiplying two matrices of 4×4 dimensions requires 64 basic operations (multiplication+accumulation). Therefore, at least perform this matrix multiplication in four cycles, i.e., 64 basic operations.

[0084] The operation marked "(3)" (matrix inversion) includes elementary operations that depend on each other. The results of some elementary operations are necessary to implement other elementary operations. Parallel processing is not suitable. Therefore, the inversion algorithm must be decomposed into N processing steps. Each step can be performed on one ALU in one cycle, but the data is different from each other and the process is different from each other.

[0085] step_1→step_2→step_3→step_4→step_5→…→step_N

[0086] To implement operations "(1)" and "(2)", processor 1 adopts SIMD architecture. To implement operation "(3)", processor 1 adopts MISD architecture.

[0087] For example, operation "(3)" includes nine steps (N=9). Three iterations or three loops are therefore necessary. Each loop is implemented by a processing unit PU. For example, the N steps in the loop are distributed to the ALU of the processing unit PU as follows:

[0088] Loop 1:

[0089] ALU 0 → Step_1

[0090] ALU 1 → Step_2

[0091] ALU 2 → Step 3

[0092] ALU 3 → Step 4

[0093] Loop 2:

[0094] ALU 0 → Step 5

[0095] ALU 1 → Step 6

[0096] ALU 2 → Step 7

[0097] ALU 3 → Step 8

[0098] Loop 3:

[0099] ALU 0 → Step 9

[0100] During cycle 3, ALU 1, ALU 2, and ALU 3 are not used.

[0101] As indicated previously, the control unit 3 may dynamically apply the operating architecture depending on the data and current instructions received as input to the processor 1. This covers two cases.

[0102] In the first case, the architecture and allocation of resources are fixed during compilation. In other words, the developers of third-party programs (in addition to those who control the inherent operation of the processor) can include specific configuration instructions in the source code. The specific instructions are transcribed into the target language (during compilation) in the specific instructions (machine code) recognized by the control unit 3. When received on the processor 1, the control unit 3 imposes the architecture on the processing unit 5 in a manner predefined by the instructions. In this case, the responsibility for optimizing the operation of the processor can be left to the creator of the third-party program. Based on the program, the programmer is free to impose or not impose specific operations of the processor, that is, the architecture selected here from SI SD, MI SD, MI MD or a combination thereof.

[0103] In the second case, the architecture and allocation of resources are fixed in a pre-established manner according to a machine instruction set implemented in the processor. This instruction set is usually implemented before the processor is sold and used. The machine instruction set is not expected to be modified by the user of the processor. In this second case, when an instruction is received on the processor 1, before implementing the instruction received as input, the control unit 3 implements an architecture management, or architecture configuration, method. For example, the control unit 3 first transmits configuration data dedicated to each processing unit PU to each processing unit PU. Each of the configuration data sets is stored in a configuration register accessible to the corresponding processing unit. Next, the processing unit PU receives a general processing instruction (common to all PUs) from the instruction bus. Each PU implements the processing instruction in a manner that varies according to the configuration data previously received and stored in the configuration register. In other words, each PU interprets the general processing instruction through the configuration data to adapt to the processing to be implemented. The second case can introduce flexibility into the control. Regardless of which architecture (SIMD, MI SD, MI MD) is adopted, the general instruction can be transmitted to all PUs. The previous transmission of configuration data can select the architecture actually adopted by the PU when the general instruction is received.

[0104] In both cases, the architecture may be dynamic, that is to say evolving during the steps of executing the received instructions, in particular according to the nature of the calculations to be performed. For example, a SIMD architecture may be applied by default and a MISD architecture may be applied for recursive calculations. Both cases are compatible: the processor 1 may be arranged to implement the architecture management method according to specific configuration instructions received (contained in machine code resulting from compilation) and to implement the architecture management method according to a machine instruction set without or in addition to the specific configuration instructions from the instructions received as input.

[0105] According to another perspective, it can be considered that the control unit 3 transforms the processing instructions usually received as input into adaptation instructions or "macro instructions" (or "custom instructions") by implementing configuration instructions that are intended to adapt to the architecture of the processor 1 in operation. The adaptation instructions include both processing instructions and configuration instructions. When the adaptation instructions transmitted to each of the processing units 5 are the same, the processor operates in SIMD mode. The processing units 5 all perform the same operation on different data to be processed. When the adaptation instructions transmitted to each of the processing units 5 are different from each other, the processor operates in MI SD or MI MD mode. The processing units 5 perform different operations on the same (MI SD) or different (MI MD) data to be processed.

[0106] A second example of a computer code to perform a calculation is reproduced below:

[0107] void processing()

[0108] {

[0109] matrix A(4,4)[2];

[0110] matrix D(4,4)[2];

[0111] D = inv(A); / / (3)

[0112] }

[0113] The example defines an array of matrices, each matrix being of 4×4 dimensions, the matrix having a size of 2 (comprising two matrices). The function denoted as "inv" on the matrix array consists in inverting each element in the array, i.e., inverting each of the two matrices of 4×4 dimensions. As in the previous example, the processor comprises four ALUs.

[0114] For example, such an assignment of N steps to the ALU is accomplished as follows:

[0115] Loop 1: steps 1 to 4 for matrix A[0];

[0116] Loop 2: steps 1 to 4 for matrix A[1];

[0117] Loop 3: steps 5 to 8 for matrix A[0];

[0118] Loop 4: steps 5 to 8 for matrix A[1];

[0119] Loop 5: Step 9 for matrix A[0];

[0120] Loop 6: Step 9 for matrix A[1].

[0121] The execution of the "inv" function can also be optimized by grouping loops 5 and 6 together in a common loop. Thus, a single PU is required to implement step 9 for both matrices. As a variant, ALU 0 can be assigned to calculations related to matrix A[0], while ALU 1 can be assigned to calculations related to matrix A[1].

[0122] If at least some data is known at this stage, in particular the size of the matrices and the size of the arrays, the allocation of each ALU to the operations can be planned from the compilation. The allocation can be done dynamically. For example, the allocation can be applied by the control unit 3 according to a machine instruction set implemented on the processor 1. In this case, the machine instruction set is stored on a non-transitory storage medium (for example, a part of the memory unit 9), which can be read by the control unit 3 to implement the method for managing the architecture of the processor 1.

[0123] For example, the control unit 3 is arranged to impose the implementation of the first set of operations by all ALUs on the processing unit 5, which is then repeated on each of the array elements (each of the matrix in the previous example). Next, the number of operations that can be performed in parallel (not dependent on each other) is estimated. For example, the number of resources (the number of ALUs) is divided by the number of operations to be implemented. Finally, the allocation of operations to each ALU is performed in such a way that different ALUs of different processing units 5 perform at least some operations in parallel with each other.

[0124] Thus, the architecture of the processing unit 5 may change over time. During processing operations, the architecture of the processing unit 5 may alternate between SIMD, MI SD and MI MD.

[0125] The invention is not limited to the examples of processors described above by way of example only, but covers all variants that a person skilled in the art can envisage within the scope of the protection sought. The invention also relates to a machine instruction set that can be implemented on a processor to obtain this processor, the implementation of this machine instruction set on a processor, a processor architecture management method implemented by a processor, a computer program comprising a corresponding machine instruction set, and a storage medium on which such a machine instruction set is electronically stored.

Claims

1. A processor (1) comprising a control unit (3) and a plurality of processing units (5), the plurality of processing units (5) interacting with each other according to an operating architecture dynamically imposed by the control unit from at least two of the following architectures and a combination of the following architectures: Single Instruction Multiple Data (SIMD) streaming architecture, A cascaded multiple instruction single data (MISD) streaming architecture comprising a plurality of processing units (5) exhibiting cascaded operation, wherein a processing unit (5) performs calculations on data which are themselves the result of calculations performed by other processing units (5), The operating architecture is dynamically applied by the control unit based on: Configuration functions contained in machine code, and / or The data to be processed and the current processing instructions received as input to the processor are: a first portion of source code corresponding to data processing instructions comprising a concatenated sequence of elementary operations, and A second portion of the source code corresponds to data processing instructions comprising mutually independent elementary operations.

2. A method for compiling source code implemented by a computing device, the method comprising the following steps: Receives source code as input, Search in said source code: configuration data that applies the processor's operating architecture, a first portion of said source code corresponding to data processing instructions comprising a concatenated sequence of elementary operations, and a second portion of said source code corresponding to data processing instructions comprising mutually independent elementary operations, The method further comprises the following steps: compile said source code into machine code, In case at least one configuration data imposing an operating architecture of a processor has been identified and / or in case at least one first portion of the source code and at least one second portion of the source code has been identified, the compiling comprises including a configuration function in the machine code, the configuration function being arranged to dynamically apply an architecture from at least two of the following architectures and a combination of the following architectures to a processor executing the machine code: Single Instruction Multiple Data (SIMD) streaming architecture, A cascaded multiple instruction single data (MISD) streaming architecture comprising a plurality of processing units (5) exhibiting cascaded operation, wherein a processing unit (5) performs computations on data which are themselves the result of computations performed by other processing units (5).

3. The method of claim 2, further comprising verifying compliance with a set of rules pre-established in the input processing instructions, and selecting the configuration function included in the machine code during the compilation based on compliance with the rules.

4. A computer-readable non-transitory storage medium having stored thereon a compiled program including instructions for implementing the method according to any one of claims 2 and 3.

5. A computer program product comprising instructions for implementing the method for compiling source code according to any one of claims 2 and 3 when the program is run by a processor.

6. A method for managing the architecture of a processor (1) implemented by a computing device, the method comprising the following steps: receiving data to be processed and processing instructions as input to said processor, a first portion of source code corresponding to data processing instructions comprising a concatenated sequence of elementary operations, and a second portion of said source code corresponding to data processing instructions comprising mutually independent elementary operations, as well as Dynamically applying an operating architecture to at least one processing unit (5) of the processor according to the data to be processed and the received processing instructions, wherein the operating architecture is selected from at least two of the following architectures and a combination of the following architectures: Single Instruction Multiple Data (SIMD) streaming architecture, A cascaded multiple instruction single data (MISD) streaming architecture comprising a plurality of processing units (5) exhibiting cascaded operation, wherein a processing unit (5) performs computations on data which are themselves the result of computations performed by other processing units (5).

7. A non-transitory storage medium readable by a control unit (3) of a processor (1), on which a machine instruction set for implementing the method according to claim 6 is stored.

8. A computer program product comprising a set of machine instructions for implementing the method according to claim 6 when the set of machine instructions is executed by a control unit of a processor.

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