UIS test circuit

Abstract

The present application provides a UIS test circuit, comprising: an inductor, a controllable constant voltage current clamp circuit, a drive circuit and a timing control circuit. The first end of the inductor is used to electrically connect the first end of the controllable switch tube to be tested. The first end of the controllable constant voltage current clamp circuit is electrically connected to the second end of the inductor. The first end of the drive circuit is used to electrically connect to the control end of the controllable switch tube to be tested. The second end of the drive circuit and the second end of the controllable constant voltage current clamp circuit are both used to be connected in common with the second end of the controllable switch tube to be tested. The timing control circuit is electrically connected to the third end of the drive circuit and the third end of the controllable constant voltage current clamp source respectively. The timing control circuit is used to control the conduction and disconnection of the controllable switch tube to be tested through the drive circuit. When the controllable switch tube to be tested is turned on, the controllable constant voltage current clamp circuit determines whether to output constant voltage current clamp based on the set constant voltage clamp value.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit testing, and in particular to a UIS testing circuit. Background Art

[0002] In integrated circuit testing, for power devices such as MOSFET or IGBT, UIS (Single-Pulse Unclamped Inductive Switching) parameter testing is usually required. In addition to the device under test (DUT), the circuit topology of the UIS parameter test also includes the inductor L, current measurement circuit, current comparison circuit, Vgs drive circuit, high-speed cut-off switch, Vdd power supply and timing control circuit. In order to monitor the avalanche establishment process in the UIS parameter test, a voltage measurement circuit and a time measurement circuit are added to test the device breakdown voltage and avalanche time respectively, to determine whether the device UIS test is abnormal.

[0003] When the above-mentioned traditional circuit topology is used for UIS parameter testing, from the detection that Id (the current flowing through the device under test DUT) reaches the set current threshold PeakI to the rapid shutdown of the DUT, the current measurement circuit measures Id, the current comparison circuit compares Id with PeakI, the timing control circuit performs Vgs drive control, and the DUT is rapidly shut down. These hardware response processes have a certain control delay, which will cause a certain difference between the actual shutdown current and PeakI, resulting in false triggering of protection, etc. Summary of the invention

[0004] Based on this, it is necessary to perform UIS parameter testing on traditional circuit topologies. There is a certain control delay, which will cause a certain difference between the actual shutdown current and the set current threshold, and there is a problem of false triggering protection. A UIS test circuit is provided.

[0005] A UIS test circuit, comprising:

[0006] An inductor, wherein a first end of the inductor is used to electrically connect to a first end of a controllable switch tube to be tested;

[0007] A controllable constant voltage current clamp circuit, wherein a first end of the controllable constant voltage current clamp circuit is electrically connected to a second end of the inductor;

[0008] a driving circuit, wherein a first end of the driving circuit is used to be electrically connected to a control end of the controllable switch tube to be tested, and a second end of the driving circuit and a second end of the controllable constant voltage current clamp circuit are both used to be commonly connected to a second end of the controllable switch tube to be tested; and

[0009] A timing control circuit, electrically connected to the third end of the driving circuit and the third end of the controllable constant voltage clamp current source, respectively, and used for controlling the on and off of the controllable switch tube to be tested through the driving circuit;

[0010] When the controllable switch tube to be tested is turned on, the controllable constant voltage current clamp circuit determines whether to output constant voltage current clamp based on the set constant voltage clamp value.

[0011] In one of the embodiments, the controllable constant voltage current clamp circuit is used to compare the set constant voltage clamp value with the output current of the controllable constant voltage current clamp circuit;

[0012] If the output current of the controllable constant voltage current clamp circuit exceeds the set constant voltage clamp value, the controllable constant voltage current clamp circuit clamps the current output;

[0013] If the output current of the controllable constant-voltage current clamp circuit does not exceed the set constant-voltage clamp value, the controllable constant-voltage current clamp circuit outputs a constant voltage.

[0014] In one of the embodiments, when the controllable constant voltage current clamping circuit outputs current clamping, the timing control circuit controls the controllable switch tube to be tested to be disconnected through the driving circuit within a preset delay time.

[0015] In one embodiment, the controllable constant voltage current clamp circuit comprises:

[0016] A power amplifier circuit, wherein a first end of the power amplifier circuit is used to be electrically connected to a second end of the controllable switch tube to be tested;

[0017] a current measuring circuit, wherein a first end of the current measuring circuit is electrically connected to a second end of the power amplifier circuit and is used to measure an output current of the power amplifier circuit to obtain a first current;

[0018] a clamping circuit, wherein a first end of the clamping circuit is electrically connected to a second end of the current measuring circuit, and a second end of the clamping circuit is electrically connected to the timing control circuit;

[0019] a pressure measuring circuit, wherein a first end of the pressure measuring circuit and a third end of the current measuring circuit are commonly connected to a second end of the inductor, a second end of the pressure measuring circuit is electrically connected to a first end of the power amplifier circuit, a third end of the pressure measuring circuit is electrically connected to the timing control circuit, and a fourth end of the pressure measuring circuit is electrically connected to a third end of the clamping circuit, and is used to measure an output voltage of the power amplifier circuit to obtain a first voltage, and compare the first voltage with a set voltage to obtain a comparison result; and

[0020] an integrating circuit, wherein a first end of the integrating circuit is electrically connected to a fourth end of the clamping circuit, a second end of the integrating circuit is electrically connected to a third end of the power amplifier circuit, and a third end of the integrating circuit is electrically connected to a fifth end of the voltage measuring circuit;

[0021] The clamp circuit is used to determine whether to output a clamp instruction according to the first current, the set constant voltage clamp value and the comparison result. If the clamp circuit outputs a clamp instruction, the integration circuit is used to control the constant voltage clamp current output of the power amplifier circuit based on the clamp instruction and the comparison result.

[0022] In one embodiment,

[0023] The clamping circuit is used to determine whether to output a clamping instruction according to the first current, the set constant voltage clamping value and the comparison result, including:

[0024] The clamping circuit is used to sum the voltage value corresponding to the first current, the voltage value corresponding to the set constant voltage clamping value and the comparison result to obtain a second voltage;

[0025] If the second voltage exceeds a preset reference voltage, the clamping circuit outputs the clamping instruction;

[0026] If the second voltage does not exceed the preset reference voltage, the clamping circuit does not output the clamping instruction.

[0027] In one embodiment, if the clamp circuit does not output the clamp instruction, the integration circuit controls the power amplifier circuit to output a constant voltage based on the comparison result.

[0028] In one embodiment, the clamp circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a first operational amplifier, a first diode, and a second diode;

[0029] The first end of the first resistor is electrically connected to the timing control circuit, the second end of the first resistor, the first end of the second resistor, the first end of the third resistor, the first end of the fourth resistor, the anode of the first diode and the first end of the first operational amplifier are commonly connected, the second end of the second resistor is electrically connected to the second end of the current measuring circuit, the second end of the third resistor is electrically connected to the fourth end of the voltage measuring circuit, the second end of the first operational amplifier is grounded, the output end of the first operational amplifier, the cathode of the first diode and the anode of the second diode are commonly connected, and the cathode of the second diode and the second end of the fourth resistor are electrically connected to the first end of the integration circuit.

[0030] In one embodiment, the voltage measuring circuit includes: a first voltage follower, a second voltage follower, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor and a third operational amplifier;

[0031] The first end of the first voltage follower is electrically connected to the second end of the inductor, the second end of the first voltage follower and the output end of the first voltage follower are commonly connected to the first end of the fifth resistor, and the second end of the fifth resistor, the first end of the second operational amplifier, and the first end of the sixth resistor are commonly connected;

[0032] The first end of the second voltage follower is electrically connected to the first end of the power amplifier circuit, the second end of the second voltage follower and the output end of the second voltage follower are electrically connected to the first end of the seventh resistor, and the second end of the seventh resistor and the second end of the second operational amplifier are grounded through the eighth resistor;

[0033] The output end of the second operational amplifier is connected to the second end of the sixth resistor and the first end of the ninth resistor, the first end of the tenth resistor is electrically connected to the timing control circuit, the second end of the ninth resistor, the second end of the tenth resistor, the first end of the eleventh resistor and the first end of the third operational amplifier are connected to each other, the second end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the eleventh resistor are electrically connected to the third end of the clamping circuit.

[0034] In one embodiment, the integration circuit includes: a fifth resistor, a sixth resistor, a second operational amplifier and a capacitor;

[0035] The first end of the fifth resistor is electrically connected to the fourth end of the clamping circuit, the first end of the sixth resistor is electrically connected to the fifth end of the voltage measuring circuit, the second end of the fifth resistor, the second end of the sixth resistor, the first end of the second operational amplifier and the first end of the capacitor are connected in common, the second end of the second operational amplifier is grounded, and the output end of the second operational amplifier and the second end of the capacitor are electrically connected to the third end of the power amplifier circuit.

[0036] In one embodiment, the UIS test circuit further includes:

[0037] A voltage measurement circuit, wherein the first end of the voltage measurement circuit is used to be electrically connected to the first end of the controllable switch tube to be tested, the second end of the voltage measurement circuit is used to be electrically connected to the second end of the controllable switch tube to be tested, and the output end of the voltage measurement circuit is electrically connected to the timing control circuit, and is used to measure the avalanche voltage between the first end and the second end of the controllable switch tube to be tested.

[0038] In one embodiment, the UIS test circuit further includes:

[0039] A time measurement circuit, wherein the first end of the time measurement circuit is electrically connected to the first end of the controllable switch tube to be tested, and the second end of the time measurement circuit is electrically connected to the timing control circuit, and is used to measure the avalanche time of the controllable switch tube to be tested.

[0040] Compared with the prior art, in the above-mentioned UIS test circuit, the timing control circuit controls the on and off of the controllable switch tube to be tested through the driving circuit, and cooperates with the inductor and the controllable constant voltage current clamp circuit. When the controllable switch tube to be tested is turned on, the controllable constant voltage current clamp circuit determines whether to output a constant voltage current clamp based on a set constant voltage clamp value, thereby preventing the current flowing through the controllable switch tube to be tested from continuing to increase and causing a false triggering of protection, thereby reducing the delayed response speed of the shutdown control of the controllable switch tube to be tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1 A circuit principle block diagram of a UIS test circuit provided in one embodiment of the present application;

[0043] Figure 2 A circuit diagram of a driving circuit provided in an embodiment of the present application;

[0044] Figure 3 A logic schematic diagram of a UIS test circuit provided in an embodiment of the present application;

[0045] Figure 4 A logic schematic diagram of a UIS test circuit provided by another embodiment of the present application;

[0046] Figure 5 A circuit principle block diagram of a controllable constant voltage current clamp circuit provided in an embodiment of the present application;

[0047] Figure 6 A circuit diagram of a current measuring circuit provided in an embodiment of the present application;

[0048] Figure 7 A circuit diagram of a clamping circuit provided in an embodiment of the present application;

[0049] Figure 8A circuit diagram of a clamping circuit provided in another embodiment of the present application;

[0050] Fig. 9 A circuit diagram of a pressure measuring circuit provided in an embodiment of the present application;

[0051] Fig.10 A circuit diagram of an integration circuit provided in an embodiment of the present application;

[0052] Fig.11 A circuit block diagram of a UIS test circuit provided in another embodiment of the present application;

[0053] Fig.12 A circuit diagram of a voltage measurement circuit provided in an embodiment of the present application;

[0054] Fig.13 A circuit diagram of a time measurement circuit provided by an embodiment of the present application;

[0055] Fig.14 A test timing diagram of a time measurement circuit provided in one embodiment of the present application.

[0056] Description of reference numerals:

[0057] 10UIS test circuit

[0058] 100 Inductor

[0059] 110 Controllable switch tube to be tested

[0060] 200 controllable constant voltage current clamp circuit

[0061] 210 power amplifier circuit

[0062] 220 current measuring circuit

[0063] 230 clamp circuit

[0064] 231 First resistor

[0065] 232 Second resistor

[0066] 233 The third resistor

[0067] 234 Fourth resistor

[0068] 235 First Operational Amplifier

[0069] 236 First Diode

[0070] 237 Second diode

[0071] 240 pressure measuring circuit

[0072] 250 Integrator Circuit

[0073] 251 Fifth resistor

[0074] 252 Sixth resistor

[0075] 253 Second operational amplifier

[0076] 254 capacitor

[0077] 300 drive circuit

[0078] 400 timing control circuit

[0079] 500 Voltage Measurement Circuit

[0080] 600 time measurement circuit DETAILED DESCRIPTION

[0081] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific implementation disclosed below.

[0082] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0084] See also Figure 1 In one embodiment of the present application, a UIS test circuit 10 is provided, comprising: an inductor 100, a controllable constant voltage current clamp circuit 200, a drive circuit 300 and a timing control circuit 400. The first end of the inductor 100 is used to electrically connect to the first end of the controllable switch tube 110 to be tested. The first end of the controllable constant voltage current clamp circuit 200 is electrically connected to the second end of the inductor 100. The first end of the drive circuit 300 is used to electrically connect to the control end of the controllable switch tube 110 to be tested. The second end of the drive circuit 300 and the second end of the controllable constant voltage current clamp circuit 200 are both used to be connected in common with the second end of the controllable switch tube 110 to be tested.

[0085] The timing control circuit 400 is electrically connected to the third end of the driving circuit 300 and the third end of the controllable constant voltage clamp current source 200 respectively. The timing control circuit 400 is used to control the on and off of the controllable switch tube 110 to be tested through the driving circuit 300. When the controllable switch tube 110 to be tested is turned on, the controllable constant voltage clamp current circuit 200 determines whether to output constant voltage clamp current based on the set constant voltage clamp value.

[0086] In one embodiment, the controllable switch tube 110 to be tested may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The controllable switch tube 110 to be tested may also be an IGBT (Insulated Gate Bipolar Transistor). The controllable switch tube 110 to be tested may also be a triode, etc.

[0087] It can be understood that the specific circuit topology of the controllable constant voltage current clamp circuit 200 is not limited, as long as it has the function of determining whether to output constant voltage current clamp based on the set constant voltage clamp value. In one embodiment, the controllable constant voltage current clamp circuit 200 may be composed of a current sensor, a power amplifier, a clamp device, a voltage sensor, a comparison device, and an integral summing circuit. In one embodiment, the controllable constant voltage current clamp circuit 200 may also be a controllable integrated chip with constant voltage output and constant voltage current clamp output functions.

[0088] It can be understood that the specific circuit topology of the driving circuit 300 is not limited, as long as it has the function of driving the controllable switch tube 110 to be tested to be turned on and off. In one embodiment, the driving circuit 300 can be a switch tube driver. In one embodiment, the driving circuit 300 can also be a Figure 2 The circuit topology shown. Specifically, the driving circuit 300 may include an optocoupler device U71 and transistors Q71 and Q72. The timing control circuit 400 may output a control signal (Vgs_trig) to control the on or off state of the optocoupler device U71, thereby driving the transistor Q71 or Q72 to be in the on state, and finally realizing the on or off control of the controllable switch tube 110 device to be tested.

[0089] It can be understood that the specific circuit topology of the timing control circuit 400 is not limited, as long as it has the function of controlling the on and off of the controllable switch tube 110 to be tested through the driving circuit 300. In one embodiment, the timing control circuit 400 can be an FPGA (Field Programmable Gate Array) chip. The timing control circuit 400 can also be a single-chip microcomputer.

[0090] In one embodiment, the controllable constant voltage current clamp circuit 200 determines whether to output constant voltage current clamp based on the set constant voltage clamp value, which means that the controllable constant voltage current clamp circuit 200 can compare the set constant voltage clamp value with the output current of the controllable constant voltage current clamp circuit 200. If the output current of the controllable constant voltage current clamp circuit 200 exceeds the range of the set constant voltage clamp value, then the controllable constant voltage current clamp circuit 200 outputs current clamp at this time. If the output voltage of the controllable constant voltage current clamp circuit 200 does not exceed the range of the set constant voltage clamp value, then the controllable constant voltage current clamp circuit 200 outputs constant voltage at this time.

[0091] Specifically, Figure 3 As shown, when the timing control circuit 400 controls the controllable switch tube 110 to be tested (i.e., DUT) to be turned on through the driving circuit 300, that is, when the driving circuit 300 outputs a Vgs driving signal to drive the DUT to be turned on, a closed loop is formed between the inductor 100, the controllable constant voltage current clamp circuit 200, and the controllable switch tube 110 to be tested, that is, the charging loop of the inductor 100 is formed. At this time, the current Id flowing through the DUT starts to rise from zero, that is, the output current of the controllable constant voltage current clamp circuit 200 starts to rise from zero. When the output current of the controllable constant voltage current clamp circuit 200 reaches the set constant voltage clamp value (i.e., PeakI), the controllable constant voltage current clamp circuit 200 clamps the current output. That is, at point B4, the output current of the controllable constant voltage current clamp circuit 200 is clamped and controlled at the set constant voltage clamp value. After GateV arrives at point C4, the timing control circuit controls the Vgs output by the driving circuit 300 to drive the DUT to turn off quickly; that is, the timing control circuit 400 controls the DUT to turn off through the driving circuit 300 within the preset delay time, and at this time, the charging circuit of the inductor 100 is disconnected. The preset delay time is the time from B4 to C4.

[0092] After the DUT is turned off, the avalanche process is established, and the inductor 100 discharges to form a breakdown voltage Vds that breaks down the DUT. At this time, Id drops to zero after T42 time, and the avalanche ends. At the same time, the breakdown voltage Vds falls back to the Vdd voltage (that is, Vds is equal to Vdd). At point E4, the controllable constant voltage current clamp circuit 200 is restored, and the Vds voltage gradually returns to zero. Figure 3 In the process from point B4 to point C4, due to the current clamping control of the controllable constant voltage current clamping circuit 200, Id will not continue to increase, thereby avoiding the phenomenon of false triggering of protection, thereby reducing the delayed response speed of the DUT shutdown control.

[0093] like Figure 4As shown, after the DUT is broken down and short-circuited during the avalanche process, at point D5, Id rises again, and when it reaches the set constant voltage clamp value PeakI again, the output current of the controllable constant voltage clamp circuit 200 is still clamped and controlled at the set constant voltage clamp value. After the constant voltage clamp is restored at point E5, the energy of the inductor 100 is released through the controllable constant voltage clamp circuit 200, so that Id quickly returns to zero. In this way, the reliability of the UIS test can be improved by using the above logic.

[0094] In this embodiment, the timing control circuit 400 controls the on and off of the controllable switch tube 110 to be tested through the driving circuit 300, and cooperates with the inductor 100 and the controllable constant voltage current clamp circuit 200. When the controllable switch tube 110 to be tested is turned on, the controllable constant voltage current clamp circuit 200 determines whether to output a constant voltage current clamp based on a set constant voltage clamp value, thereby preventing the current flowing through the controllable switch tube 110 to be tested from continuing to increase and causing a false triggering of protection, thereby reducing the delayed response speed of the shutdown control of the controllable switch tube 110 to be tested.

[0095] Please attend Figure 5 In one embodiment, the controllable constant voltage current clamp circuit 200 includes: a power amplifier circuit 210, a current measuring circuit 220, a clamp circuit 230, a voltage measuring circuit 240 and an integration circuit 250. The first end of the power amplifier circuit 210 is used to be electrically connected to the second end of the controllable switch tube 110 to be measured. The first end of the current measuring circuit 220 is electrically connected to the second end of the power amplifier circuit 210. The current measuring circuit 220 is used to measure the output current of the power amplifier circuit 210 and obtain a first current. The first end of the clamp circuit 230 is electrically connected to the second end of the current measuring circuit 220. The second end of the clamp circuit 230 is electrically connected to the timing control circuit 400. The first end of the voltage measuring circuit 240 and the third end of the current measuring circuit 220 are connected in common with the second end of the inductor 100. The second end of the voltage measuring circuit 240 is electrically connected to the first end of the power amplifier circuit 210. The third end of the voltage measuring circuit 240 is electrically connected to the timing control circuit 400. The fourth terminal of the voltage measuring circuit 240 is electrically connected to the third terminal of the clamping circuit 230 .

[0096] The voltage measuring circuit 240 is used to measure the output voltage of the power amplifier circuit 210 to obtain a first voltage, and compare the first voltage with a set voltage to obtain a comparison result. The first end of the integration circuit 250 is electrically connected to the fourth end of the clamp circuit 230. The second end of the integration circuit 250 is electrically connected to the third end of the power amplifier circuit 210. The third end of the integration circuit 250 is electrically connected to the fifth end of the voltage measuring circuit 240. The clamp circuit 230 is used to determine whether to output a clamp instruction according to the first current, the set constant voltage clamp value and the comparison result. If the clamp circuit outputs a clamp instruction, the integration circuit 250 is used to control the constant voltage clamp current output of the power amplifier circuit 210 based on the clamp instruction and the comparison result.

[0097] In one embodiment, the specific circuit topology of the power amplifier circuit 210 is not limited, and it can be a power amplifier. It can be understood that the specific circuit topology of the current measuring circuit 220 is not limited, as long as it has the function of measuring the output current of the power amplifier circuit 210 and obtaining the first current. In one embodiment, the circuit topology of the current measuring circuit 220 is as follows: Figure 6 As shown, it specifically includes: a current measuring resistor R21, voltage followers OP21 and OP22, a differential operation circuit OP23, and resistors R22, R23, R24, and R25. The output current of the power amplifier circuit 210 flows in from FL and flows out from FH, so that a voltage drop is generated at both ends of the current measuring resistor R21. Then, the voltage is followed by the voltage followers OP21 and OP22, and then the current signal Imeas (i.e., the first current) is obtained after the differential operation circuit OP23 performs operation. And the current signal Imeas is output to the clamping circuit 230, so that the clamping circuit 230 determines whether to control the current clamping output of the power amplifier circuit 210. In one embodiment, the differential operation circuit OP23 can be a differential operational amplifier.

[0098] In one embodiment, the current measuring circuit 220 may also be disposed between the power amplifier circuit 210 and the controllable switch tube 110 to be measured, as long as the current measuring circuit 220 can measure the output current of the power amplifier circuit 210 and obtain the first current.

[0099] It can be understood that the specific circuit topology of the clamp circuit 230 is not limited, as long as it has the function of determining whether to output a clamp instruction according to the first current, the set constant voltage clamp value and the comparison result. In one embodiment, the clamp circuit 230 may be composed of a plurality of resistors, diodes and operational amplifier circuits. In one embodiment, the clamp circuit 230 may also adopt Figure 7The circuit topology shown specifically includes: a first resistor 231 , a second resistor 232 , a third resistor 233 , a fourth resistor 234 , a first operational amplifier 235 , a first diode 236 , and a second diode 237 .

[0100] Specifically, the first end of the first resistor 231 is electrically connected to the timing control circuit 400. The second end of the first resistor 231, the first end of the second resistor 232, the first end of the third resistor 233, the first end of the fourth resistor 234, the anode of the first diode 236, and the first end of the first operational amplifier 235 are connected in common. The second end of the second resistor 232 is electrically connected to the second end of the current measuring circuit 220. The second end of the third resistor 233 is electrically connected to the fourth end of the voltage measuring circuit 240, and the second end of the first operational amplifier 235 is grounded. The output end of the first operational amplifier 235, the cathode of the first diode 236, and the anode of the second diode 237 are connected in common. The cathode of the second diode 237 and the second end of the fourth resistor 234 are electrically connected to the first end of the integration circuit 250.

[0101] The first operational amplifier 235 can sum the voltage value (Vs+) corresponding to the set constant voltage clamp value output by the timing control circuit 400, the voltage value (Vo) corresponding to the current signal Imeas, and the comparison result Vctrl to obtain a second voltage. Determine whether the clamping condition is met based on the second voltage. Specifically, the second voltage can be compared with a preset reference voltage. If the second voltage exceeds the range of the preset reference voltage, it means that the output current of the power amplifier circuit 210 exceeds the range of the set constant voltage clamp value. At this time, the clamping condition is met, and the second diode 237 is forward-conducted and outputs the clamping instruction Iclamp+ to the integration circuit 250. The integration circuit 250 can control the constant voltage clamp current output of the power amplifier circuit 210 based on the clamping instruction Iclamp+ and the comparison result.

[0102] If the second voltage does not exceed the range of the preset reference voltage, it means that the output current of the power amplifier circuit 210 does not exceed the range of the set constant voltage clamp value, and the clamping condition is not met at this time, so the second diode 237 is reversely cut off. At this time, the clamping instruction Iclamp+ is not output to the integration circuit 250, and the integration circuit 250 can control the constant voltage output of the power amplifier circuit 210 based on the comparison result.

[0103] In one embodiment, the clamp circuit 230 using the above circuit topology can clamp forward voltage. If a negative voltage is to be clamped, the anode and cathode of the first diode 236 and the second diode 237 in the above circuit topology can be interchanged (for example, Figure 8 shown).

[0104] It can be understood that the specific circuit topology of the pressure measuring circuit 240 is not limited, as long as it has the function of measuring the output voltage of the power amplifier circuit 210 to obtain a first voltage, and comparing the first voltage with a set voltage to obtain a comparison result. In one embodiment, the pressure measuring circuit 240 can be composed of a voltage sensor and a comparator. In one embodiment, the circuit topology of the pressure measuring circuit 240 can also be as follows: Fig. 9 As shown, it specifically includes: voltage followers OP11 and OP12, differential operation circuit OP13, operation circuit OP14 and resistors R11, R12, R13, R14, R15, R16, R17. The voltage follower OP11 follows the voltage signal SH at the second end of the inductor 100, and outputs the followed voltage signal to the differential operation circuit OP13. The voltage follower OP12 follows the voltage signal SL at the first end of the power amplifier circuit 210, and outputs the followed voltage signal to the differential operation circuit OP13.

[0105] The differential operation circuit OP13 performs a differential operation on the two following voltage signals to obtain Vmeas (i.e., the first voltage). In one embodiment, the operation circuit OP14 can compare Vmeas with the set voltage and obtain a comparison result Vctrl. In one embodiment, the operation circuit OP14 can also sum Vmeas with the preset voltage Vse, and compare the summation result with the set voltage to obtain a comparison result Vctrl, and output Vctrl to the clamp circuit 230 and the integration circuit 250 respectively for subsequent calculations. In one embodiment, the comparison result Vctrl is a voltage signal. In one embodiment, the operation circuit OP14 can be a summing operational amplifier. The differential operation circuit OP13 can be a differential operational amplifier.

[0106] In one embodiment, the voltage measuring circuit 240 compares the first voltage with the set voltage to obtain a comparison result, which means that the voltage measuring circuit 240 can compare the first voltage with the set voltage, and if the first voltage is not equal to the set voltage, the integration circuit 250 can adjust the output voltage of the power amplifier circuit 210 based on the comparison result to achieve constant voltage output. If the first voltage is equal to the set voltage, the integration circuit 250 does not adjust the output voltage of the power amplifier circuit 210.

[0107] It can be understood that the specific circuit topology of the integration circuit 250 is not limited, as long as it has the function of controlling the constant voltage clamp current output of the power amplifier circuit based on the clamp instruction and the comparison result. In one embodiment, the integration circuit 250 can be composed of an operational amplifier and a capacitor. In one embodiment, the circuit topology of the integration circuit 250 can also be as follows: Fig.10 As shown, it specifically includes: a fifth resistor 251, a sixth resistor 252, a second operational amplifier 253 and a capacitor 254. The first end of the fifth resistor 251 is electrically connected to the fourth end of the clamp circuit 230. The first end of the sixth resistor 252 is electrically connected to the fifth end of the voltage measuring circuit 240. The second end of the fifth resistor 251, the second end of the sixth resistor 252, the first end of the second operational amplifier 253 and the first end of the capacitor 254 are commonly connected. The second end of the second operational amplifier 253 is grounded. The output end of the second operational amplifier 253 and the second end of the capacitor 254 are electrically connected to the third end of the power amplifier circuit 210.

[0108] The second operational amplifier 253 cooperates with the fifth resistor 251 and the sixth resistor 252 to sum the clamping instruction output by the clamping circuit 230 and the comparison result, and then cooperates with the capacitor 254 to perform an integral operation, thereby controlling the constant voltage clamping current output of the power amplifier circuit 210 based on the operation result. When the clamping circuit 230 can clamp both the positive voltage and the negative voltage, the integral circuit 250 may further include a seventh resistor R42. That is, the negative clamping instruction Iclamp- output by the clamping circuit 230 is input to the second operational amplifier 253 through the seventh resistor R42.

[0109] Please attend Fig.11 In one embodiment, the UIS test circuit 10 further includes: a voltage measurement circuit 500. The first end of the voltage measurement circuit 500 is used to be electrically connected to the first end of the controllable switch tube 110 to be tested. The second end of the voltage measurement circuit 500 is used to be electrically connected to the second end of the controllable switch tube 110 to be tested. The output end of the voltage measurement circuit 500 is electrically connected to the timing control circuit 400. The voltage measurement circuit 500 is used to measure the avalanche voltage between the first end and the second end of the controllable switch tube 110 to be tested.

[0110] It can be understood that the specific circuit structure of the voltage measurement circuit 500 is not limited, as long as it has the function of measuring the avalanche voltage between the first end and the second end of the controllable switch tube 110 to be measured. In one embodiment, the voltage measurement circuit 500 can be a traditional circuit with a voltage measurement function, such as an RC circuit. In one embodiment, the circuit topology of the voltage measurement circuit 500 can also be as follows: Fig.12As shown, it specifically includes: voltage followers OP51 and OP52, differential operation circuit OP53 and resistors R51, R52, R53 and R54. The voltage followers OP51 and OP52 follow and measure Vdrain (i.e., the first terminal voltage of the controllable switch tube 110 to be tested) and Vsource (i.e., the second terminal voltage of the controllable switch tube 110 to be tested) to perform differential operation through the differential operation circuit OP53, and output a Vds signal to the timing control circuit 400.

[0111] In one embodiment, the UIS test circuit 10 further includes: a time measurement circuit 600. A first end of the time measurement circuit 600 is used to be electrically connected to a first end of the controllable switch tube 110 to be tested. A second end of the time measurement circuit 600 is used to be electrically connected to a second end of the controllable switch tube 110 to be tested and the timing control circuit 400. The time measurement circuit 600 is used to measure the avalanche time of the controllable switch tube 110 to be tested.

[0112] In one embodiment, the specific circuit topology of the time measurement circuit 600 is as follows: Fig.13 As shown, it specifically includes: two comparators OP61 and OP62. The comparators OP61 and OP62 compare the tested signal Vdrain with V_trig+ and V_trig-, and the obtained level signal is sent to the timing control circuit 400 for timing, so that the pulse width of Vds (ie, avalanche time) can be measured.

[0113] In one embodiment, if the controllable switch tube 110 to be tested is NMOS, the time measurement circuit 600 cooperates with the timing control circuit 400 to obtain the following: Fig.14 The test timing diagram shown in FIG. 1 shows a timing diagram of the test. In which, by setting the V_trig+ value to be greater than Vd and less than Vds, the T_trig+ waveform can be obtained.

[0114] In summary, the present application adopts the timing control circuit 400 to control the on and off of the controllable switch tube 110 to be tested through the driving circuit 300, and cooperates with the inductor 100 and the controllable constant voltage current clamp circuit 200. When the controllable switch tube 110 to be tested is turned on, the controllable constant voltage current clamp circuit 200 determines whether to output a constant voltage current clamp based on the set constant voltage clamp value, thereby preventing the current flowing through the controllable switch tube 110 to be tested from continuing to increase, resulting in the phenomenon of false triggering of protection, thereby reducing the delayed response speed of the shutdown control of the controllable switch tube 110 to be tested.

[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A UIS test circuit, characterized in that: The invention comprises an inductor (100), a controllable constant voltage current clamp circuit (200), a driving circuit (300) and a timing control circuit (400), wherein the controllable constant voltage current clamp circuit (200) comprises a power amplifier circuit (210), a current measuring circuit (220), a clamp circuit (230), a voltage measuring circuit (240) and an integration circuit (250), wherein: The first end of the inductor (100) is used to electrically connect to the first end of the controllable switch tube (110) to be tested; The first end of the power amplifier circuit (210) is used to be electrically connected to the second end of the controllable switch tube (110) to be tested; The first end of the current measuring circuit (220) is electrically connected to the second end of the power amplifier circuit (210) and is used to measure the output current of the power amplifier circuit (210) to obtain a first current; The first end of the clamp circuit (230) is electrically connected to the second end of the current measuring circuit (220), and the second end of the clamp circuit (230) is electrically connected to the timing control circuit (400); The first end of the voltage measuring circuit (240) and the third end of the current measuring circuit (220) are connected to the second end of the inductor (100); the second end of the voltage measuring circuit (240) is electrically connected to the first end of the power amplifier circuit (210); the third end of the voltage measuring circuit (240) is electrically connected to the timing control circuit (400); and the fourth end of the voltage measuring circuit (240) is electrically connected to the third end of the clamping circuit (230), for measuring the output voltage of the power amplifier circuit (210) to obtain a first voltage, and comparing the first voltage with a set voltage to obtain a comparison result; and The first end of the integration circuit (250) is electrically connected to the fourth end of the clamping circuit (230), the second end of the integration circuit (250) is electrically connected to the third end of the power amplifier circuit (210), and the third end of the integration circuit (250) is electrically connected to the fifth end of the voltage measuring circuit (240); The clamp circuit (230) is used to determine whether to output a clamp instruction according to the first current, a set constant voltage clamp value and the comparison result; if the clamp circuit (230) outputs a clamp instruction, the integration circuit (250) is used to control the constant voltage clamp current output of the power amplifier circuit (210) based on the clamp instruction and the comparison result; The first end of the driving circuit (300) is used to be electrically connected to the control end of the controllable switch tube (110) to be tested, and the second end of the driving circuit (300) and the second end of the controllable constant voltage current clamp circuit (200) are both used to be commonly connected to the second end of the controllable switch tube (110) to be tested; and The timing control circuit (400) is electrically connected to the third end of the driving circuit (300) and the third end of the controllable constant voltage current clamp circuit (200) respectively, and is used to control the on and off of the controllable switch tube (110) to be tested through the driving circuit (300); When the controllable switch tube (110) to be tested is turned on, the controllable constant voltage current clamping circuit (200) determines whether to output a constant voltage current clamping based on the set constant voltage clamping value.

2. The UIS test circuit according to claim 1, characterized in that: The controllable constant voltage current clamp circuit (200) is used to compare the set constant voltage clamp value with the output current of the controllable constant voltage current clamp circuit (200); If the output current of the controllable constant voltage current clamping circuit (200) exceeds the set constant voltage clamping value, the controllable constant voltage current clamping circuit (200) clamps the current output; If the output current of the controllable constant voltage current clamp circuit (200) does not exceed the set constant voltage clamp value, the controllable constant voltage current clamp circuit (200) outputs a constant voltage.

3. The UIS test circuit as claimed in claim 2, characterized in that: When the controllable constant voltage current clamping circuit (200) outputs current clamping, the timing control circuit (400) controls the controllable switch tube (110) to be tested to be disconnected through the driving circuit (300) within a preset delay time.

4. The UIS test circuit according to claim 1, characterized in that: The clamp circuit (230) is used to determine whether to output a clamp instruction according to the first current, the set constant voltage clamp value and the comparison result, comprising: The clamping circuit (230) is used to sum the voltage value corresponding to the first current, the voltage value corresponding to the set constant voltage clamping value and the comparison result to obtain a second voltage; If the second voltage exceeds a preset reference voltage, the clamping circuit (230) outputs the clamping instruction; If the second voltage does not exceed the preset reference voltage, the clamping circuit (230) does not output the clamping instruction.

5. The UIS test circuit as claimed in claim 4, characterized in that: If the clamp circuit (230) does not output the clamp instruction, the integration circuit (250) controls the power amplifier circuit (210) to output a constant voltage based on the comparison result.

6. The UIS test circuit according to claim 1, characterized in that: The clamping circuit (230) comprises: a first resistor (231), a second resistor (232), a third resistor (233), a fourth resistor (234), a first operational amplifier (235), a first diode (236) and a second diode (237); The first end of the first resistor (231) is electrically connected to the timing control circuit (400); the second end of the first resistor (231), the first end of the second resistor (232), the first end of the third resistor (233), the first end of the fourth resistor (234), the anode of the first diode (236) and the first end of the first operational amplifier (235) are connected in common; the second end of the second resistor (232) is electrically connected to the second end of the current measuring circuit (220); the second end of the third resistor (233) is electrically connected to the fourth end of the voltage measuring circuit (240); the second end of the first operational amplifier (235) is grounded; the output end of the first operational amplifier (235), the cathode of the first diode (236) and the anode of the second diode (237) are connected in common; the cathode of the second diode (237) and the second end of the fourth resistor (234) are electrically connected to the first end of the integration circuit (250).

7. The UIS test circuit according to claim 1, characterized in that: The integration circuit (250) comprises: a fifth resistor (251), a sixth resistor (252), a second operational amplifier (253) and a capacitor (254); The first end of the fifth resistor (251) is electrically connected to the fourth end of the clamp circuit (230), the first end of the sixth resistor (252) is electrically connected to the fifth end of the voltage measuring circuit (240), the second end of the fifth resistor (251), the second end of the sixth resistor (252), the first end of the second operational amplifier (253) and the first end of the capacitor (254) are connected in common, the second end of the second operational amplifier (253) is grounded, and the output end of the second operational amplifier (253) and the second end of the capacitor (254) are electrically connected to the third end of the power amplifier circuit (210).

8. The UIS test circuit according to claim 1, characterized in that: The voltage measuring circuit comprises: a first voltage follower, a second voltage follower, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a second operational amplifier, a ninth resistor, a tenth resistor, an eleventh resistor and a third operational amplifier; The first end of the first voltage follower is electrically connected to the second end of the inductor, the second end of the first voltage follower and the output end of the first voltage follower are connected to the first end of the fifth resistor, and the second end of the fifth resistor, the first end of the second operational amplifier, and the first end of the sixth resistor are connected to each other; the first end of the second voltage follower is electrically connected to the first end of the power amplifier circuit, the second end of the second voltage follower and the output end of the second voltage follower are electrically connected to the first end of the seventh resistor, and the second end of the seventh resistor and the second end of the second operational amplifier are grounded through the eighth resistor; the output end of the second operational amplifier is connected to the second end of the sixth resistor and the first end of the ninth resistor, the first end of the tenth resistor is electrically connected to the timing control circuit, the second end of the ninth resistor, the second end of the tenth resistor, the first end of the eleventh resistor, and the first end of the third operational amplifier are connected to each other, the second end of the third operational amplifier is grounded, and the output end of the third operational amplifier and the second end of the eleventh resistor are electrically connected to the third end of the clamping circuit.

9. The UIS test circuit according to any one of claims 1 to 8, characterized in that: Also includes: A voltage measurement circuit (500), wherein a first end of the voltage measurement circuit (500) is used to be electrically connected to a first end of the controllable switch tube (110) to be tested, a second end of the voltage measurement circuit (500) is used to be electrically connected to a second end of the controllable switch tube (110) to be tested, and an output end of the voltage measurement circuit (500) is electrically connected to the timing control circuit (400) for measuring an avalanche voltage between the first end and the second end of the controllable switch tube (110) to be tested.

10. The UIS test circuit according to any one of claims 1 to 8, characterized in that: Also includes: A time measurement circuit (600), wherein a first end of the time measurement circuit (600) is electrically connected to a first end of the controllable switch tube (110) to be tested, and a second end of the time measurement circuit (600) is electrically connected to the timing control circuit (400) to measure the avalanche time of the controllable switch tube (110) to be tested.

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