Electronic panel and electronic device including the same

Abstract

An electronic panel and an electronic device are provided. The electronic panel includes a display unit and an input sensing unit, wherein: the display unit includes a plurality of pixels, an encapsulation layer covering the pixels, and a planarization layer disposed on the encapsulation layer, the display unit including, in a plan view, an active area displaying an image and a peripheral area adjacent to the active area; the input sensing unit is disposed on the display unit and is configured to detect an external input. An upper surface of the encapsulation layer includes a planar surface and a non-planar surface, wherein the planar surface is disposed in the active area, and the non-planar surface is disposed in the peripheral area and is curved compared to the planar surface. The planarization layer covers the non-planar surface. The input sensing unit is disposed above the planar surface and is disposed above the non-planar surface.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0014485, filed with the Korean Intellectual Property Office on February 7, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to an electronic panel and an electronic device including the electronic panel, and more specifically, to an electronic panel including a reliable display unit and an input sensing unit and an electronic device including the electronic panel. Background Technology

[0004] An electronic device activated in response to an electrical signal may include sub-devices composed of various electronic components, such as a display unit for displaying an image or an input sensing unit for detecting external input. The electronic components may be electrically interconnected via signal lines arranged in various configurations.

[0005] The display unit includes light-emitting elements for generating images. The input sensing unit may include sensing electrodes for detecting external inputs. When the display unit and the input sensing unit are included in different panels, the electronic device may have increased thickness and increased manufacturing costs. On the other hand, when the display unit and the input sensing unit are integrated in a single base substrate, interference may occur between the various electronic components in the display unit and / or the input sensing unit. Summary of the Invention

[0006] The present invention provides an electronic device and a method for manufacturing the electronic device, which can enhance the integration of the display unit and the input sensing unit and improve reliability.

[0007] An exemplary embodiment of the present invention provides an electronic panel including a display unit and an input sensing unit, wherein: the display unit includes a plurality of pixels, an encapsulation layer covering the pixels, and a planarization layer disposed on the encapsulation layer, the display unit including, in a planar view, an effective area for displaying an image and a peripheral area adjacent to the effective area; the input sensing unit is disposed on the display unit and configured to detect external input, wherein the upper surface of the encapsulation layer includes a flat surface and a non-flat surface, the flat surface being disposed in the effective area, the non-flat surface being disposed in the peripheral area and being curved compared to the flat surface, wherein the planarization layer covers the non-flat surface, and the input sensing unit is disposed above the flat surface and above the non-flat surface.

[0008] In an exemplary embodiment of the present invention, the upper surface of the planarization layer may be parallel to the planar surface.

[0009] In an exemplary embodiment of the present invention, at least a portion of the planarization layer may cover a flat surface.

[0010] In an exemplary embodiment of the present invention, the planarization layer can completely cover the flat surface.

[0011] In an exemplary embodiment of the present invention, the upper surface of the planarization layer may define a plane that is substantially the same as the plane of the planar surface.

[0012] In an exemplary embodiment of the present invention, the encapsulation layer may include a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer, wherein the non-planar surface may not overlap with the organic layer in a planar view.

[0013] In an exemplary embodiment of the present invention, the display unit may further include a dam portion disposed in the peripheral region and not overlapping with the organic layer in the plan view, wherein the planarization layer may be configured to overlap with the dam portion in the plan view.

[0014] In an exemplary embodiment of the present invention, the input sensing unit may include a plurality of sensing electrodes disposed in an effective area and a plurality of detection lines connected to the sensing electrodes, wherein the detection lines may be disposed on a planarization layer and may be configured to overlap with a non-planar surface in a planar view.

[0015] In an exemplary embodiment of the present invention, an electronic device includes an electronic panel and an electronic module, wherein: the electronic panel is configured to display an image and detect external input; the electronic module overlaps with the electronic panel in a planar view, wherein the electronic panel includes a base substrate, a plurality of pixels, an encapsulation layer, a planarization layer, and an input sensing unit, wherein the base substrate includes an effective region and a peripheral region adjacent to the effective region, the plurality of pixels are disposed on the base substrate and configured to display an image in the effective region, the encapsulation layer includes an upper surface, the upper surface including a flat surface and a first non-flat surface, wherein the flat surface is defined in the effective region and overlaps with the pixels in the planar view, the first non-flat surface is defined in the peripheral region and is curved compared to the flat surface, the planarization layer is disposed on the first non-flat surface, and the input sensing unit is disposed on the encapsulation layer and the planarization layer and includes a plurality of sensing electrodes and a plurality of detection lines connected to the sensing electrodes.

[0016] In an exemplary embodiment of the present invention, a hole region may be defined in the region of the effective area that overlaps with the electronic module, wherein at least some of the pixels located in the hole region may be removed.

[0017] In an exemplary embodiment of the present invention, at least some of the sensing electrodes located in the hole region can be removed.

[0018] In an exemplary embodiment of the present invention, the encapsulation layer may further include a second non-planar surface overlapping the hole region, wherein the electronic panel may further include a hole planarization layer disposed on the second non-planar surface overlapping the hole region.

[0019] In an exemplary embodiment of the present invention, each of the sensing electrodes may include a plurality of detection patterns and a plurality of connection patterns, wherein the plurality of connection patterns are each disposed between the detection patterns and connect two adjacent detection patterns, wherein at least some of the detection patterns and connection patterns may be disposed on a hole planarization layer to overlap with a second non-planar surface that overlaps with the hole region in a planar view.

[0020] In an exemplary embodiment of the present invention, the electronic panel may further include a panel hole defined in the hole region and extending through the electronic panel, wherein the electronic module may be configured to overlap with the panel hole.

[0021] In an exemplary embodiment of the present invention, the connecting pattern disposed in the hole area can extend along the edge of the panel hole.

[0022] In an exemplary embodiment of the present invention, the electronic panel may further include a dam portion disposed in the peripheral region, wherein the planarization layer may overlap with the dam portion in a plan view.

[0023] In an exemplary embodiment of the present invention, some of the detection lines may be configured on the planarization layer to overlap with the dam portion in the plan view.

[0024] In an exemplary embodiment of the present invention, the planarization layer may cover at least a portion of the planar surface.

[0025] In an exemplary embodiment of the present invention, the planarization layer can be configured on a flat surface to overlap with the effective area.

[0026] In an exemplary embodiment of the present invention, the upper surface of the planarization layer may define a plane that is substantially the same as the plane of the planar surface.

[0027] In an exemplary embodiment of the present invention, the upper surface of the planarization layer may define a plane parallel to the planar surface.

[0028] In an exemplary embodiment of the present invention, an electronic panel includes a display unit, an encapsulation layer, a planarization layer, and an input sensing unit, wherein: the display unit includes an effective area for displaying an image and a peripheral area adjacent to the effective area; the encapsulation layer is formed in the display unit and includes a first flat surface and a non-flat surface, wherein the first flat surface is disposed in the effective area and extends to a portion of the peripheral area, and the non-flat surface is disposed in the peripheral area; the planarization layer is disposed on the non-flat surface of the encapsulation layer and provides a second flat surface; the input sensing unit is disposed on the first flat surface and the second flat surface and configured to detect external input, wherein the input sensing unit may include a plurality of sensing electrodes and a plurality of detection lines, wherein the plurality of sensing electrodes are disposed in the effective area, and the plurality of detection lines are disposed on the second flat surface, connected to the sensing electrodes, and overlap with the non-flat surface of the encapsulation layer in a planar view.

[0029] In an exemplary embodiment of the present invention, the input sensing unit may further include a detection insulating layer that covers a first flat surface and a second flat surface. Attached Figure Description

[0030] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0031] Figure 1A This is an assembled perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention;

[0032] Figure 1B This is an exploded perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention;

[0033] Figure 2A and Figure 2B yes Figure 1B A 3D view of some of the configurations shown;

[0034] Figure 2C This is an exploded perspective view of an electronic panel according to an exemplary embodiment of the concept of the present invention;

[0035] Figure 3A It is along Figure 2A The sectional view shown is taken by line I-I'.

[0036] Figure 3B and Figure 3C This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the present invention, and for ease of explanation, it is shown in conjunction with... Figure 3A The corresponding area;

[0037] Figures 4A to 4C This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the concept of the present invention;

[0038] Figures 5A to 5C This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the concept of the present invention;

[0039] Figure 6A This is an assembled perspective view of an electronic device according to an exemplary embodiment of the concept of the present invention;

[0040] Figure 6B yes Figure 6A An exploded perspective view of the electronic device shown;

[0041] Figure 6C This is a block diagram of an electronic device according to an exemplary embodiment of the present invention;

[0042] Figure 7A This is a plan view of a display unit according to an exemplary embodiment of the concept of the present invention;

[0043] Figure 7B It is shown Figure 7A A magnified plan view of a portion of the area;

[0044] Figure 7C This is a plan view of a sensing unit according to an exemplary embodiment of the present invention; and

[0045] Figure 8 This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the present invention.

[0046] because Figures 1A to 8 The accompanying drawings are for illustrative purposes, and therefore the elements in the drawings are not necessarily drawn to scale. For example, some elements may be enlarged or exaggerated for clarity. Detailed Implementation

[0047] In this specification, when a component (or region, layer, part, etc.) is referred to as being “on”, “connected to”, or “combined to” another component, it means that the component may be directly on, directly connected to, or directly combined to the other component, or that a third component may be present between the component and the other component.

[0048] The same reference numerals denote the same elements.

[0049] As used herein, the term “and / or” includes any and all combinations of one or more of the related listed components.

[0050] It will be understood that the terms “first,” “second,” “third,” etc., are used herein to describe various components, but these components should not be limited by these terms. The terms above are used only to distinguish one component from another. For example, without departing from the teachings of the inventive concept, a first component may be referred to as a second component, and vice versa, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0051] Additionally, terms such as “below,” “lower side,” “upper,” and “upper side” are used to describe the relationships of the configurations shown in the accompanying drawings. These terms are described as relative concepts based on the orientations shown in the drawings, and it will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings.

[0052] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. Furthermore, terms, such as those defined in common dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an ideal or overly formal sense unless expressly defined in this specification.

[0053] In various exemplary embodiments of the present invention, the terms "comprising," "including," "comprising," or "containing" specify properties, areas, fixed quantities, steps, processes, elements, and / or components, but do not exclude other properties, areas, fixed quantities, steps, processes, elements, and / or components.

[0054] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0055] Figure 1A This is an assembled perspective view of an electronic device according to an exemplary embodiment of the present invention. Figure 1B This is an exploded perspective view of an electronic device according to an exemplary embodiment of the present invention. Figure 2A and Figure 2B yes Figure 1B A 3D view of some of the configurations shown. Figure 2C This is an exploded perspective view of an electronic panel according to an exemplary embodiment of the present invention. In the following, reference will be made to... Figures 1A to 2C The concept of the present invention will be described.

[0056] like Figure 1AAs shown, the electronic device EA can display an image IM on its front surface FS. The front surface FS can be parallel to the plane defined by a first direction DR1 and a second direction DR2. The front surface FS includes a transmissive region TA and a border region BZA adjacent to the transmissive region TA.

[0057] Electronic device EA displays image IM in transmission region TA. Image IM may include at least one of still image and moving image. Figure 1A The image IM example shows an internet search window.

[0058] The transmission region TA can be rectangular in shape, having a short side parallel to the first direction DR1 and a long side parallel to the second direction DR2, respectively. However, this is illustrated by way of example, and the transmission region TA can have various shapes and is not limited to any one exemplary embodiment. For example, in various exemplary embodiments of the inventive concept, the transmission region TA can be configured as a polygonal shape, a circular shape, an elliptical shape, or a shape corresponding to a portion of these shapes.

[0059] The border region BZA is adjacent to the transmission region TA and may surround the transmission region TA. However, this is illustrated illustratively, and the border region BZA may be configured to be adjacent only to one side of the transmission region TA, or it may be omitted. Electronic devices according to exemplary embodiments of the present invention may include various exemplary embodiments and are not limited to any one of them.

[0060] The normal direction of the front surface FS can correspond to the thickness direction DR3 of the electronic device EA (hereinafter referred to as the third direction). In this exemplary embodiment, the front (or upper) surface and rear (or lower) surface of each component are defined with reference to the direction of the displayed image IM. The front and rear surfaces are opposite to each other in the third direction DR3.

[0061] The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 can be converted into other directions as relative concepts. In the following text, the first direction to the third direction are referred to by the same reference numerals as the corresponding directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3.

[0062] The electronic device EA according to the present invention can detect user input TC (hereinafter referred to as external input) applied from the outside. User input TC includes various types of external input, such as a part of the user's body, light, heat, sound, or pressure. In addition, the electronic device EA can detect inputs in contact with the electronic device EA, as well as inputs that are close to or near the electronic device EA.

[0063] In this exemplary embodiment, user input TC is shown when the user's hand is applied to the front surface FS. However, this is illustrated by way of example, and as mentioned above, user input TC can be provided in various forms, and furthermore, depending on the structure of the electronic device EA, the electronic device EA can detect user input TC applied to the side surface or rear surface of the electronic device EA, and is not limited to any one exemplary embodiment.

[0064] like Figure 1B As shown, the electronic device EA may include a window 100, an electronic panel 200, a circuit substrate 300, and a housing 400. The window 100 and the housing 400 are combined together to define the appearance of the electronic device EA. For example, the electronic panel 200 and the circuit substrate 300 may be surrounded by the window 100 and the housing 400. In an exemplary embodiment of the inventive concept, the window 100 is coupled to the housing 400 to secure the electronic panel 200 and the circuit substrate 300 in place.

[0065] A window 100 is disposed on the electronic panel 200 to cover the front surface IS of the electronic panel 200, and may comprise an optically transparent insulating material. For example, the window 100 may comprise glass or plastic. The window 100 may have a multilayer or single-layer structure. For example, the window 100 may have a laminated structure of multiple plastic films bonded using an adhesive, or it may have a laminated structure of a glass substrate and plastic films bonded using an adhesive. In the case of a flexible display device, a plastic film with excellent ductility can be used to form the window 100.

[0066] Window 100 includes a front surface FS exposed to the outside. The front surface FS of electronic device EA may be substantially defined by the front surface FS of window 100.

[0067] The transmission region TA can be an optically transparent region and can have a shape corresponding to the effective region AA. For example, the transmission region TA overlaps with the entire surface or at least a portion of the effective region AA. The image IM displayed in the effective region AA of the electronic panel 200 can be viewed from the outside through the transmission region TA.

[0068] Compared to the transmission region TA, the border region BZA can be a region with lower light transmittance. The border region BZA defines the shape of the transmission region TA. The border region BZA is adjacent to the transmission region TA and can surround the transmission region TA.

[0069] The border area BZA can have a predetermined color. When the window 100 is set as a glass substrate or a plastic substrate, the border area BZA can be a color layer printed or deposited on one side of the glass substrate or plastic substrate. Alternatively, the border area BZA can be formed by coloring a corresponding area of ​​the glass substrate or plastic substrate.

[0070] The border region BZA covers the peripheral region NAA of the electronic panel 200 to prevent the peripheral region NAA from being visually identified from the outside. However, this is illustrated by way of example, and the inventive concept is not limited thereto. For example, in a window 100 according to an exemplary embodiment of the inventive concept, the border region BZA may be omitted.

[0071] The electronic panel 200 can display an image IM and detect external input TC. In a plan view, the electronic panel 200 may include a separate active area AA and a peripheral area NAA. The active area AA may be an area activated according to an electrical signal. In this exemplary embodiment, the active area AA is the area for displaying the image IM and simultaneously the area for detecting the external input TC. However, this is illustrative, and the area for displaying the image IM and the area for detecting the external input TC within the active area AA may be separate from each other and are not limited to any one exemplary embodiment. Alternatively, the area for displaying the image IM and the area for detecting the external input TC within the active area AA may partially overlap each other.

[0072] The peripheral region NAA is adjacent to the active region AA. For example, the electronic panel 200 may include an active region AA for displaying an image IM and a peripheral region NAA formed adjacent to the active region AA. The peripheral region NAA may surround the edge of the active region AA. However, this is illustrated illustratively, and the peripheral region NAA may only be adjacent to a portion of the edge of the active region AA, and is not limited to any one exemplary embodiment.

[0073] Within the peripheral area NAA, various signal lines, pads, or electronic components can be configured to provide electrical signals to the active area AA. The peripheral area NAA can be covered by the border area BZA and is not visible from the outside.

[0074] A portion of the electronic panel 200 according to an exemplary embodiment of the present invention can be bent. For example, as Figure 2A and Figure 2B As shown, the electronic panel 200 may include a non-curved portion NBR and a curved portion BR. Figure 2A An electronic panel 200 in an unbent state is shown, and Figure 2B An electronic panel 200 in a bent state is shown.

[0075] The bent portion BR can be bent by an external force based on a bending axis BX extending along a first direction DR1. The bending axis BX can be defined on the rear surface of the electronic panel 200.

[0076] On the other hand, the electronic panel 200 may also include a stress-relieving pattern SNP disposed in the bent portion BR. The stress-relieving pattern SNP may be disposed between the effective area AA and the pad area PA where the pads PD are disposed. The stress-relieving pattern SNP may include organic materials. When the bent portion BR bends, the stress-relieving pattern SNP can prevent damage to the bent portion BR due to bending stress.

[0077] When the curved portion BR bends around the bending axis BX, the area of ​​the peripheral region NAA, as observed from the front surface FS of the window 100, can be reduced. For example, this allows some of the peripheral region NAA to be positioned behind the effective area AA of the electronic panel 200, thereby reducing or eliminating the need for the peripheral region NAA to be hidden under a shield or device housing. Therefore, the border area BZA can be reduced, thereby enhancing the aesthetics of the electronic device EA. However, this is illustrative, and the inventive concept is not limited thereto. For example, in an exemplary embodiment of the electronic panel 200 according to the inventive concept, the curved portion BR may be omitted.

[0078] like Figure 2C As shown, the electronic panel 200 may include a display unit 210 and an input sensing unit 220. Figure 2C For ease of explanation, the display unit 210 and the input sensing unit 220 are shown separately.

[0079] Display unit 210 can generate and display image IM in effective area AA. Display unit 210 may include a base substrate BS, multiple signal lines GL, DL, PL and RL (see...). Figure 2A ), pixel PX and gate drive circuit GDR.

[0080] The base substrate BS can correspond to the shape of the electronic panel 200 in a planar plane. Specifically, the base substrate BS can be generally configured to provide a curved portion BR and a non-curved portion NBR. The base substrate BS can be flexible so that it can be bent. For example, the base substrate BS can be an insulating polymer film. The insulating polymer film can include a polymer film material with excellent ductility (e.g., polyimide).

[0081] Signal lines GL, DL, PL, and RL are disposed on the base substrate BS and may include a gate line GL, a data line DL, a first power line PL, and a wiring RL. The gate line GL, the data line DL, and the first power line PL may each transmit different electrical signals.

[0082] Gate line GL extends along a first direction DR1. Although multiple gate lines GL can be provided and arranged to be spaced apart from each other along a second direction DR2, a single gate line GL is shown as an example for ease of illustration.

[0083] The gate drive circuit GDR provides an electrical signal to the gate line GL, and the gate drive circuit GDR can be mounted on the base substrate BS. The display unit 210 may also include a gate pad for electrical connection to the externally disposed gate drive circuit GDR.

[0084] The data line DL extends along the second direction DR2 and may be electrically insulated from the gate line GL. Although multiple data lines DL can be provided and arranged to be spaced apart from each other along the first direction DR1, a single data line DL is shown as an example for ease of illustration. The data line DL provides data signals to the pixel PX.

[0085] A first power line PL extends along a second direction DR2 and may be electrically insulated from the gate line GL and the data line DL. Although multiple first power lines PL can be provided and arranged to be spaced apart from each other along a first direction DR1, a single first power line PL is shown as an example for ease of illustration. The first power line PL can provide a power signal (hereinafter referred to as the first power signal) to the pixel PX.

[0086] The wiring RL is disposed in the peripheral area NAA and can be configured to overlap with the stress relief pattern SNP in the planar view. The wiring RL connects the pad PD and the signal line corresponding to the pad PD. The signal line may include lines connected to the data line DL, the gate line GL, and the gate drive circuit GDR, as well as lines connected to the first power supply line PL. On the other hand, this is illustrated illustratively, and the wiring RL may have an integral shape connected to the corresponding signal line, and is not limited to any one exemplary embodiment.

[0087] A pixel (PX) realizes an image (IM) by displaying light based on electrical signals. Each pixel (PX) can display, for example, red, green, blue, or white light. Figure 2C An equivalent circuit diagram of a single pixel PX is illustrated exemplarily. Multiple pixels PX can be provided, but for ease of illustration, a single pixel PX is shown. In an exemplary embodiment of the inventive concept, multiple pixels PX can be arranged in a matrix shape, but the inventive concept is not limited thereto. For example, multiple pixels PX can be arranged in a pentile matrix shape or a rhombus shape. Furthermore, the pixel PX according to this exemplary embodiment can be implemented using various circuits and is not limited to any one of the exemplary embodiments.

[0088] A pixel PX may include a first thin-film transistor TR1, a second thin-film transistor TR2, a capacitor CP, and a light-emitting element ELD. The first thin-film transistor TR1, the second thin-film transistor TR2, the capacitor CP, and the light-emitting element ELD are electrically connected.

[0089] The first thin-film transistor TR1 can be a switching transistor used to control the on and off states of pixel PX. The first thin-film transistor TR1 is connected to the gate line GL and the data line DL. The first thin-film transistor TR1 is turned on by a gate signal provided via the gate line GL and provides a data signal provided via the data line DL to the capacitor CP.

[0090] Capacitor CP is connected to the first thin-film transistor TR1 and the first power supply line PL. Capacitor CP stores the amount of voltage corresponding to the difference between the data voltage transmitted from the first thin-film transistor TR1 and the first power supply voltage applied to the first power supply line PL.

[0091] A second thin-film transistor TR2 is connected to a first thin-film transistor TR1, a capacitor CP, and a light-emitting element ELD. The second thin-film transistor TR2 can be a drive transistor used to control the drive current flowing to the light-emitting element ELD in accordance with the amount of voltage stored in the capacitor CP. The light-emitting element ELD can then emit light with a predetermined brightness using the drive current flowing to it. The on-time of the second thin-film transistor TR2 can be determined based on the amount of charge or voltage stored in the capacitor CP. During the on-time, the second thin-film transistor TR2 supplies a first power supply voltage, transmitted via a first power line PL, to the light-emitting element ELD.

[0092] Light-emitting elements (ELDs) can generate light or control the amount of light based on electrical signals. For example, ELDs can include organic light-emitting elements, quantum dot light-emitting elements, electrophoretic elements, or electrowetting elements.

[0093] The light-emitting element ELD is connected to the second thin-film transistor TR2 and the power supply terminal VSS. The light-emitting element ELD emits light at a voltage corresponding to the difference between the voltage transmitted via the second thin-film transistor TR2 and the second power supply voltage received via the power supply terminal VSS. The light-emitting element ELD can emit light during the on-time of the second thin-film transistor TR2.

[0094] A light-emitting element (ELD) includes a light-emitting material and can generate light of a color corresponding to the light-emitting material. The color of light generated in an ELD can be any of red, green, blue, and white.

[0095] This is illustrated by way of example, and the pixel PX may include electronic components with various configurations and arrangements, and is not limited to any one exemplary embodiment. The display unit 210 can generate a predetermined image by means of light emitted from the pixel PX.

[0096] A gate drive circuit (GDR) is disposed in the peripheral region (NAA) and generates a gate drive signal. A gate line (GL) is connected to the gate drive circuit (GDR) to transmit the gate drive signal to the pixel (PX). In this exemplary embodiment, the provided gate drive circuit (GDR) can be mounted on the base substrate (BS). However, this is illustrative, and the inventive concept is not limited thereto. For example, the gate drive circuit (GDR) of the exemplary embodiment of the inventive concept can be provided in the form of a chip, or it can be mounted on a separate circuit substrate and attached to the base substrate (BS).

[0097] The pad PD can be set in the display unit 210, and can include the display pad PDD and the detection pad PDT.

[0098] The display pad PDD provides electrical signals to the display unit 210. Specifically, the display pad PDD provides electrical signals to the pixel PX and the gate drive circuit GDR via multiple signal lines. For example, the display pad PDD may include pads connected to the data line DL, pads connected to the first power line PL, pads connected to the gate drive circuit GDR, and pads connected to the power terminal VSS.

[0099] The detection pad PDT can provide an electrical signal to the input sensing unit 220. For example, the detection pad PDT can be connected to the terminal pads TP of the input sensing unit 220. This will be described in detail later.

[0100] According to the present invention, by setting a display pad PDD and a detection pad PDT in a pad area PA, it is possible to communicate via a circuit substrate 300 (see...) Figure 1B Simultaneously driving the display unit 210 and the input sensing unit 220 can improve assemblability and simplify the process. However, this is an illustrative description, and the inventive concept is not limited thereto. For example, in an exemplary embodiment of the electronic panel 200 according to the inventive concept, the detection pad PDT can be disposed in the input sensing unit 220, and can be disposed in a space separate from the display pad PDD.

[0101] The input sensing unit 220 can be disposed on the display unit 210 and can be configured to detect external input TC and obtain the position or intensity information of external input TC. The input sensing unit 220 may include multiple sensing electrodes TE1 and TE2, multiple detection lines TL1 and TL2, and multiple detection pads PDT.

[0102] Sensing electrodes TE1 and TE2 are disposed in the effective region AA. Sensing electrodes TE1 and TE2 may include a first sensing electrode TE1 and a second sensing electrode TE2 that receive different electrical signals from each other. The input sensing unit 220 can obtain information related to the external input TC by means of the capacitance change between the first sensing electrode TE1 and the second sensing electrode TE2.

[0103] The first sensing electrode TE1 extends along the second direction DR2 and can be configured in multiples and arranged spaced apart from each other along the first direction DR1. The first sensing electrode TE1 may include a plurality of first detection patterns SP1 arranged along the second direction DR2 and electrically connected to each other. Two of the first detection patterns SP1, respectively arranged at two opposite ends of the first sensing electrode TE1, may have a smaller size (e.g., half the size) than the first detection pattern SP1 arranged at the center.

[0104] The second sensing electrode TE2 extends along the first direction DR1 and can be configured in multiples and arranged spaced apart from each other along the second direction DR2. The second sensing electrode TE2 may include a plurality of second detection patterns SP2 arranged along the first direction DR1 and electrically connected to each other. Two of the second detection patterns SP2, respectively arranged at two opposite ends of the second sensing electrode TE2, may have a smaller size (e.g., half the size) than the second detection pattern SP2 arranged at the center.

[0105] Detection lines TL1 and TL2, and terminal pad TP are located in the peripheral area NAA. Terminal pad TP is connected to detection lines TL1 and TL2, respectively. Terminal pad TP is electrically connected to the detection pad PDT of pad PD.

[0106] The detection lines TL1 and TL2 include a first detection line TL1 and a second detection line TL2. The first detection line TL1 connects the terminal pad TP corresponding to the first sensing electrode TE1 and the first detection pattern SP1 in the terminal pad TP, so as to transmit the electrical signal provided from the outside via the detection pad PDT to the first sensing electrode TE1. The second detection line TL2 connects the terminal pad TP corresponding to the second sensing electrode TE2 and the second detection pattern SP2 in the terminal pad TP, so as to transmit the electrical signal provided from the outside via the detection pad PDT to the second sensing electrode TE2.

[0107] Refer again Figure 1BThe circuit substrate 300 can be connected to the electronic panel 200. The circuit substrate 300 may include a flexible substrate CF and a main substrate MB. The flexible substrate CF may include an insulating film and conductive lines mounted on the insulating film. The conductive lines are connected to pads PD to electrically connect the circuit substrate 300 and the electronic panel 200. However, in this exemplary embodiment, the flexible substrate CF may be omitted, and the main substrate MB may be directly connected to the electronic panel 200.

[0108] The main substrate MB may include signal lines and electronic components. The electronic components may be connected to the signal lines and electrically connected to the electronic panel 200. The electronic components generate various electrical signals (e.g., signals for generating an image IM or signals for detecting an external input TC), or process the detected signals. Alternatively, multiple main substrate MBs may be configured to generate each of the signals and process each of the detected signals, and the main substrate MB is not limited to any one exemplary embodiment.

[0109] The housing 400 is disposed on the underside of the electronic panel 200 and may comprise a material with relatively high rigidity compared to the electronic panel 200. For example, the housing 400 may comprise multiple frames and / or a plate made of, for example, glass, plastic, metal, or a combination thereof.

[0110] The housing 400 provides a predetermined receiving space. The electronic panel 200 and the circuit substrate 300 can be housed within this receiving space and protected from external impacts. According to the present invention, an electronic device EA can be provided that is capable of displaying an image IM using a single electronic panel 200 and simultaneously detecting external input TC in an environment where use is possible. For example, the display unit 210 and the input sensing unit 220 are integrated within a single electronic panel 200 on a single base substrate BS. Therefore, the thickness of the electronic device EA can be reduced, and an electronic device EA with enhanced assemblability can be provided.

[0111] Figure 3A It is along Figure 2A The sectional view shown is taken by line I-I'. Figure 3B and Figure 3C This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the present invention, and for ease of explanation, it is shown in conjunction with... Figure 3A The corresponding area. This will be referred to in the following text. Figures 3A to 3C The concept of the present invention will be described.

[0112] like Figure 3A As shown, the electronic panel 200 includes a base substrate BS, pixels PX, multiple insulating layers 10, 20, 30, 40, 50, and 60, as well as detection lines TSL and detection patterns SP'. Figure 3AFor ease of explanation, the configuration of the second thin-film transistor TR (hereinafter referred to as pixel transistor) and the light-emitting element ELD of the pixel PX are illustrated in the diagram.

[0113] The base substrate BS may include an insulating material. For example, the base substrate BS may include polyimide (PI). Therefore, as... Figure 2B As shown, at least a portion of the electronic panel 200 can be easily bent. However, this is an exemplary description, and the base substrate BS can be configured to be rigid. For example, the base substrate BS can be formed of various materials (such as glass, plastic, and combinations thereof), and is not limited to any one exemplary embodiment.

[0114] A first insulating layer 10 is disposed on a base substrate BS. The first insulating layer 10 covers the front surface of the base substrate BS and may include a barrier layer 11 and a buffer layer 12.

[0115] The barrier layer 11 may comprise an inorganic material and prevent oxygen or moisture flowing through the base substrate BS from penetrating the pixel PX. The buffer layer 12 may comprise an inorganic material, such as silicon oxide (SiO2), silicon nitride (Si3N4), and / or silicon oxynitride (SiON). The buffer layer 12 may provide the pixel PX with a surface energy lower than that provided by the base substrate BS, thereby allowing the pixel PX to be stably formed on the base substrate BS.

[0116] exist Figure 3A In this illustration, for ease of explanation, the barrier layer 11 and the buffer layer 12 are each shown as a single layer. However, this is an illustrative illustration, and the barrier layer 11 and the buffer layer 12 of the exemplary embodiment of the present invention can be provided in multiples and can be stacked alternately on top of each other. Alternatively, at least one of the barrier layer 11 and the buffer layer 12 can be provided in multiples, or can be omitted.

[0117] The pixel transistor TR includes a semiconductor pattern SP, a control electrode CE, an input electrode IE, and an output electrode OE. The semiconductor pattern SP is disposed on a base substrate BS and may comprise a semiconductor material, such as polysilicon. The control electrode CE is spaced apart from the semiconductor pattern SP, and a second insulating layer 20 is interposed between the control electrode CE and the semiconductor pattern SP. The control electrode CE can be connected to one electrode of the first thin-film transistor TR1 and the capacitor CP. Here, the control electrode CE may correspond to the gate electrode of the pixel transistor TR.

[0118] The input electrode IE and output electrode OE are spaced apart from the control electrode CE, and a third insulating layer 30 is disposed between the input electrode IE, output electrode OE and control electrode CE. The input electrode IE and output electrode OE of the pixel transistor TR pass through the second insulating layer 20 and the third insulating layer 30, and are electrically connected to one side and the other side of the semiconductor pattern SP, respectively. For example, the input electrode IE and output electrode OE of the pixel transistor TR may correspond to the source electrode and drain electrode of the pixel transistor TR.

[0119] A fourth insulating layer 40 is disposed on the third insulating layer 30 to cover the input electrode IE and the output electrode OE. The fourth insulating layer 40 may include organic and / or inorganic materials and may have a single-layer or laminated structure.

[0120] In a pixel transistor TR, a semiconductor pattern SP can be disposed on the control electrode CE. Alternatively, the semiconductor pattern SP can be disposed on the input electrode IE and the output electrode OE. Alternatively, the input electrode IE and the output electrode OE can be disposed on the same layer as the semiconductor pattern SP and directly connected to the semiconductor pattern SP. The pixel transistor TR of the exemplary embodiment of the present invention can be formed in various structures and is not limited to any one exemplary embodiment.

[0121] A light-emitting element (ELD) is disposed on a fourth insulating layer 40. The ELD includes a first electrode E1, a light-emitting layer EL, and a second electrode E2. The first electrode E1 can be connected to a pixel transistor TR via the fourth insulating layer 40. Furthermore, the electronic panel 200 may also include a separate connection electrode disposed between the first electrode E1 and the pixel transistor TR, and simultaneously, the first electrode E1 can be electrically connected to the pixel transistor TR via the connection electrode.

[0122] A fifth insulating layer 50 is disposed on the fourth insulating layer 40. An opening 50_OP may be defined in the fifth insulating layer 50. The opening 50_OP exposes at least a portion of the first electrode E1. The fifth insulating layer 50 may include an organic material, such as polyimide. In this exemplary embodiment, the fifth insulating layer 50 may be a pixel-defining film.

[0123] A light-emitting layer EL is disposed in the opening portion 50_OP and on the first electrode E1 exposed through the opening portion 50_OP. The light-emitting layer EL may include a light-emitting material. For example, the light-emitting layer EL may include at least one of materials emitting red, green, and blue light, and may include fluorescent or phosphorescent materials. The light-emitting layer EL may include organic or inorganic light-emitting materials. For example, in an exemplary embodiment of the present invention, the display unit 210 of the electronic panel 200 may include an organic light-emitting display unit or a quantum dot light-emitting display unit. The light-emitting layer EL of the organic light-emitting display unit may include organic light-emitting materials. The light-emitting layer EL of the quantum dot light-emitting display unit may include quantum dots and quantum rods. The light-emitting layer EL may emit light in response to the potential difference between the first electrode E1 and the second electrode E2.

[0124] The second electrode E2 is disposed on the light-emitting layer EL and may be opposite to the first electrode E1. The second electrode E2 may have an integral shape extending from the effective region AA to the peripheral region NAA, and may be commonly provided to multiple pixels PX. Each light-emitting element ELD disposed in each of the pixels PX receives a common second power supply voltage via the second electrode E2.

[0125] The second electrode E2 may comprise a transparent or semi-transparent conductive material. In an exemplary embodiment of the present invention, the second electrode E2 may comprise a transparent conductive oxide, and the transparent conductive oxide may include, but is not limited to, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), etc. Therefore, light generated in the light-emitting layer EL can be easily emitted toward a third party DR3 through the second electrode E2. However, this is illustrated by way of example. Depending on the design, the light-emitting element ELD of the exemplary embodiment of the present invention may be driven by a rear-surface light-emitting system or by a dual-sided light-emitting system, but is not limited to any one of the exemplary embodiments, wherein, in a rear-surface light-emitting system, the first electrode E1 comprises a transparent or semi-transparent material, and in a dual-sided light-emitting system, light is emitted toward both the front and rear surfaces.

[0126] A sixth insulating layer 60 is disposed on the light-emitting element ELD to seal the light-emitting element ELD. In this exemplary embodiment, the sixth insulating layer 60 may be an encapsulation layer. The sixth insulating layer 60 may have an integral shape extending from the active region AA to the peripheral region NAA. The sixth insulating layer 60 may be commonly provided to multiple pixels PX. For example, the display unit 210 may include multiple pixels PX, and the encapsulation layer (sixth insulating layer 60) may be configured to cover the multiple pixels PX. A capping layer covering the second electrode E2 may also be disposed between the second electrode E2 and the sixth insulating layer 60.

[0127] The sixth insulating layer 60 may include a first inorganic layer 61, an organic layer 62, and a second inorganic layer 63 stacked sequentially along the third direction DR3. In this exemplary embodiment, each of the first inorganic layer 61, the organic layer 62, and the second inorganic layer 63 is shown as a single layer. However, this is illustrative, and at least one of the first inorganic layer 61, the organic layer 62, and the second inorganic layer 63 may be provided as multiple layers, or may be omitted, but is not limited to any one of the exemplary embodiments.

[0128] The first inorganic layer 61 may cover the second electrode E2. The first inorganic layer 61 may prevent external moisture or oxygen from penetrating the light-emitting element (ELD). For example, the first inorganic layer 61 may include silicon nitride (Si3N4), silicon oxide (SiO2), or a combination thereof. The first inorganic layer 61 may be formed via a deposition process.

[0129] The organic layer 62 may be disposed on and in contact with the first inorganic layer 61. The organic layer 62 may provide a flat surface on the first inorganic layer 61. Specifically, the organic layer 62 may provide a flat surface to the effective area AA.

[0130] The bends formed on the upper surface of the first inorganic layer 61 and the particles present on the first inorganic layer 61 are covered by the organic layer 62, which prevents the surface state of the upper surface of the first inorganic layer 61 from affecting the structure formed on the organic layer 62. Furthermore, the organic layer 62 can alleviate stress between contact layers. The organic layer 62 may comprise organic materials and may be formed via solution processes (such as spin coating, slot coating, or inkjet printing). In exemplary embodiments of the inventive concept, the organic material of the organic layer 62 may include, for example, imide-based polymers, general-purpose polymers (such as polymethyl methacrylate (PMMA) and polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, aryl ether polymers, amide polymers, fluoropolymers, p-xylylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0131] A second inorganic layer 63 is disposed on the organic layer 62 to cover the organic layer 62. Compared to the layer disposed on the first inorganic layer 61, the second inorganic layer 63 can be stably formed on a relatively flat surface. The second inorganic layer 63 seals away moisture and other substances emanating from the organic layer 62 to prevent them from being introduced to the outside. The second inorganic layer 63 may include silicon nitride (Si3N4), silicon oxide (SiO2), or a combination thereof. The second inorganic layer 63 can be formed via a deposition process.

[0132] A planarization layer FL is disposed on the sixth insulating layer 60 (encapsulation layer) to cover at least a portion of the upper surface of the sixth insulating layer 60. The upper surface of the sixth insulating layer 60 may include a flat surface 60_S and a non-flat surface that is curved compared to the flat surface 60_S, wherein the flat surface 60_S has the same plane as the plane disposed in the effective region AA. The non-flat surface may be a region in which the organic layer 62 is substantially not disposed, and may be a region in which dam portions DM1 and DM2 are disposed. For example, the non-flat surface may not overlap with the organic layer 62 in a plan view, and may be a region that includes only the first inorganic layer 61 and the second inorganic layer 63.

[0133] A planarization layer FL may be disposed in the peripheral region NAA to cover non-planar surfaces in the upper surface of the sixth insulating layer 60. The planarization layer FL provides a flat surface FL_S on its upper side. The planarization layer FL comprises an organic material. In an exemplary embodiment of the inventive concept, the organic material of the planarization layer FL may include, for example, an imide-based polymer, a general-purpose polymer (such as polymethyl methacrylate (PMMA) and polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an aryl ether-based polymer, an amide-based polymer, a fluoropolymer, a p-xylylene-based polymer, a vinyl alcohol-based polymer, or mixtures thereof. In this exemplary embodiment, the flat surface FL_S defined by the planarization layer FL is shown as defining a plane substantially identical to the plane of the flat surface 60_S defined by the sixth insulating layer 60. However, this is illustrative; when the flat surface FL_S defined by the planarization layer FL has a plane substantially parallel to the plane of the flat surface 60_S defined by the sixth insulating layer 60, the height of the flat surface FL_S defined by the planarization layer FL can be designed differently, and is not limited to any one exemplary embodiment. In this exemplary embodiment, as Figure 3A As shown, the electronic panel 200 includes a planarization layer FL covering the non-planar surface of the display unit 210 (e.g., the non-planar surface of the sixth insulating layer 60). Therefore, the detection line TSL of the input sensing unit 220 can be disposed on the planarization layer FL. Thus, the area where the input sensing unit 220 can be disposed can be extended to the non-planar surface of the display unit 210 (e.g., the non-planar surface of the sixth insulating layer 60). Therefore, the electronic panel 200 can have better electrical reliability, and the input sensing unit 220 can have better process reliability.

[0134] Figure 3A The detection line TSL and detection pattern SP' of the input sensing unit 220 are shown as an example. The detection pattern SP' is set in the effective area AA. The detection pattern SP' can be either the first detection pattern SP1 or the second detection pattern SP2.

[0135] The detection pattern SP' comprises a conductive material. On the other hand, the detection pattern SP' can be optically transparent. Therefore, even if the detection pattern SP' overlaps with the light-emitting layer EL disposed in the opening portion 50_OP in the plan view, it is possible to prevent the problem of not being able to visually identify the light generated from the light-emitting layer EL due to the detection pattern SP'.

[0136] This is an illustrative illustration, and the detection pattern SP' may include multiple grid lines. In this case, the detection pattern SP' may be configured not to overlap with the opening portion 50_OP. The detection pattern SP' of the exemplary embodiment of the present invention can be designed using various materials and various shapes, and is not limited to any one exemplary embodiment. For example, when the detection pattern SP' includes multiple grid lines, the detection pattern SP' may include a transparent or opaque conductive material.

[0137] The detection line TSL is disposed in the peripheral region NAA. The detection line TSL may be part of the first detection line TL1. In this exemplary embodiment, the detection line TSL may include the same material as the detection pattern SP'. For example, the detection line TSL may include a transparent material or may include multiple grid lines. For example, a detection line TSL with multiple grid lines may include, for example, one of silver (Ag), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), nickel (Ni), and titanium (Ti), but this disclosure is not limited thereto. The transparent conductive material may include a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). However, this is an exemplary description, and the detection line TSL may include a different material than the detection pattern SP' and may be disposed on different layers, and is not limited to any one of the exemplary embodiments.

[0138] Some of the detection lines TSL can be disposed on the planarization layer FL. For example, in a planar view, some of the detection lines TSL can be disposed on the planarization layer FL to overlap with the dam portions DM1 and DM2. The planar surface FL_S of the planarization layer FL can define a plane that is substantially the same as the plane of the planar surface 60_S of the sixth insulating layer 60. According to the present invention, the electronic panel 200 also includes a planarization layer FL such that the area where the detection lines TSL are disposed can extend outside the planar surface 60_S of the sixth insulating layer 60. Specifically, the planarization layer FL covers the area providing a non-planar surface (this area is different from the effective area AA of the planar surface 60_S of the sixth insulating layer 60) to provide a planar surface FL_S. When the detection lines TSL are disposed on the planarization layer FL, they can also be formed on the upper surface of the sixth insulating layer 60 that provides a non-planar surface. For example, the input sensing unit 220 may include a plurality of sensing electrodes TE1 and TE2 disposed in the effective area AA, and a plurality of detection lines TSL (e.g., Figure 7C TL1, TL2 and TL3 shown can be connected to multiple sensing electrodes TE1 and TE2, wherein the detection line TSL can be disposed on the planarization layer FL and can overlap with the non-planar surface of the encapsulation layer (sixth insulating layer 60) in the planar view.

[0139] According to the present invention, the area of ​​the peripheral region NAA used to provide the detection lines TSL can be reduced, and the area of ​​the effective region AA can be prevented from being reduced. Furthermore, as the area where the detection lines TSL are provided widens, the spacing between the detection lines TSL can be stably ensured, and electrical interference between the detection lines TSL can be reduced. Therefore, the electrical reliability of the electronic panel 200 can be enhanced.

[0140] According to the present invention, when the detection line TSL and the detection pattern SP' are disposed on a flat surface, the detection line TSL and the detection pattern SP' can be stably formed on the display unit 210. Therefore, the process reliability of the input sensing unit 220 can be enhanced.

[0141] According to the present invention, the electronic panel 200 may further include a thin-film transistor TR-D (hereinafter referred to as a driving transistor), multiple signal patterns VSS1, E-CNT1, V-INT and CL, and multiple dam portions DM1 and DM2 disposed in the peripheral region NAA. The driving transistor TR-D, the signal patterns VSS1, E-CNT1, V-INT and CL, and the dam portions DM1 and DM2 constitute the display unit 210 (see [reference]). Figure 2C On the other hand, the gate drive circuit GDR (see...) Figure 2C It can be configured by driving transistor TR-D and some of the signal patterns VSS1, E-CNT1, V-INT and CL.

[0142] The driving transistor TR-D is illustrated illustratively as having a structure corresponding to the pixel transistor TR. For example, the driving transistor TR-D may include a semiconductor pattern SP disposed on a first insulating layer 10, a control electrode CE disposed on a second insulating layer 20, and an input electrode IE and an output electrode OE disposed on a third insulating layer 30.

[0143] Pixel transistors TR and driving transistors TR-D can be formed simultaneously using the same process, thereby simplifying the process and reducing process costs. However, this is illustrative, and compared to the electrode and semiconductor pattern of the pixel transistor TR, the driving transistor TR-D of the exemplary embodiment of the present invention includes electrodes and semiconductor patterns arranged on different layers, or has a structure different from that of the pixel transistor TR, and is not limited to any one of the exemplary embodiments.

[0144] The signal patterns VSS1, E-CNT1, V-INT, and CL include the power supply line VSS1, the connection electrode E-CNT1, the initialization voltage line V-INT, and the drive signal line CL. The power supply line VSS1 may correspond to the power supply terminal VSS of the pixel PX. The power supply line VSS1 supplies a second power supply voltage to the light-emitting element ELD.

[0145] Power line VSS1 is disposed on the third insulating layer 30. Power line VSS1 is disposed on the same layer as the input electrode IE or output electrode OE of the driving transistor TR-D. Power line VSS1 can be patterned simultaneously using a mask in the same process as the input electrode IE or output electrode OE of the driving transistor TR-D. However, this is illustrated by way of example, and power line VSS1 can be disposed on a different layer than the input electrode IE or output electrode OE of the driving transistor TR-D, and can be formed via a separate process, and is not limited to any one of the exemplary embodiments.

[0146] The connecting electrode E-CNT1 is disposed on the fourth insulating layer 40 and is electrically connected to the power line VSS1. The connecting electrode E-CNT1 covers the power line VSS1 exposed from the fourth insulating layer 40.

[0147] The second electrode E2 of the light-emitting element (ELD) extends from the effective region AA and connects to the connecting electrode E-CNT1. For example, the second electrode E2 can be disposed over the entire surface of the effective region AA and can be formed as a single unit to cover multiple pixels PX. The second electrode E2 can extend to a portion of the peripheral region NAA to connect to the connecting electrode E-CNT1. The connecting electrode E-CNT1 can receive a second power supply voltage from the power line VSS1. Therefore, the second power supply voltage is transmitted to the second electrode E2 via the connecting electrode E-CNT1, thereby supplying a common second power supply voltage to each pixel PX.

[0148] The connecting electrode E-CNT1 can be disposed on the same layer as the first electrode E1 of the light-emitting element ELD, and can be formed simultaneously with the first electrode E1. However, this is shown illustratively, and the connecting electrode E-CNT1 can also be disposed on a different layer than the first electrode E1.

[0149] Multiple drive signal lines CL can be configured and disposed on the third insulating layer 30. The drive signal lines CL can be disposed within the peripheral area NAA. The drive signal lines CL can be wiring connected to pads or lines constituting an integrated circuit (IC). The drive signal lines CL are configured to be spaced apart from each other in the first direction DR1 and transmit electrical signals independently.

[0150] The initialization voltage line V-INT provides an initialization voltage to pixel PX, and can be set to multiple lines to provide an initialization voltage to each of multiple pixels PX.

[0151] The drive signal line CL and the initialization voltage line V-INT can be disposed on the same layer and can be formed simultaneously via the same process. However, this is merely exemplary, and the drive signal line CL and the initialization voltage line V-INT can be formed independently via separate processes, and are not limited to any one of the exemplary embodiments.

[0152] Dam sections DM1 and DM2 are located within the outer perimeter NAA. Dam sections DM1 and DM2 prevent the organic layer 62 from overflowing from the effective area AA towards the outside of dam sections DM1 and DM2, for example, towards the area formed by... Figure 3A The arrow in the image indicates the opposite direction of the first direction DR1.

[0153] Dam sections DM1 and DM2 can be positioned adjacent to at least one side of the effective area AA. Dam sections DM1 and DM2 can surround the effective area AA in the plan view. Multiple dam sections DM1 and DM2 can be configured, and may include a first dam section DM1 and a second dam section DM2.

[0154] Compared to the second dam section DM2, the first dam section DM1 can be positioned closer to the effective area AA, and in a plan view, it can be positioned to overlap with the power line VSS1. In this exemplary embodiment, the connecting electrode E-CNT1 can cross between the first dam section DM1 and the power line VSS1 in cross-section.

[0155] In this exemplary embodiment, the first dam portion DM1 comprises the same material as the fourth insulating layer 40 and can be formed simultaneously with the fourth insulating layer 40 via a mask. Therefore, a separate process for forming the first dam portion DM1 can be omitted, thereby reducing process costs and simplifying the process.

[0156] Compared to the first dam section DM1, the second dam section DM2 can be positioned relatively outward. The second dam section DM2 can be located at a position used to cover a portion of the power line VSS1. In this exemplary embodiment, the second dam section DM2 can have a multi-layer structure including a first layer P1, a second layer P2, and a third layer P3. Although in Figures 3A to 3C The diagram shows that the first dam section DM1 has a double-layer structure and the second dam section DM2 has a triple-layer structure, but the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, the first dam section DM1 and the second dam section DM2 may have a single-layer structure, or have three or more layers.

[0157] In this exemplary embodiment, the connecting electrode E-CNT1 may partially overlap with and be disposed on the first layer P1 of the second dam portion DM2. The end of the connecting electrode E-CNT1 may be inserted between the first layer P1 and the second layer P2 of the second dam portion DM2. However, this is illustrative, and the connecting electrode E-CNT1 may not extend into the second dam portion DM2, and is not limited to any one of the exemplary embodiments.

[0158] The electronic panel 200 according to an exemplary embodiment of the present invention may further include a crack dam CRD. The crack dam CRD may be disposed in the peripheral region NAA and disposed adjacent to the side surface of the base substrate BS. For ease of illustration, Figure 3A The diagram shows one of the multiple side surfaces of the base substrate BS, BS-E, and the crack dam CRD adjacent to side surface BS-E.

[0159] The crack dam (CRD) can extend along the extension direction of the side surface BS-E of the adjacent base substrate BS. Figure 3A The crack dam CRD in the diagram is shown as having a second direction DR2 intersecting the first direction DR1 (see [reference]). Figure 2BThe extended strip shape. The crack dam CRD can prevent damage such as cracks extending from the side surface BS-E of the base substrate BS from spreading to the effective area AA, thereby enhancing the reliability of the electronic panel 200.

[0160] The crack dam (CRD) may include multiple insulating patterns (IPs) and covering patterns (CVPs). Each of the insulating patterns (IPs) may extend along a second direction (DR2) and may be arranged spaced apart from each other along a first direction (DR1). The insulating patterns (IPs) interrupt the path of an impact or crack extending along the first direction (DR1). Therefore, the reliability of the electronic panel 200 can be enhanced.

[0161] Each of the insulating pattern IPs can have a laminated structure including a first layer A1 and a second layer A2. The first layer A1 can be disposed on the same layer as the second insulating layer 20 and can be formed simultaneously with the second insulating layer 20. The second layer A2 can be disposed on the same layer as the third insulating layer 30 and can be formed simultaneously with the third insulating layer 30. Therefore, the insulating pattern IPs can be formed simultaneously with the formation of the electronic panel 200 without the need for additional processes, thereby simplifying the process and reducing process costs. On the other hand, this is illustrative, and each of the insulating pattern IPs can include a layer formed simultaneously with the first insulating layer 10, and is not limited to any one of the exemplary embodiments.

[0162] The overlay pattern CVP covers the insulating pattern IP and can fill the gaps between the insulating pattern IPs. Compared to the insulating pattern IP, the overlay pattern CVP can include a relatively soft material. For example, the overlay pattern CVP can include organic or conductive materials. Therefore, it is possible to easily prevent damage such as cracks generated in the insulating pattern IP from extending to the effective area AA. On the other hand, this is illustrated illustratively, and the inventive concept is not limited thereto. For example, in an exemplary embodiment of the electronic panel 200 according to the inventive concept, multiple crack dams CRDs may be provided or omitted.

[0163] According to the present invention, a planarization layer FL covers the non-planar surface in the peripheral region NAA. The non-planar surface can exist in the region where a dam portion DM, a crack dam CRD, and various driving elements TR-D, VSS1, E-CNT1, V-INT, and CL are formed. The planarization layer FL is disposed on the dam portion DM, the crack dam CRD, and the various driving elements TR-D, VSS1, E-CNT1, V-INT, and CL to provide a flat surface FL_S to the upper side. Therefore, an input sensing unit 220 including a detection line TSL can be stably disposed on the dam portion DM, the crack dam CRD, and the various driving elements TR-D, VSS1, E-CNT1, V-INT, and CL. For example, the planarization layer FL can cover the non-planar surface of the sixth insulating layer 60 (encapsulation layer), and the input sensing unit 220 can be disposed on both the flat surface 60_S and the non-planar surface of the sixth insulating layer 60 (encapsulation layer). For example, the input sensing unit 220 can be disposed on the flat surface 60_S of the sixth insulating layer 60 (encapsulation layer) and the flat surface FL_S of the planarization layer FL, which is disposed on the non-flat surface of the sixth insulating layer 60 (encapsulation layer). Therefore, the area of ​​the input sensing unit 220 disposed on the display unit 210 can be easily ensured, thereby enhancing the electrical reliability of the electronic panel 200.

[0164] like Figure 3B As shown, in the electronic panel 200-A, the input sensing unit 220 may further include a detection insulating layer SIL. The detection insulating layer SIL covers the flat surface 60_S of the sixth insulating layer 60 and the flat surface FL_S of the planarization layer FL, respectively.

[0165] In the electronic panel 200-A, the detection line TSL-A can have a laminated structure comprising multiple layers. For example, each of the detection lines TSL-A can include a first layer L1 and a second layer L2. The detection line TSL-A has a laminated structure, which allows it to have enhanced transmittance. Therefore, the influence of the input sensing unit 220 stacked on the display unit 210 on the display characteristics of the display unit 210 can be reduced. Alternatively, the detection line TSL-A can have a laminated structure, which allows it to have enhanced conductivity. Therefore, the sensitivity of the input sensing unit 220 can be enhanced.

[0166] exist Figure 3B In this example, unlike the detection line TSL-A, the detection pattern SP-A has a single-layer structure. That is, the detection pattern SP-A and the detection line TSL-A can be designed independently of each other. However, this is shown illustratively, and as... Figure 3A As shown, the detection line TSL and the detection pattern SP' can have the same structure and are not limited to any one of the exemplary embodiments.

[0167] like Figure 3C As shown, in the electronic panel 200-B, each of the detection lines TSL-B includes a first layer L11 and a second layer L21 connected to each other via a detection insulating layer SIL. Therefore, the resistance of each of the detection lines TSL-B can be reduced, thereby enhancing the sensitivity of the electronic panel 200-B. Additionally, deformation (such as bending of the electronic panel 200-B) or defects (such as breakage of the detection lines TSL-B) caused by external impacts can be reduced. Therefore, the electrical reliability of the electronic panel 200-B can be enhanced. Each of the first layer L11 and the second layer L21 in an exemplary embodiment of the present invention can have a single-layer structure or a stacked multilayer structure. A single-layer structure can include a metal layer or a transparent conductive layer. A multilayer structure can include multiple metal layers. The multiple metal layers can have, for example, a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). Alternatively, the multilayer structure can include at least one metal layer and at least one transparent conductive layer.

[0168] Figures 4A to 4C This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the present invention. Figures 4A to 4C For ease of explanation, the diagram shows the relationship with... Figure 3A The corresponding region, and except for the planarization layer FL (see Figure 3A Apart from that, essentially the same configuration is shown. In the following text, reference will be made to... Figures 4A to 4C The inventive concept is described below. Furthermore, in conjunction with reference to... Figures 1A to 3C Components that are described in the same way are given the same reference numerals, and repeated descriptions will be omitted.

[0169] like Figure 4A As shown, in electronic panel 200-1, planarization layer FL-1 can extend to the active area AA. Planarization layer FL-1 can cover at least a portion of the peripheral area NAA and the active area AA. For example, planarization layer FL-1 can completely cover the planar surface 60_S of the sixth insulating layer 60 (encapsulation layer). Planarization layer FL-1 provides a planar surface FL_S1 with substantially the same plane in both the peripheral area NAA and the active area AA.

[0170] The input sensing unit 220-1, including the detection line TSL, is disposed on the flat surface FL_S1. According to the present invention, since the flat surface FL_S1 of the effective region AA and the peripheral region NAA is formed by a planarization layer FL-1, the flatness of the flat surface FL_S1 can be uniformly and continuously exhibited in the effective region AA and the peripheral region NAA. Therefore, the input sensing unit 220-1 can be indirectly disposed on both the flat surface 60_S and the non-flat surface of the sixth insulating layer 60 (encapsulation layer). Therefore, the area of ​​the input sensing unit 220-1 disposed on the display unit 210 can be easily ensured. Thus, the process reliability of the input sensing unit 220-1 can be enhanced, and the electrical reliability can also be enhanced.

[0171] Alternatively, such as Figure 4B As shown, in the electronic panel 200-2, the planarization layer FL-2 can cover a portion of the flat surface 60_S formed by the sixth insulating layer 60. For example, the planarization layer FL-2 can cover the non-flat surface of the sixth insulating layer 60 and extend to cover some areas of the flat surface 60_S. In other words, at least a portion of the planarization layer FL-2 can cover the flat surface 60_S of the sixth insulating layer 60 (encapsulation layer).

[0172] The planarization layer FL-2 has a predetermined thickness TH on the planar surface 60_S formed by the sixth insulating layer 60. Therefore, the planar surface FL_S2 defined by the planarization layer FL-2 and the planar surface 60_S formed by the sixth insulating layer 60 can define different planes. In this exemplary embodiment, the planar surface FL_S2 defined by the planarization layer FL-2 is also spaced apart from the planar surface 60_S formed by the sixth insulating layer 60 on the third-direction DR3.

[0173] The input sensing unit 220-2 may include a detection line TSLL and a detection line TSLH. The detection line TSLL is disposed on a flat surface 60_S formed by the sixth insulating layer 60, and the detection line TSLH is disposed on a flat surface FL_S2 defined by the planarization layer FL-2. The flat surface 60_S formed by the sixth insulating layer 60 and the flat surface FL_S2 defined by the planarization layer FL-2 may define different planes, but they are both flat surfaces. Therefore, each of the two detection lines TSLL and TSLH is formed on a flat surface, allowing for stable formation.

[0174] Alternatively, such as Figure 4C As shown, in electronic panel 200-3, planarization layer FL-3 can cover crack dam CRD. The planar surface FL_S3 defined by planarization layer FL-3 can extend to the region adjacent to the side surface BS-E of the base substrate BS.

[0175] According to the present invention, the input sensing unit 220-3 can also be formed in a region other than the region where the organic layer 62 is disposed, thereby increasing the area where the input sensing unit 220-3 can be disposed. Furthermore, since the area where the detection lines TSL disposed in the peripheral region NAA can be disposed is increased, the input sensing unit 220-3 can be designed to include a greater number of detection lines TSL or to increase the spacing between the detection lines TSL. Therefore, an electronic panel 200-3 with enhanced electrical reliability and enhanced sensitivity can be provided.

[0176] Figures 5A to 5C This is a cross-sectional view of an electronic panel 200 according to an exemplary embodiment of the present invention. Figure 5A It is along Figure 2A The sectional view shown is taken by line II-II', and Figure 5B and Figure 5C It shows the relationship with Figure 5A The corresponding area. This will be referred to in the following text. Figures 5A to 5C The inventive concept is described below. Meanwhile, in conjunction with reference to... Figures 1A to 4C Components that are described in the same way are given the same reference numerals, and repeated descriptions will be omitted.

[0177] Figure 5A The area shown may be the lower region of the electronic panel 200, which includes the side surface of the base substrate BS and the pad region PA (see [reference]). Figure 2A The adjacent side surface BS-E1. (e.g.) Figure 5A As shown, multiple pads PD1 and PD2, stress relief pattern SNP, first power pattern VDD, second power pattern VSS2, connecting electrode E-CNT2, and multiple conductive lines CL1 can be arranged in the lower region of the electronic panel 200.

[0178] Pads PD1 and PD2 may include a first pad PD1 and a second pad PD2. The first pad PD1 is disposed on the third insulating layer 30. Although the first pad PD1 is shown as a single-layer structure, this is for illustrative purposes. The first pad PD1 of an exemplary embodiment of the present invention may have a structure in which multiple layers are stacked, and is not limited to any one exemplary embodiment.

[0179] The first pad PD1 may be at least partially exposed by an insulating pattern IPP. The insulating pattern IPP is disposed on the third insulating layer 30. An opening portion IPP_OP defined in the insulating pattern IPP exposes at least a portion of the first pad PD1. Circuit substrate 300 (see...) Figure 1B It is connected to the exposed portion of the first pad PD1 and electrically connected to the electronic panel 200.

[0180] The second pad PD2 is shown as a laminated structure. For example, the second pad PD2 includes a first pattern PP1 disposed on the second insulating layer 20 and a second pattern PP2 disposed on the third insulating layer 30. The second pattern PP2 is connected to the first pattern PP1 via the third insulating layer 30. The circuit substrate 300 can be electrically connected to the electronic panel 200 via the second pattern PP2.

[0181] The first pad PD1 and the second pad PD2 can receive substantially different electrical signals. For example, the first pad PD1 could be the display pad PDD (see...). Figure 2C One of the following, and the second pad PD2 can be the detection pad PDT (see [link to relevant documentation]). Figure 2C One of the following. According to the present invention, an electronic panel 200 may include an input sensing unit 220 for detecting input (see...). Figure 2C The signals and the signals used to drive the display unit 210 (see) Figure 2C The signal of the electronic panel 200 can be enhanced, and the integration level of the electronic device EA can be reduced. Figure 1A The thickness of ).

[0182] In this exemplary embodiment, the first pad PD1 and the second pad PD2 are shown arranged on the second direction DR2. However, this is an illustrative illustration for ease of explanation, and in the electronic panel 200 of the exemplary embodiment of the present invention, the first pad PD1 and the second pad PD2 may be arranged along the first direction DR1, and are not limited to any one of the exemplary embodiments.

[0183] The stress-relieving pattern SNP is disposed in the peripheral region NAA. In this exemplary embodiment, for ease of illustration, the width in the second direction DR2 is shown to be relatively narrow compared to other structures. For ease of illustration, Figure 5A A wiring RL is shown that is connected to any of the conductive lines CL1_P of the conductive line CL1.

[0184] The wiring RL may include at least one of the signal lines connected between the first pad PD1 and the display unit 210 and the signal lines connected between the second pad PD2 and the input sensing unit 220. Figure 5A The wiring RL shown illustrates a wiring RL connected to any one of the conductive lines CL1_P in the conductive lines CL1. This wiring RL electrically connects the first pattern PP1 of the second pad PD2 and a conductive line CL1_P. Therefore, even if a portion of the panel is bent, the electrical signal received via the second pad PD2 can still be received by the corresponding conductive line CL1_P via the wiring RL and provided to the effective area AA.

[0185] The stress-relieving pattern SNP may include organic materials. The stress-relieving pattern SNP may be disposed on the opening OP defined in the insulating layer. The opening OP may be formed by connecting the opening OP_1 passing through the first insulating layer 10 and the opening OP_2 passing through the second insulating layer 20 and the third insulating layer 30.

[0186] The stress-relieving pattern SNP mitigates the bending stress applied when a portion of the electronic panel 200 (e.g., the bent portion BR) is bent. Therefore, damage to the wiring RL disposed on the stress-relieving pattern SNP can be prevented when the bent portion BR is bent. This enhances the reliability of the electronic panel 200.

[0187] The first power pattern VDD is connected to the first power line PL described above. The first power pattern VDD is connected via any one of the wiring RLs to the pads PD1 and PD2 to which the first power signal is applied, in order to receive the first power signal. The first power pattern VDD may be connected to multiple first power lines PL to provide the same first power signal or voltage to each of the first power lines PL. However, this is illustrative, and the first power pattern VDD in the electronic panel 200 may be omitted, and is not limited to any one exemplary embodiment.

[0188] The second power pattern VSS2 is disposed on the third insulating layer 30. The second power pattern VSS2 is connected via any one of the traces RL to the pads PD1 and PD2 to which the second power signal or voltage is applied, in order to receive the second power signal or voltage. The second power pattern VSS2 is connected to the aforementioned power line VSS1 (see...). Figure 3A ).

[0189] The connecting electrode E-CNT2 can be disposed on the fourth insulating layer 40, and on the same layer as the first electrode E1. The connecting electrode E-CNT2 covers the upper surface of the second power pattern VSS2 and can be connected to the second power pattern VSS2. The second electrode E2 extends from the active region AA and is connected to the connecting electrode E-CNT2. For example, the second electrode E2 can be arranged on the entire surface of the active region AA and can be formed integrally to cover multiple pixels PX. The second electrode E2 can extend to a portion of the peripheral region NAA to connect to the connecting electrode E-CNT2. Therefore, the second power signal or voltage transmitted to the second power pattern VSS2 can be easily transmitted to the second electrode E2. The connecting electrode E-CNT2 can substantially have the same... Figure 3A The connecting electrode E-CNT1 shown (see Figure 3A The configuration is the same as the configuration.

[0190] Multiple conductive lines CL1 are disposed between the second insulating layer 20 and the third insulating layer 30. In this exemplary embodiment, the conductive lines CL1 may be disposed on the same layer as the control electrode CE. The conductive lines CL1 may include at least one of a data line, a gate line, and a variety of control signal lines electrically connected to the active region AA.

[0191] The electronic panel 200 may include dam sections DM11, DM21, and DM3. Dam sections DM11, DM21, and DM3 may include a first dam section DM11, a second dam section DM21, and a third dam section DM3. The first dam section DM11, the second dam section DM21, and the third dam section DM3 are arranged sequentially along a direction away from the effective area AA (i.e., the direction opposite to the second direction DR2 indicated by the arrow).

[0192] Dam sections DM11, DM21, and DM3 prevent the overflow of organic layer 62. Dam sections DM11, DM21, and DM3 may have connections to... Figure 3C The dam sections DM1 and DM2 shown can have an overall shape, or they can be arranged separately. Each of the dam sections DM11, DM21, and DM3 can include two layers P1 and P2 or three layers P1, P2, and P3. Although in Figures 5A to 5C The illustration shows a first dam section DM11 and a second dam section DM21 with a double-layer structure, and a third dam section DM3 with a triple-layer structure; however, the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, each of the dam sections DM11, DM21, and DM3 may have a single-layer structure, or a three- or more-layer structure. The dam sections DM11, DM21, and DM3 may have various structures and are not limited to any one exemplary embodiment.

[0193] According to the present invention, the planarization layer FL can be disposed on the dam portions DM11, DM21, and DM3. The planarization layer FL can cover the non-planar surfaces not covered by the organic layer 62 to provide a flat surface. Therefore, the arrangement area of ​​the detection lines TSL can be increased, allowing the input sensing unit 220 to be stably formed on the display unit 210. For example, the display unit 210 may include dam portions DM11, DM21, and DM3 disposed in the peripheral region NAA in the plan view and not overlapping with the organic layer 62, wherein the planarization layer FL can be disposed to overlap with the dam portions DM11, DM21, and DM3 in the plan view.

[0194] Alternatively, such as Figure 5BAs shown, in the electronic panel 200-11, the planarization layer FL-11 may cover at least a portion of the active area AA. In this exemplary embodiment, the planarization layer FL-11 extends to the active area AA to provide a flat surface FL_S11 on the upper portion. For example, the planarization layer FL-11 may completely cover the flat surface 60_S of the sixth insulating layer 60 (encapsulation layer). The planarization layer FL-11 provides a flat surface FL_S11 having substantially the same plane in both the peripheral area NAA and the active area AA. The planarization layer FL-11 may substantially correspond to Figure 4A The planarization layer FL-1 is shown in the figure.

[0195] Alternatively, such as Figure 5C As shown, in the electronic panel 200-21, due to process errors, the flat surface FL_S21 formed by the planarization layer FL-21 may define a plane different from the flat surface 60_S of the sixth insulating layer 60. The planarization layer FL-21 may cover the non-flat surface of the sixth insulating layer 60 and extend to cover some areas of the flat surface 60_S. For example, at least a portion of the planarization layer FL-21 may cover the flat surface 60_S of the sixth insulating layer 60 (encapsulation layer). However, since each of the flat surface FL_S21 and the flat surface 60_S provides a flat upper surface, the input sensing unit 220 including the detection line TSL can be stably formed on the display unit 210. Furthermore, according to the present invention, the area where the detection line TSL can be set can extend to the area overlapping with the dam portions DM11, DM21 and DM3, thereby preventing the reduction of the effective area AA and increasing the utilization rate of the peripheral area NAA. The planarization layer FL-21 may substantially correspond to Figure 4B The planarization layer FL-2 shown in the figure.

[0196] Figure 6A This is an assembled perspective view of an electronic device according to an exemplary embodiment of the present invention. Figure 6B yes Figure 6A An exploded perspective view of the electronic device shown. Figure 6C This is a block diagram of an electronic device according to an exemplary embodiment of the present invention. In the following, reference will be made to... Figures 6A to 6C The inventive concept is described below. Meanwhile, in conjunction with reference to... Figures 1A to 5C Components described identically are given the same reference numerals, and repeated descriptions will be omitted.

[0197] The electronic device EA-H can display an image IM through an effective area AA activated by an electrical signal and detect external input TC. In the electronic device EA-H according to this exemplary embodiment, an aperture area HA can be defined on the front surface FS. The electronic device EA-H may include a window 100, an electronic panel 200-H, a circuit substrate 300-H, a housing 400, and an electronic module 500. Since the window 100 and the housing 400 correspond to Figure 1B The window 100 and housing 400 shown are therefore omitted from repeated descriptions.

[0198] In this exemplary embodiment, the electronic panel 200-H is assembled in a flat state, in which the active area AA and the peripheral area NAA face the window 100. However, this is shown illustratively, and a portion of the peripheral area NAA of the electronic panel 200-H can be like... Figure 2B The electronic panel 200 shown (see Figure 2B They are assembled in a bent state, just like other assembly methods.

[0199] The electronic panel 200-H includes a display unit 210-H and an input sensing unit 220-H. The display unit 210-H can be configured to substantially generate an image IM, and the input sensing unit 220-H can be configured to detect an external input TC. Meanwhile, in Figure 6B In this illustration, for ease of explanation, the display unit 210-H and the input sensing unit 220-H are shown as separate layers.

[0200] The circuit substrate 300-H is electrically connected to the display unit 210-H and the input sensing unit 220-H, and includes a main circuit substrate MB, a first flexible film CF1 and a second flexible film CF2.

[0201] A first flexible film CF1 is electrically connected to the display unit 210-H and can connect the display unit 210-H and the main circuit substrate MB. The first flexible film CF1 may include an insulating film and conductive lines mounted on the insulating film. The first flexible film CF1 can be connected to the pads (display pads PDD) of the display unit 210-H disposed in the peripheral region NAA to electrically connect the main circuit substrate MB and the display unit 210-H. The first flexible film CF1 provides electrical signals to the display unit 210-H for driving the display unit 210-H. These electrical signals can be generated in the first flexible film CF1 or in the main circuit substrate MB.

[0202] The second flexible film CF2 is electrically connected to the input sensing unit 220-H and can connect the input sensing unit 220-H to the main circuit substrate MB. The second flexible film CF2 may include an insulating film and conductive lines mounted on the insulating film. In this exemplary embodiment, the second flexible film CF2 can be connected to the pads (detection pads PDT) of the input sensing unit 220-H disposed in the peripheral region NAA to electrically connect the main circuit substrate MB and the input sensing unit 220-H. The second flexible film CF2 provides an electrical signal to the input sensing unit 220-H for driving the input sensing unit 220-H. The electrical signal can be generated in the second flexible film CF2 or in the main circuit substrate MB.

[0203] The main circuit substrate MB may include various driving circuits for driving the electronic panel 200-H or connectors for power supply. Each of the first flexible film CF1 and the second flexible film CF2 may be connected to the main circuit substrate MB. According to the present invention, the electronic panel 200-H can be easily controlled via a main circuit substrate MB. However, this is illustrative and the present invention is not limited thereto. For example, in the electronic device EA-H of an exemplary embodiment of the present invention, the display unit 210-H and the input sensing unit 220-H may be connected to different main circuit substrates, and either the first flexible film CF1 or the second flexible film CF2 may not be connected to the main circuit substrate MB. This is not limited to any one of the exemplary embodiments. Alternatively, in the electronic device EA-H of an exemplary embodiment of the present invention, at least one of the first flexible film CF1 and the second flexible film CF2 may be omitted.

[0204] The electronic module 500 is located on the lower side of the window 100 and can be housed within the housing 400. (See reference...) Figure 6C The electronic device EA-H may include an electronic panel 200-H, a power module PM, a first electronic module EM1, and a second electronic module EM2. The electronic module 500 may include either the first electronic module EM1 or the second electronic module EM2.

[0205] The electronic panel 200-H, power module PM, first electronic module EM1, and second electronic module EM2 can be electrically connected to each other. Figure 6C An exemplary configuration of an electronic panel 200-H includes a display unit 210-H and an input sensing unit (detection unit) 220-H.

[0206] The power module PM supplies the power necessary for the overall operation of the electronic device EA-H. The power module PM may include a typical battery module.

[0207] The first electronic module EM1 and the second electronic module EM2 include various functional modules for operating the electronic device EA-H. The first electronic module EM1 can be directly mounted on a motherboard electrically connected to the electronic panel 200-H, or it can be mounted on a separate substrate and electrically connected to the motherboard via connectors, etc.

[0208] The first electronic module EM1 may include a control module CM, a wireless communication module TM, a video input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of these modules may not be mounted on the motherboard, but may be electrically connected to the motherboard via a flexible circuit substrate.

[0209] The control module CM controls the overall operation of the electronic device EA-H. The control module CM can be a microprocessor. For example, the control module CM can activate or deactivate the electronic panel 200-H. The control module CM can also control other modules, such as the image input module (video input module) IIM or the audio input module AIM, based on touch signals received from the electronic panel 200-H.

[0210] The wireless communication module™ can transmit / receive wireless signals to / from another terminal using Bluetooth or Wi-Fi lines. The wireless communication module™ can also transmit / receive voice signals using standard communication lines. The wireless communication module™ includes a transmission unit TM1 for modulating and transmitting the signal to be transmitted, and a receiving unit TM2 for demodulating the received signal.

[0211] The image input module (video input module) IIM processes image signals and converts them into image data that can be displayed on the electronic panel 200-H, for example, image data displayed on the display unit 210-H. The audio input module AIM receives external audio signals through a microphone in recording mode, voice recognition mode, etc., and converts them into electronic voice data.

[0212] The external interface IF serves as an interface for connecting to an external charger, a wired / wireless data port, and a card (e.g., memory card, SIM / UIM card) slot.

[0213] The second electronic module EM2 may include an audio output module AOM, an optical transmitter module LM, an optical receiver module LRM, and a camera module CMM. These components can be directly mounted on the motherboard, or mounted on a separate substrate and electrically connected to the electronic panel 200-H via connectors, or electrically connected to the first electronic module EM1.

[0214] The audio output module AOM converts audio data received from the wireless communication module TM or stored in the memory MM, and outputs the audio data to the outside.

[0215] A light emitting module (LM) generates and outputs light, and can output infrared light. For example, the light emitting module LM may include LED elements. A light receiving module (LRM) can detect infrared light. The LRM can be activated when a predetermined level or higher of infrared light is detected. The LRM may include a CMOS sensor. After outputting the infrared light generated by the light emitting module LM, the infrared light is reflected by an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the LRM. A camera module (CMM) captures the external image.

[0216] An electronic module 500 according to an exemplary embodiment of the present invention may include at least one of a first electronic module EM1 and a second electronic module EM2. For example, the electronic module 500 may include at least one of a camera, a speaker, a light detection sensor, and a thermal detection sensor. The electronic module 500 may detect external objects received via a aperture region HA, or provide sound signals such as speech to the outside via the aperture region HA. Furthermore, the electronic module 500 may include various configurations and is not limited to any one exemplary embodiment.

[0217] Electronic module 500 is configured to overlap with electronic panel 200-H in the plan view. Electronic module 500 can also be configured to overlap with hole area HA.

[0218] In the region corresponding to the aperture region HA of the electronic panel 200-H according to an exemplary embodiment of the present invention, a portion of the display unit 210-H or a portion of the input sensing unit 220-H may be removed. In the electronic panel 200-H, the aperture region HA can have a relatively high transmittance compared to the ordinary effective region AA. Therefore, the electronic module 500, configured to overlap with the aperture region HA, can easily visualize external objects via the aperture region HA, and the output signal generated by the electronic module 500 can be easily transmitted to the outside.

[0219] like Figure 6B As shown, a predetermined hole MH (hereinafter, panel hole) corresponding to the hole region HA can be defined in the electronic panel 200-H. The panel hole MH can be defined in the area overlapping with the hole region HA in the plan view. The panel hole MH is defined in the effective area AA and passes through the electronic panel 200-H. The display unit 210-H and the input sensing unit 220-H can be penetrated by the panel hole MH. The electronic module 500 can be configured to overlap with the panel hole MH. Therefore, even if the electronic module 500 is assembled to overlap with the electronic panel 200-H in the plan view, it can easily communicate with the outside via the panel hole MH. Therefore, the area of ​​the bezel region BZA of the electronic device EA-H can be reduced, thereby enhancing the aesthetics of the electronic device EA-H.

[0220] Figure 7A This is a plan view of a display unit according to an exemplary embodiment of the concept of the present invention. Figure 7B It is shown Figure 7A A magnified plan view of a portion of the area. Figure 7C This is a plan view of an input sensing unit according to an exemplary embodiment of the present invention. Figure 7B The diagram schematically illustrates the display unit 210-H, and... Figure 6B The region XX' shown corresponds to the region shown, and for ease of explanation, in Figures 7A to 7C Some components have been omitted. They will be referred to in the following text. Figures 7A to 7C The inventive concept will now be described. Meanwhile, in conjunction with reference to... Figures 1A to 6C Components that are described in the same way are given the same reference numerals, and repeated descriptions will be omitted.

[0221] like Figure 7A As shown, display unit 210-H includes a base substrate BS, multiple pixels PX, multiple signal lines GL, DL, and PL, and multiple display pads PDD. The active area AA and the peripheral area NAA can be areas provided by the base substrate BS. The base substrate BS can include an insulating substrate. For example, the base substrate BS can be composed of a glass substrate, a plastic substrate, or a combination thereof. The base substrate BS can be flexible to be bent. For example, the base substrate BS can be an insulating polymer film. The insulating polymer film can include a polymer film material with excellent ductility (e.g., polyimide). Descriptions of the pixels PX, signal lines GL, DL, and PL, and display pads PDD will be omitted.

[0222] In display unit 210-H, some of the configurations of display unit 210-H can be removed in the area corresponding to the hole region HA. At least some of the pixels PX can be excluded from the hole region HA. In other words, at least some of the pixels PX can be removed from the hole region HA.

[0223] Reference Figure 7B Pixels PX are arranged adjacent to the aperture region HA. In this exemplary embodiment, pixels PX are not disposed in the aperture region HA. Pixels PX may be arranged along the edge of the aperture region HA. However, this is illustrated illustratively, and some pixels PX may be disposed in the aperture region HA. However, for the same area, the number of pixels PX disposed in the aperture region HA may be less than the number of pixels PX disposed in the effective area AA.

[0224] The recessed portion GV has a closed line shape surrounding the panel hole MH or an intermittent line shape surrounding at least a portion of the edge of the panel hole MH, and is not limited to any one embodiment. The recessed portion GV can prevent damage to components disposed in the effective area AA by cutting off the permeation path of external moisture or oxygen.

[0225] In this exemplary embodiment, a panel hole MH is defined in the display unit 210-H, passing through the display unit 210-H. The panel hole MH is shown as being defined in a hole region HA. Multiple signal lines SL1 and SL2 connected to the pixel PX can be disposed in the hole region HA. The signal lines SL1 and SL2 are connected to the pixel PX via the hole region HA. For ease of description, Figure 7B The diagram exemplarily illustrates a first signal line SL1 and a second signal line SL2 among multiple signal lines connected to pixel PX. Although in Figure 7A and Figure 7B One panel hole MH is shown as being defined within the hole region HA, but the inventive concept is not limited thereto. For example, in an exemplary embodiment of the inventive concept, two or more panel holes MH may be defined in the electronic panel 200-H.

[0226] A first signal line SL1 extends along a first direction DR1. The first signal line SL1 connects to pixels in the same row within the pixel PX that are arranged along the first direction DR1. The first signal line SL1 is illustratively described as corresponding to a gate line GL.

[0227] Some of the pixels connected to the first signal line SL1 are located on the left side of the panel hole MH, and another portion are located on the right side of the panel hole MH. The first signal line SL1 on the right and the first signal line SL1 on the left can be connected to each other using a portion of the first signal line SL1 that is located within the hole region HA and bypasses the panel hole MH. Therefore, even if some pixels in the same row connected to the first signal line SL1 are omitted from the panel hole MH, these pixels can be turned on / off by substantially the same gate signal.

[0228] The second signal line SL2 extends along the second direction DR2. The second signal line SL2 connects to pixels of pixel PX that are arranged in the same column along the second direction DR2. The second signal line SL2 is illustratively described as corresponding to the data line DL.

[0229] Some pixels connected to the second signal line SL2 are located on the upper side based on the panel hole MH, and others are located on the lower side based on the panel hole MH. The upper and lower second signal lines SL2 can be connected to each other using a portion of the second signal line SL2 that is located within the hole region HA and bypasses the panel hole MH. Therefore, even if some pixels around the panel hole MH are omitted, pixels connected to the second signal line SL2 and located in the same column can receive data signals via the same line.

[0230] An electronic panel 200-H according to an exemplary embodiment of the present invention may further include a connection pattern disposed in the hole region HA. In this case, the first signal line SL1 may be disconnected in the region overlapping with the hole region HA. The disconnected portion of the first signal line SL1 may be connected via the connection pattern. Similarly, the second signal line SL2 may be disconnected in the region overlapping with the hole region HA, and a connection pattern may also be provided to connect the disconnected portion of the second signal line SL2.

[0231] Refer again Figure 7A The display pad PDD can include a first pad D1 and a second pad D2. Multiple first pads D1 can be connected to data lines DL respectively.

[0232] The second pad D2 can be connected to the first power pattern VDD and electrically connected to the first power line PL. The display unit 210-H can provide electrical signals supplied externally via the display pad PDD to the pixel PX. In addition to the first pad D1 and the second pad D2, the display pad PDD may also include pads for receiving electrical signals, and is not limited to any one of the exemplary embodiments. Figure 6B As shown, the first flexible film CF1 can be connected to the display pad PDD disposed in the peripheral region NAA of the display unit 210-H to electrically connect the main circuit substrate MB and the display unit 210-H.

[0233] Reference Figure 7C The input sensing unit 220-H is disposed on the display unit 210-H. The input sensing unit 220-H includes a first sensing electrode TE1, a second sensing electrode TE2, multiple detection lines TL1, TL2 and TL3, and multiple detection pads PDT.

[0234] The diagram shows a first sensing electrode TE1 comprising a first detection pattern SP1 and a first connection pattern BP1 connecting adjacent first detection patterns SP1. For example, the first sensing electrode TE1 may include a plurality of first detection patterns SP1 arranged along a first direction DR1 and electrically connected to each other via the first connection pattern BP1. The diagram also shows a second sensing electrode TE2 comprising a second detection pattern SP2 and a second connection pattern BP2 connecting adjacent second detection patterns SP2. For example, the second sensing electrode TE2 may include a plurality of second detection patterns SP2 arranged along a second direction DR2 and electrically connected to each other via the second connection pattern BP2.

[0235] The first sensing electrode TE1 and the second sensing electrode TE2 are disposed in the effective area AA. The input sensing unit 220-H can obtain information related to the external input TC by means of the capacitance change between the first sensing electrode TE1 and the second sensing electrode TE2.

[0236] Detection lines TL1, TL2, and TL3 are disposed in the peripheral region NAA. Detection lines TL1, TL2, and TL3 may include a first detection line TL1, a second detection line TL2, and a third detection line TL3. The first detection line TL1 is connected to a first sensing electrode TE1. The second detection line TL2 is connected to one end of a second sensing electrode TE2.

[0237] The third detection line TL3 is connected to the other end of the second sensing electrode TE2. The other end of the second sensing electrode TE2 may be the portion opposite to the first end of the second sensing electrode TE2. According to the present invention, the second sensing electrode TE2 may be connected to both the second detection line TL2 and the third detection line TL3. Therefore, for the second sensing electrode TE2, which has a relatively longer length than the first sensing electrode TE1, the sensitivity of each region can be maintained uniformly. On the other hand, this is illustrated illustratively. The third detection line TL3 may be omitted and is not limited to any one of the exemplary embodiments. Alternatively, in an exemplary embodiment of the present invention, the first detection line TL1 is connected to one end of the first sensing electrode TE1, and a fourth detection line may be added to connect to the other end of the first sensing electrode TE1, thereby enhancing the sensing sensitivity.

[0238] The detection pad PDT is located in the peripheral area NAA. The detection pad PDT may include a first detection pad T1, a second detection pad T2, and a third detection pad T3. The first detection pad T1 is connected to a first detection line TL1 to provide an external signal to the first sensing electrode TE1. The second detection pad T2 is connected to a second detection line TL2, and the third detection pad T3 is connected to a third detection line TL3 to connect to the second sensing electrode TE2. Figure 6BAs shown, the second flexible film CF2 can be connected to the detection pad PDT disposed in the peripheral region NAA of the input sensing unit 220-H to electrically connect the main circuit substrate MB and the input sensing unit 220-H.

[0239] In the input sensing unit 220-H, some of the configuration of the input sensing unit 220-H can be removed in the region corresponding to the aperture region HA. For example, at least a portion of the first sensing electrode TE1 and the second sensing electrode TE2 may not be disposed in the aperture region HA. In this exemplary embodiment, the first sensing electrode TE1, which is disposed to overlap with the aperture region HA, includes a first detection pattern SP1 having a partially removed shape, and the second sensing electrode TE2 may include a second detection pattern SP2 having a partially removed shape.

[0240] In this exemplary embodiment, a portion of the first connection pattern BP1 can connect two adjacent first detection patterns SP1 via the hole region HA. Similarly, a portion of the second connection pattern BP2 can connect two adjacent second detection patterns SP2 via the hole region HA. The connection pattern BP1 or BP2 disposed in the hole region HA can extend along the edge of the panel hole MH. According to the present invention, removing the portions of sensing electrodes TE1 and TE2 located in the area overlapping with the hole region HA avoids the problem of the electronic module 500 being covered by the first sensing electrode TE1 or the second sensing electrode TE2.

[0241] Figure 8 This is a cross-sectional view of an electronic panel according to an exemplary embodiment of the present invention. For ease of explanation, Figure 8 It shows that it is set with Figure 7A A cross-sectional view of the panel hole MH area of ​​the electronic panel 200-H shown. Referring below... Figure 8 The inventive concept is described below. Meanwhile, in conjunction with reference to... Figures 1A to 7C Components that are described in the same way are given the same reference numerals, and repeated descriptions will be omitted.

[0242] For ease of explanation, the width of the panel hole MH is in Figure 8 The middle part is shown as relatively narrow. For example... Figure 8 As shown, the hole region HA can include panel hole MH and line region LA.

[0243] The panel aperture MH passes through the electronic panel 200-H. Specifically, the panel aperture MH can pass through the base substrate BS, the first insulating layer 10, the deposited pattern ELP, the first inorganic layer 61, and the second inorganic layer 63.

[0244] The deposited pattern ELP may include at least one of the light-emitting layer EL and the second electrode E2 in the configuration of the light-emitting element ELD. The deposited pattern ELP may be a pattern formed separately from the light-emitting element ELD formed in the effective area AA when forming the light-emitting layer EL or the second electrode E2. On the other hand, in the electronic panel 200-H according to this exemplary embodiment, the deposited pattern ELP may be omitted.

[0245] The line area LA can be the area between the panel hole MH and the effective area AA. In the plan view, the line area LA can surround the panel hole MH. In the line area LA, recessed portions GV1, GV2 and GV3, dam portion DMP, signal line SL of display unit 210-H and detection line TSL_H of input sensing unit 220-H can be set.

[0246] The recessed portions GV1, GV2, and GV3 may be spaced apart from each other. The recessed portions GV1, GV2, and GV3 are illustrated illustratively in a direction away from the effective area AA and close to the panel hole MH. Each of the first recessed portion GV1, the second recessed portion GV2, and the third recessed portion GV3 has a closed line shape surrounding the panel hole MH or a discontinuous line shape surrounding at least a portion of the edge of the panel hole MH, and is not limited to any one of the exemplary embodiments.

[0247] Each of the recessed portions GV1, GV2, and GV3 is defined as being recessed from the upper surface of the base substrate BS. Each of the recessed portions GV1, GV2, and GV3 can be formed by removing at least a portion of the base substrate BS. Each of the recessed portions GV1, GV2, and GV3 may be provided with a deposited pattern ELP and may be covered by at least one of the first inorganic layer 61 and the second inorganic layer 63.

[0248] The electronic panel 200-H according to the present invention also includes recessed portions GV1, GV2, and GV3, thereby blocking the continuity between the deposited pattern ELP and the light-emitting element ELD. Therefore, damage to the element disposed in the effective area AA can be prevented by cutting off the penetration path of external moisture or oxygen.

[0249] The deposited pattern ELP disposed in each of the recessed portions GV1, GV2, and GV3 is covered by a first inorganic layer 61 or a second inorganic layer 63, thereby preventing the deposited pattern ELP from transferring to other devices and affecting them during the manufacturing process of the electronic panel 200-H. Therefore, the process reliability of the electronic panel 200-H can be enhanced. On the other hand, this is illustrative, and in the electronic panel 200-H of the exemplary embodiment conceived according to the present invention, the recessed portions GV1, GV2, and GV3 may be provided as a single portion, or may be omitted, and are not limited to any one of the exemplary embodiments. Alternatively, more than three recessed portions may be provided.

[0250] In the online region LA, the dam portion DMP is configured to divide the formation area of ​​the organic layer 62 into predetermined regions and prevent further expansion. For example, the dam portion DMP can prevent the organic layer 62 from overflowing from the effective region AA toward the panel hole MH. Multiple dam portion DMPs can be configured and can be positioned between the recessed portions GV1, GV2, and GV3. The dam portion DMP is shown as a laminated structure comprising a first layer P11, a second layer P12, and a third layer P13. However, this is illustrative, and the dam portion DMP can have a single-layer structure, a double-layer structure, or a structure with four or more layers, and is not limited to any one exemplary embodiment.

[0251] In the electronic panel 200-H according to the present invention, a planarization layer FL_H may be disposed in the via region HA. The planarization layer FL_H covers the non-planar surface defined by the dam portion DMP or recess portions GV1, GV2, and GV3 disposed in the line region LA to provide a flat surface FL_SH on the upper portion. The flat surface FL_SH of the planarization layer FL_H may define a plane substantially identical to the flat surface 60_S of the sixth insulating layer 60. For example, the encapsulation layer (sixth insulating layer 60) may include a non-planar surface overlapping the via region HA, and the planarization layer FL_H may be disposed on the non-planar surface overlapping the via region HA to provide the flat surface FL_SH.

[0252] The detection pattern SP_H and the detection line TSL_H can be disposed on the flat surface 60_S of the sixth insulating layer 60 and the flat surface FL_SH of the planarization layer FL_H. The detection line TSL_H can be the first connection pattern BP1 (see...). Figure 7C ) or the second connection pattern BP2 (see Figure 7CThe pattern of the through-hole region HA in the display unit 210-H. For example, at least some of the detection patterns SP1 and SP2 and the connecting patterns BP1 and BP2 can be disposed on the planarization layer FL_H to overlap with the non-planar surface that overlaps with the through-hole region HA in the planar view. According to the concept of the present invention, by further including the planarization layer FL_H, the area where the detection line TSL_H can be disposed can extend to the through-hole region HA where the dam portion DMP or the groove portions GV1, GV2 and GV3 are formed. Therefore, the process reliability of the input sensing unit 220-H disposed on the display unit 210-H can be enhanced, and the electrical reliability can be enhanced.

[0253] The electronic panel 200-H according to the present invention may further include a metal pattern MTL disposed in the hole region HA. The metal pattern MTL may be disposed along the edge of the panel hole MH and cover at least a portion of the planarization layer FL_H. The metal pattern MTL may be spaced apart from the detection line TSL_H. Therefore, electrical short circuits between the metal pattern MTL and the detection line TSL_H can be prevented.

[0254] The metal pattern MTL prevents the planarization layer FL_H from being damaged by lasers or other means during the formation of the panel aperture MH. Furthermore, since the detection line TSL_H is spaced apart from the metal pattern MTL, it also prevents the detection line TSL_H from being damaged by lasers or other means.

[0255] According to the present invention, the input sensing unit 220-H can be disposed in the hole region HA with a non-flat surface, thereby enhancing the design freedom of the input sensing unit 220-H. Furthermore, according to the present invention, even if a panel hole MH is formed, the area of ​​the detection line TSL_H can be reliably ensured, thereby preventing a decrease in the reliability of the input sensing unit 220-H.

[0256] According to the present invention, since the input sensing unit can be disposed on a non-flat surface, the area of ​​the input sensing unit disposed on the display unit can be ensured. Therefore, an electronic panel with enhanced integration of the input sensing unit and enhanced reliability can be stably provided.

[0257] Although exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these exemplary embodiments, but rather that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the inventive concept as defined in the appended claims.

Claims

1. Electronic panels, including: A display unit includes: a plurality of pixels; an encapsulation layer covering the pixels; and a planarization layer disposed on the encapsulation layer, wherein the display unit includes, in a planar view, an effective area for displaying an image and a peripheral area adjacent to the effective area; And an input sensing unit, disposed on the display unit and configured to detect external input, including a plurality of sensing electrodes disposed in the effective area and a plurality of detection lines connected to the sensing electrodes; The upper surface of the encapsulation layer includes: A flat surface is provided in the effective area; and A first non-flat surface is disposed in the peripheral region and is curved compared to the flat surface, wherein the planarization layer covers the first non-flat surface, and The input sensing unit is disposed above the flat surface and also above the first non-flat surface. The effective region includes a hole region. In this process, at least some of the pixels located in the hole region are removed. The encapsulation layer further includes a second non-planar surface that overlaps with the hole region; The electronic panel further includes a hole planarization layer disposed on a second non-planar surface overlapping the hole region. Each of the sensing electrodes includes multiple detection patterns and multiple connection patterns, wherein each of the multiple connection patterns is disposed between the detection patterns and connects two adjacent detection patterns. Wherein, at least some of the detection pattern and the connection pattern are disposed on the hole planarization layer to overlap with the second non-planar surface that overlaps with the hole region in the planar view.

2. The electronic panel according to claim 1, wherein, The upper surface of the planarization layer is parallel to the planar surface.

3. The electronic panel according to claim 2, wherein, At least a portion of the planarization layer covers the planar surface.

4. The electronic panel according to claim 3, wherein, The planarization layer completely covers the planar surface.

5. The electronic panel according to claim 1, wherein, The upper surface of the planarization layer defines a plane that is the same as the plane of the planar surface.

6. The electronic panel according to claim 1, wherein, The encapsulation layer includes a first inorganic layer, a second inorganic layer disposed on the first inorganic layer, and an organic layer disposed between the first inorganic layer and the second inorganic layer. Wherein, the non-planar surface does not overlap with the organic layer in the planar view.

7. The electronic panel according to claim 6, wherein, The display unit further includes a dam portion, which is disposed in the peripheral area and does not overlap with the organic layer in the plan view. The planarization layer is configured to overlap with the dam portion in the plan view.

8. The electronic panel according to claim 1, wherein, The detection line is disposed on the planarization layer and is configured to overlap with the non-planar surface in the plan view.

9. Electronic devices, including: An electronic panel configured to display images and detect external input; as well as The electronic module overlaps with the electronic panel in the plan view. The electronic panel includes: The base substrate includes an effective region and a peripheral region adjacent to the effective region; Multiple pixels are disposed on the base substrate and configured to display the image in the effective area; An encapsulation layer includes an upper surface comprising a flat surface and a first non-flat surface, wherein the flat surface is defined in the effective region and overlaps with the pixel in the planar view, and the first non-flat surface is defined in the peripheral region and is curved compared to the flat surface; A planarization layer is disposed on the first non-planar surface; And an input sensing unit, disposed on the encapsulation layer and the planarization layer, including multiple sensing electrodes and multiple detection lines connected to the sensing electrodes. A hole region is defined in the region of the effective area that overlaps with the electronic module. In this process, at least some of the pixels located in the hole region are removed. The encapsulation layer further includes a second non-planar surface that overlaps with the hole region; The electronic panel further includes a hole planarization layer, which is disposed on the second non-planar surface overlapping the hole region. Each of the sensing electrodes includes multiple detection patterns and multiple connection patterns, wherein each of the multiple connection patterns is disposed between the detection patterns and connects two adjacent detection patterns. Wherein, at least some of the detection pattern and the connection pattern are disposed on the hole planarization layer to overlap with the second non-planar surface that overlaps with the hole region in the planar view.

10. The electronic device according to claim 9, wherein, At least some of the sensing electrodes located in the hole region are removed.

11. The electronic device according to claim 9, wherein, The electronic panel also includes a panel aperture defined in the aperture region and extending through the electronic panel. The electronic module is configured to overlap with the panel hole.

12. The electronic device according to claim 11, wherein, The connection pattern, which is located in the hole area, extends along the edge of the panel hole.

13. The electronic device according to claim 9, wherein, The electronic panel also includes a dam section disposed in the peripheral area. The planarization layer overlaps with the dam portion in the plan view.

14. The electronic device according to claim 13, wherein, Some of the detection lines are arranged on the planarization layer to overlap with the dam portion in the plan view.

15. The electronic device according to claim 9, wherein, The planarization layer covers at least a portion of the planar surface.

16. The electronic device according to claim 15, wherein, The planarization layer is configured on the flat surface to overlap with the effective area.

17. The electronic device according to claim 9, wherein, The upper surface of the planarization layer defines a plane that is the same as the plane of the planar surface.

18. The electronic device according to claim 9, wherein, The upper surface of the planarization layer defines a plane parallel to the planar surface.

19. Electronic panels, including: The display unit includes an effective area for displaying an image and a peripheral area adjacent to the effective area; Multiple pixels; An encapsulation layer is formed in the display unit and includes a first flat surface and a first non-flat surface, wherein the first flat surface is disposed in the effective region and extends into a portion of the peripheral region, and the first non-flat surface is disposed in the peripheral region; a planarization layer is disposed on the non-flat surface of the encapsulation layer and provides a second flat surface; An input sensing unit is disposed on the first flat surface and the second flat surface and configured to detect external input; The input sensing unit includes: The system comprises multiple sensing electrodes and multiple detection lines, wherein the multiple sensing electrodes are disposed in the effective region, and the multiple detection lines are disposed on the second flat surface, connected to the sensing electrodes, and overlap with the first non-flat surface of the encapsulation layer in a planar view. The effective region includes a hole region. In this process, at least some of the pixels located in the hole region are removed. The encapsulation layer further includes a second non-planar surface that overlaps with the hole region; The electronic panel further includes a hole planarization layer disposed on a second non-planar surface overlapping the hole region. Each of the sensing electrodes includes multiple detection patterns and multiple connection patterns, wherein each of the multiple connection patterns is disposed between the detection patterns and connects two adjacent detection patterns. Wherein, at least some of the detection pattern and the connection pattern are disposed on the hole planarization layer to overlap with the second non-planar surface that overlaps with the hole region in the planar view.

20. The electronic panel according to claim 19, wherein, The input sensing unit further includes a detection insulating layer that covers the first flat surface and the second flat surface.

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