Wafer testing structure and method

Abstract

The present invention relates to the field of wafer testing. Disclosed are a wafer testing structure and method, wherein the wafer testing structure includes a wafer and multiple cluster units formed on the wafer. The cluster units include multiple integrated circuits (ICs) and a test control unit. The test terminals of each IC are connected to an input terminal of the test control unit via a switch circuit. The control terminal of the switch circuit is connected to a control output terminal of the test control unit. The test control unit is provided with an output terminal for communicating with a CP test pin card. The present invention can reduce the number of CP test pin cards and the number of needle insertions, improve wafer CP testing efficiency, and reduce wafer CP testing costs.

Description

Technical Field

[0001] The present invention belongs to the field of wafer testing, and in particular relates to a wafer testing structure and method. Background Art

[0002] Every IC (integrated circuit) must undergo wafer probing (CP) before post-processing to verify the proper functionality of the IC die and identify defective IC dies. CP testing has become a critical step in process control, finished product yield management, product quality, and reducing testing costs.

[0003] CP testing uses a test instrument to contact the pads (PADs) on the wafer via a probe card to transmit electrical signals. Existing testing methods require each IC on the wafer to be individually probed. This approach has drawbacks: with advances in semiconductor manufacturing processes, the number of bare ICs on a single wafer is increasing (for example, RFID tag ICs can hold tens of thousands of bare ICs on a single wafer). This requires an increasing number of probe cards and a higher number of probes to perform CP testing, resulting in low test efficiency and high testing costs. Improvements are necessary. Summary of the Invention

[0004] The purpose of the present invention is to provide a wafer testing structure and method to solve the above-mentioned technical problems.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a wafer test structure, including a wafer and multiple cluster units formed on the wafer, the cluster units including multiple ICs and a test control unit, the test ends of each IC are connected to the input end of the test control unit through a switching circuit, the control end of the switching circuit is connected to the control output end of the test control unit, and the test control unit is provided with an output end for communicating with the CP test pin card.

[0006] Furthermore, a power line and a ground line connected to the plurality of cluster units are formed on the wafer, and the power line is used to provide power to each cluster unit.

[0007] Furthermore, the multiple ICs of each cluster unit are evenly divided into N groups, and the test control unit is provided with N input terminals, and the N input terminals correspond one-to-one to the N groups of ICs, where N is an integer greater than 1, and the number of ICs in each group of ICs is n. The test control unit is provided with n control output terminals, and the control terminals of the n switching circuits corresponding to each group of ICs are respectively connected to the n control output terminals.

[0008] Furthermore, the test control unit is composed of an MCU processor and an ADC circuit. The MCU processor is connected to the ADC circuit, and the input end of the ADC circuit is connected to N input ends of the test control unit.

[0009] Furthermore, the number of the ADC circuit is one, the ADC circuit has N channels, and the input ends of the N channels are respectively connected to the N input ends of the test control unit.

[0010] Furthermore, the number of the ADC circuits is N, and the input terminals of the N ADC circuits are respectively connected to the N input terminals of the test control unit.

[0011] Furthermore, the switch circuit is implemented using a MOS tube.

[0012] Furthermore, the IC is an RFID chip IC.

[0013] The present invention also provides a wafer testing method, comprising the following steps:

[0014] S1, providing a wafer;

[0015] S2, forming a plurality of cluster units on the wafer, the cluster units including a plurality of ICs and a test control unit, wherein a test terminal of each IC is connected to an input terminal of the test control unit via a switch circuit, a control terminal of the switch circuit is connected to a control output terminal of the test control unit, and the test control unit has an output terminal;

[0016] S3, power is supplied to the cluster unit, and the test control unit controls each switch circuit to conduct accordingly, tests each IC in turn, and records the position of the IC, the result value, and the result judgment value;

[0017] S4, using the test needle card of the test machine to communicate with the output end of the test control unit to read the test result of the cluster unit.

[0018] Beneficial technical effects of the present invention:

[0019] The present invention sets cluster units on the wafer and adopts a cluster method to perform testing, which can greatly reduce the number of CP test needle cards and the number of needle insertions, improve the wafer CP test efficiency, and reduce the wafer CP test cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 Schematic diagram of the structure of the wafer test structure according to the first embodiment of the present invention;

[0022] Figure 2 This is a schematic structural diagram of a cluster unit according to the first embodiment of the present invention;

[0023] Figure 3 This is a schematic structural diagram of a cluster unit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0024] To further illustrate various embodiments, the present invention is provided with accompanying drawings. These drawings form part of the present disclosure and are primarily used to illustrate the embodiments and, in conjunction with the relevant description in the specification, to explain the operating principles of the embodiments. By referring to these drawings, one of ordinary skill in the art will understand other possible embodiments and the advantages of the present invention. The components in the figures are not drawn to scale, and similar reference numerals are generally used to represent similar components.

[0025] The present invention will now be further described with reference to the accompanying drawings and specific embodiments.

[0026] Example 1

[0027] like Figure 1 and 2 As shown, a wafer test structure includes a wafer 1 and multiple cluster units 2 formed on the wafer 1. The cluster unit 2 includes multiple ICs 21 and a test control unit 22. The test end of each IC 21 in each cluster unit 2 is connected to the input end of the test control unit 22 through a switch circuit 23. The control end of the switch circuit 23 is connected to the control output end of the test control unit 22 (not shown in the figure to avoid overly complicated wiring). The test control unit 22 is provided with an output end for contacting and communicating with the CP test pin card.

[0028] In this specific embodiment, the IC 21 is an RFID tag IC, but is not limited thereto. In other embodiments, the IC 21 may also be various other ICs.

[0029] In this specific embodiment, the multiple ICs 21 of each cluster unit 2 are arranged around the test control unit 2, making the structure compact, reducing the size of each cluster unit 2, reducing the waste of the wafer 1, and thus reducing the cost, but the present invention is not limited thereto.

[0030] In this specific embodiment, each cluster unit 2 includes 200 ICs 21, but is not limited thereto. In other embodiments, the number of ICs 21 in each cluster unit 2 can be set according to actual needs, such as more than 200 or less than 200.

[0031] Preferably, the 200 ICs 21 of each cluster unit 2 are evenly divided into N groups. In this specific embodiment, the 200 ICs 21 of each cluster unit 2 are evenly divided into 10 groups, that is, each group has 20 ICs 21. The test control unit 22 is provided with 10 input terminals 223, and the 10 input terminals 223 correspond one-to-one to the 10 groups of ICs 21, that is, one input terminal 223 is simultaneously connected to 20 ICs 21 in a group of ICs 21. The test control unit 22 is provided with 20 control output terminals, and the control terminals of the 20 switch circuits 23 corresponding to each group of ICs 21 are respectively connected to the 20 control output terminals, that is, each control output terminal of the test control unit 22 is simultaneously connected to the control terminal of a switch circuit 23 in each group of ICs 21. By adopting this structure, the number of IO ports can be greatly saved, and it is easy to manufacture and low in cost.

[0032] Of course, in other embodiments, the multiple ICs 21 of each cluster unit 2 may also be evenly divided into more than 10 groups or less than 10 groups. The specific selection can be made based on actual conditions, which will not be elaborated here.

[0033] Of course, in other embodiments, the multiple ICs 21 of each cluster unit 2 may not be grouped and may be connected to the same input terminal 223 , and the switch circuit 23 corresponding to each IC 21 may be connected to a control output terminal respectively.

[0034] In this specific embodiment, the test control unit 22 is composed of an MCU processor 222 and an ADC circuit 221. The MCU processor 222 is connected to the ADC circuit 221, and the input end of the ADC circuit 221 is connected to N input ends 223 of the test control unit 22. The test control unit 22 structure is simple and easy to implement, but the present invention is not limited to this. In other embodiments, other existing test control units may be used, such as an MCU processor with ADC acquisition function.

[0035] In this specific embodiment, there is one ADC circuit 221, which has 10 channels. The input terminals of the 10 channels are respectively connected to the 10 input terminals 223. During testing, each control output terminal simultaneously selects one IC 21 in each group of ICs 21, and the ADC circuit 221 collects data from the 10 channels using a polling method. Using a single ADC circuit 221 provides a simple structure, a small size, and low cost, but the present invention is not limited to this embodiment.

[0036] In this specific embodiment, the switch circuit 23 is preferably implemented by a MOS switch, which has high sensitivity and low energy consumption, but is not limited thereto. In other embodiments, the switch circuit 23 may also be implemented by other existing switch tubes.

[0037] In this specific embodiment, a power line 3 and a ground line 4 connected to multiple cluster units 2 are also formed on the wafer 1. The power line 3 is used to provide power to each cluster unit 2. By adopting this structure, unified power supply for multiple cluster units 2 can be achieved, the number of power supply pads (PADs) can be reduced, the process difficulty can be reduced, and the cost can be reduced, but it is not limited to this.

[0038] In this specific embodiment, the output end of the test control unit 22 includes a pair of communication ports 2221 and a status indication port 2222. Both the communication port 2221 and the status indication port 2222 are formed with solder pads for performing needle communication connection with the test needle card of the test machine.

[0039] Example 2

[0040] like Figure 3 As shown, the difference between this embodiment and the first embodiment is that the number of ADC circuits 221 in this embodiment is 10, and the input terminals of the 10 ADC circuits 221 are respectively connected to the 10 input terminals 223 of the test control unit 22, so that 10 ICs 21 can be tested simultaneously, which greatly improves the test efficiency.

[0041] Of course, in other embodiments, the number of ADC circuits 221 may be more than 1 and less than 10, such as 5. Each ADC circuit 221 has two channels connected to two input terminals 223, which not only improves the test efficiency but also controls the number of ADC circuits 221 to a certain extent, thereby avoiding excessive costs.

[0042] The present invention also provides a wafer testing method, comprising the following steps:

[0043] S1, providing a wafer 1.

[0044] S2, forming a plurality of the above-mentioned cluster units 2 on the wafer 1. The formation process can adopt the existing semiconductor processing technology, which is a very mature existing technology and will not be described in detail.

[0045] S3, power is supplied to the cluster unit 2 through the power line 3 and the ground line 4, and the test control unit 22 controls each switch circuit 23 to be turned on accordingly, tests each IC 21 in turn, and records the position, result value and result judgment value of the IC 21.

[0046] S4, use the test needle card of the test machine to connect with the communication port 2221 and the status indication port 2222 (output end) of the test control unit 22 for needle communication. The test machine detects the electrical level of the status indication port 2222. After it changes from a high level to a low level, it can communicate through the communication port 2221 to read the test result of the cluster unit 2. With one set of needle cards and one needle insertion, 200 ICs 21 can be tested, which greatly reduces the number of CP test needle cards and the number of needle insertions, improves the wafer CP test efficiency, and reduces the wafer CP test cost.

[0047] The present invention is particularly suitable for CP testing of small-sized ICs that are used without subsequent packaging, such as CP testing of RFID tag ICs.

[0048] Although the present invention has been particularly shown and described in conjunction with preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made to the present invention without departing from the spirit and scope of the invention as defined in the appended claims, and all such changes are within the scope of protection of the present invention.

Claims

1. A wafer testing structure, characterized in that: The device comprises a wafer and a plurality of cluster units formed on the wafer. The cluster units comprise a plurality of ICs and a test control unit. The test end of each IC is connected to the input end of the test control unit via a switch circuit. The control end of the switch circuit is connected to the control output end of the test control unit. The test control unit is provided with an output end for communicating with a CP test pin card. A power line and a ground line connected to the plurality of cluster units are also formed on the wafer, and the power line is used to provide power to each cluster unit; The multiple ICs of each cluster unit are evenly divided into N groups. The test control unit is provided with N input terminals, and the N input terminals correspond one-to-one to the N groups of ICs, where N is an integer greater than 1, and the number of ICs in each group is n. The test control unit is provided with n control output terminals, and the control terminals of the n switch circuits corresponding to each group of ICs are respectively connected to the n control output terminals. The test control unit is composed of an MCU processor and an ADC circuit. The MCU processor is connected to the ADC circuit, and the input end of the ADC circuit is connected to N input ends of the test control unit.

2. The wafer testing structure according to claim 1, wherein: There is one ADC circuit, and the ADC circuit has N channels. Input ends of the N channels are respectively connected to the N input ends of the test control unit.

3. The wafer testing structure according to claim 1, wherein: The number of the ADC circuits is N, and the input terminals of the N ADC circuits are respectively connected to the N input terminals of the test control unit.

4. The wafer testing structure according to claim 1, wherein: The switch circuit is implemented using a MOS tube.

5. The wafer testing structure according to claim 1, wherein: The IC is an RFID chip IC.

6. A wafer testing method, characterized in that: The steps include: S1, providing a wafer; the wafer having the wafer test structure according to any one of claims 1 to 5; S2, power is supplied to the cluster unit, and the test control unit controls each switch circuit to conduct accordingly, tests each IC in turn, and records the position of the IC, the result value, and the result judgment value; S3, using the test needle card of the test machine to communicate with the output end of the test control unit to read the test result of the cluster unit.

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