Method for manufacturing semiconductor device

Abstract

The technical problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can reduce the moisture contained in the organic planarization film and reduce the variation in the characteristics of the thin film transistor. The semiconductor device of the present invention includes: a semiconductor substrate formed with a thin film transistor having a source electrode; a pixel electrode; an organic planarization film; a barrier film formed on the organic planarization film; a capacitor insulating film formed on the barrier film; and a through hole, which is provided in the organic planarization film, the barrier film and the capacitor insulating film so that the source electrode is exposed. The through hole has: a first portion where the organic planarization film is exposed; and a second portion where the organic planarization film is not exposed. The pixel electrode is connected to the source electrode inside the through hole.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular, to a semiconductor device such as a display device having a thin film transistor using an oxide semiconductor and a method for manufacturing the semiconductor device. Background Art

[0002] In a light-emitting device represented by an electroluminescent display device, a technique for suppressing degradation of a light-emitting element as much as possible has been proposed (for example, Japanese Patent Application Laid-Open No. 2004-79509 (Patent Document 1)).

[0003] Japanese Patent Gazette No. 2004-79509 discloses: "In the first opening, the barrier film 122 and the first passivation film 118 are in contact with each other in the range of 1 to 5 μm (typically 2 to 3 μm), so that the planarization film 121 is completely sealed by the barrier film 122 and the first passivation film 118. As a result, even if an organic resin film or a spin-on glass (SOG) film is used as the planarization film 121, the generation of degassing caused by time-dependent changes can be effectively suppressed, thereby suppressing the time-dependent degradation of the transistor characteristics and the light-emitting element caused thereby. (See paragraph 0028)".

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2004-79509 Summary of the invention

[0007] Technical problem to be solved by the invention

[0008] The organic resin film (organic planarizing film) used as the planarizing film may contain a lot of water. When the water contained in the organic resin film diffuses into the formation region of the thin film transistor (TFT), the characteristics of the thin film transistor may change.

[0009] An object of the present invention is to provide a technology capable of reducing the amount of water contained in an organic planarizing film and reducing the variation in the characteristics of a thin film transistor.

[0010] Other technical problems and new features will become clear from the description of this specification and the accompanying drawings.

[0011] Means for solving technical problems

[0012] The outline of the representative technical aspects of the present invention will be briefly described as follows.

[0013] That is, the present invention provides a semiconductor device, characterized in that it includes: a semiconductor substrate having a thin film transistor having a source electrode; a first electrode; an organic planarization film; a barrier film formed on the organic planarization film; an insulating film formed on the barrier film; and a through hole, which is provided in the organic planarization film, the barrier film and the insulating film so that the source electrode is exposed. The through hole has: a first portion where the organic planarization film is exposed; and a second portion where the organic planarization film is not exposed. The first electrode is connected to the source electrode inside the through hole.

[0014] In addition, the present invention provides a method for manufacturing a semiconductor device, characterized in that it includes: a process of preparing a semiconductor substrate, on which a thin film transistor having a source electrode is formed; a process of selectively forming an organic planarization film in a manner that the upper surface of the above-mentioned source electrode is exposed; a process of performing a first baking process; a process of forming a barrier film on the above-mentioned organic planarization film after performing the above-mentioned first baking process; a process of selectively forming a second electrode on the above-mentioned barrier film; a process of forming an insulating film in a manner that covers the above-mentioned second electrode and the above-mentioned barrier film; a process of forming a through hole in the above-mentioned barrier film and the above-mentioned insulating film to expose the above-mentioned upper surface of the above-mentioned source electrode and the above-mentioned organic planarization film at the bottom of the above-mentioned through hole; and a process of performing a second baking process after the process of exposing the above-mentioned upper surface of the above-mentioned source electrode and the above-mentioned organic planarization film.

[0015] In addition, the present invention provides a method for manufacturing a semiconductor device, characterized in that it includes: a process of preparing a semiconductor substrate, on which a thin film transistor having a source electrode is formed; a process of selectively forming an organic planarization film in a manner that the upper surface of the above-mentioned source electrode is exposed; a process of performing a first baking process; a process of forming a barrier film on the above-mentioned organic planarization film after performing the above-mentioned first baking process; a process of forming a through hole in the above-mentioned barrier film so that the above-mentioned upper surface of the above-mentioned source electrode and the above-mentioned organic planarization film are exposed at the bottom of the above-mentioned through hole; a process of performing a second baking process after the process of exposing the above-mentioned upper surface of the above-mentioned source electrode and the above-mentioned organic planarization film; and a process of selectively forming a second electrode on the above-mentioned barrier film and forming a connecting electrode in a manner that covers the above-mentioned upper surface of the above-mentioned source electrode exposed at the bottom of the above-mentioned through hole and the above-mentioned organic planarization film. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a plan view showing a structural example of a display device according to an embodiment.

[0017] Figure 2 It is along Figure 1 Cross-sectional view of line AA.

[0018] Figure 3 A diagram showing the basic structure of a pixel and an equivalent circuit of a display device.

[0019] Figure 4 This is an example of a cross-sectional view of a display device according to an embodiment.

[0020] Figure 5 It is a cross-sectional view showing a state where an organic planarizing film is formed so as to cover the drain electrode and the source electrode.

[0021] Figure 6 It is a cross-sectional view showing a state where a barrier film is formed on the organic planarizing film after the first baking step.

[0022] Figure 7 It is a cross-sectional view showing a state where a common electrode is selectively formed.

[0023] Figure 8 It is a cross-sectional view showing a state where a capacitor insulating film is formed.

[0024] Fig. 9 It is a cross-sectional view showing a state where a through hole is formed.

[0025] Fig.10 It is a cross-sectional view showing a state where pixel electrodes are selectively formed.

[0026] Fig.11 It is a cross-sectional view showing a state where an alignment film is formed.

[0027] Fig.12 It is a cross-sectional view showing an enlarged through-hole portion.

[0028] Fig.13 This is a modification example and is a cross-sectional view showing a state in which an organic planarizing film is formed so as to cover the drain electrode and the source electrode.

[0029] Fig.14 It is a cross-sectional view showing a state where a barrier film is formed on the organic planarizing film after the first baking step.

[0030] Fig.15 It is a cross-sectional view showing a state where a through hole is formed.

[0031] Fig.16 It is a cross-sectional view showing a state where a common electrode and a connection electrode are selectively formed.

[0032] Fig.17 It is a cross-sectional view showing a state where a capacitor insulating film is formed.

[0033] Fig.18 It is a cross-sectional view showing a state where a through hole is formed in a capacitor insulating film.

[0034] Fig.19 It is a cross-sectional view showing a state where pixel electrodes are selectively formed.

[0035] Fig. 20 It is a cross-sectional view showing a state where an alignment film is formed.

[0036] Description of Reference Numerals

[0037] DSP: Display Device

[0038] PNL: Display Panel

[0039] PX: Pixel

[0040] DA: Display unit

[0041] NDA: Non-display department

[0042] SE: Seals

[0043] SUB1: First substrate (TFT substrate)

[0044] SUB2: Second substrate (opposing substrate)

[0045] 100: substrate

[0046] 101: Light-shielding film

[0047] 102: Basement membrane

[0048] 103: Oxide semiconductor

[0049] 104: Gate insulating film

[0050] 105: Gate electrode

[0051] 106: Interlayer insulation film

[0052] 107: Inorganic passivation film

[0053] 110: Drain electrode

[0054] 111: Source electrode

[0055] 112: Organic planarization film

[0056] 113: Barrier film

[0057] 114: Common electrode

[0058] 115: Capacitor insulation film

[0059] 116: Pixel electrode

[0060] 117: Oriented film

[0061] 1141: Connecting electrodes DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0063] The disclosed content is only an example, and appropriate changes that can be easily thought of by those skilled in the art and that maintain the main purpose of the present invention are of course also included in the scope of the present invention. In the drawings, in order to make the description clearer, the width, thickness, shape, etc. of each part are schematically shown compared with the actual form, but it is only an example and does not limit the interpretation of the present invention.

[0064] In this specification and each drawing, the same elements as those described with respect to the previously described drawings are denoted by the same reference numerals in some cases, and the detailed description thereof is appropriately omitted.

[0065] In this embodiment, a liquid crystal display device is disclosed as an example of a display device among semiconductor devices. The liquid crystal display device can be used in various devices such as smartphones, tablet terminals, mobile phone terminals, personal computers, television receivers, vehicle-mounted devices, and game devices.

[0066] In this specification and claims, the expressions "upper" and "lower" when describing the drawings express the relative positional relationship between the structure concerned and other structures. Specifically, when viewed from the side, the direction from the first substrate (array substrate) to the second substrate (opposing substrate) is defined as "upper", and the opposite direction is defined as "lower".

[0067] "Inside" and "outside" indicate the relative positional relationship of two parts with respect to the display area. That is, "inside" refers to a side relatively close to the display area with respect to a part, and "outside" refers to a side relatively far from the display area with respect to a part. However, the definitions of "inside" and "outside" mentioned here refer to the definition when the liquid crystal display device is not bent.

[0068] "Display device" refers to all display devices that use a display panel to display images. "Display panel" refers to a structure that uses an electro-optical layer to display images. For example, the term display panel sometimes refers to a display unit including an electro-optical layer, and sometimes refers to a structure in which other optical components (for example, polarization components, backlight sources, touch panels, etc.) are installed on the display unit. Here, as long as there is no technical contradiction, the "electro-optical layer" may include a liquid crystal layer, an electrochromic (EC) layer, an organic light-emitting diode (OLED), a micron LED (μLED), etc. Therefore, for the embodiments described below, a liquid crystal panel including a liquid crystal layer is exemplified as a display panel, but it does not exclude application to display panels including the above-mentioned other electro-optical layers.

[0069] (Implementation Method)

[0070] Hereinafter, the embodiments will be described using the drawings.

[0071] (Overall Configuration Example of Display Device)

[0072] Figure 1 It is a plan view showing a structural example of a display device according to an embodiment. Figure 2 It is along Figure 1 The cross-sectional view of the AA line. Figure 1 and Figure 2 In the embodiment, the display device DSP includes a display panel PNL, a flexible printed circuit board 1, an IC chip 2 and a circuit board 3. The display panel PNL is a liquid crystal display panel, including a first substrate (TFT substrate, also called an array substrate) SUB1, a second substrate (also called an opposing substrate) SUB2, a liquid crystal layer LC and a seal SE.

[0073] The display panel PNL includes: a display portion (display area) DA for displaying an image; and a frame-shaped non-display portion (non-display area) NDA surrounding the periphery of the display portion DA. The second substrate SUB2 is opposite to the first substrate SUB1. The first substrate SUB1 has a mounting portion MA extending in the second direction Y than the second substrate SUB2. The seal SE is located in the non-display portion NDA, bonds the first substrate SUB1 to the second substrate SUB2, and seals the liquid crystal layer LC.

[0074] Reference Figure 2 A lower polarizing plate 200 is attached under the first substrate SUB1, and an upper polarizing plate 201 is attached to the upper side of the second substrate SUB2. The combination of the first substrate SUB1, the second substrate SUB2, the lower polarizing plate 200, the upper polarizing plate 201 and the liquid crystal layer LC is called a display panel PNL. The display panel PNL itself does not emit light, so a backlight source 202 is configured on the back of the display panel PNL.

[0075] A plurality of external terminals are formed on the mounting portion MA. The flexible wiring board 1 is connected to the plurality of external terminals of the mounting portion MA. A driver IC 2 for supplying image signals and the like is mounted on the flexible wiring board 1. A circuit board 3 is connected to the flexible wiring board 1, and the circuit board 3 is used to supply signals and power to the driver IC 2 and the display device DSP from the outside. Alternatively, the IC chip 2 may be mounted on the mounting portion MA. The IC chip 2 has a built-in display driver DD that outputs a signal required for image display in a display mode for displaying an image.

[0076] like Figure 1 As shown, in the display area DA, a plurality of pixels PX are formed in a matrix, and each pixel PX has a thin film transistor (TFT) as a switching element. In the non-display area NDA, a driving circuit for controlling and driving the scanning lines, image signal lines, etc. is formed. The driving circuit has a thin film transistor (TFT).

[0077] The TFT used as the switching element of the pixel PX needs to have a small leakage current. The TFT formed by an oxide semiconductor can reduce the leakage current. Hereinafter, the oxide semiconductor will be referred to as Oxide (Oxide Semiconductor). Oxide includes IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), IGO (Indium Gallium Oxide), etc. Hereinafter, Oxide will be used to represent oxide semiconductors for explanation. The mobility of carriers in oxide is small, so it is difficult to use TFTs using oxide to form a driving circuit built into the display device DSP.

[0078] On the other hand, LTPS (Low Temperature Poly-Si) has high mobility and is suitable as a TFT constituting a driving circuit. In liquid crystal display devices, polycrystalline silicon (Poly-Si) mostly uses LTPS. Poly-Si is also referred to as LTPS below. The mobility of a TFT formed by LTPS is large, so a driving circuit can be formed using a thin film transistor (TFT) using LTPS.

[0079] That is, the thin film transistor (TFT) used in the pixel PX needs to have a small leakage current, so an oxide semiconductor (Oxide) is used, and the thin film transistor (TFT) used in the driving circuit needs to have a large mobility, so LTPS is used, which is reasonable.

[0080] However, depending on the application product, the mobility of amorphous silicon (a-Si) or oxide may also be designed. Therefore, the technical solution of the present invention is also effective when a-Si or oxide is used in the driving circuit.

[0081] The display panel PNL of this embodiment can be a transmissive type, a reflective type or a semi-transmissive type, wherein the transmissive type has a transmissive display function of displaying an image by selectively transmitting light from the back side of the first substrate SUB1, the reflective type has a reflective display function of displaying an image by selectively reflecting light from the front side of the second substrate SUB2, and the semi-transmissive type has a transmissive display function and a reflective display function.

[0082] The detailed structure of the display panel PNL is omitted here, but the display panel PNL can have any structure corresponding to the following display modes: a display mode using a longitudinal electric field along the normal line of the main surface of the substrate; a display mode using an oblique electric field inclined in an oblique direction relative to the main surface of the substrate; and a display mode using a suitable combination of the above-mentioned transverse electric field, longitudinal electric field and oblique electric field. The main surface of the substrate mentioned here is a surface parallel to the XY plane defined by the first direction X and the second direction Y.

[0083] (Circuit Configuration Example of Display Device)

[0084] Figure 3 It is a diagram showing the basic structure of a pixel PX and an equivalent circuit of a display device DSP. A plurality of pixels PX are arranged in a matrix in a first direction X and a second direction Y. A plurality of scan lines G (G1, G2...) are connected to a scan line driving circuit GD. A plurality of signal lines S (S1, S2...) are connected to a signal line driving circuit SD. A plurality of common electrodes CE (CE1, CE2...) are connected to a voltage supply unit CD of a common voltage (Vcom) and are arranged across a plurality of pixels PX. One pixel PX is connected to one scan line, one signal line and one common electrode CE. The scan line G and the signal line S may not necessarily extend in a straight line, but may be partially bent. For example, it is assumed that the signal line S extends in the second direction Y even if a portion of it is bent. The scan line driving circuit GD, the signal line driving circuit SD and the voltage supply unit CD are composed of thin film transistors (TFT).

[0085] Each pixel PX includes a switching element SW, a pixel electrode PE, a common electrode CE, a liquid crystal layer LC, etc. The switching element SW is, for example, composed of a thin film transistor (TFT), and is electrically connected to a scanning line G and a signal line S. The scanning line G is connected to the switching element SW of each pixel PX arranged in a first direction X. The signal line S is connected to the switching element SW of each pixel PX arranged in a second direction Y. The pixel electrode PE is electrically connected to the switching element SW. The pixel electrodes PE are each opposite to the common electrode CE, and the liquid crystal layer LC is driven by an electric field generated between the pixel electrode PE and the common electrode CE. The holding capacitor CS is, for example, formed between an electrode having the same potential as the common electrode CE and an electrode having the same potential as the pixel electrode PE.

[0086] (Cross-sectional structure of display device)

[0087] Figure 4 2 is an example of a cross-sectional view of a display device according to an embodiment. Figure 4 As shown, the display device DSP uses a thin film transistor (TFT) using an oxide semiconductor (Oxide) 103. The oxide semiconductor TFT has a small leakage current and is therefore suitable as a thin film transistor constituting a switching element SW of a pixel PX.

[0088] Oxide semiconductors include IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), and IGO (Indium Gallium Oxide). In this embodiment, InGaZnO classified as IGZO is used as the oxide semiconductor.

[0089] Figure 4 Although a thin film transistor having a top gate structure is shown, the thin film transistor is not limited thereto and may be a thin film transistor having a bottom gate structure.

[0090] exist Figure 4 In the embodiment, a light shielding film 101 is formed of metal on a substrate 100 formed of a resin such as glass or polyimide. The metal may be the same as the gate electrode 105 described later. The light shielding film 101 is used to shield light so that light from a backlight source does not irradiate the channel portion of the oxide semiconductor TFT formed later.

[0091] A base film 102 is formed so as to cover the light shielding film 101. The base film 102 is used to prevent the oxide semiconductor 103 formed thereon from being contaminated by impurities from the substrate 100. The base film 102 is often formed of a stacked film of a silicon oxide film (hereinafter referred to as SiO) and a silicon nitride film (hereinafter referred to as SiN). In addition, a barrier film formed of, for example, an aluminum oxide film (hereinafter referred to as AlO) may be further stacked.

[0092] exist Figure 4 In the present invention, an oxide semiconductor 103 constituting an oxide semiconductor TFT is formed on a base film 102. The thickness of the oxide semiconductor 103 is, for example, 10 nm to 100 nm. A gate insulating film 104 is formed of, for example, SiO to cover the oxide semiconductor 103. A gate electrode 105 is formed to cover the gate insulating film 104.

[0093] An interlayer insulating film 106 is formed of, for example, SiO so as to cover the gate electrode 105. The thickness of the interlayer insulating film 106 is, for example, 150 nm to 300 nm. An inorganic passivation film 107 is formed of, for example, SiN on the interlayer insulating film 106. The thickness of the inorganic passivation film 107 is, for example, 100 to 200 nm. It may be a single layer of SiO, a single layer of SiN, or a lower layer of SiN and an upper layer of SiO.

[0094] Through holes 108 and 109 are formed to penetrate the inorganic passivation film 107, the interlayer insulating film 106, and the gate insulating film 104. The through holes 108 and 109 are provided to connect the oxide semiconductor 103 to the drain electrode 110 or to connect the oxide semiconductor 103 to the source electrode 111. Figure 4 The drain electrode 110 in the circuit is also served by the image signal line (source line S). Figure 4 The source electrode 111 in FIG. 1 is connected to the pixel electrode (PE, first electrode) 116 via the through hole 130. The through hole 130 has a first portion 131 and a second portion 132 as described below.

[0095] exist Figure 4 In the embodiment, an organic planarization film 112 is formed in a manner covering the drain electrode 110 and the source electrode 111. The organic planarization film (organic resin film) 112 is formed of, for example, acrylic resin or the like. The organic planarization film 112 has a function as a planarization film, and is formed to be thicker by about 2 μm to 4 μm in order to reduce the stray capacitance between the image signal line (source line S) and the common electrode (CE, second electrode) 114. A barrier film 113 is formed on the organic planarization film 112. The barrier film 113 is formed of, for example, SiN. The organic planarization film 112 is dehydrated by the first baking process, and the barrier film 113 has a function of preventing the organic planarization film 112 from absorbing water after the first baking process.

[0096] On the barrier film 113, a common electrode 114 is formed by a transparent conductive film such as ITO (Indium Tin Oxide). The common electrode 114 is formed in a planar shape for a plurality of pixels. A capacitor insulating film 115 is formed by SiN in a manner covering the common electrode 114. A pixel electrode 116 is formed by a transparent conductive film such as ITO (Indium Tin Oxide) in a manner covering the capacitor insulating film 115. The pixel electrode 116 is formed in a comb-tooth shape. The capacitor insulating film 115 forms a pixel capacitor (CS) between the common electrode 114 and the pixel electrode 116. In order to connect the source electrode 111 and the pixel electrode 116, a through hole 130 is formed in the organic planarizing film 112, the barrier film 113 and the capacitor insulating film 115.

[0097] An alignment film 117 is formed to cover the pixel electrode 116. The alignment film 117 defines the initial alignment direction of the liquid crystal molecules 301. The alignment treatment of the alignment film 117 can be an alignment treatment using friction or an optical alignment treatment using polarized ultraviolet rays. In the IPS (In Plane Switching) method, a pretilt angle is not required, so the optical alignment treatment is advantageous.

[0098] exist Figure 4 In the embodiment, a counter substrate 201 is arranged with a liquid crystal layer 300 interposed therebetween. A color filter 202 and a black matrix 203 are formed on the counter substrate 201, and a protective film (overcoat film) 204 is formed thereon. An alignment film 205 is formed on the protective film 204. The function and alignment treatment of the alignment film 205 are the same as those of the alignment film 117 on the substrate 100 side.

[0099] exist Figure 4 When a voltage is applied between the common electrode 114 and the pixel electrode 116, the following Figure 4 The electric lines of force indicated by the arrows rotate the liquid crystal molecules 301 to control the transmittance of light from the backlight source caused by the liquid crystal layer 300. By controlling the transmittance of light for each pixel, an image is displayed.

[0100] exist Figure 4In the embodiment, the through hole 130 has a first portion 131 and a second portion 132. The first portion 131 is a portion of the organic planarizing film 112 that is not covered by the barrier film 113 and the capacitor insulating film 115. The second portion 132 is a portion of the organic planarizing film 112 that is covered by the barrier film 113 and the capacitor insulating film 115. The through hole 130 has the first portion 131, and therefore, in the second baking process of the organic planarizing film 112 after the through hole 130 is formed, the moisture contained in the organic planarizing film 112 is easily dehydrated from the first portion 131. Therefore, the amount of moisture contained in the organic planarizing film 112 can be reduced, and thus, the variation of the characteristics of the thin film transistor caused by the diffusion of the moisture contained in the organic planarizing film 112 to the formation region of the thin film transistor can be reduced.

[0101] (Semiconductor device manufacturing process)

[0102] Next, use Figure 5 to Figure 11 A method for manufacturing a semiconductor device used in a display device DSP will be described.

[0103] Figure 5 1 is a cross-sectional view showing a state where an organic planarization film 112 is selectively formed so as to cover the drain electrode 110 and the source electrode 111. Here, as a semiconductor device, a semiconductor substrate on which the drain electrode 110 and the source electrode 111 of an oxide semiconductor TFT are formed is prepared. Figure 4 It is formed as follows as described in .

[0104] On a substrate 100 formed of a resin such as glass or polyimide, a metal light shielding film 101 is formed, a base film 102 is formed of a stacked film of SiO and SiN so as to cover the light shielding film 101, and an oxide semiconductor 103 constituting an oxide semiconductor TFT is formed of InGaZnO on the base film 102. Next, a gate insulating film 104 is formed of SiO so as to cover the oxide semiconductor 103, and an interlayer insulating film 106 is formed of SiO so as to cover the gate electrode 105. Then, an inorganic passivation film 107 is formed of SiN on the interlayer insulating film 106. Thereafter, through holes 108 and 109 are formed so as to penetrate the inorganic passivation film 107, the interlayer insulating film 106, and the gate insulating film 104. A drain electrode 110 and a source electrode 111 are provided in the through holes 108 and 109 to connect the oxide semiconductor 103 to the drain electrode 110 or to connect the oxide semiconductor 103 to the source electrode 111. Thus, a semiconductor substrate on which the drain electrode 110 and the source electrode 111 of the oxide semiconductor TFT are formed is prepared.

[0105] Then, if Figure 5As shown in FIG. 1 , an organic planarizing film 112 is selectively formed in a manner covering the drain electrode 110 and the source electrode 111. In the organic planarizing film 112, a through hole 134 is selectively formed in a manner that a portion of the upper surface of the source electrode 111 is exposed. The organic planarizing film 112 is formed of, for example, an acrylic resin or the like. After the organic planarizing film 112 is formed, a first baking step for removing moisture contained in the organic planarizing film 112 is performed. The moisture contained in the organic planarizing film 112 is removed as shown by the arrow.

[0106] Figure 6 1 is a cross-sectional view showing a state where a barrier film 113 is formed on the organic planarizing film 112 after the first calcining step. After the first calcining step, the barrier film 113 is formed so as to cover the organic planarizing film 112 and the source electrode 111 exposed at the bottom of the through hole 134. The barrier film 113 is formed of, for example, SiN. The barrier film 113 has a function of preventing the organic planarizing film 112 from absorbing moisture after the first calcining step.

[0107] Figure 7 1 is a cross-sectional view showing a state where a common electrode 114 is selectively formed. The common electrode 114 is selectively formed on the barrier film 113. The common electrode (second electrode) 114 is formed of a transparent conductive film (first transparent conductive film) such as ITO (Indium Tin Oxide).

[0108] Figure 8 1 is a cross-sectional view showing a state where a capacitor insulating film 115 is formed. The capacitor insulating film 115 is formed so as to cover the barrier film 113 and the common electrode 114. The capacitor insulating film 115 is formed of SiN.

[0109] Fig. 9 It is a cross-sectional view representing the state of forming a through hole 130. Through hole 130 is formed in organic planarizing film 112, barrier film 113 and capacitor insulating film 115. Through hole 130 can be formed in the following manner: at the bottom of through hole 134 and the side near the bottom, selectively remove barrier film 113 and capacitor insulating film 115 so as to form perforations in barrier film 113 and capacitor insulating film 115 so that source electrode 111 and organic planarizing film 112 are exposed. When barrier film 113 and capacitor insulating film 115 are formed by SIN, the patterning process of barrier film 113 and capacitor insulating film 115 by photolithography and dry etching can be carried out in a lump.

[0110] The through hole 130 is provided to connect the source electrode 111 and the pixel electrode 116. The through hole 130 has a first portion 131 and a second portion 132. The first portion 131 is a portion of the organic planarization film 112 that is not covered by the barrier film 113 and the capacitor insulating film 115. The second portion 132 is a portion of the organic planarization film 112 that is covered by the barrier film 113 and the capacitor insulating film 115. After the through hole 130 is formed, a second baking process is performed. In the second baking process, the through hole 130 has a first portion 131, so that the moisture contained in the organic planarization film 112 is easily dehydrated from the first portion 131 as shown by the arrow. Therefore, the amount of moisture contained in the organic planarization film 112 can be reduced. As a result, the characteristic variation of the thin film transistor caused by the diffusion of the moisture contained in the organic planarization film 112 to the formation region of the thin film transistor can be reduced.

[0111] Fig.10 1 is a cross-sectional view showing a state where a pixel electrode 116 is selectively formed. A pixel electrode (first electrode) 116 is formed by a transparent conductive film (second transparent conductive film) such as ITO (Indium Tin Oxide) in a manner covering the capacitor insulating film 115. The pixel electrode 116 is formed in a comb-tooth shape. The pixel electrode 116 is formed inside the through hole 130 and is connected to the source electrode 111.

[0112] Fig.11 1 is a cross-sectional view showing a state where an alignment film 117 is formed. The alignment film 117 is formed so as to cover the capacitor insulating film 115 and the pixel electrode 116. The semiconductor substrate formed as described above is formed on Figure 1 and Figure 2 The first substrate (SUB1) described in .

[0113] Fig.12 FIG. 1 is a cross-sectional view showing an enlarged portion of the through hole 130. Fig.12 The capacitive insulating film 115 is omitted in the figure. Fig.12 As shown, regarding the depth H of the through hole 130 provided in the organic planarization film 112, since the film thickness of the organic planarization film 112 is formed relatively thick at about 2 μm to 4 μm, the depth H of the through hole 130 is also relatively deep. Therefore, it can be considered that at the bottom of the through hole 130, the exposure amount during the resist patterning is insufficient, resulting in a state where the resist is easily left. However, if it is on the source electrode 111, reflected light can be expected, so it is more or less easy to avoid the resist residue caused by insufficient exposure. Therefore, in order to avoid the film residue of the blocking film 113 caused by the resist residue, it is preferred that the opening line width Wb of the blocking film 113 is less than the width WSL of the source electrode 111.

[0114] In addition, although it also depends on the standing time and environment after the first baking step (dehydration baking step) of the organic planarizing film 112 until the barrier film 113 is formed, in order to ensure the minimum dehydration path in the second baking step, it is preferred that the opening size L of the first portion 131 where a part of the barrier film 113 is removed is at least 10 nm. The opening size L is preferably 50 nm or more.

[0115] According to the embodiment, the following effects can be obtained.

[0116] 1) A barrier film 113 is formed on the organic planarization film 112. The barrier film 113 is preferably formed of SIN. In the portion of the through hole 130 provided in the organic planarization film 112, a portion of the barrier film 113 is removed, and a first portion 131 of the organic planarization film 112 is exposed. The organic planarization film 112 after the first baking process absorbs less water, so even if the first portion 131 as a water release path is small or has a small area, the organic planarization film 112 can be subjected to a second baking process to remove the water from the organic planarization film 112. Therefore, it is not easy for water to remain in the organic passivation film 112 after the second baking process.

[0117] 2) Water is less likely to remain in the organic planarizing film 112 , and thus, it is possible to reduce the variation in the characteristics of the thin film transistor caused by diffusion of water contained in the organic planarizing film 112 into the formation region of the thin film transistor.

[0118] 3) The period from the first baking step for dehydrating the organic planarizing film 112 to the formation of the barrier film 113 is short, so that water absorption of the organic planarizing film 112 can be reduced.

[0119] 4) Since both the barrier film 113 and the capacitor insulating film 115 are formed of a film composed of the same component such as SIN, the barrier film 113 and the capacitor insulating film 115 can be patterned by photolithography and dry etching at the same time.

[0120] (Variation Example)

[0121] Next, use Figures 13 to 20 A method for manufacturing a semiconductor device according to a modified example will be described.

[0122] Fig.13 It is a cross-sectional view showing a state where an organic planarizing film is selectively formed so as to cover the drain electrode and the source electrode. Fig.13 and Figure 5 Similarly, as a semiconductor device, a semiconductor substrate on which a drain electrode 110 and a source electrode 111 of an oxide semiconductor TFT are formed is prepared. Figure 5It is formed as follows as described in .

[0123] On a substrate 100 formed of a resin such as glass or polyimide, a metal light shielding film 101 is formed, a base film 102 is formed of a stacked film of SiO and SiN so as to cover the light shielding film 101, and an oxide semiconductor 103 constituting an oxide semiconductor TFT is formed of InGaZnO on the base film 102. Next, a gate insulating film 104 is formed of SiO so as to cover the oxide semiconductor 103, and an interlayer insulating film 106 is formed of SiO so as to cover the gate electrode 105. Then, an inorganic passivation film 107 is formed of SiN on the interlayer insulating film 106. Thereafter, through holes 108 and 109 are formed so as to penetrate the inorganic passivation film 107, the interlayer insulating film 106, and the gate insulating film 104. A drain electrode 110 and a source electrode 111 are provided in the through holes 108 and 109 to connect the oxide semiconductor 103 to the drain electrode 110 or to connect the oxide semiconductor 103 to the source electrode 111. Thus, a semiconductor substrate on which the drain electrode 110 and the source electrode 111 of the oxide semiconductor TFT are formed is prepared.

[0124] Then, if Fig.13 As shown in FIG. 1 , an organic planarizing film 112 is selectively formed in a manner covering the drain electrode 110 and the source electrode 111. In the organic planarizing film 112, a through hole 134 is selectively formed in a manner that a portion of the upper surface of the source electrode 111 is exposed. The organic planarizing film 112 is formed of, for example, an acrylic resin or the like. After the organic planarizing film 112 is formed, a first baking step is performed to remove moisture contained in the organic planarizing film 112. The moisture contained in the organic planarizing film 112 is removed as shown by the arrow.

[0125] Fig.14 It is a cross-sectional view showing a state where a barrier film is formed on the organic planarizing film after the first baking step. Fig.14 and Figure 6 Similarly, after the first calcination step, a barrier film 113 is formed to cover the organic planarization film 112 and the source electrode 111 exposed at the bottom of the through hole 134. The barrier film 113 is formed of, for example, SiN. The barrier film 113 has a function of preventing the organic planarization film 112 from absorbing moisture after the first calcination step.

[0126] Fig.151 is a cross-sectional view showing a state where a through hole 130 is formed. The through hole 130 is formed in the organic planarizing film 112 and the barrier film 113. The through hole 130 can be formed by selectively removing the barrier film 113 at the bottom of the through hole 134 and the side surface near the bottom to form an opening in the barrier film 113 so that the source electrode 111 and the organic planarizing film 112 are exposed.

[0127] The through hole 130 is provided to connect the source electrode 111 and the pixel electrode 116. The through hole 130 has a first portion 131 and a second portion 132. The first portion 131 is a portion of the organic planarizing film 112 that is not covered by the barrier film 113. The second portion 132 is a portion of the organic planarizing film 112 that is covered by the barrier film 113. After the through hole 130 is formed, a second baking process is performed. In the second baking process, the through hole 130 has the first portion 131, so that the moisture contained in the organic planarizing film 112 is easily removed from the first portion 131 as shown by the arrow. Therefore, the amount of moisture contained in the organic planarizing film 112 can be reduced. As a result, the characteristic variation of the thin film transistor caused by the diffusion of moisture contained in the organic planarizing film 112 to the formation area of ​​the thin film transistor can be reduced.

[0128] Fig.16 1 is a cross-sectional view showing a state where a common electrode 114 and a connecting electrode 1141 are selectively formed. A common electrode (second electrode) 114 is selectively formed on the barrier film 113, and a connecting electrode 1141 is selectively formed at the bottom of the through hole 130. The common electrode 114 and the connecting electrode 1141 are formed of a transparent conductive film (first transparent conductive film) such as ITO (Indium Tin Oxide). At the bottom of the through hole 130, the connecting electrode 1141 is formed in a manner that covers the exposed source electrode 111, the organic planarizing film 112 exposed in the first portion 131, and the barrier film 113 corresponding to the lower side of the second portion 132. That is, the connecting electrode 1141 has a function as a cover that covers the organic planarizing film 112 exposed in the first portion 131, so that the organic planarizing film 112 becomes less likely to absorb moisture. The connecting electrode 1141 also has a function as an electrode for connecting the source electrode 111 and the pixel electrode 116.

[0129] Fig.17 1 is a cross-sectional view showing a state where a capacitor insulating film 115 is formed. The capacitor insulating film 115 is formed so as to cover the barrier film 113, the common electrode 114, and the connection electrode 1141. The capacitor insulating film 115 is formed of SiN.

[0130] Fig.181 is a cross-sectional view showing a state where a through hole 135 is formed in the capacitor insulating film 115. The through hole 135 is formed by selectively removing the capacitor insulating film 115 to expose the connection electrode 1141.

[0131] Fig.19 1 is a cross-sectional view showing a state where a pixel electrode 116 is selectively formed. The pixel electrode (first electrode) 116 is formed by a transparent conductive film (second transparent conductive film) such as ITO (Indium Tin Oxide) in a manner covering the capacitor insulating film 115. The pixel electrode 116 is formed in a comb-tooth shape. The pixel electrode 116 is connected to the exposed connection electrode 1141 inside the through hole 135.

[0132] Fig. 20 1 is a cross-sectional view showing a state where an alignment film 117 is formed. The alignment film 117 is formed so as to cover the capacitor insulating film 115 and the pixel electrode 116. The semiconductor substrate formed as described above is constituted Figure 1 and Figure 2 The first substrate (SUB1) described in .

[0133] According to the modification example, the following effects can be obtained similarly to the embodiment.

[0134] 1) In the portion of the through hole 130 provided in the organic planarizing film 112, a portion of the barrier film 113 is removed, and a first portion 131 of the organic planarizing film 112 is exposed. The organic planarizing film 112 after the first calcining step absorbs less moisture, so even if the first portion 131, which is a moisture release path, is small or has a small area, the moisture of the organic planarizing film 112 can be removed by performing the second calcining step on the organic planarizing film 112. Therefore, it is not easy for moisture to remain in the organic planarizing film 112 after the second calcining step.

[0135] 2) Water is less likely to remain in the organic planarizing film 112 , and thus, it is possible to reduce the variation in the characteristics of the thin film transistor caused by diffusion of water contained in the organic planarizing film 112 into the formation region of the thin film transistor.

[0136] Based on the display device described above as an embodiment of the present invention, all display devices that can be implemented by those skilled in the art by appropriately making design changes fall within the scope of the present invention as long as they include the gist of the present invention. In addition, semiconductor devices having sensor functions, etc. are also included in the scope.

[0137] In the scope of the concept of the present invention, as long as a person skilled in the art can think of various variations and modifications, these variations and modifications should also be understood to belong to the scope of the present invention. For example, for each of the above-mentioned embodiments, the embodiment obtained by the technicians appropriately adding, deleting or changing the design of the constituent elements, or adding, omitting or changing the conditions of the process, as long as it contains the gist of the present invention, is also included in the scope of the present invention.

[0138] Other effects brought about by the method described in this embodiment should of course be understood as effects brought about by the present invention as long as they can be clearly understood from the description of this specification or can be reasonably imagined by those skilled in the art.

[0139] Various technical solutions can be formed by appropriately combining the multiple components disclosed in the above embodiments. For example, several components can be deleted from all the components shown in the embodiments. Moreover, the components of different embodiments can be appropriately combined.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A step of preparing a semiconductor substrate on which a thin film transistor having a source electrode is formed; forming an organic planarization film having a first through hole through which the upper surface of the source electrode is exposed; performing a first calcination step for dehydrating water contained in the organic planarizing film; After performing the first calcination step, forming a barrier film of SiN on the organic planarization film so as to cover the organic planarization film and the first through hole; A step of selectively forming a second electrode on the barrier film; forming an insulating film so as to cover the second electrode and the barrier film; forming a second through hole in the barrier film and the insulating film in the first through hole to expose the upper surface of the source electrode and the organic planarization film; and After the step of exposing the upper surface of the source electrode and the organic planarizing film, a second baking step is performed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: include: a step of selectively forming a first electrode so as to cover the upper surface of the source electrode exposed at the bottom of the second through hole and the organic planarization film; and A step of forming an alignment film so as to cover the insulating film and the first electrode.

3. A method for manufacturing a semiconductor device, characterized in that: include: A step of preparing a semiconductor substrate on which a thin film transistor having a source electrode is formed; forming an organic planarization film having a first through hole through which the upper surface of the source electrode is exposed; performing a first calcination step for dehydrating water contained in the organic planarizing film; After performing the first calcination step, forming a barrier film of SiN on the organic planarization film so as to cover the organic planarization film and the first through hole; forming a second through hole in the barrier film within the first through hole to expose the upper surface of the source electrode and the organic planarization film; After the step of exposing the upper surface of the source electrode and the organic planarization film, performing a second baking step; and A step of selectively forming a second electrode on the barrier film and forming a connection electrode so as to cover the upper surface of the source electrode exposed at the bottom of the second through hole and the organic planarization film.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: include: forming an insulating film so as to cover the barrier film, the second electrode and the connection electrode; forming a third through hole in the insulating film so that the connection electrode is exposed; a step of selectively forming a first electrode so as to cover the connection electrode and the organic planarization film exposed inside the third through hole; and A step of forming an alignment film so as to cover the insulating film and the first electrode.

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