Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device may include a first sub-chip and a second sub-chip sequentially stacked, and a through contact portion that electrically connects the first sub-chip and the second sub-chip to each other. Each of the first sub-chip and the second sub-chip includes a substrate and a plurality of interconnection lines interposed between the substrates. The interconnection lines of the second sub-chip may include a first interconnection line and a second interconnection line having a first opening and a second opening, respectively, and the first opening and the second opening are horizontally offset from each other. The through contact portion extends from the substrate of the second sub-chip toward the first sub-chip and may include an auxiliary contact portion that extends through the first opening and the second opening toward the first sub-chip and has a bottom surface higher than a top surface of the uppermost interconnection line among the interconnection lines of the first sub-chip.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority of Korean Patent Application No. 10 - 2019 - 0018425, filed with the Korean Intellectual Property Office on February 18, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including semiconductor chips stacked at a wafer level and a method of manufacturing the same. Background Art

[0004] Due to the small size, multi - functionality, and / or low - cost characteristics of semiconductor devices, they are regarded as important components in the electronics industry. Semiconductor devices are classified into memory devices for storing data, logic devices for processing data, and hybrid devices including both memory and logic elements. To meet the growing demand for high - speed and / or low - power electronic devices, it may be necessary to implement highly reliable, high - performance, and / or multi - functional semiconductor devices. To meet these technical parameters, the complexity and / or integration density of semiconductor devices are increasing.

[0005] An image sensor is a device that converts an optical image into an electrical signal. With the continuous development of the computer and communication industries, the demand for high - performance image sensors is growing in various applications such as digital cameras, camcorders, personal communication systems, game consoles, security cameras, medical micro - cameras, and / or robots.

[0006] Image sensors are generally classified into charge - coupled device (CCD) image sensors and complementary metal - oxide - semiconductor (CMOS) image sensors. For CMOS image sensors, since a CMOS image sensor can be operated by a simple operation method and the signal processing circuit of the CMOS image sensor can be integrated on a single chip, the product size can be reduced. In addition, the CMOS image sensor has relatively low power consumption and can thus be used in products with limited battery capacity. Summary of the Invention

[0007] Some embodiments of the inventive concept provide a semiconductor device in which a through - contact portion having high structural stability is provided.

[0008] Some embodiments of the inventive concept provide a method of manufacturing a semiconductor device in which a through - contact portion having high structural stability is provided.

[0009] In some embodiments according to the inventive concept, a semiconductor device may include: a first sub-chip including a first substrate and a first plurality of interconnections on the first substrate; and a second sub-chip including a second substrate and a second plurality of interconnections on the second substrate. The second sub-chip is stacked on the first sub-chip, the first plurality of interconnections of the first sub-chip and the second plurality of interconnections of the second sub-chip are located between the first substrate and the second substrate, and a through contact portion extends from the second substrate toward the first sub-chip to electrically connect the first sub-chip and the second sub-chip to each other. The second plurality of interconnections of the second sub-chip may include a first interconnection having a first opening and a second interconnection having a second opening. The center of the second opening may be horizontally offset with respect to the center of the first opening in a direction parallel to the first substrate and the second substrate. The through contact portion may include an auxiliary contact portion extending toward the first sub-chip in the first opening and the second opening. The height of the bottom surface of the auxiliary contact portion may be higher than the height of the top surface of the uppermost interconnection among the first plurality of interconnections of the first sub-chip with respect to the first substrate.

[0010] In some embodiments according to the inventive concept, a semiconductor device may include: a first sub-chip including a first substrate and a first plurality of interconnections on the first substrate; and a second sub-chip including a second substrate and a second plurality of interconnections on the second substrate. The second sub-chip is stacked on the first sub-chip. The semiconductor device includes a through contact portion penetrating the second sub-chip and electrically connecting the first sub-chip and the second sub-chip to each other. The second plurality of interconnections of the second sub-chip may include a first interconnection having a first opening and a second interconnection having a second opening. The center of the second opening may be horizontally offset with respect to the center of the first opening. The through contact portion may include an auxiliary contact portion extending toward the first sub-chip in the first opening and the second opening and a main contact portion electrically connected to the uppermost interconnection among the first plurality of interconnections of the first sub-chip. The height of the bottom surface of the auxiliary contact portion may be higher than the height of the bottom surface of the main contact portion with respect to the first substrate.

[0011] In some embodiments according to the inventive concept, a semiconductor device may include a first substrate, lower interconnections on the first substrate, upper interconnections on the lower interconnections, and a through contact portion vertically extending from the upper interconnections to the lower interconnections to electrically connect the upper interconnections and the lower interconnections to each other. The upper interconnections may include a first interconnection having a first opening and a second interconnection having a second opening on the first interconnection. The center of the second opening may be horizontally offset with respect to the center of the first opening in a direction parallel to the first substrate. The through contact portion may include an auxiliary contact portion extending toward the first substrate in the second opening and the first opening and a main contact portion electrically connected to the lower interconnections. The height of the bottom surface of the auxiliary contact portion may be higher than the height of the bottom surface of the main contact portion with respect to the first substrate.

[0012] In some embodiments according to the inventive concept, a method of manufacturing a semiconductor device may include: forming a first sub-chip including a first substrate and a first plurality of interconnects on the first substrate; forming a second sub-chip including a second substrate and a second plurality of interconnects on the second substrate; stacking the first sub-chip and the second sub-chip facing each other; forming a via contact hole to penetrate the second sub-chip and expose the uppermost interconnect among the first plurality of interconnects of the first sub-chip; and forming a via contact portion to fill the via contact hole. The formation of the second sub-chip may include: forming a first interconnect, which is one of the second plurality of interconnects and has a first opening; and forming a second interconnect on the first interconnect to have a second opening, wherein the second opening is horizontally offset with respect to the first opening. The formation of the via contact hole may include forming an auxiliary contact hole extending through the first opening and the second opening. The height of the bottom surface of the auxiliary contact hole may be higher than the height of the top surface of the uppermost interconnect of the first sub-chip with respect to the first substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings. The drawings illustrate non-limiting example embodiments described herein.

[0014] Figure 1A 、 Figure 2A 、 Figure 3A and Figure 4A are plan views showing a method of forming a via contact portion of a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 1B 、 Figure 2B 、 Figure 3B and Figure 4B are cross-sectional views taken along lines I-I' of Figure 1A 、 Figure 2A 、 Figure 3A and Figure 4A respectively.

[0016] Figure 5 is a circuit diagram showing an example of a unit pixel included in a pixel array according to some embodiments of the inventive concept.

[0017] Figure 6 is a cross-sectional view showing a semiconductor package in which a semiconductor device according to some embodiments of the inventive concept is mounted.

[0018] Figure 7 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0019] Figure 8 is a cross-sectional view taken along lines I-I' and II-II' of Figure 7 respectively.

[0020] Figures 9 to 13 are cross-sectional views taken along lines I-I' and II-II' of Figure 7 to illustrate a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0021] Figure 14 is a cross-sectional view of a certain region of a semiconductor device according to some embodiments of the inventive concept.

[0022] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in certain example embodiments and supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the exact structure or performance characteristics of any given embodiment, and should not be construed as limiting or restricting the scope of the values or characteristics included in the example embodiments. For example, for clarity, the relative thicknesses and positions of modules, layers, regions, and / or structural elements may be reduced or enlarged. The use of like or identical reference numerals in the various drawings is intended to indicate the presence of like or identical elements or features. Detailed Description

[0023] Figure 1A , Figure 2A , Figure 3A and Figure 4A are plan views showing a method of forming a through contact of a semiconductor device according to some embodiments of the inventive concept. Figure 1B , Figure 2B , Figure 3B and Figure 4B are cross-sectional views taken along lines I-I' of Figure 1A , Figure 2A , Figure 3A and Figure 4A respectively.

[0024] Referring to Figure 1A and Figure 1B , a conductive layer CDL may be formed on a substrate SUB. Although not shown, the conductive layer CDL may be electrically connected to a device (e.g., a transistor) formed on the substrate SUB. According to some embodiments, the conductive layer CDL may be an interconnect layer on a transistor. In some embodiments, the conductive layer CDL may be a gate electrode of a transistor. In some embodiments, the conductive layer CDL may be a source / drain electrode of a transistor. The conductive layer CDL may be formed of or include at least one of the following: a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0025] A first insulating layer IDL1 may be formed on the conductive layer CDL. A first mask layer ML1 may be formed on the first insulating layer IDL1. A first opening OP1 may be formed in the first mask layer ML1. The formation of the first opening OP1 may include forming a photoresist pattern on the first mask layer ML1 and patterning the first mask layer ML1 using the photoresist pattern as an etching mask.

[0026] When measured in the second direction D2, the first opening OP1 may have a first width W1. As an example, the first opening OP1 may have the minimum feature size achievable by the exposure process used to form the photoresist pattern. The top surface of the first insulating layer IDL1 may be partially exposed through the first opening OP1.

[0027] Reference Figure 2A and Figure 2B , a second insulating layer IDL2 may be formed on the first mask layer ML1. The second insulating layer IDL2 may be located in or fill the first opening OP1. A second mask layer ML2 may be formed on the second insulating layer IDL2. A second opening OP2 may be formed in the second mask layer ML2. The second opening OP2 may have a second width W2 in the second direction D2. The second width W2 may be less than, greater than, or substantially equal to the first width W1. In other words, the planar size of the second opening OP2 may be less than, greater than, or substantially equal to the planar size of the first opening OP1.

[0028] The second opening OP2 may be formed to be offset relative to the first opening OP1. The center of the second opening OP2 may be offset relative to the center of the first opening OP1. The center of the second opening OP2 may be offset relative to the center of the first opening OP1 in one or both of the first direction D1 and the second direction D2. For example, the first direction D1 and the second direction D2 may be horizontal directions parallel to the surface of the substrate SUB, and the first direction D1 and the second direction D2 may cross each other, for example, perpendicularly. Additionally, a third direction D3 may be a vertical direction relative to the surface of the substrate SUB, for example, perpendicular to the surface of the substrate SUB. "Vertically" as mentioned in the following description may refer to the third direction D3. When observed in a plan view, the second opening OP2 and the first opening OP1 may partially overlap each other, and this partial overlap region between the first opening OP1 and the second opening OP2 will be represented by the overlap region OVR.

[0029] The overlap region OVR may have a third width W3 in the second direction D2. The third width W3 may be less than the first width W1 and may be less than the second width W2. In other words, the planar size of the overlap region OVR may be less than the planar size of the first opening OP1 and may be less than the planar size of the second opening OP2.

[0030] Reference Figure 3A and Figure 3B , a third insulating layer IDL3 may be formed on the second mask layer ML2. The third insulating layer IDL3 may be located in or fill the second opening OP2. A photoresist pattern PR may be formed on the third insulating layer IDL3. The photoresist pattern PR may define the position and shape of a viacon contact TCT to be described below.

[0031] The first to third insulating layers IDL1, IDL2, and IDL3 may be etched by using the photoresist pattern PR as an etch mask to form a viacon hole TCH. The etching process may be an anisotropic etching process. The etching process may be performed by using an etch recipe capable of selectively etching the first to third insulating layers IDL1, IDL2, and IDL3. For example, the etching process may be performed to inhibit or prevent the first mask layer ML1 and the second mask layer ML2 from being etched or damaged. In other words, the first mask layer ML1 and the second mask layer ML2 may serve as etch masks for the etching process. The etching process may be performed to expose the top surface of the conductive layer CDL.

[0032] The width of the viacon hole TCH in the second direction D2 may decrease as the distance from the conductive layer CDL (i.e., in the third direction D3) decreases. The width of the bottom TCHb of the viacon hole TCH may have substantially the same width as the overlap region OVR (i.e., the third width W3). In other words, the planar size of the bottom TCHb of the viacon hole TCH may be substantially equal to the planar size of the overlap region OVR. This may be because, during the etching process, only the portion of the first insulating layer TDL1 located below the overlap region OVR is selectively etched.

[0033] Reference Figure 4A and 4B , a viacon contact TCT may be formed by at least partially filling the viacon hole TCH with a conductive material. The photoresist pattern PR may be selectively removed. The bottom TCTb of the viacon contact TCT may contact the top surface of the conductive layer CDL. The width of the bottom TCTb of the viacon contact TCT may have substantially the same width as the overlap region OVR (i.e., the third width W3). In other words, the planar size of the bottom TCTb of the viacon contact TCT may be substantially equal to the planar size of the overlap region OVR.

[0034] In some embodiments, since the first opening OP1 of the first mask layer ML1 and the second opening OP2 of the second mask layer ML2 are formed to be offset from each other, the planar size of the bottom TCTb of the via contact TCT can be adjusted to a size smaller than the planar size of each of the first opening OP1 and the second opening OP2. That is, according to some embodiments of the inventive concept, the bottom TCTb of the via contact TCT can be formed to have a pattern size smaller than the minimum value of the pattern sizes achievable by an exposure process.

[0035] Figure 5 is a circuit diagram showing an example of a unit pixel included in a pixel array according to some embodiments of the inventive concept.

[0036] Reference Figure 5 , the unit pixel in the pixel array PA may include a photodiode PD serving as a photosensitive device. The unit pixel may include a transfer transistor TX, a reset transistor RX, a driving transistor DX, and a selection transistor SX, which may be arranged to form a readout circuit.

[0037] The photodiode PD may receive external light (e.g., visible light or infrared light) and generate photo charges from the received light. In some embodiments, the unit pixel may include a phototransistor, a photogate, or a pinned photodiode arranged together with or in place of the photodiode PD.

[0038] The photo charges generated in the photodiode PD may be transferred to the floating diffusion node FD through the transfer transistor TX. For example, when the transfer control signal TG has a first level (e.g., a high level), the transfer transistor TX may be turned on, and the photo charges generated in the photodiode PD may be transferred to the floating diffusion node FD through the turned-on transfer transistor TX.

[0039] The driving transistor DX may serve as a source follower buffer amplifier. The driving transistor DX may amplify a signal based on the amount of photo charges stored in the floating diffusion node FD. The selection transistor SX may transfer the amplified signal to the column line COL in response to a selection signal SEL. The floating diffusion node FD may be reset through the reset transistor RX. The reset transistor RX may be controlled by a reset signal RS. For example, when the reset signal RS has a first level (e.g., a high level), the reset transistor RX may be turned on, and the floating diffusion node FD may be reset.

[0040] Figure 6 is a cross-sectional view of a semiconductor package in which a semiconductor device according to some embodiments of the inventive concept is mounted. Figure 7 is a plan view of a semiconductor device according to some embodiments of the inventive concept. Figure 8 is alongFigure 7 Cross-sectional views taken along lines I-I' and II-II'.

[0041] Referring to Figure 6 、 Figure 7 and Figure 8 ,a semiconductor device 20 can be mounted on a package substrate 10. In some embodiments, the semiconductor device 20 can be an image sensor chip. A transparent substrate 40 can be disposed on the semiconductor device 20. A holder 30 can be disposed between the package substrate 10 and the transparent substrate 40. The holder 30 can support the transparent substrate 40. The holder 30 can be configured to separate the transparent substrate 40 from the semiconductor device 20 in a vertical direction.

[0042] The semiconductor device 20 can have a first surface 20a facing the package substrate 10 and a second surface 20b opposite to the first surface 20a. The semiconductor device 20 can include a first sub-chip CH1 and a second sub-chip CH2 stacked vertically. A plurality of microlenses ML can be disposed on the second surface 20b of the semiconductor device 20. Pads 8 for forming electrical connections to the semiconductor device 20 can be spaced apart from the microlenses ML.

[0043] The first sub-chip CH1 can include at least one of a logic region, a memory cell region, a peripheral circuit region, or a signal processing region. The second sub-chip CH2 can be a pixel array chip. As an example, the second sub-chip CH2 can include a pixel array of an image sensor.

[0044] Referring again to Figure 7 and Figure 8 ,the semiconductor device 20 can include a first sub-chip CH1, a second sub-chip CH2, and an interlayer 300 between the first sub-chip CH1 and the second sub-chip CH2. The first sub-chip CH1 and the second sub-chip CH2 can be stacked vertically. The interlayer 300 can be configured to physically and electrically connect the first sub-chip CH1 and the second sub-chip CH2 to each other.

[0045] The first sub-chip CH1 can include a first region RG1 and a second region RG1 spaced apart from each other. The first region RG1 can be a memory cell region in which a memory device including memory transistors is provided. As an example, the first region RG1 can be a memory cell region in which a DRAM device is provided. The second region RG2 can be a peripheral circuit region in which peripheral transistors LT are provided.

[0046] The first sub-chip CH1 can include a first substrate 100. The first substrate 100 can include a first surface 100a and a second surface 100b opposite to the first surface 100a. The second surface 100b of the first substrate 100 can be the one previously referred to Figure 6The first surface 20a of the semiconductor device 20 described above. In other words, the second surface 100b of the first substrate 100 can be disposed facing the package substrate in the semiconductor package.

[0047] Hereinafter, the first region RG1 of the first sub-chip CH1 will be described in more detail below. The device isolation layer ST that defines the first active region ACT1 can be disposed on the first region RG1 of the first substrate 100. The device isolation layer ST can include, for example, at least one of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0048] The gate line GL can be disposed in the first substrate 100 to intersect the first active region ACT1. The gate line GL can be buried in the first substrate 100. The gate line GL can be formed of or include a conductive material. For example, the conductive material can be at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0049] The gate insulating pattern GI can be interposed between each gate line GL and the first active region ACT1. The gate insulating pattern GI can include, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0050] The first capping pattern CP1 can be disposed on the top surface of each gate line GL. The top surface of the first capping pattern CP1 can be substantially coplanar with the first surface 100a of the first substrate 100. As an example, the first capping pattern CP1 can include a silicon nitride layer or a silicon oxynitride layer.

[0051] The first impurity region SD1 and a pair of second impurity regions SD2 can be disposed in each first active region ACT1. The pair of second impurity regions SD2 can be spaced apart from each other in the second direction D2, and the first impurity region SD1 is interposed therebetween.

[0052] The first impurity region SD1 can be disposed between a pair of adjacent gate lines GL in the first active region ACT1. The second impurity regions SD2 can be disposed in two opposite portions of the first active region ACT1 on both sides of the pair of gate lines GL. The second impurity regions SD2 can be spaced apart from each other, and the pair of gate lines GL is interposed therebetween. The first impurity region SD1 can have the same conductivity type as the second impurity regions SD2.

[0053] The first lower insulating layer 110 can be disposed on the first surface 100a of the first substrate 100 to cover and / or overlap with the first active region ACT1. The first lower insulating layer 110 can include a silicon oxide layer or a silicon oxynitride layer.

[0054] The bit line BL can be disposed in the first lower insulating layer 110. Each bit line BL can be electrically connected to the first impurity region SD1. The bit line BL can include at least one of, for example, a doped semiconductor material, a conductive metal nitride, a metal material, or a metal-semiconductor compound. The second capping pattern CP2 can be disposed on the top surface of each bit line BL. The second capping pattern CP2 can include, for example, a silicon nitride layer or a silicon oxynitride layer.

[0055] The first contact CT1 and the landing pad LP can be disposed in the first lower insulating layer 110. Each landing pad LP can be disposed on the first contact CT1. Each first contact CT1 can be electrically connected to the second impurity region SD2. The first contact CT1 and the landing pad LP can include at least one conductive material, such as doped silicon or a metal material.

[0056] The capacitor CAP can be disposed on the first lower insulating layer 110. Each capacitor CAP can include a first electrode LEL1, a second electrode LEL2, and a dielectric layer DIL interposed between the first electrode LEL1 and the second electrode LEL2. The first electrode LEL1 can be respectively disposed on the landing pad LP. Each first electrode LEL1 can be electrically connected to the second impurity region SD2 through the landing pad LP and the first contact CT1.

[0057] Each first electrode LEL1 can be a cylindrical or cup-shaped pattern having a bottom and sidewall portions vertically extending from the bottom. The bottom and the sidewall portions of each first electrode LEL1 can have substantially the same thickness. The first electrode LEL1 can have substantially the same planar diameter.

[0058] The first electrode LEL1 can include at least one of a doped semiconductor material, a conductive metal nitride, a metal material, or a metal-semiconductor compound. As an example, the first electrode LEL1 can include a metal nitride layer (e.g., a titanium nitride layer (TiN), a titanium silicon nitride layer (TiSiN), a titanium aluminum nitride layer (TiAlN), a tantalum nitride layer (TaN), a tantalum silicon nitride layer (TaSiN), a tantalum aluminum nitride layer (TaAlN), or a tungsten nitride layer (WN)).

[0059] The dielectric layer DIL can be disposed on the surface of the first electrode LEL1 with a uniform thickness. For example, the dielectric layer DIL can include at least one high-k dielectric material (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2).

[0060] The second electrode LEL2 may be disposed on the dielectric layer DIL. The second electrode LEL2 may cover and / or surround a plurality of first electrodes and / or overlap with the plurality of first electrodes, and the dielectric layer DIL may be interposed between the second electrode LEL2 and the first electrode LEL1. A part of the second electrode LEL2 may fill the inner space of the cylindrical or cup-shaped first electrode LEL1. The second electrode LEL2 may include at least one of a doped semiconductor material, a conductive metal nitride, a metal material, or a metal-semiconductor compound. As an example, the second electrode LEL2 may include a metal nitride layer and a semiconductor layer stacked in sequence.

[0061] The second to fifth lower insulating layers 120, 130, 140, and 150 may be stacked on the capacitor CAP. At least one second contact portion CT2 may be provided to penetrate the second lower insulating layer 120 and be electrically connected to the second electrode LEL2. Interconnect lines IL and via plugs VI may be provided in the third to fifth lower insulating layers 130, 140, and 150. The via plugs VI may connect the interconnect lines IL located at different vertical heights to each other. As an example, the interconnect lines IL of the first sub-chip CH1 may be electrically connected to the capacitor CAP through the second contact portion CT2. The interconnect lines IL of the first sub-chip CH1 may include lower interconnect lines of the semiconductor device 20.

[0062] Hereinafter, the second region RG2 of the first sub-chip CH1 will be described in more detail. The device isolation layer ST may be disposed on the second region RG2 of the first substrate 100. The device isolation layer ST may define a second active region ACT2 in the second region RG2 of the first substrate 100.

[0063] Peripheral transistors LT may be disposed on the second active region ACT2. Specifically, the peripheral transistors LT may include gate electrodes arranged to cross the second active region ACT2 and impurity regions formed in the upper region of the second active region ACT2.

[0064] The first to fifth lower insulating layers 110, 120, 130, 140, and 150 may be sequentially formed on the peripheral transistors LT. The first lower insulating layer 110 on the second region RG2 may cover the peripheral transistors LT. At least one third contact portion CT3 may be provided to penetrate the second lower insulating layer 120 and the first lower insulating layer 110 and be electrically connected to the peripheral transistors LT. Interconnect lines IL and via plugs VI may be provided in the third to fifth lower insulating layers 130, 140, and 150.

[0065] The second sub-chip CH2 may include a first region RG1 and a second region RG2 spaced apart from each other. The first region RG1 of the second sub-chip CH2 may be disposed on the first region RG1 of the first sub-chip CH1, and the second region RG2 of the second sub-chip CH2 may be disposed on the second region RG2 of the first sub-chip CH1.

[0066] The first region RG1 of the second sub-chip CH2 may be an image sensing region in which an image sensor is disposed. The second region RG2 of the second sub-chip CH2 may be a peripheral region. As an example, the pad 8 on the second surface 20b of the semiconductor device 20 may be disposed on the second region RG2 of the second sub-chip CH2.

[0067] The second sub-chip CH2 may include a second substrate 200, a photoelectric conversion device PCD, a floating diffusion region FDA, and a readout circuit device RCX formed on the second substrate 200. As an example, the second substrate 200 may be a p-type semiconductor substrate doped with impurities.

[0068] The readout circuit device RCX may be disposed on the first surface 200a of the second substrate 200. The readout circuit device RCX may include a plurality of transistors (e.g., Figure 5 the transfer transistor TX, reset transistor RX, drive transistor DX, and selection transistor SX) for transmitting or amplifying an electrical signal (e.g., photo-charge) corresponding to incident light as described in detail Figure 5 .

[0069] The color filter CF and the microlens ML may be disposed on the second surface 200b of the second substrate 200 to provide incident light to the photoelectric conversion device PCD. The second surface 200b may be opposite to the first surface 200a.

[0070] Each photoelectric conversion device PCD may include a photodiode. The photoelectric conversion device PCD may be disposed in the second substrate 200. The photoelectric conversion device PCD may generate photo-charge corresponding to incident light. For example, an electron-hole pair corresponding to incident light may be generated in each photoelectric conversion device PCD. The photoelectric conversion device PCD may be doped to have a different conductivity type (e.g., n-type) from the second substrate 200.

[0071] Each color filter CF may be disposed on a corresponding photoelectric conversion device PCD. The color filters CF may be arranged in a matrix shape to provide a color filter array.

[0072] In some embodiments, the color filter array may be disposed in the form of a Bayer pattern including red, green, and blue color filters. Each color filter CF may be one of the red, green, and blue color filters.

[0073] In some embodiments, the color filter array may be disposed in the form of a Bayer pattern including yellow, magenta, and cyan color filters. Each color filter CF may be one of the yellow, magenta, and cyan color filters.

[0074] Each microlens ML can be disposed on a corresponding color filter CF. Each microlens ML can adjust the path of incident light to allow the incident light to be focused on a photoelectric conversion device PCD disposed therebelow. The microlenses ML can be arranged in a matrix shape to provide a microlens array.

[0075] Each photoelectric conversion device PCD and the corresponding color filter CF and microlens ML can define a pixel PX of the image sensor.

[0076] An antireflection layer 205 can be disposed between the second surface 200b of the second substrate 200 and the color filter CF. The antireflection layer 205 can prevent the incident light from being reflected by the second surface 200b of the second substrate 200. As an example, the antireflection layer 205 can be a multilayer structure in which at least two thin films with different refractive indexes are alternately stacked. If the number of stacked thin films increases, the amount of light incident on the photoelectric conversion device PCD can be increased.

[0077] The first to fourth upper insulating layers 210, 220, 230, and 240 can be stacked on the first surface 200a of the second substrate 200. Interconnection lines IL and via plugs VI can be disposed in the first to fourth upper insulating layers 210, 220, 230, and 240. The via plugs VI can connect the interconnection lines IL located at different vertical heights with respect to the first substrate 100 and / or the second substrate 200 to each other. As an example, the interconnection lines IL of the second sub-chip CH2 can be electrically connected to the readout circuit RCX. The interconnection lines IL of the second sub-chip CH2 can include upper interconnection lines of semiconductor devices 20.

[0078] The photoelectric conversion device PCD of the second sub-chip CH2 can be configured to generate photo charges from incident light incident through the second surface 200b of the second substrate 200. In other words, the semiconductor device 20 according to the present embodiment can be a back-illuminated image sensor (BIS).

[0079] An insertion layer 300 can be interposed between the first sub-chip CH1 and the second sub-chip CH2. The insertion layer 300 can physically connect the first sub-chip CH1 and the second sub-chip CH2 to each other. The first sub-chip CH1 and the second sub-chip CH2 can be attached to each other through the insertion layer 300. The insertion layer 300 can include a first insulating layer 350a and a second insulating layer 350b. As an example, the first insulating layer 350a and the second insulating layer 350b can be formed of or include silicon oxide.

[0080] The through contact portion TCT can be disposed on the second region RG2 of the semiconductor device 20. The through contact portion TCT can extend vertically from the second substrate 200 of the second sub-chip CH2 to the fifth lower insulating layer 150 of the first sub-chip CH1. In other words, the through contact portion TCT can be arranged to penetrate the second sub-chip CH2 and the insertion layer 300.

[0081] The through contact portion TCT can be in contact with the interconnection line IL of the second sub-chip CH2. The through contact portion TCT can be in contact with the uppermost interconnection line among the interconnection lines IL of the first sub-chip CH1. The through contact portion TCT can electrically connect the interconnection line IL of the second sub-chip CH2 to the uppermost interconnection line among the interconnection lines IL of the first sub-chip CH1. In other words, the first sub-chip CH1 and the second sub-chip CH2 can be electrically connected to each other through the through contact portion TCT.

[0082] The through contact portion TCT can include a main body portion BP, an auxiliary contact portion AC extending vertically from the main body portion BP toward the first sub-chip CH1, and a main contact portion MC extending vertically from the main body portion BP toward the first sub-chip CH1.

[0083] Specifically, the interconnection line IL of the second sub-chip CH2 can include a first interconnection line IL1 and a second interconnection line IL2 disposed on the second region RG2. The first interconnection line IL1 can be disposed in the second upper insulating layer 220, and the second interconnection line IL2 can be disposed in the fourth upper insulating layer 240. The first interconnection line IL1 can be closer to the second substrate 200 than the second interconnection line IL2. In other words, the first interconnection line IL1 can be the lower interconnection line of the second sub-chip CH2, and the second interconnection line IL2 can be the upper interconnection line of the second sub-chip CH2.

[0084] The main body portion BP can be disposed on the first interconnection line IL1. The top surface of the main body portion BP can be substantially coplanar with the second surface 200b of the second substrate 200. The bottom surface of the main body portion BP can be in contact with the top surface of the first interconnection line IL1.

[0085] The main contact portion MC can extend from the bottom surface of the main body portion BP toward the first sub-chip CH1. The main contact portion MC can penetrate the insertion layer 300 and can be coupled to the uppermost interconnection line among the interconnection lines IL of the first sub-chip CH1. The bottom surface of the main contact portion MC can be lower than the bottom surface of the auxiliary contact portion AC. In other words, the vertical distance between the bottom surface of the main contact portion MC and the first substrate 100 can be shorter than the vertical distance between the bottom surface of the auxiliary contact portion AC and the first substrate 100. The bottom of the main contact portion MC can be in direct contact with the uppermost interconnection line among the interconnection lines IL of the first sub-chip CH1. The main contact portion MC extending toward the first sub-chip CH1 can be in contact with the side surfaces of the first interconnection line IL1 and the second interconnection line IL2.

[0086] The first interconnecting line IL1 may have a first opening OP1, and the second interconnecting line IL2 may have a second opening OP2. The first opening OP1 and the second opening OP2 may be horizontally offset from each other. As an example, the center OP1c of the first opening OP1 may be offset from the center OP2c of the second opening OP2 in one or both of a first direction D1 and a second direction D2.

[0087] The auxiliary contact portion AC may pass through the first opening OP1 and the second opening OP2 and may extend vertically toward the first sub-chip CH1. The width of the auxiliary contact portion AC in the second direction D2 may decrease as the distance from the first sub-chip CH1 decreases. Specifically, the width of the auxiliary contact portion AC may suddenly decrease in the second opening OP2. For example, the auxiliary contact portion AC may have a fourth width W4 in the first opening OP1 and a fifth width W5 in the second opening OP2. The fifth width W5 may be less than the fourth width W4.

[0088] The planar shape of the bottom ACb of the auxiliary contact portion AC may be defined by an overlapping region between the first opening OP1 and the second opening OP2. The width of the bottom ACb of the auxiliary contact portion AC may be substantially equal to or less than the width of the overlapping region between the first opening OP1 and the second opening OP2.

[0089] The auxiliary contact portion AC may be spaced apart from the uppermost interconnecting line among the interconnecting lines IL of the first sub-chip CH1. The bottom surface of the auxiliary contact portion AC may be located at a height higher than the top surface of the uppermost interconnecting line among the interconnecting lines IL of the first sub-chip CH1. The auxiliary contact portion AC may not penetrate the entire insertion layer 300. The height of the bottom surface of the auxiliary contact portion AC may be higher than the height of the bottom surface of the insertion layer 300 and may be lower than the height of the top surface of the insertion layer 300.

[0090] The auxiliary contact portion AC may be in contact with the first interconnecting line IL1 and the second interconnecting line IL2. The auxiliary contact portion AC may increase the contact area between the via contact portion TCT and the interconnecting line IL of the second sub-chip CH2. This area increase of the auxiliary contact portion AC may result in a reduction in the resistance between the via contact portion TCT and the interconnecting line IL of the second sub-chip CH2. In addition, the auxiliary contact portion AC may be configured to increase the physical adhesion strength between the via contact portion TCT and the second sub-chip CH2. The auxiliary contact portion AC may act like a nail and may fix the via contact portion TCT to the second sub-chip CH2.

[0091] Figures 9 to 13 is a cross-sectional view taken along Figure 7 lines I-I' and II-II' to illustrate a method of manufacturing a semiconductor device according to an embodiment of the inventive concept. For the sake of brevity of description, previously referred toFigures 6 to 8 The elements described above can be identified by the same reference numerals and will not be described further.

[0092] Reference Figure 9 , a first substrate 100 including a first region RG1 and a second region RG2 can be provided. A device isolation layer ST can be formed in the first substrate 100. The device isolation layer ST can be formed by using a shallow trench isolation (STI) process. The device isolation layer ST in the first region RG1 can define a first active region ACT1 of the first substrate 100. The device isolation layer ST in the second region RG2 can define a second active region ACT2 of the first substrate 100.

[0093] A gate line GL can be formed over the first substrate 100 to cross the first active region ACT1. A gate insulating pattern GI can be formed between each gate line GL and the first active region ACT1. The formation of the gate line GL and the gate insulating pattern GI can include: etching the first active region ACT1 and the device isolation layer ST to form a linear trench, forming a gate insulating layer to fill at least a part of each trench, and forming a conductive layer to fill the remaining part of each trench. A first capping pattern CP1 can be formed on the gate line GL.

[0094] An ion implantation process can be performed on the first active region ACT1 to form a first impurity region SD1 and a pair of second impurity regions SD2 in each first active region ACT1. A first lower insulating layer 110 can be formed on the first substrate 100.

[0095] A bit line BL, a first contact CT1, and a landing pad LP can be formed in the first lower insulating layer 110 of the first region RG1. Each bit line BL can be formed to be electrically connected to the first impurity region SD1. Each first contact CT1 can be formed to be electrically connected to the second impurity region SD2. Each landing pad LP can be formed on the first contact CT1.

[0096] Peripheral transistors LT can be formed in the first lower insulating layer 110 of the second region RG2. In some embodiments, at least a part of each peripheral transistor LT can be formed during the formation of the bit line BL.

[0097] A capacitor CAP can be formed on the first lower insulating layer 110 of the first region RG1. The formation of the capacitor CAP can include: forming a first electrode LEL1 on the landing pad LP, conformally forming a dielectric layer DIL on the first electrode LEL1, and forming a second electrode LEL2 on the dielectric layer DIL.

[0098] Reference Figure 10, the second to fifth lower insulating layers 120, 130, 140, and 150 can be formed on the capacitor CAP and the first lower insulating layer 110. The second contact portion CT2 can be formed to penetrate the second lower insulating layer 120 and be electrically connected to the second electrode LEL2. At least one third contact portion CT3 can be formed to penetrate the second lower insulating layer 120 and the first lower insulating layer 110 and be electrically connected to the peripheral transistor LT. Interconnect lines IL and via plugs VI can be formed in the third to fifth lower insulating layers 130, 140, and 150. The first insulating layer 350a can be formed on the fifth lower insulating layer 150.

[0099] As a reference Figure 9 and Figure 10 As a result of the above-described process, the first sub-chip CH1 can be fabricated.

[0100] Reference Figure 11 , the second sub-chip CH2 to be stacked on the first sub-chip CH1 can be fabricated. For example, a photoelectric conversion device PCD can be formed in the second substrate 200. A readout circuit device RCX can be formed on the first surface 200a of the second substrate 200. The first to fourth upper insulating layers 210, 220, 230, and 240 can be formed on the readout circuit device RCX. Via plugs VI and interconnect lines IL can be formed in the first to fourth upper insulating layers 210, 220, 230, and 240. The second insulating layer 350b can be formed on the fourth upper insulating layer 240.

[0101] The formation of the interconnect lines IL can include forming a first interconnect line IL1 in the second upper insulating layer 220 of the second region RG2 and forming a second interconnect line IL2 in the fourth upper insulating layer 240 of the second region RG2. The first interconnect line IL1 can be formed to have a first opening OP1. The second interconnect line IL2 can be formed to have a second opening OP2. In some embodiments, the first opening OP1 can be formed to be offset in the second direction D2 with respect to the second opening OP2.

[0102] Reference Figure 12 , the second sub-chip CH2 can be flipped, and then a planarization process can be performed on the second surface 200b of the second substrate 200. An antireflection layer 205, a color filter CF, and a microlens ML can be formed on the second surface 200b of the second substrate 200 in the first region RG1.

[0103] Reference Figure 13, a semiconductor device 20 can be formed by stacking a first sub-chip CH1 and a second sub-chip CH2 prepared by the above process. In some embodiments, the semiconductor device 20 can be an image sensor chip. The first insulating layer 350a of the first sub-chip CH1 and the second insulating layer 350b of the second sub-chip CH2 can be attached to each other to form an insertion layer 300. The first sub-chip CH1 and the second sub-chip CH2 can be physically bonded to each other through the insertion layer 300.

[0104] A via contact hole TCH can be formed by performing an etching process on the second sub-chip CH2 in the second region R62. The via contact hole TCH can be formed in a manner similar to that Figures 1A to 3B described above.

[0105] The formation of the via contact hole TCH can include forming a photoresist pattern on the second substrate 200 in the second region R62 to define the via contact hole TCH, and then using the photoresist pattern as an etching mask to perform an etching process to expose the uppermost interconnect line in the interconnect lines IL of the first sub-chip CH1. During the etching process, the second substrate 200, the first to fourth upper insulating layers 210, 220, 230, and 240, and the insertion layer 300 can be selectively etched.

[0106] During the etching process, the interconnect lines IL can not be etched. During the etching process, the first interconnect line IL1 and the second interconnect line IL2 can be used as etching masks. In other words, the first interconnect line IL1 and the second interconnect line IL2 can be similar to the first mask layer ML1 and the second mask layer ML2 Figures 1A to 3B described previously.

[0107] The via contact hole TCH can include a main contact hole MCH and an auxiliary contact hole ACH. The main contact hole MCH can be formed to expose at least a part of the uppermost interconnect line in the interconnect lines IL of the first sub-chip CH1.

[0108] The auxiliary contact hole ACH can be formed through a first opening OP1 of the first interconnect line IL1 and a second opening OP2 of the second interconnect line IL2. Specifically, the auxiliary contact hole ACH can be formed by removing the second upper insulating layer 220 filling the first opening OP1 and the fourth upper insulating layer 240 filling the second opening OP2 through an etching process.

[0109] Since the first opening OP1 and the second opening OP2 are offset from each other, the planar dimension of the bottom of the auxiliary contact hole ACH can be smaller than the planar dimension of each of the first opening OP1 and the second opening OP2. The width of the bottom of the auxiliary contact hole ACH can be reduced by the first opening OP1 and the second opening OP2, and in this case, the auxiliary contact hole ACH can be etched to a depth shallower than or less than the depth of the main contact hole MCH with respect to the first substrate 100 and / or the second substrate 200. Accordingly, the auxiliary contact hole ACH may not expose the uppermost interconnect line in the interconnect lines IL of the first sub-chip CH1.

[0110] Referring again to Figure 7 and Figure 8 , a through contact portion TCT can be formed to fill the through contact hole TCH. The through contact portion TCT can include a main contact portion MC that fills at least a part of the main contact hole MCH and / or an auxiliary contact portion AC that fills at least a part of the auxiliary contact hole ACH. The first sub-chip CH1 and the second sub-chip CH2 can be electrically connected to each other through the through contact portion TCT.

[0111] Figure 14 is a cross-sectional view of a certain region of a semiconductor device showing some embodiments according to the inventive concept. For the sake of brevity of description, the elements described previously with reference to Figures 6 to 8 may be identified by the same reference numerals and will not be described again.

[0112] Referring to Figure 14 , a semiconductor device 20 according to some embodiments of the inventive concept may include a first sub-chip CH1, a second sub-chip CH2, and an interposing layer 300 between the first sub-chip CH1 and the second sub-chip CH2. The first sub-chip CH1 and the second sub-chip CH2 are vertically stacked, and the interposing layer 300 may physically connect the first sub-chip CH1 and the second sub-chip CH2 to each other.

[0113] The first sub-chip CH1 may include a first integrated circuit IC1, and the second sub-chip CH2 may include a second integrated circuit IC2. As an example, the first sub-chip CH1 may be a logic chip. The first integrated circuit IC1 may include logic units for processing data and / or control information, and / or may include a power circuit for controlling the operation of the logic units. The second sub-chip CH2 may be a memory chip, such as a DRAM chip or a flash memory chip. The second integrated circuit IC2 may include memory units for storing data and / or control information, and / or may include a power circuit for controlling the operation of the memory units.

[0114] The first integrated circuit IC1 can be disposed on the first surface 100a of the first substrate 100. The first integrated circuit IC1 can include a plurality of first transistors TR1. The first transistors TR1 can form logic units.

[0115] The first to eighth lower insulating layers 110 - 180 can be stacked on the first surface 100a of the first substrate 100. At least one contact CT can pass through the first lower insulating layer 110 and can be electrically connected to the first transistor TR1. Interconnect lines IL and via plugs VI can be disposed in the second to eighth lower insulating layers 120 - 180.

[0116] The second integrated circuit IC2 can be disposed on the first surface 200a of the second substrate 200. The second integrated circuit IC2 can include a plurality of second transistors TR2. The second transistors TR2 can form memory cells.

[0117] The first to eighth upper insulating layers 210 - 280 can be stacked on the first surface 200a of the second substrate 200. At least one contact CT can pass through the first upper insulating layer 210 and can be electrically connected to the second transistor TR2. Interconnect lines IL and via plugs VI can be disposed in the second to eighth upper insulating layers 220 - 280.

[0118] The interconnect line IL of the second sub - chip CH2 can include a first interconnect line IL1 in the fourth upper insulating layer 240 and a second interconnect line IL2 in the sixth upper insulating layer 260. The first interconnect line IL1 can have a first opening OP1, and the second interconnect line IL2 can have a second opening OP2. The first opening OP1 and the second opening OP2 can be horizontally offset from each other.

[0119] The semiconductor device 20 can include at least one through - contact TCT that penetrates the second sub - chip CH2. The main contact MC of the through - contact TCT can electrically connect the interconnect line IL of the second sub - chip CH2 to the uppermost interconnect line in the interconnect line IL of the first sub - chip CH1.

[0120] The auxiliary contact AC of the through - contact TCT can pass through the first opening OP1 of the first interconnect line IL1 and the second opening OP2 of the second interconnect line IL2 and can extend vertically toward the first sub - chip CH1. The planar size of the auxiliary contact AC can be defined by the planar size of the overlapping region between the first opening OP1 and the second opening OP2.

[0121] According to some embodiments of the inventive concept, a semiconductor device may include a semiconductor chip in which two sub-chips are stacked. The sub-chips may be electrically connected to each other through a through contact of the semiconductor chip. In a method of manufacturing a semiconductor device according to some embodiments of the inventive concept, the size of an auxiliary contact of the through contact may be easily adjusted. Accordingly, process defects may be reduced or prevented, and the through contact may be fixed to the sub-chip through the auxiliary contact.

[0122] Although example embodiments of the inventive concept have been specifically shown and described, those of ordinary skill in the art will understand that changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A first sub-chip, comprising a first substrate and a first plurality of interconnect lines on the first substrate; A second sub-chip, comprising a second substrate and a second plurality of interconnect lines on the second substrate, wherein the second sub-chip is stacked on the first sub-chip, and wherein the first plurality of interconnect lines of the first sub-chip and the second plurality of interconnect lines of the second sub-chip are located between the first substrate and the second substrate; and Through-vias, extending from the second substrate towards the first sub-chip to electrically connect the first sub-chip and the second sub-chip to each other; And An insertion layer, located between the first sub-chip and the second sub-chip and physically connecting the first sub-chip to the second sub-chip, wherein the second plurality of interconnect lines of the second sub-chip includes a first interconnect line having a first opening and a second interconnect line having a second opening, wherein the center of the second opening is horizontally offset relative to the center of the first opening in a direction parallel to the first substrate and the second substrate, wherein the through-vias include auxiliary contacts that extend towards the first sub-chip in the first opening and the second opening, wherein, relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the top surface of the uppermost interconnect line among the first plurality of interconnect lines of the first sub-chip, and wherein, relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the insertion layer and lower than the height of the top surface of the insertion layer.

2. The semiconductor device according to claim 1, wherein the auxiliary contact portion has a first width in the first opening, wherein the auxiliary contact portion has a second width in the second opening, and wherein the second width is less than the first width.

3. The semiconductor device according to claim 1, wherein the bottom of the auxiliary contact portion includes a planar shape, and wherein the overlapping region between the first opening and the second opening includes the planar shape.

4. The semiconductor device according to claim 1, further comprising: A transistor, located on a first surface of the second substrate, wherein the second substrate includes a second surface opposite to the first surface, and wherein the through-vias extend vertically from the second surface of the second substrate towards the first sub-chip.

5. The semiconductor device according to claim 1, wherein the through contact portion further includes a main contact portion electrically connected to the uppermost interconnection line among the first plurality of interconnection lines.

6. The semiconductor device according to claim 5, wherein the height of the bottom surface of the auxiliary contact portion is higher than the height of the bottom surface of the main contact portion with respect to the first substrate.

7. The semiconductor device according to claim 5, wherein the main contact portion contacts the first interconnection line and the second interconnection line.

8. The semiconductor device according to claim 1, wherein the second sub-chip further includes a photoelectric conversion device in the second substrate, and wherein the first sub-chip further includes a memory transistor on the first substrate.

9. The semiconductor device according to claim 1, wherein the auxiliary contact portion has a first width in the first opening, wherein the auxiliary contact portion has a second width smaller than the first width in the second opening, and wherein the second width of the auxiliary contact portion decreases as the distance from the first opening increases.

10. A semiconductor device, comprising: A first sub-chip, comprising a first substrate and a first plurality of interconnect lines on the first substrate; A second sub-chip, comprising a second substrate and a second plurality of interconnect lines on the second substrate, wherein the second sub-chip is stacked on the first sub-chip; and Through-vias, penetrating the second sub-chip and electrically connecting the first sub-chip and the second sub-chip to each other; And An insertion layer, located between the first sub-chip and the second sub-chip and physically connecting the first sub-chip to the second sub-chip, wherein the second plurality of interconnect lines of the second sub-chip includes a first interconnect line having a first opening and a second interconnect line having a second opening, wherein the center of the second opening is horizontally offset relative to the center of the first opening, wherein the through-vias include: Auxiliary contacts, extending towards the first sub-chip in the first opening and the second opening; And Main contacts, electrically connected to the uppermost interconnect line among the first plurality of interconnect lines of the first sub-chip, wherein, relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the main contacts, and wherein, relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the insertion layer and lower than the height of the top surface of the insertion layer.

11. The semiconductor device according to claim 10, wherein the auxiliary contact portion has a first width in the first opening, wherein the auxiliary contact portion has a second width in the second opening, and wherein the second width is smaller than the first width 12. The semiconductor device according to claim 10, wherein, with respect to the first substrate, the height of the bottom surface of the auxiliary contact portion is higher than the height of the top surface of the uppermost interconnect line among the first plurality of interconnect lines.

13. The semiconductor device according to claim 10, further comprising: A transistor, located on a first surface of the second substrate, wherein the second substrate includes a second surface opposite to the first surface, and wherein the via contact extends vertically from the second surface of the second substrate towards the first sub-chip.

14. The semiconductor device according to claim 10, wherein the main contact portion contacts the first interconnect line and the second interconnect line.

15. A semiconductor device, comprising: A first substrate; Lower interconnect lines on the first substrate and upper interconnect lines on the lower interconnect lines; And Via contacts that extend vertically from the upper interconnect lines to the lower interconnect lines to electrically connect the upper interconnect lines and the lower interconnect lines to each other; And An insertion layer, located between the lower interconnect lines and the upper interconnect lines, wherein the upper interconnect lines include a first interconnect line having a first opening and a second interconnect line on the first interconnect line and having a second opening, wherein the center of the second opening is horizontally offset relative to the center of the first opening in a direction parallel to the first substrate, wherein the via contact includes: Auxiliary contacts that extend towards the first substrate in the second opening and the first opening; And Main contacts that are electrically connected to the lower interconnect lines, wherein relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the main contacts, and wherein relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the insertion layer and lower than the height of the top surface of the insertion layer.

16. The semiconductor device according to claim 14, wherein the auxiliary contact portion has a first width in the first opening, wherein the auxiliary contact portion has a second width in the second opening, and wherein the first width is less than the second width.

17. The semiconductor device according to claim 14, wherein the height of the bottom surface of the auxiliary contact portion is higher than the height of the top surface of the lower interconnect with respect to the first substrate.

18. The semiconductor device according to claim 14, further comprising: A second substrate on the upper interconnect lines, wherein the via contact extends from the second substrate through the upper interconnect lines to the lower interconnect lines.

19. The semiconductor device according to claim 14, wherein the bottom of the auxiliary contact portion has a planar shape, and wherein the overlapping region between the first opening and the second opening includes the planar shape.

20. A method of manufacturing a semiconductor device, comprising: Form a first sub-chip, wherein the first sub-chip includes a first substrate and a first plurality of interconnect lines on the first substrate; Form a second sub-chip, wherein the second sub-chip includes a second substrate and a second plurality of interconnect lines on the second substrate; Stack the first sub-chip and the second sub-chip face to face; Form a via contact hole to penetrate the second sub-chip and expose the uppermost interconnect line among the first plurality of interconnect lines of the first sub-chip; Form a via contact in the via contact hole; And Form an insertion layer, the insertion layer being located between the first sub-chip and the second sub-chip and physically connecting the first sub-chip to the second sub-chip, wherein forming the second sub-chip includes: Form a first interconnect line among the second plurality of interconnect lines on the second substrate to have a first opening; And Form a second interconnect line on the first interconnect line to have a second opening horizontally offset relative to the first opening, wherein forming the via contact hole includes forming an auxiliary contact hole extending in the first opening and the second opening, wherein relative to the first substrate, the height of the bottom surface of the auxiliary contact hole is higher than the height of the top surface of the uppermost interconnect line among the first plurality of interconnect lines, wherein relative to the first substrate, the height of the bottom surface of the auxiliary contacts is higher than the height of the bottom surface of the insertion layer and lower than the height of the top surface of the insertion layer.

21. The method according to claim 20, wherein the auxiliary contact hole has a first width in the first opening, wherein the auxiliary contact hole has a second width in the second opening, and wherein the second width is less than the first width.

22. The method according to claim 20, wherein forming the through contact hole further comprises: A main contact hole is formed to expose a first side surface of the first interconnecting line, a second side surface of the second interconnecting line, and the uppermost interconnecting line among the first plurality of interconnecting lines. Wherein, with respect to the first substrate, a height of a bottom surface of the auxiliary contact hole is higher than a height of a bottom surface of the main contact hole.

23. The method according to claim 20, wherein the bottom of the auxiliary contact hole comprises a planar shape, and wherein the overlapping region between the first opening and the second opening comprises the planar shape.

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