A thin film transistor structure and manufacturing method

Abstract

The present invention discloses a thin film transistor structure and a manufacturing method, comprising a substrate and a first metal layer, an active layer, and a second metal layer on the substrate; the active layer comprises: a side wall active layer, the first metal layer is a columnar structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the side wall active layer surrounds the side of the first metal layer, an active layer electrical channel is formed between the side of the side wall active layer and the side of the first metal layer, and an insulating layer is also provided in the channel; and a second metal layer is connected to the top two ends of the side wall active layer. The side surface of the first metal layer and the active layer are effectively used to form an active layer conductive channel, so as to improve the reaction rate and on-state current of the TFT device, which is conducive to the application in ultra-high resolution panels. In addition, the TFT structure provided has a smaller deformation when the device is stretched and bent, and can better disperse the stress generated by the deformation, so that the device remains stable, which is conducive to the future manufacture of bendable or stretchable panels.

Description

Technical Field

[0001] The invention relates to the field of TFT device manufacturing, and in particular to a thin film transistor structure and a manufacturing method. Background Art

[0002] In recent years, manufacturers have continuously released 8K display panels and VR glasses equipped with ultra-high-resolution displays. Judging from the market response, 4K resolution, curved screens, and ultra-wide ratios have become the focus of consumer attention. In the future, displays will continue to develop towards high resolution, curved surfaces, and ultra-wide ratios. For TVs or VR, an important factor that determines the experience is PPD (pixel per degree), that is, the number of pixels that can be perceived per viewing angle. For a person with a standard visual acuity of 1.0, the best PPD must reach 60 to completely eliminate the screen graininess. To enhance the immersive experience of VR applications, the resolution must reach 8K or above to improve the "screen door effect" that is prevalent in current VR headsets, and may even be further increased to 12K and 24K in the future. Therefore, with the development of high-resolution panels, how to reduce the size of pixels and the TFT devices behind the pixels has become a difficult problem that needs to be overcome. Summary of the invention

[0003] Therefore, it is necessary to provide a thin film transistor structure and a manufacturing method to reduce the size of the TFT device behind the pixel.

[0004] To achieve the above object, the inventor provides a thin film transistor structure, including a substrate and a first metal layer, an active layer, and a second metal layer on the substrate;

[0005] The active layer includes: a sidewall active layer, the first metal layer is a columnar structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the sidewall active layer surrounds the side surface of the first metal layer, an active layer electrical channel is formed between the side surface of the sidewall active layer and the side surface of the first metal layer, and an insulating layer is also provided in the channel; the top two ends of the sidewall active layer are respectively connected to a second metal layer.

[0006] Furthermore, it also includes: a buffer layer, wherein the buffer layer is arranged on the substrate, and the sidewall active layer and the insulating layer are arranged on the buffer layer.

[0007] Furthermore, the active layer also includes: a bottom active layer, the bottom active layer is placed on the buffer layer, the bottom active layer is parallel to the upper surface of the substrate, and an insulating layer is also arranged between the bottom active layer and the first metal layer; the upper surface of the bottom active layer is connected to the bottom of the sidewall active layer.

[0008] Furthermore, it also includes: a passivation layer, which is placed on the top layer of the thin film transistor structure and is used to protect the TFT structure.

[0009] Furthermore, it also includes: a third metal layer; the third metal layer is a columnar structure with an open top and a hollow interior, and the third metal layer is sleeved on the outer periphery of the active layer; the bottom of the third metal layer is connected to the substrate, and an insulating layer is also provided between the third metal and the active layer.

[0010] Furthermore, there are multiple first metal layers; or the first metal layer is in a cylindrical, curved cylindrical, or square cylindrical structure; or the top of the first metal layer protrudes above the upper surface of the second metal layer.

[0011] The inventors provide a method for manufacturing a thin film transistor structure, comprising the steps of:

[0012] Making a first insulating layer, making a first through hole, and a sidewall active layer;

[0013] A second metal layer is formed on the top of the sidewall active layer, and two ends of the top of the sidewall active layer are respectively connected with a second metal layer;

[0014] A second insulating layer, a second through hole in the middle, and a first metal layer are deposited so that the sidewall active layer surrounds the side of the first metal layer.

[0015] Furthermore, the “making a first insulating layer, making a first through hole, and a sidewall active layer” comprises the steps of:

[0016] Depositing a first insulating layer, and etching a first through hole on the first insulating layer;

[0017] A sidewall active layer is deposited in the first through hole.

[0018] Furthermore, the “second insulating layer, a second through hole in the middle, and depositing a first metal layer” comprises the steps of:

[0019] The first insulating layer and the second insulating layer are etched to obtain a second through hole, and a first metal layer is deposited in the second through hole.

[0020] Furthermore, before the step of "making a first insulating layer and making a first through hole", the method further includes the steps of: making a buffer layer on the substrate, and making a bottom active layer on the buffer layer.

[0021] Different from the prior art, the above technical solution provides a thin film transistor structure. In the present invention, a first metal layer with a columnar structure and an active layer arranged around it are provided. The side surface of the first metal layer and the active layer are effectively used to form an active layer conductive channel, thereby improving the reaction rate and on-state current of the TFT device, while reducing the size of the TFT, which is beneficial for application in ultra-high resolution panels. In addition, the TFT structure provided has a smaller deformation when the device is stretched and bent, and can better disperse the stress generated by the deformation, so that the device remains stable, which is beneficial for the future manufacture of bendable or stretchable panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The TFT structure described in the specific implementation manner;

[0023] Figure 2 It is the TFT structure in the background technology;

[0024] Figure 3 It is the conductive channel of the active layer;

[0025] Figure 4 This is a stress comparison diagram of TFT structure;

[0026] Figure 5 It is a top view of the TFT structure;

[0027] Figure 6 It is a cross-sectional view of the TFT structure;

[0028] Figure 7 are multiple first metal layer structure diagrams;

[0029] Figure 8 The bottom active layer structure diagram is made for Example 1;

[0030] Fig. 9 A first metal layer structure diagram is prepared for Example 1;

[0031] Fig.10 An insulating layer structure diagram is prepared for Example 1;

[0032] Fig.11 The sidewall active layer structure diagram is produced for Example 1;

[0033] Fig.12 A second metal layer structure diagram is prepared for Example 1;

[0034] Fig.13 A passivation layer structure diagram is prepared for Example 1;

[0035] Fig.14 A structural diagram of the first metal layer and the insulating layer is produced for Example 2;

[0036] Fig.15The sidewall active layer and the second metal layer structure diagram are made for the second embodiment;

[0037] Fig.16 A passivation layer structure diagram is prepared for Example 2;

[0038] Fig.17 The structure diagram of the buffer layer and the bottom active layer is made for Example 3;

[0039] Fig.18 The structure diagram of the insulating layer and the sidewall active layer is made for the third embodiment;

[0040] Fig.19 The structure diagram of the first metal layer and the second metal layer is made for Example 3;

[0041] Fig. 20 This is a structural diagram of embodiment 3;

[0042] Fig.21 The structure diagram of the buffer layer and the bottom active layer is made for Example 4;

[0043] Fig. 22 The structure diagram of the insulating layer and the sidewall active layer is made for the fourth embodiment;

[0044] Fig.23 A second metal layer structure diagram is prepared for Example 4;

[0045] Fig.24 The structure diagram of the first metal layer and the passivation layer is made for Example 4;

[0046] Fig.25 This is a structural diagram of Embodiment 4;

[0047] Fig.26 This is a structural diagram of Embodiment 5;

[0048] Fig. 27 The structure diagram of the buffer layer and the bottom active layer is made for Example 6;

[0049] Fig.28 A first metal layer structure diagram is prepared for Example 6;

[0050] Fig.29 The side wall active layer structure diagram is made for Example 6;

[0051] Fig.30 A second metal layer structure diagram is prepared for Example 6;

[0052] Fig.31 This is a structural diagram of Embodiment 6;

[0053] Fig.32 This is a structural diagram of embodiment 1 with the buffer layer removed;

[0054] Fig.33This is a structural diagram of Embodiment 7;

[0055] Fig.34 This is a structural diagram of Embodiment 8;

[0056] Description of reference numerals:

[0057] 1. First metal layer; 2. Second metal layer; 3. Third metal layer; 4. Active layer; 5. Substrate; 6. Buffer layer;

[0058] 41. Bottom active layer; 42. Sidewall active layer. DETAILED DESCRIPTION

[0059] In order to explain the technical content, structural features, achieved objectives and effects of the technical solution in detail, the following is a detailed description in conjunction with specific embodiments and accompanying drawings.

[0060] See also Figures 1 to 34 This embodiment provides a method for manufacturing a thin film transistor structure, which can be manufactured on a substrate, a wafer or a chip. It includes eight embodiments, which can more effectively utilize the side surface and the bottom surface of the gate to form a conductive channel of the active layer 4, improve the reaction rate and on-state current of the TFT device, and reduce the size of the TFT, which is conducive to the application in ultra-high resolution panels. In addition, the TFT structure provided has a smaller deformation when the device is stretched and bent, and can better disperse the stress generated by the deformation, so that the device remains stable, which is conducive to the future manufacture of bendable or stretchable panels.

[0061] See also Figures 8 to 13 , wherein the first embodiment includes the following steps: making a buffer layer on the substrate; specifically, making the buffer layer on the substrate, the material can be selected from inorganic oxides or insulating compounds, such as silicon oxide (SiOx), silicon nitride (SiNx), titanium oxide, aluminum oxide and other materials for single-layer coating or multi-layer coating, or other organic insulating materials as the buffer layer. Of course, in some embodiments, the buffer layer may not be made.

[0062] After the buffer layer is made, a bottom active layer 41 is made on the buffer layer, and the bottom active layer 41 serves as a part of the active layer 4; specifically, the active layer 4 material, such as polysilicon, oxide semiconductor, graphene, carbon nanotubes, organic semiconductors, etc., is plated on the buffer layer. Among them, the oxide semiconductor can be an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In), and their composite oxides such as zinc oxide (ZnO), indium gallium zinc oxide (InGaZnO4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), indium aluminum oxide (In-Al-O), indium zinc aluminum oxide (In-Zn-A1-O), indium tin aluminum oxide (In-Sn-A l-O) indium aluminum gallium oxide (In-Al-Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O) and hafnium indium zinc oxide (Hf-In-Zn-O), and the organic semiconductor can be pentacene, polythiophene (Poly (3-alkyl) thiophene), phthalocyanine compound (phthalocyanincecompound) and other materials. Or the buffer layer can also be made without making.

[0063] In some embodiments, the bottom active layer 41 can also be replaced with a conductive material to serve as a conductive layer. The conductive film can be an oxide conductive film, such as ITO, or one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, as well as carbon nanotubes, graphene, etc.

[0064] In the first embodiment, in order to improve the overall or local conductivity or semiconductor property, gas treatment such as H2, O2, NO, NO2, CH4 and the like may be performed on the surface of the bottom active layer 41 or the edge surface of the bottom active layer 41 .

[0065] Then, a first insulating layer is formed on the bottom active layer 41; the first insulating layer material is plated, and inorganic oxides or insulating compounds such as SiOx, SiNx, titanium oxide, aluminum oxide and other materials can be selected for single-layer coating or multi-layer coating, and the first insulating layer covers the bottom active layer 41. It should be noted that the insulating layer includes multiple insulating layers, which can also be regarded as a single layer. Specifically, in the TFT structure, the insulating layer is a single-layer structure; in the TFT structure manufacturing method, because the insulating layer plays a role in shaping the metal, it is necessary to sequentially manufacture multiple insulating layers.

[0066] After the first insulating layer is made, the first metal layer 1 is made on the first insulating layer on the bottom active layer 41; the material of the first metal layer 1 is plated, and one or more metals with excellent conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys can be selected to form the first metal layer 1 on the first insulating layer on the bottom active layer 41. The width of the first metal layer 1 is smaller than the width of the bottom active layer 41. In the present application, the first metal layer 1, as the gate of the TFT, can be cylindrical, curved cylindrical, square cylindrical, and any other geometric cylindrical shapes. Compared with the traditional flat shape, the first metal layer 1 with a cylindrical structure can more effectively utilize the side surface and the bottom surface of the gate to form an active layer conductive channel, thereby improving the reaction rate and on-state current of the TFT device, while reducing the size of the TFT, which is conducive to the application in ultra-high resolution panels.

[0067] After the first metal layer 1 is made, a second insulating layer is made on the first insulating layer and the first metal layer 1; the second insulating layer material is plated, and the material can be selected from inorganic oxides or insulating compounds, such as SiOx, SiNx, titanium oxide, aluminum oxide and other materials for single-layer coating or multi-layer coating. Then, through holes penetrating the second insulating layer and the first insulating layer are etched on the bottom active layer 41 on both sides of the first metal layer 1 to expose the upper surface of the bottom active layer 41 on both sides of the first metal layer 1. The through holes are used to make the sidewall active layer 42 of the active layer.

[0068] Then, a sidewall active layer 42 is made on the second insulating layer. The material selection range of the sidewall active layer 42 is consistent with that of the bottom active layer 41. The materials of the bottom active layer 41 and the sidewall active layer 42 can be freely matched and are not limited to the same material. The sidewall active layer 42 is connected to the bottom active layer 41 through a through hole on the second insulating layer that is connected to the bottom active layer 41. The sidewall active layer 42 is arranged around the first metal layer 1, and the sidewall active layer 42 and the first metal layer 1 form an active layer electrical channel. The sidewall active layer 42 also has a surface located on the top of the second insulating layer, and the sidewall active layer 42 and the bottom active layer 41 together serve as the active layer of the TFT. Among them, in order to enable the active layer to better fill the third insulating layer via, the solution method can be preferably used to make the sidewall active layer 42.

[0069] Similarly, gas treatment such as H2, O2, NO, NO2, CH4 or the like may be performed on the upper surface of the sidewall active layer 42 or the edge surface of the sidewall active layer 42 to improve the overall or local conductivity or semiconductor properties.

[0070] After the sidewall active layer 42 is made, a columnar second metal layer 2 is made on the sidewall active layer 42 and the second insulating layer. The second metal layer 2 material is plated, and the second metal layer 2 material can be selected from one or more metals with good conductivity such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys. Then, the second metal layer 2 is formed on the sidewall active layer 42 and the second insulating layer. The second metal layer 2 includes a source electrode and a drain electrode, the source electrode is connected to the sidewall active layer 42 on one side of the first metal layer 1, and the drain electrode is connected to the sidewall active layer 42 on the other side of the first metal layer 1.

[0071] Finally, a passivation layer can be formed on the second metal layer 2; specifically, the passivation layer material can be plated, and inorganic oxides or insulating compounds such as SiOx, SiNx, titanium oxide, aluminum oxide and other materials can be used for single-layer coating or multi-layer coating, or other organic insulating materials can be used to form a passivation layer covering the second metal layer 2 and the second metal layer 2. The passivation layer is placed on the top layer of the thin film transistor structure to protect the TFT structure.

[0072] See also Figure 7 In a further embodiment, there are multiple first metal layers 1 and they are arranged in an array, and then the active layer (bottom active layer 41 and sidewall active layer 42) surrounds the multiple first metal layers 1, and the active layer is connected to the second metal layer (source and drain) at both ends.

[0073] See also Figures 14 to 16 In the second embodiment, based on the first embodiment, some process improvements are made, including the following steps: directly making the first metal layer 1 on the substrate (no need to make the buffer layer and bottom active layer 41 of the first embodiment), the steps are the same as the first embodiment. After the first metal layer 1 is made, a first insulating layer covering the first metal layer 1 is made on the first metal layer 1, and through holes are etched on the first insulating layer on both sides of the first metal layer 1. The bottom of the through hole can be the substrate or the place where the first insulating layer is close to the substrate. Then, a sidewall active layer 42 is made in the through hole on the first insulating layer, and then a second metal layer 2 (source and drain) is made on the sidewall active layer 42. The material, structure and distribution of the sidewall active layer 42 and the second metal layer 2 are the same as those of the first embodiment. Finally, a passivation layer is made on the TFT, and the passivation layer can protect the TFT. Compared with the first embodiment, the second embodiment can save two insulating layers and one bottom active layer 41.

[0074] See also Figures 17 to 20In the third embodiment, based on the first embodiment, some process improvements are made, including the following steps: Similarly, a buffer layer is made on the substrate, and the steps are the same as those in the first embodiment. Then, a bottom active layer 41 is made on the buffer layer, and the steps are the same as those in the first embodiment. Then, a first insulating layer is made on the bottom active layer 41, and the steps are the same as those in the first embodiment. The difference is that holes for placing the first metal layer 1 and the sidewall active layer 42 are made on the first insulating layer at the same time. Exposure can be performed through a grayscale mask, and the etching time can be controlled by the etching rate to make holes of different depths in the first insulating layer. The grayscale mask can be a mask with a light-shielding area, a light-transmitting area and a semi-light-transmitting area. The semi-light-transmitting area corresponds to the third hole (accommodating the first metal layer 1), and the light-transmitting area or the light-shielding area (depending on the positive photoresist or the negative photoresist) corresponds to the first hole and the second hole. The first hole and the second hole expose the surface of the bottom active layer 41 on the outside, and the third hole is a blind hole, and the surface of the active layer is not exposed between the first hole and the second hole. Similarly, the exposed bottom active layer 41 can be subjected to gas treatment. Then, a sidewall active layer 42 is formed on the first insulating layer, and the sidewall active layer 42 is connected to the bottom active layer 41 through the first hole and the second hole, and is located on the first insulating layer. After the sidewall active layer 42 is completed, a columnar first metal layer 1 (gate) is continuously formed to fill the third hole on the second insulating layer. Similarly, a second metal layer 2 (source and drain) is formed on the sidewall active layer 42 and the first insulating layer, and the source is connected to the sidewall active layer 42 on one side of the first metal layer 1, and the drain is connected to the sidewall active layer 42 on the other side of the first metal layer 1. The materials, structures and connections of the first metal layer 1, the second metal layer 2 and the insulating layer are the same as those in Example 1, but one insulating layer is saved compared to Example 1.

[0075] See also Figure 21 to Figure 25 In the fourth embodiment, based on the third embodiment, some processes are improved; the steps include: making a buffer layer on the substrate, then making a bottom active layer 41 on the buffer layer, and then making a first insulating layer on the bottom active layer 41. The third embodiment makes the first hole, the second hole and the third hole in the first insulating layer, and the fourth embodiment makes the first hole and the second hole on the first insulating layer, and the bottom of the first hole and the second hole is the bottom active layer 41. Then make a sidewall insulating layer on the first insulating layer, and the sidewall insulating layer is connected to the bottom active layer 41 through the first hole and the second hole. Then make a second metal layer 2 (source and drain) on the sidewall insulating layer and the first insulating layer, and the source and the drain are connected to the sidewall active layer 42 on one side. Make a second insulating layer covering the second metal layer 2 on the second metal layer 2 and the first insulating layer, and the second insulating layer is used to form the shape of the first metal layer 1.

[0076] After the second metal layer 2 and the second insulating layer are produced, the second insulating layer is etched to the first insulating layer on the second insulating layer in the middle area of ​​the side wall active layer 42 by controlling the etching time to form a third hole. The third hole is a blind hole and the bottom of the hole is the part of the first insulating layer close to the bottom active layer 41, and the surface of the active layer is not exposed.

[0077] Then, a columnar first metal layer 1 (gate) is made in the third hole on the second insulating layer, and the first metal layer 1 also has a portion located on the second insulating layer, which is surrounded by the outer sidewall active layer 42 and the second metal layer 2. Different from the previous embodiments, the height of the first metal layer 1 exceeds the second metal layer 2, and this structure is conducive to the design layout of TFT devices in the panel.

[0078] See also Fig.26 , Example 5 is based on Example 4. In order to save process costs and steps, the buffer layer and bottom active layer 41 in Example 4 can be omitted. First, a first insulating layer is made on the substrate and the first hole and the second hole are etched. Then, the sidewall active layer 42, the second metal layer 2, the second insulating layer (making the third hole), the first metal layer 1 and the passivation layer are sequentially made. One insulating layer and one bottom active layer 41 can be saved.

[0079] See also Figures 27 to 31 In Example 6, based on Example 1, some process improvements are made, including the following steps: a buffer layer is made on the substrate, and the steps are the same as in Example 1. After the buffer layer is made, a bottom active layer 41 is made on the buffer layer, and the steps are the same as in Example 1. Then a first insulating layer covering the bottom active layer 41 is made on the buffer layer and the bottom active layer 41, and the steps are the same as in Example 1. Then a columnar first metal layer 1 is made on the first insulating layer in the bottom active layer 41 area, and the steps are the same as in Example 1. After the first metal layer 1 is made, a second insulating layer covering the first metal layer 1 is made on the first metal layer 1 and the first insulating layer. Then through holes are made on the second insulating layer on both sides of the first metal layer 1, and the bottom of the through hole is the bottom active layer 41. At this time, the surface of the second insulating layer can be treated with gas after the through hole is made, such as H2, O2, NO, NO2, CH4, SiH4 and other gases, to improve the contact characteristics of the through hole surface. Compared with Implementation Plans 1 and 4, the thickness of the insulating layer in Example 6 is thinner, and the depth of the hole required is lower.

[0080] Then, a sidewall active layer 42 is made on the second insulating layer. The sidewall active layer 42 is connected to the bottom active layer 41 through the through holes on both sides of the first metal layer 1 in the second insulating layer. The two parts of the sidewall active layer 42 are tightly attached to the second insulating layer covering the first metal layer 1. The sidewall active layer 42 also has a part located on the second insulating layer surface covering the first metal layer 1.

[0081] After the sidewall active layer 42 is made, a third insulating layer is made on the second insulating layer and the sidewall active layer 42, and then two through holes connecting the sidewall active layer 42 are made on the third insulating layer on the sidewall active layer 42. After that, a second metal layer 2 (source and drain) is made on the third insulating layer, the source is connected to the sidewall active layer 42 on one side of the first metal layer 1 through a through hole on the third insulating layer, and the drain is connected to the sidewall active layer 42 on the other side of the first metal layer 1 through a through hole on another third insulating layer. Of course, the part of the second metal layer 2 located on the third insulating layer outside the through hole can be retained as a connection point for the external circuit. Finally, a passivation layer with a protective effect is made on the second metal layer 2 and the third insulating layer. Since most of the area of ​​the TFT structure of Example 6 is not affected by the etching gas when the through hole is made, the contact surface is smoother, which is conducive to the electrical debugging of the TFT.

[0082] Embodiments 1 to 6 provide a TFT structure in which an active layer surrounds the first metal layer 1 , and embodiments 7 and 8 provide a TFT structure in which the first metal layer 1 is placed in a hole.

[0083] See also Fig.33 In the seventh embodiment, the following steps are included: a buffer layer is made on the substrate, and then a through hole is made on the buffer layer for placing the third metal layer 3, and the bottom of the through hole can be the buffer layer or the substrate. Then a third metal layer 3 (also used as the gate of the TFT) is made in the through hole on the buffer layer, and the third metal layer 3 covers the bottom and side wall of the through hole on the buffer layer, and can also cover the buffer layer on the outside of part of the hole. The third metal layer 3 is a cylindrical structure with an open top and a hollow interior, and the third metal layer 3 is sleeved on the active layer. Then a first insulating layer covering the third metal layer 3 is made on the third metal layer 3 and the buffer layer, and the first insulating layer also forms a hole in the third metal layer 3 region, and the first insulating layer has an insulating effect. An active layer is made on the first insulating layer in the third metal layer 3 region, and the active layer covers the hole on the first insulating layer in the third metal layer 3 region, and has a portion located on the first insulating layer. Finally, a second metal layer 2 is made on the active layer on the first insulating layer, and the second metal layer 2 is used as a source electrode on the active layer on one side, and the second metal layer 2 is used as a drain electrode on the active layer on the other side. Of course, the second metal layer 2 can also extend to the surface of the first insulating layer or to the through hole inside the third metal layer 3. Finally, a second insulating layer can be made on the TFT, and the second insulating layer is used for protection. The film layers of the TFT of the structure of embodiment 7 from the center of the through hole on the buffer layer to the outside are: the second insulating layer, the active layer, the first insulating layer, and the third metal layer 3. In some embodiments, the third metal layer can be used alone as the first metal layer, that is, the third metal layer is used as a gate.

[0084] See also Fig.34In Example 8, some process improvements are made based on Example 8. After the second insulating layer is made in Example 8, a hole for accommodating the first metal layer 1 (gate) can be made on the second insulating layer in the area of ​​the third metal layer 3. The hole on the second insulating layer is located in the through hole of the buffer layer, and then the first metal layer 1 is made in the hole on the second insulating layer. The first metal layer 1 is also used as the gate of the TFT. The film layers of the TFT of the structure of Example 8 from the center of the through hole on the buffer layer to the outside are: first metal layer 1, second insulating layer, active layer, first insulating layer, third metal layer 3. Finally, a third insulating layer covering the first metal layer 1 can be made on the first metal layer 1 and the second insulating layer. The third insulating layer is used for protection.

[0085] It should be noted that, in the present application, the first metal layer 1 of each embodiment may be made of the same material, and the second metal layer 2 and the insulating layer may also be made of the same material.

[0086] It should be noted that, although the above embodiments have been described in this article, the patent protection scope of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, changes and modifications made to the embodiments described herein, or equivalent structures or equivalent process changes made using the contents of the present invention specification and drawings, directly or indirectly applying the above technical solutions to other related technical fields, are all included in the patent protection scope of the present invention.

Claims

1. A thin film transistor structure, characterized in that: It comprises a substrate and a first metal layer, an active layer, a second metal layer and a third metal layer on the substrate; The active layer comprises: a sidewall active layer, the first metal layer is a columnar structure, the bottom surface of the first metal layer is parallel to the upper surface of the substrate, the sidewall active layer surrounds the side surface of the first metal layer, an active layer electrical channel is formed between the side surface of the sidewall active layer and the side surface of the first metal layer, and an insulating layer is also provided in the channel; Two ends of the top of the sidewall active layer are respectively connected with a second metal layer; The third metal layer is a columnar structure with an open top and a hollow interior, and the third metal layer is sleeved on the outer periphery of the active layer; the bottom of the third metal layer is connected to the substrate, and an insulating layer is also provided between the third metal and the active layer.

2. A thin film transistor structure according to claim 1, characterized in that: Also includes: A buffer layer is disposed on the substrate, and the sidewall active layer and the insulating layer are disposed on the buffer layer.

3. A thin film transistor structure according to claim 2, characterized in that: The active layer also includes: a bottom active layer, which is placed on the buffer layer, parallel to the upper surface of the substrate, and an insulating layer is also arranged between the bottom active layer and the first metal layer; the upper surface of the bottom active layer is connected to the bottom of the sidewall active layer.

4. A thin film transistor structure according to claim 1, characterized in that: Also includes: A passivation layer is disposed on the top layer of the thin film transistor structure and is used to protect the TFT structure.

5. A thin film transistor structure according to claim 1, characterized in that: There are multiple first metal layers; or the first metal layer is in a cylindrical, curved cylindrical, or square cylindrical structure; or the top of the first metal layer protrudes from the upper surface of the second metal layer.

6. A method for manufacturing a thin film transistor structure, characterized in that: Includes steps: Making a first insulating layer, making a first through hole, and a sidewall active layer; A second metal layer is formed on the top of the sidewall active layer, and two ends of the top of the sidewall active layer are respectively connected with a second metal layer; A second insulating layer, a second through hole in the middle, and a first metal layer are deposited so that the sidewall active layer surrounds the side of the first metal layer.

7. The method for manufacturing a thin film transistor structure according to claim 6, characterized in that: The "making a first insulating layer, making a first through hole, and a sidewall active layer" comprises the following steps: Depositing a first insulating layer, and etching a first through hole on the first insulating layer; A sidewall active layer is deposited in the first through hole.

8. The method for manufacturing a thin film transistor structure according to claim 6, characterized in that: The "second insulating layer, the second through hole in the middle, and the deposition of the first metal layer" comprises the following steps: The first insulating layer and the second insulating layer are etched to obtain a second through hole, and a first metal layer is deposited in the second through hole.

9. The method for manufacturing a thin film transistor structure according to claim 8, characterized in that: Before the step of "making a first insulating layer and making a first through hole", the method further includes the steps of: making a buffer layer on the substrate, and making a bottom active layer on the buffer layer.

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