Device with physical unclonable function of floating gate transistor and method for manufacturing the same

Abstract

Devices with physical unclonable functions of floating gate transistors and methods for manufacturing the same are described herein. According to one embodiment, a physical unclonable function device includes: a set of floating gate transistor pairs, the floating gate transistors in the floating gate transistor pair set having randomly distributed effective threshold voltages belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of the floating gate transistors of the floating gate transistor pairs in the floating gate transistor pair set, and identify the floating gate transistor pairs in which the measured threshold difference is less than a margin value as unreliable floating gate transistor pairs; and a write circuit configured to shift the effective threshold voltages of the floating gate transistors of the unreliable floating gate transistor pairs to within the common random distribution.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from French patent application No. 1901791 filed on February 22, 2019, which is hereby incorporated herein by reference. Technical Field

[0003] Implementations and embodiments of the present invention relate to physically unclonable functions (PUFs), particularly in structures including floating gate transistors. Background Art

[0004] Physically unclonable functions allow for the automatic generation of unique unpredictable codes that rely on random physical properties. Therefore, cloning such functions is very difficult, if not impossible.

[0005] On the one hand, it is desirable that the physical unclonable functions are sufficiently robust so that they do not change over time, in particular after repeated use or in case of temperature changes. On the other hand, it is desirable that random changes in physical properties are easily identifiable so that various data can be clearly distinguished. Furthermore, it is desirable that the generation of the physical unclonable functions requires no or only few dedicated manufacturing steps.

[0006] The unique unpredictable code usually consists of a random sequence of data and is primarily used as an encryption key. This data is usually kept secret.

[0007] The fact is that there are some techniques, in particular those using scanning capacitance microscopy (SCM) or scanning electron microscopy (SEM), which are able to extract secret data, ie to read the data by measurement, inspection and / or analysis.

[0008] This is especially true for conventional structures that are intended to achieve robust data retention and data readability. Specifically, conventional techniques that increase the ability to retain and distinguish data for readout also typically increase the ability of extraction techniques to distinguish data. Summary of the invention

[0009] According to one embodiment, a physically unclonable functional device includes: a set of floating gate transistor pairs, the floating gate transistors in the floating gate transistor pair set having randomly distributed effective threshold voltages belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of the floating gate transistors of the floating gate transistor pairs in the floating gate transistor pair set, and identify the floating gate transistor pairs in which the measured threshold difference is less than a margin value as unreliable floating gate transistor pairs; and a write circuit configured to shift the effective threshold voltages of the floating gate transistors of the unreliable floating gate transistor pairs to within the common random distribution.

[0010] According to another embodiment, a method includes: providing a set of floating gate transistor pairs, wherein effective threshold voltages of the floating gate transistors in the set of floating gate transistor pairs are randomly distributed according to a common random distribution; measuring a threshold difference between the effective threshold voltages of the floating gate transistors in the set of floating gate transistor pairs, and identifying a floating gate transistor pair in the set of floating gate transistor pairs whose measured threshold difference is less than a margin value as an unreliable floating gate transistor pair; and shifting the effective threshold voltages of the floating gate transistors in the unreliable floating gate transistor pair to within the common random distribution.

[0011] According to yet another embodiment, an integrated circuit includes: a plurality of floating gate transistor pairs, wherein a first floating gate transistor of each of the plurality of floating gate transistor pairs is coupled to a first bit line, and a second floating gate transistor of each of the plurality of floating gate transistor pairs is coupled to a second bit line, and the floating gate transistors in the plurality of floating gate transistor pairs have a randomly distributed effective threshold voltage according to a common random distribution; a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to measure a threshold difference between the first floating gate transistor and the second floating gate transistor of each of the plurality of floating gate transistor pairs, and compare the measured threshold difference with a predetermined threshold; and a write circuit coupled to gates of the first floating gate transistor and the second floating gate transistor of each of the plurality of floating gate transistor pairs, wherein the write circuit is configured to shift the effective threshold voltage of the first floating gate transistor and the second floating gate transistor of each floating gate transistor pair so that the measured threshold difference is greater than the predetermined threshold and within the common random distribution. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other advantages and features of the present invention will become apparent by examining the detailed description of a purely non-limiting implementation and embodiment and the accompanying drawings, in which:

[0013] Figure 1A The threshold distribution of the memory is illustrated;

[0014] Figure 1B A scanning capacitance micrograph SC of a transistor storing data is shown;

[0015] Figure 2 An example embodiment of the present invention is illustrated;

[0016] Figure 3 An example embodiment of the present invention is illustrated;

[0017] Figure 4 An example embodiment of the present invention is illustrated;

[0018] Figure 5 An example embodiment of the present invention is illustrated;

[0019] Figure 6 An example embodiment of the present invention is illustrated;

[0020] Figure 7 An example embodiment of the present invention is illustrated;

[0021] Figure 8 An example implementation of the present invention is illustrated;

[0022] Fig. 9 An example implementation of the present invention is illustrated;

[0023] Fig.10 An exemplary embodiment of the present invention is illustrated. DETAILED DESCRIPTION

[0024] Implementations and embodiments of the present invention relate to physically unclonable functions (PUFs), particularly in structures including floating gate transistors.

[0025] According to one embodiment, the differential read circuit is further configured to read a logic state of a pair of floating gate transistors, the logic state being defined by a difference between values ​​of effective threshold voltages of the pair of floating gate transistors that is greater than a margin value.

[0026] According to one embodiment, the write circuit is configured to shift the effective threshold voltage of each unreliable pair of floating gate transistors so as to increase the difference between the effective threshold voltages above a margin value.

[0027] According to one embodiment, a write circuit for shifting an effective threshold voltage of a floating gate transistor is configured to generate a series of write pulses, each write pulse injecting a substantial amount of charge into a floating gate of the floating gate transistor.

[0028] According to one embodiment, the differential read circuit is configured to perform a margin verification between at least some of the write pulses, the margin verification comprising comparing a difference between values ​​of effective threshold voltages of a pair of floating gate transistors to a margin value.

[0029] According to one embodiment, the logic states of the sets of paired floating-gate transistors are intended to form a random data sequence.

[0030] An integrated circuit may comprise a physically unclonable functional device such as defined in the following embodiments, and an encryption device configured to encrypt data using a key, the key advantageously comprising a random data sequence.

[0031] According to another aspect, a process is provided that includes generating a physically unclonable function, the generation comprising: manufacturing a set of pairs of floating gate transistors intended to have the same threshold voltage; randomly dispersing the effective values ​​of the threshold voltages of the floating gate transistors to form a common random distribution of the threshold voltages of the floating gate transistors; measuring the difference between the effective threshold voltages of the pairs of floating gate transistors, and identifying so-called unreliable pairs of floating gate transistors whose difference between their effective threshold voltages is less than a margin value; shifting the effective threshold voltage of the floating gate transistors in each unreliable pair in a controlled and limited manner so that the shifted threshold voltage remains within the common random distribution.

[0032] According to one implementation, the common random distribution is the distribution of threshold voltages of pristine floating-gate transistors that have never been written to.

[0033] According to one implementation, the process also includes reading a logic state of a pair of floating gate transistors, the logic state defined by a difference between values ​​of effective threshold voltages of the pair of floating gate transistors that is greater than a margin value.

[0034] For example, the shifting includes increasing the difference between the effective threshold voltages of the floating gate transistors in the unreliable pair above a margin value.

[0035] According to one implementation, the shifting of the effective threshold voltage of one of the floating-gate transistors in the unreliable pair includes a series of write pulses, each write pulse injecting a substantial amount of charge into the floating gate of the floating-gate transistor.

[0036] Advantageously, the shifting comprises a margin verification between at least some of the write pulses, the margin verification comprising measuring the difference between the values ​​of the effective threshold voltages of pairs of floating-gate transistors and comparing the measured difference with a margin value.

[0037] According to one implementation, the logic states of the sets of pairs of floating-gate transistors are intended to form a random data sequence.

[0038] The encryption method may advantageously comprise encrypting the data using a key comprising a random data sequence obtained using a process such as defined by the latter implementation.

[0039] Figure 1A A conventional technique for achieving robust data retention and data readability is illustrated, in which data is defined by the level of a floating gate transistor threshold voltage Vt. The threshold voltage level is set by injecting positive or negative charge into the floating gate. A first floating gate transistor has a threshold voltage Vt belonging to a low level distribution D1, which allows, for example, a first logic value "1" to be defined. A second floating gate transistor has a threshold voltage Vt belonging to a high level distribution D0, which allows, for example, a second logic value "0" to be defined.

[0040] Figure 1B Illustrated using reference Figure 1A Scanning capacitance micrograph SC of a floating gate transistor that stores data using the technology presented. If the position of the floating gate transistor is known, the stored data sequence 1010 can be easily extracted. Specifically, the channel region of the first floating gate transistor in the black circle (whose threshold voltage belongs to the low level distribution D1) and the channel region of the second floating gate transistor in the white circle (whose threshold voltage belongs to the high level distribution D0) can be seen in the image SC. Of course, this is problematic.

[0041] Therefore, there is a need to provide a physically unclonable functional structure that is robust against external changes or aging and whose data can be clearly distinguished for readout while being difficult to extract. Furthermore, it would be beneficial if the structure could be easily manufactured in the prior art.

[0042] According to one aspect, a physically unclonable functional device is provided, comprising: a set of pairs of floating gate transistors intended to have the same threshold voltage but each having an effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure the difference between the effective threshold voltages of the pairs of floating gate transistors and identify so-called unreliable pairs of floating gate transistors whose difference between their effective threshold voltages is less than a margin value; and a write circuit configured to shift the effective threshold voltage of the floating gate transistor in each unreliable pair in a controlled and limited manner so that the shifted threshold voltage remains within the common random distribution.

[0043] Therefore, the device according to this aspect benefits from the advantages of floating gate transistor data storage, i.e. very good retention, robustness and well characterized manufacturing process and operating parameters. Since the effective threshold voltages all belong to a common random distribution, the function is not only physically unclonable, but also cannot be extracted using the microscopic techniques of the art. In unreliable pairs, the shift of the effective threshold voltage allows to ensure the feasibility of the technology, in particular to ensure the distinction between two effective threshold voltages that may be equal or very close.

[0044] The common random distribution is advantageously the distribution of threshold voltages of pristine floating-gate transistors that have never been written to.

[0045] Figure 2 An example embodiment of a physically unclonable functional device DIS is shown.The device DIS comprises a set ENS of pairs P of floating gate transistors FGT1, FGT2.

[0046] Conventionally, a floating gate transistor includes: a source region and a drain region implanted in a semiconductor body; a channel region in the body between the source region and the drain region; and a conductive floating gate insulated from the channel region and from a control gate located above the floating gate. The threshold voltage of a floating gate transistor is the voltage between the source region and the control gate, according to which the channel region is depleted and turned on.

[0047] A floating gate transistor is written when charge is injected into the floating gate and trapped therein. The charge modifies the threshold voltage of the transistor being written, depending on its sign, and is then programmed or erased.

[0048] The floating gate transistors FGT1 , FGT2 of the set ENS are intended to have the same threshold voltage.

[0049] As such, the effective threshold voltage (i.e., the actual value of the threshold voltage) varies slightly according to random dispersion, for example due to physical manufacturing variables. This type of dispersion is common and known per se. The effective threshold voltage of each pair of floating gate transistors referenced by FGT1 is referenced by A1-F1, and the effective threshold voltage of each pair of floating gate transistors referenced by FGT2 is referenced by A2-F2.

[0050] Therefore, both floating gate transistors FGT1, FGT2 of the set ENS have effective threshold voltages belonging to a common random distribution.

[0051] In particular, the floating gate transistors FGT1, FGT2 can advantageously remain in the original state, ie without charge injection into their floating gates. Thus, in this particular case, the common random distribution is the distribution of the threshold voltages Vteff of the original floating gate transistors that have never been written to.

[0052] Figure 3 The diagram shows a scanning capacitance micrograph of a floating gate transistor belonging to the set ENS. Each floating gate transistor has an effective threshold voltage that belongs to a common distribution of the original floating gate transistor threshold voltages Vteff. Therefore, it is not possible to see any difference between the values ​​of the threshold voltages using current microscopy techniques.

[0053] Alternatively, the floating-gate transistors FGT1 , FGT2 of the set ENS may optionally all be programmed (ie all have a negative charge on their floating gates) or erased (ie have positive charge injected into their floating gates).

[0054] Reference again Figure 2 , the device DIS comprises a differential read circuit LECT, which is configured to measure the difference between the effective threshold voltages of the pair P of floating-gate transistors FGT1, FGT2.

[0055] The differential read circuit LECT comprises two differential inputs to which each pair P of floating-gate transistors FGT1 , FGT2 is coupled, in particular, via a corresponding bit line BL1 , BL2 , respectively.

[0056] In this regard, now refer to Figure 4 and Figure 5 .

[0057] Figure 4 An example of an embodiment of a differential read circuit LECT coupled to a pair of floating gate transistors FGT1, FGT2 via respective bit lines BL1, BL2 is shown. In this example, the floating gate transistors FGT1, FGT2 belong to respective memory cells CEL1, CEL2, wherein the access floating gate transistors TA1, TA2 are connected via their drains to the sources of the floating gate transistors FGT1, FGT2 and via their sources to the ground GND.

[0058] The access floating-gate transistors TA1, TA2 are controlled via their gates by signals transmitted on the respective word lines WL1, WL2. As will become clear below, the word lines WL1, WL2 may optionally be common to a pair, i.e., electrically connected or even formed by the same conductive line. The control gates of the floating-gate transistors FGT1, FGT2 are connected to the respective control gate lines CGL1, CGL2. Likewise, the control gate lines CGL1, CGL2 may optionally be common to a pair of floating-gate transistors, i.e., electrically connected or even formed by the same conductive line. The drains of the floating-gate transistors FGT1, FGT2 are connected, for their part, to the respective bit lines BL1, BL2.

[0059] Bit line BL1 allows one floating gate transistor FGT1 of the pair to be coupled to a first input E1 of a sense amplifier AMP. Bit line BL2 allows the other floating gate transistor FGT2 of the pair to be coupled to a second input E2 of the sense amplifier AMP.

[0060] The other floating-gate transistors in the set ENS of pairs P are coupled in the same way to the sense amplifier AMP, and the respective input switches TBL1 , TBL2 allow the desired pair of bit lines BL1 , BL2 to be selected.

[0061] Furthermore, the read circuit LECT comprises a reference current generator IGEN which generates a reference current IREF drawn by the first input E1 or by the second input E2 depending on the position of the respective switch SW1 , SW2 .

[0062] Figure 5An example of an embodiment of a differential read circuit LECT in operation is shown. The read amplifier AMP is configured to amplify the difference between the current through its first input E1 and the current through its second input E2. To this end, the input switches TBL1, TBL2 are controlled so as to couple the bit lines BL1, BL2 of the desired pair of floating gate transistors. The access floating gate transistors TA1, TA2 of each floating gate transistor FGT1, FGT2 are turned on by the voltage transmitted on the word lines WL1, WL2. Likewise, the floating gate transistors FGT1, FGT2 are controlled by the control gate voltage transmitted on the control gate lines CGL1, CGL2.

[0063] Therefore, the floating gate transistor FGT1 in the pair is placed so that the read current I1 flows from the first input E1 to the ground GND. The other floating gate transistor FGT2 in the pair is also placed so that the read current I2 flows from the second input E2 to the ground GND.

[0064] Since the read currents I1 , I2 represent the effective threshold voltages of the respective floating gate transistors FGT1 , FGT2 , the difference between the currents I1 , I2 represents the difference between the effective threshold voltages of the pair of floating gate transistors FGT1 , FGT2 .

[0065] Therefore, the differential read circuit LECT is able to measure the difference between the effective threshold voltages of the pair of floating gate transistors FGT1, FGT2.

[0066] Furthermore, an additional current IREF generated by one of the reference current generators IGEN can be added to one of the currents I1, I2 through the inputs E1, E2 via control of the switches SW1, SW2. In the example shown, the switch SW2 is closed and the current IREF is added to the current I2 of the second input E2.

[0067] This allows the difference between the effective threshold voltages to be measured relative to a certain margin. The value of the margin corresponds to the current IREF, which represents the reference voltage deviation. In particular, the margin value is selected according to the accuracy of the differential read circuit LECT.

[0068] Reference now Figure 6 , which shows examples of various threshold voltage values ​​A1, B1, C1, D1, E1, F1 of one floating gate transistor FGT1 in each pair of the set ENS, and threshold voltage values ​​A2, B2, C2, D2, E2, F2 of the corresponding other floating gate transistor FGT2 in each pair. The values ​​A1 to F1, A2 to F2 all belong to a common random distribution DST of the effective threshold voltage Vteff.

[0069] According to an example embodiment, a differential read circuit LECT (eg, as shown in FIG. Figure 4 and Figure 5The described) is also configured to read the logic state DAT of each pair of floating gate transistors FGT1, FGT2. The logic state DAT is defined by the difference between the effective threshold voltage values ​​of the pair that is greater than the margin value MRG. For example, if X1>X2+MRG, then DAT=1, and if X2>X1+MRG, then DAT=0, where X1 is any one of the values ​​A1 to F1, and X2 is any one of the values ​​A2 to F2.

[0070] Thus, a logical state is obtained in a physically unclonable manner using random deviations in the values ​​of the effective threshold voltages of the two floating gate transistors in a pair. Assuming these effective threshold voltages are close and belong to a common random distribution DST, it is not possible to distinguish either of the two stored data by microscopic inspection.

[0071] It will be noted that in the figure, some pairs of threshold voltage values ​​C1, C2 and E1, E2 may be close and their deviation is less than the margin value MRG. Pairs of floating gate transistors having these pairs of values ​​are called unreliable pairs NF.

[0072] Reference again Figure 2 , the differential read circuit LECT is configured to use, for example, a reference circuit such as the above Figure 4 and Figure 5 The differential measurement is used to identify the floating-gate transistors of the pair P belonging to the so-called unreliable pair NF. If the difference between the effective threshold voltages of the floating-gate transistors is less than the margin value (e.g., as described above with reference to Figure 4 and Figure 5 The margin value MRG), the floating gate transistors FGT1 and FGT2 in pair P are called unreliable.

[0073] The device DIS finally comprises a write circuit ECR capable, inter alia, of generating a write pulse IMP.

[0074] The write pulse IMP is configured to obtain a condition for soft programming the floating gate transistor so as to increase a threshold voltage value of the floating gate transistor by injecting hot carriers into the floating gate.

[0075] In other words, in contrast to a conventional EEPROM memory erase or program pulse in which the drain-floating-gate voltage is approximately 8 to 12 volts, the write pulse IMP is limited such that the drain-floating-gate voltage is, for example, approximately 4.5 to 5 volts.

[0076] Furthermore, the generation of the write pulses is controlled, ie, for example, this includes checking the phase in order to adjust the generation of the pulses. In this respect, reference may be made to the following references Fig. 9 An example implementation is described.

[0077] Thus, unlike creating two populations of floating-gate transistors whose threshold voltages are strictly different (e.g., Figure 1A In contrast to conventional programming and erasing (as shown in FIG. 1 ), the controlled and limited write pulse IMP allows the threshold voltage to shift slightly so that the newly shifted threshold voltage can be reasonably considered to belong to the same common random distribution.

[0078] In this regard, reference Figure 7 , which returns Figure 6 In the example shown, the effective threshold voltages C2 and E1 of one floating gate transistor in each unreliable pair NF have been shifted to shifted values ​​C2', E1'.

[0079] The write circuit ECR is configured to shift the effective threshold voltages C2, E1 of the floating gate transistors in each unreliable pair NF so as to increase the difference between the effective threshold voltages above a margin value MRG.

[0080] This allows the logic state DAT defined by the difference between the values ​​of the effective threshold voltages of the pair that is greater than the margin value MRG to be reliably read in the pair identified as the unreliable pair NF.

[0081] Of course, in theory, this means slightly modifying the initial distribution DST to a shifted distribution DST'. In this way, it is reasonable to consider that the shifted values ​​C2' and E1' belong to the initial common distribution (i.e., the common random distribution DST obtained at the time of manufacturing). In particular, compared with the threshold voltage distribution D1 of the conventionally programmed transistor and the threshold voltage distribution D0 of the conventionally erased transistor (also corresponding to Figure 1A ), distributions DST and DST' are very similar and are considered to be the same.

[0082] In other words, the write circuit ECR is configured to shift the effective threshold voltage of the floating gate transistors in each unreliable pair NF in a controlled and limited manner within the common random distribution DST.

[0083] In any case, as long as the values ​​of the shifted threshold voltages cannot be distinguished using scanning microscopy techniques, they can be considered to lie within a common random distribution DST.

[0084] The populations of programmed and erased transistors of the distributions D1, D0 can be distinguished by a microscope, but the populations of floating-gate transistors of the initial distribution DST and the shifted distribution DST' cannot be distinguished.

[0085] Figure 8 Examples of implementations, including in particular the process of generating a physical unclonable function, are shown. Figures 2 to 7 related.

[0086] The process comprises a step 71 of manufacturing a set ENS of floating-gate transistors FGT1 , FGT2 in pairs P. The manufacturing of the floating-gate transistors is identical, so that the manufactured floating-gate transistors are intended to have the same threshold voltage.

[0087] For example, the transistor so fabricated is intended to have the threshold voltage of an original floating gate transistor that has never been written to.

[0088] The process includes a random dispersion 72 of the effective values ​​of the threshold voltages Vteff of the floating gate transistors. The dispersion is caused in particular by physical manufacturing variations and is therefore at least partially accomplished directly in the manufacturing step 71. The dispersion of the effective values ​​forms a common random distribution DST of the threshold voltages of the floating gate transistors of the set ENS.

[0089] It is conceivable that the conditions for enhanced random dispersion are achieved in a dedicated step or in the manufacturing step 71 .

[0090] The process comprises the steps of measuring 73 the difference between the effective threshold voltages Vteff of pairs of floating gate transistors and identifying 74 pairs of floating gate transistors considered to be unreliable pairs NF, the difference between the effective threshold voltages of the unreliable pairs NF being smaller than a margin value MRG.

[0091] Finally, the process consists in shifting 75 the effective threshold voltage of the floating gate transistors in each unreliable pair NF in a controlled and limited manner within the common random distribution DST.

[0092] The shift 75 is implemented in order to increase the difference between the effective threshold voltages of the floating gate transistors in the unreliable pair NF above the margin value MRG.

[0093] Reference now Fig. 9 , Fig. 9 An example of an implementation of the shift 75 is illustrated. In this example, the shift 75 of the effective threshold voltage comprises a series of write pulses 751. Each write pulse 751 injects a substantial amount of charge into the floating gate of the floating gate transistor whose threshold voltage is to be shifted. In the sequence, a margin verification (752, 753) is performed between at least some of the write pulses 751. The margin verification comprises measuring 752 the difference between the values ​​of the effective threshold voltages of pairs of floating gate transistors after one or more write pulses 751, and then comparing 753 the measured difference with a margin value MRG.

[0094] If the measured difference 752 is smaller than the margin value MRG(nok), a new cycle including a write pulse 751 and margin verification 752, 753 is added to the sequence.

[0095] When the measured difference 752 is greater than or equal to the margin value MRG(ok), the shift 75 ends 754. By means of the margin verification 752, 753 in the sequence of write pulses 751, the threshold voltage is shifted in a controlled manner so as not to cause the threshold voltage value to lie outside the common random distribution DST obtained during manufacturing.

[0096] Reference again Figure 8 , the process may further include step 76 of reading a logic state DAT of the pair of floating-gate transistors, the logic state being defined by a difference between the values ​​of the effective threshold voltage Vteff of the pair being greater than a margin value MRG.

[0097] The logic state DAT thus formed in the set ENS of pairs P of floating-gate transistors FGT1 , FGT2 may be intended, for example, to form a random data sequence.

[0098] Fig.10 For example, using references such as those above Figure 8 and Fig. 9 The integrated circuit CI obtained by the described process includes the integrated circuit CI as described above. Figures 2 to 7 The physically unclonable functional device DIS described.

[0099] In the device DIS, the logic states DAT of the set ENS of pairs P of floating-gate transistors FGT1 , FGT2 are therefore intended to form a random data sequence.

[0100] In this example, the integrated circuit CI is able to execute an encryption method consisting in encrypting the CFR data DNC using a key K comprising a random data sequence formed and stored in the set ENS of pairs of floating-gate transistors.

[0101] The encryption circuit CFR incorporated in the integrated circuit CI is configured to encrypt the data DNC using the key K.

[0102] Furthermore, the integrated circuit CI may comprise a non-volatile memory NVM comprising memory cells each having a floating gate state transistor advantageously manufactured in the same manufacturing step 71 as the set ENS of pairs P of floating gate transistors FGT1 , FGT2 .

[0103] In summary, a physical unclonable function technology has been proposed in which the logic state is defined by the relative difference between two pieces of information belonging to the same distribution. The data cannot be extracted using prior art methods (scanning capacitance microscopy (SCM) or scanning electron microscopy (SEM)). The technology does not require a specific and dedicated process.

[0104] Furthermore, the present invention is not limited to these embodiments, but covers, for example, all modifications thereof, even if the above reference Figure 4 and Figure 5 The example embodiments described involve current mode differential sense amplifiers, but differential sensing can also be performed in voltage mode, or indeed even Figure 6 and Figure 7 The shift direction shown in is increasing, but it can also be reduced by injecting charges of opposite sign.

Claims

1. A physically unclonable functional device, comprising: a set of floating gate transistor pairs, the floating gate transistors in the set of floating gate transistor pairs having randomly distributed effective threshold voltages belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of floating gate transistors of a floating gate transistor pair in the set of floating gate transistor pairs, and identify a floating gate transistor pair in which the measured threshold difference is less than a margin value as an unreliable floating gate transistor pair, and detect a first logic state when the effective threshold voltage of a first transistor of the floating gate transistor pair is greater than a sum of an effective threshold voltage of a second transistor of the floating gate transistor pair and the margin value; and the differential read circuit is configured to detect a second logic state when the effective threshold of the second transistor of the floating gate transistor pair is greater than the sum of the effective threshold of the first transistor and the margin value; as well as A write circuit is configured to shift the effective threshold voltage of the floating gate transistor of the unreliable floating gate transistor pair to within the common random distribution. 2 . The device of claim 1 , wherein the common random distribution is a distribution of threshold voltages of floating-gate transistors that have never been written to.

3. The device of claim 1, wherein the write circuit is configured to shift the effective threshold voltage of the floating gate transistor by generating conditions for hot carrier injection to trap charge in a gate dielectric of the floating gate transistor.

4. The device of claim 3 , wherein the write circuit is configured to generate the conditions for hot carrier injection by applying a series of write pulses, each of the write pulses being configured to inject a substantial amount of charge into the floating gate of the floating gate transistor.

5. The device of claim 4, wherein the differential read circuit is configured to perform a margin verification after at least one write pulse in the series of write pulses, wherein performing the margin verification comprises comparing the measured threshold difference with the margin value.

6. The device of claim 1 , wherein the differential read circuit is further configured to read a logic state of a floating gate transistor pair in the floating gate transistor pair set, wherein when a voltage difference between the effective threshold voltages of the floating gate transistors in the floating gate transistor pair exceeds the margin value, the logic state is defined by the voltage difference.

7. The device of claim 6, wherein the logic states of the set of floating gate transistor pairs form a random data sequence.

8. An integrated circuit comprising: The physically unclonable functional device according to claim 7; as well as An encryption device is configured to encrypt data using a key, wherein the key includes the random data sequence.

9. A method for preventing physical cloning, comprising: providing a set of floating gate transistor pairs, wherein effective threshold voltages of floating gate transistors in the set of floating gate transistor pairs are randomly distributed according to a common random distribution; measuring a threshold difference between effective threshold voltages of floating gate transistors in the floating gate transistor pair set, and identifying a floating gate transistor pair in the floating gate transistor pair set whose measured threshold difference is less than a margin value as an unreliable floating gate transistor pair; as well as shifting the effective threshold voltage of a floating-gate transistor in the unreliable floating-gate transistor pair to within the common random distribution; detecting a first logic state when an effective threshold of a first floating gate transistor of the floating gate transistor pair set is greater than a sum of an effective threshold of a second floating gate transistor of the floating gate transistor pair set and the margin value; and A second logic state is detected when the effective threshold of the second floating-gate transistor is greater than the sum of the effective threshold of the first floating-gate transistor and the margin value.

10. The method of claim 9, wherein the shifting comprises: The threshold difference of the unreliable floating gate transistor pair is increased above the margin value.

11. The method of claim 9, wherein shifting the effective threshold voltage of the floating gate transistor comprises: A series of write pulses are applied that each inject a substantial amount of charge into the floating gate of the floating gate transistor.

12. The method according to claim 11, further comprising: A margin verification is performed after at least one write pulse in the series of write pulses, wherein performing the margin verification includes comparing the measured threshold difference with the margin value.

13. The method according to claim 9, further comprising: A logic state of a floating gate transistor pair in the set of floating gate transistor pairs is read, wherein the logic state is defined by the threshold difference when the threshold difference exceeds a margin value.

14. The method of claim 13, wherein the logic states of the set of floating gate transistor pairs form a random data sequence.

15. The method according to claim 14, further comprising: Data is encrypted using a key, wherein the key includes the random data sequence.

16. The method according to claim 9, further comprising: The set of floating gate transistor pairs is fabricated, wherein each transistor in the set of floating gate transistor pairs is fabricated to have a same nominal threshold voltage.

17. The method of claim 16, wherein the common random distribution is a distribution of threshold voltages of floating gate transistors that have never been written to.

18. An integrated circuit comprising: a plurality of floating gate transistor pairs, wherein a first floating gate transistor of each of the plurality of floating gate transistor pairs is coupled to a first bit line, and a second floating gate transistor of each of the plurality of floating gate transistor pairs is coupled to a second bit line, and the floating gate transistors in the plurality of floating gate transistor pairs have randomly distributed effective threshold voltages according to a common random distribution; a read circuit having a first input coupled to the first bit line and a second input coupled to the second bit line, wherein the read circuit is configured to measure a threshold difference between the first floating gate transistor and the second floating gate transistor of each of the plurality of floating gate transistor pairs and compare the measured threshold difference to a predetermined threshold; as well as a write circuit coupled to gates of the first floating-gate transistor and the second floating-gate transistor of each of the plurality of floating-gate transistor pairs, wherein the write circuit is configured to shift the effective threshold voltages of the first floating-gate transistor and the second floating-gate transistor of each floating-gate transistor pair so that the measured threshold difference is greater than the predetermined threshold and within the common random distribution; wherein: A first set of floating gate transistor pairs in the plurality of floating gate transistor pairs comprises a logic state; Each logic state is one of a first logic state or a second logic state; The read circuit is configured to detect the first logic state when the effective threshold of the first floating-gate transistor is greater than the sum of the effective threshold of the second floating-gate transistor and the predetermined threshold; and The read circuit is configured to detect the second logic state when the effective threshold of the second floating-gate transistor is greater than a sum of the effective threshold of the first floating-gate transistor and the predetermined threshold.

19. The integrated circuit of claim 18, wherein the read circuit comprises: a read amplifier coupled to the first input and the second input of the read circuit; as well as A reference current generator is coupled to the first input or the second input, wherein the read circuit is configured to compare the measured threshold difference with the predetermined threshold by activating the reference current generator and measuring a voltage difference between the first input and the second input.

20. The integrated circuit of claim 18, wherein the write circuit is configured to shift the effective threshold voltage of the first floating gate transistor or the second floating gate transistor of each floating gate transistor pair by applying at least one write pulse to the corresponding first floating gate transistor or the second floating gate transistor.

21. The integrated circuit of claim 18, further comprising an encryption circuit coupled to the plurality of floating gate transistor pairs, wherein the encryption circuit is configured to use the logic states of the plurality of floating gate transistor pairs as an encryption key.

Images