Integrated Circuit Device and Method for Manufacturing the Same

Abstract

An integrated circuit device and a method of manufacturing the same are provided. The integrated circuit device may include a plurality of word line structures and a plurality of insulating films that are alternately stacked. Side surfaces of the plurality of word line structures and the plurality of insulating films define side surfaces of a channel hole that extends through the plurality of word line structures and the plurality of insulating films. The device may further include a blocking dielectric film on the side surfaces of the channel hole, and a plurality of charge storage films on the blocking dielectric film and respectively on the side surfaces of the plurality of word line structures. Each of the plurality of charge storage films may include a first charge storage film and a second charge storage film that are sequentially stacked on a corresponding one of the side surfaces of the plurality of word line structures. A surface of the second charge storage film may include a recess in a middle portion thereof.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2019 - 0021288, filed on February 22, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept relates to an integrated circuit device and a method of manufacturing the same, and more particularly, to an integrated circuit device including a non - volatile vertical memory device and a method of manufacturing the same. Background art

[0004] As the capacity and integration degree of integrated circuit devices increase, a vertical memory device has been proposed to increase the storage capacity by stacking a plurality of memory cells in a vertical direction on a substrate. When the cell stacking density in the vertical direction increases in the vertical memory device, the vertical height of each memory cell and the interval between memory cells adjacent to each other in the vertical direction decrease. Therefore, an insufficient amount of charge may not be stored in the memory cells, or interference may occur between adjacent memory cells, and thus, the reliability of the integrated circuit device may deteriorate. Summary of the invention

[0005] The present inventive concept provides an integrated circuit device and a method of manufacturing the same, which can store a sufficient amount of charge in each memory cell and have a structure capable of reducing interference between adjacent memory cells and improving reliability even when the vertical height of each memory cell and the interval between memory cells adjacent to each other in the vertical direction are relatively small in a highly miniaturized vertical memory device.

[0006] According to an aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of word line structures extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping with each other in a vertical direction perpendicular to the main surface of the substrate; a plurality of insulating films stacked alternately with the plurality of word line structures in the vertical direction and extending in the horizontal direction, wherein sides of the plurality of word line structures and sides of the plurality of insulating films define sides of a channel hole extending through the plurality of word line structures and the plurality of insulating films; a blocking dielectric film extending on the sides of the channel hole; and a plurality of charge storage films spaced apart from each other on the blocking dielectric film in the channel hole and respectively located on the sides of the plurality of word line structures, each of the plurality of charge storage films including a first charge storage film and a second charge storage film sequentially stacked on a corresponding one of the sides of the plurality of word line structures, wherein the second charge storage film includes a first surface facing the blocking dielectric film and a second surface opposite to the first surface, and the second surface of the second charge storage film includes a recess in an intermediate portion thereof in the vertical direction.

[0007] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of word line structures extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping with each other in a vertical direction perpendicular to the main surface; a plurality of insulating films stacked alternately with the plurality of word line structures in the vertical direction and extending in the horizontal direction, wherein sides of the plurality of word line structures and sides of the plurality of insulating films define sides of a channel hole extending through the plurality of word line structures and the plurality of insulating films; a channel film extending in the vertical direction in the channel hole; a blocking dielectric film located in the channel hole and extending on the sides of the plurality of word line structures and the sides of the plurality of insulating films in the channel hole, the blocking dielectric film including a surface facing the channel film, and the surface including a plurality of grooves respectively located on the sides of the plurality of word line structures; and a plurality of charge storage films, wherein at least a portion of each of the plurality of charge storage films is located in a corresponding one of the plurality of grooves of the blocking dielectric film.

[0008] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of word line structures extending on a substrate in a horizontal direction parallel to a main surface of the substrate and overlapping each other in a vertical direction perpendicular to the main surface; a plurality of insulating films stacked alternately with the plurality of word line structures in the vertical direction and extending in the horizontal direction, wherein side surfaces of the plurality of word line structures and side surfaces of the plurality of insulating films define side surfaces of channel holes extending through the plurality of word line structures and the plurality of insulating films; a channel film extending in the vertical direction in the channel holes; a blocking dielectric film extending on the side surfaces of the plurality of word line structures and the side surfaces of the plurality of insulating films in the channel holes; at least one charge storage film located on the blocking dielectric film in the channel holes; and a tunneling dielectric film extending on the blocking dielectric film and the at least one charge storage film in the channel holes, and the channel film extends on the tunneling dielectric film. A side surface of each of the plurality of insulating films facing the channel film protrudes toward the channel film beyond a side surface of each of the plurality of word line structures, a surface of the blocking dielectric film facing the channel film includes a plurality of grooves respectively located on the side surfaces of the plurality of word line structures, and at least a part of the at least one charge storage film is located in one of the plurality of grooves of the blocking dielectric film.

[0009] According to another aspect of the inventive concept, there is provided a method of manufacturing an integrated circuit device, the method including: forming a structure including a plurality of first films and a plurality of second films stacked alternately with the plurality of first films on a substrate; forming channel holes extending through the structure; forming a plurality of recessed spaces in the channel holes by removing a part of the plurality of second films through the channel holes; forming a blocking dielectric film on the plurality of first films and the plurality of second films in the channel holes, the blocking dielectric film including a plurality of grooves respectively located on the plurality of recessed spaces; and forming at least one charge storage film including a first charge storage film located in one of the plurality of grooves and a second charge storage film located on the first charge storage film. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to some embodiments of the inventive concept;

[0012] Figure 2A top view of the main components of an integrated circuit device according to some embodiments of the inventive concept;

[0013] Figure 3 is a cross-sectional view taken along the Figure 2 line X1-X1';

[0014] FIG. 4A to FIG. 4G is Figure 3 an enlarged cross-sectional view of region P1 of;

[0015] Figures 5A to 5P is an enlarged cross-sectional view showing a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept;

[0016] Fig. 6A , Figure 6C , 7A to 7I , FIG. 8A to FIG. 8C , Fig. 9A , FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C , Fig.14A and Fig.16A is an enlarged cross-sectional view showing a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept;

[0017] Figure 6B , Fig.6D , Figure 7J , Fig.8D , Fig. 9B , Fig. 10D , Fig.11 , Fig.12D , Fig.13 , Fig. 14B , Fig.15 , Fig. 16B , Fig.17 , Fig.18 , Fig.19 and Fig. 20 is an enlarged cross-sectional view of an integrated circuit device according to some embodiments of the inventive concept;

[0018] Fig.21 is a cross-sectional view of an integrated circuit device according to some embodiments of the inventive concept; specifically, Fig.21 is a cross-sectional view of the integrated circuit device at a position corresponding to the Figure 2 line X1-X1';

[0019] Fig. 22 is Fig.21 an enlarged cross-sectional view of region P2 of;

[0020] FIG. 23A to FIG. 23F is an enlarged cross-sectional view showing a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept;

[0021] Fig.24A and Fig. 24B 、 Fig.25A and 25B 、 Fig.26A 、 FIG. 27A to FIG. 27D and Figures 28A to 28D are enlarged cross-sectional views showing methods of manufacturing integrated circuit devices according to some embodiments of the inventive concept;

[0022] Fig.24C 、 Fig.25C 、 Fig.26B 、 Fig.27E and Fig.28E are enlarged cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept;

[0023] Fig.29 is a plan layout view of an integrated circuit device according to some embodiments of the inventive concept;

[0024] Fig. 30A is a schematic perspective view of an integrated circuit device according to some embodiments of the inventive concept, Fig. 30B is Fig. 30A a schematic cross-sectional view of the integrated circuit device; and

[0025] Fig.31 is a schematic perspective view of an integrated circuit device according to some embodiments of the inventive concept. Detailed Description

[0026] Figure 1 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to some embodiments of the inventive concept. Specifically, Figure 1 is an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure.

[0027] Referring to Figure 1 , the memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include a plurality of bit lines BL (BL1, BL2, …, and BLm), a plurality of word lines WL (WL1, WL2, …, WLn-1, and WLn), at least one string select line SSL, at least one ground select line GSL, and a common source line CSL. The memory cell strings MS may be formed between the bit lines BL (BL1, BL2, ..., and BLm) and the common source line CSL.

[0028] Each memory cell string MS may include a string select transistor SST, a ground select transistor GST, and a plurality of memory cell transistors MC1, MC2, ..., MCn-1, and MCn. A drain region of the string select transistor SST may be connected to a bit line BL (BL1, BL2, ..., and BLm), and a source region of the ground select transistor GST may be connected to a common source line CSL. The common source line CSL may be a region to which a plurality of source regions of the plurality of ground select transistors GST are commonly connected.

[0029] The string select transistor SST may be connected to a string select line SSL, and the ground select transistor GST may be connected to a ground select line GSL. The memory cell transistors MC1, MC2, ..., MCn-1, and MCn may be respectively connected to word lines WL (WL1, WL2, ..., WLn-1, and WLn).

[0030] Figure 2 is a top view of main constituent elements of an integrated circuit device 100 according to some embodiments of the inventive concept. Figure 3 is along Figure 2 sectional view taken along line X1-X1'. FIG. 4A to FIG. 4G is by Figure 3 is an enlarged sectional view of a region P1 indicated by a dotted line in.

[0031] Reference Figure 2 and Figure 3 and, the integrated circuit device 100 may include a substrate 102 having an active region AC. A memory cell array MCA may be formed over the active region AC of the substrate 102. The memory cell array MCA may have a circuit configuration described with reference to Figure 1 .

[0032] The substrate 102 may have a main surface 102M extending in a first direction (X direction) and a second direction (Y direction) as horizontal directions. In some embodiments, the substrate 102 may include, for example, Si, Ge, or SiGe. In some embodiments, the substrate 102 may include, for example, a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0033] Reference Figures 1 to 3, in the memory cell array MCA, the memory cell transistors MC1, MC2, ..., MCn-1, and MCn forming the memory cell string MS may have a structure connected in series in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102. A plurality of channel structures CHS included in the string selection transistor SST, the ground selection transistor GST, and the memory cell transistors MC1, MC2, ..., MCn-1, and MCn may extend in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102. The channel structures CHS may be arranged to be spaced apart from each other at intervals therebetween in a first direction (X direction) and a second direction (Y direction).

[0034] Each channel structure CHS may include a semiconductor pattern 120 in contact with the substrate 102 and in the channel hole CHH (e.g., partially filling the channel hole CHH), a channel film 150 in contact with the semiconductor pattern 120 and extending in the third direction (Z direction) in the channel hole CHH, a buried insulating film 156 in the internal space of the channel film 150 (e.g., filling the internal space of the channel film 150), and a drain region 158 in contact with the channel film 150 and in the top inlet side of the channel hole CHH (e.g., filling the top inlet side of the channel hole CHH). In some embodiments, the channel film 150 may have a cylindrical shape with an internal space, and the internal space of the channel film 150 may be filled (e.g., partially filled or completely filled) with the buried insulating film 156. The channel film 150 may include, for example, polysilicon doped with impurities or polysilicon without doped impurities (e.g., polysilicon without intentionally added dopants). The buried insulating film 156 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buried insulating film 156 may be omitted. In this case, the channel film 150 may have a columnar structure without an internal space. The drain region 158 may include, for example, a polysilicon film doped with impurities. The drain regions 158 included in the channel structures CHS may be insulated from each other by an insulating pattern 114. The insulating pattern 114 may include, for example, an oxide film, a nitride film, or a combination thereof. It should be understood that an "element having a cylindrical shape" as used herein refers to an element including a bottom portion and a vertical portion protruding from the bottom portion in the vertical direction (e.g., Z direction). The side surface of the vertical portion of the element may be perpendicular or non-perpendicular to the main surface of the substrate (e.g., substrate 102). In some embodiments, the side surface of the vertical portion of the element may be inclined with respect to the main surface 102M of the substrate 102.

[0035] In the channel hole CHH, the blocking dielectric film 125, the charge storage film 130, the tunneling dielectric film 140, the channel film 150, and the buried insulating film 156 may be sequentially arranged, and the top inlet side of the channel hole CHH may be filled (e.g., partially filled or completely filled) with the drain region 158.

[0036] In the channel hole CHH, the blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 may each have a cylindrical shape. In the channel hole CHH, the charge storage film 130 may have an annular shape by being arranged at intervals of each other in the third direction (Z direction), or may have a cylindrical shape. The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 may each include a plurality of bent portions formed in a part covering the plurality of word line structures WS and the plurality of insulating films 110. In some embodiments, a plurality of charge storage films 130 spaced apart from each other in the third direction (Z direction) may be provided in a single channel hole CHH, as Figure 3 shown.

[0037] During the process of forming the blocking dielectric film 125, the charge storage film 130, and the tunneling dielectric film 140, a recessed surface 120R may be formed in the upper surface of the semiconductor pattern 120 by removing a partial region of the upper surface of the semiconductor pattern 120. The channel film 150 may be in contact with the recessed surface 120R of the semiconductor pattern 120.

[0038] The word line structure WS may extend on the substrate 102 along the X - Y plane in a horizontal direction parallel to the main surface 102M, and in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102, the word line structures WS may be arranged to be spaced apart from each other and vertically overlap each other. It should be understood that the phrase "element A vertically overlaps element B" (or similar language) mentioned here means that there is at least one vertical line that intersects both element A and element B.

[0039] The width of the word line structure WS in the first direction (X direction) may be limited by a plurality of word line cutting regions WLC. In a top view, the word line structures WS may be repeatedly arranged to be spaced apart from each other at a constant interval through the word line cutting regions WLC. In some embodiments, the integrated circuit device 100 may include multiple groups of word line structures WS, and each of the multiple groups of word line structures WS may include word line structures WS stacked along the third direction (Z direction). In some embodiments, the width of each of the multiple groups of word line structures WS in the first direction (X direction) may be equal to the distance between two adjacent word line cutting regions WLC, and the multiple groups of word line structures WS may be spaced apart from each other in the first direction (X direction).

[0040] A plurality of common source regions 160 may extend in the second direction (Y direction) in the substrate 102. In some embodiments, the common source regions 160 may be impurity regions highly doped with n-type impurities. The common source regions 160 may be used as source regions for supplying current to the vertical memory cells.

[0041] The word line cut region WLC may be partially filled with a common source line CSL. The common source line CSL may extend in the second direction (Y direction) in the common source region 160. Insulating spacers 170 for covering the sidewalls of the common source line CSL may be formed in the word line cut region WLC. The insulating spacers 170 may electrically insulate the common source line CSL from the word lines WL (WL1, WL2,..., WLn-1 and WLn). The common source line CSL and the insulating spacers 170 may be covered with a covering insulating film 172. For example, the common source line CSL may include: a metal such as tungsten, copper or aluminum; a conductive metal nitride such as titanium nitride or tantalum nitride; a transition metal such as titanium, tantalum; or a combination thereof. The insulating spacers 170 and the covering insulating film 172 may each include, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film or a combination thereof. In some embodiments, a metal silicide film (not shown) for reducing the contact resistance may be provided between the common source region 160 and the common source line CSL. For example, the metal silicide film may include cobalt silicide, tungsten silicide or nickel silicide. It should be understood that the phrase "element A covers the surface of element B" (or similar language) means that element A is on the surface of element B, but does not necessarily mean that element A completely covers the surface of element B.

[0042] The top insulating film 180 may cover the insulating pattern 114, the drain region 158 and the covering insulating film 172. A string selection line cut region SSLC formed by removing a part of the top insulating film 180, a part of the insulating pattern 114, a part of at least two upper insulating films in the insulating film 110 and a part of the two topmost word line structures in the word line structure WS may be filled with a cut insulating film 184. The cut insulating film 184 may include, for example, an oxide film, a nitride film, an air gap or a combination thereof. The term "air gap" as used in this specification may represent a space including a gas that may be present in air or may be used in a manufacturing process.

[0043] A plurality of bit line contact pads 182 may be respectively disposed in a plurality of bit line contact holes 180H penetrating partial regions of the top insulating film 180, and a plurality of bit lines BL on the top insulating film 180 may be connected to the bit line contact pads 182.

[0044] The word line structure WS located between two adjacent word line cut regions WLC may include reference Figure 1The described ground selection line GSL, word lines WL (WL1, WL2, ..., WLn-1, and WLn), and string selection lines SSL. The number of word line structures WS stacked on the substrate 102 in the third direction (Z direction) can be variably selected as needed. One of the word line structures WS closest to the substrate 102 can form the ground selection line GSL. The two uppermost word line structures WS in the word line structure WS can both form the string selection lines SSL. The string selection lines SSL can include portions separated by a string selection line cutting region SSLC.

[0045] The word line structure WS can include, for example, metals such as tungsten, nickel, cobalt, or tantalum, metal silicides such as tungsten silicide, nickel silicide, cobalt silicide, or tantalum silicide, doped polycrystalline silicon, or combinations thereof.

[0046] In some embodiments, a dielectric thin film covering the bottom and top surfaces of the word line structure WS and the sidewalls thereof facing the channel film 150 may also be included. The dielectric thin film can include, for example, a high-k dielectric thin film having a dielectric constant higher than that of silicon oxide. In some embodiments, the high-k film can include a metal oxide such as hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide.

[0047] The insulating films 110 each extend between the word line structures WS in a horizontal direction parallel to the main surface 102M of the substrate 102. The insulating films 110 can include, for example, a silicon oxide film. In some embodiments, the insulating films 110 can also include air gaps.

[0048] The word line structure WS and the insulating film 110 can form a stacked structure ST.

[0049] Reference Figure 3 and Figure 4A , the word line structure WS can have a structure that protrudes more toward the channel film 150 than the insulating film 110. The insulating film 110 can have a recessed sidewall 110R that is farther from the channel film 150 than the sidewall WSS of each word line structure WS facing the channel film 150.

[0050] The barrier dielectric film 125 can be formed to cover the word line structure WS and the insulating film 110, extend in the third direction (Z direction) with a curved portion, and have a first groove GR1 facing the recessed sidewall 110R of the insulating film 110. The barrier dielectric film 125 can substantially conformally cover the sidewall WSS of the word line structure WS and the recessed sidewall 110R of the insulating film 110. The barrier dielectric film 125 can include, for example, a silicon oxide film or a silicon oxynitride film. In some embodiments, the barrier dielectric film 125 includes a surface facing the channel film 150 and includes a plurality of first grooves GR1, and the plurality of first grooves GR1 can be respectively located on the sides of the insulating film 110, as Figure 4A shown.

[0051] The thickness t1 of the blocking dielectric film 125 can be greater than the width W1 in the first direction (X direction) between the sidewall WSS of the word line structure WS and the recessed sidewall 110R of the insulating film 110. The blocking dielectric film 125 can completely fill the recessed space 110SP defined by the bottom surface and the top surface of the word line structure WS and the recessed sidewall 110R of the insulating film 110, such that the first groove GR1 may not extend into the recessed space 110SP.

[0052] The charge storage film 130 can be disposed on the sidewall WSS of the word line structure WS, wherein the blocking dielectric film 125 is located between the charge storage film 130 and the sidewall WSS of the word line structure WS. The charge storage film 130 can include, for example, a silicon nitride film, polysilicon, or polysilicon doped with impurities. In some embodiments, the charge storage film 130 can be a charge trapping film that is a silicon nitride film. In some embodiments, the charge storage film 130 can be a floating gate including polysilicon or polysilicon doped with impurities. In some embodiments, the first height H1 of the word line structure WS in the third direction (Z direction) can be greater than the second height H2 of the charge storage film 130 in the third direction (Z direction). In some embodiments, the height of the charge storage film 130 in the third direction (Z direction) can increase from one side of the channel film 150 toward one side of the word line structure WS, as Figure 4A shown. For example, the height of the sidewall of the charge storage film 130 facing the word line structure WS in the third direction (Z direction) can be greater than the height of the sidewall of the charge storage film 130 facing the channel film 150.

[0053] The tunneling dielectric film 140 can extend in the third direction (Z direction) with a curved portion to cover the blocking dielectric film 125 and the charge storage film 130. The tunneling dielectric film 140 can substantially conformally cover the blocking dielectric film 125 and the charge storage film 130. The tunneling dielectric film 140 can include, for example, a silicon oxide film.

[0054] The channel film 150 can extend in the third direction (Z direction) with a curved portion to cover the tunneling dielectric film 140.

[0055] The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 can extend non-linearly in the third direction (Z direction). The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 can each have a shape that protrudes recessively in a direction away from the word line structure WS in a portion facing the word line structure WS. The blocking dielectric film 125, the tunneling dielectric film 140, and the channel film 150 can each have a shape that protrudes recessively toward the insulating film 110 in a portion facing the insulating film 110.

[0056] Reference Figure 3And Figure 4B ,the integrated circuit device 100 may further include a residual layer 130R between the blocking dielectric film 125 and the tunneling dielectric film 140 in the first groove GR1. In some embodiments, the residual layer 130R may include the same material as that of the charge storage film 130. For example, the residual layer 130R may include, for example, a silicon nitride film, polysilicon, or polysilicon doped with impurities.

[0057] Reference Figure 3 And Figure 4C ,the integrated circuit device 100 may further include a residual layer 130Ra between the blocking dielectric film 125 and the tunneling dielectric film 140 in the first groove GR1. At least two residual layers 130Ra spaced apart from each other may be disposed between the blocking dielectric film 125 and the tunneling dielectric film 140 in the first groove GR1. In some embodiments, the residual layer 130Ra may include the same material as that of the charge storage film 130.

[0058] Reference Figure 3 And Figure 4D ,the integrated circuit device 100 may include a charge storage film 130Rb between the blocking dielectric film 125 and the tunneling dielectric film 140. The charge storage film 130Rb may extend between the blocking dielectric film 125 and the tunneling dielectric film 140 such that Figure 4B the charge storage film 130 and the residual layer 130R are not separated but integrally formed. In some embodiments, the charge storage film 130 and the residual layer 130R may be connected to each other, as Figure 4D shown. The thickness of the portion of the charge storage film 130Rb facing each word line structure WS in the first direction (X direction) may be greater than the thickness of the portion thereof facing each insulating film 110 in the first direction (X direction).

[0059] Reference Figure 3 And 4E ,the thickness t1a of the blocking dielectric film 125 may be less than the width W1 in the first direction (X direction) between the sidewall WSS of the word line structure WS and the recessed sidewall 110R of the insulating film 110. Since the blocking dielectric film 125 does not completely fill the recessed space 110SP defined by the bottom surface and the top surface of the word line structure WS and the recessed sidewall 110R of the insulating film 110, the first groove GR1 may extend into the recessed space 110SP.

[0060] Reference Figure 3 And 4F, the blocking dielectric film 125 may have a seam 125S extending from a sidewall of the blocking dielectric film 125 facing the channel film 150 toward the recessed sidewall 110R of the insulating film 110. The seam 125S may be formed in a process of filling the recessed space 110SP defined by the bottom and top surfaces of the word line structure WS and the recessed sidewall 110R of the insulating film 110 with the blocking dielectric film 125.

[0061] Reference Figure 3 and Figure 4G , the blocking dielectric film 125 may have a first air gap 125AG therein. The first air gap 125AG may be formed in a process of filling the recessed space 110SP defined by the bottom and top surfaces of the word line structure WS and the recessed sidewall 110R of the insulating film 110 with the blocking dielectric film 125.

[0062] Although FIG. 4E to FIG. 4G both show the residual layer 130R, the residual layer 130R may be omitted as Figure 4A shown, may be replaced with the residual layer 130Ra of Figure 4C , or may be replaced with the charge storage film 130Rb of Figure 4D instead of the charge storage film 130 and the residual layer 130R.

[0063] Figures 5A to 5P is an enlarged cross-sectional view showing a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept. Specifically, Figures 5A to 5P shows a region P1 of a method of manufacturing an integrated circuit device according to Figure 4B and mainly describes the difference between the method of manufacturing an integrated circuit device according to Figure 3 and the method of manufacturing an integrated circuit device according to Figure 3 . Figure 4A The method of manufacturing an integrated circuit device according to Figures 4C to 4G is described.

[0064] Reference Figure 3 and Figure 5A , a structure in which an insulating film 110 and a plurality of sacrificial layers PL are alternately stacked one by one is formed on a substrate 102. In some embodiments, the sacrificial layer PL may include, for example, a silicon nitride film, and the insulating film 110 may include, for example, a silicon oxide film. Both the insulating film 110 and the sacrificial layer PL may be formed by a method such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), or atomic layer deposition (ALD).

[0065] The sacrificial layer PL may provide a space for forming at least one ground selection line GSL, word line WL, and at least one string selection line SSL as shown in each subsequent process. Figure 1 shown.

[0066] In the insulating film 110, the thickness of the lowermost insulating film 110L in contact with the substrate 102 may be less than the thickness of the other insulating films 110. The thickness of the insulating film 110 formed directly above the first sacrificial layer PL in the sacrificial layer PL starting from the substrate 102 may be greater than the thickness of the other insulating films 110 located at different positions.

[0067] An insulating pattern 114 is formed on the uppermost insulating film 110, and the insulating film 110 and the sacrificial layer PL are anisotropically etched by using the insulating pattern 114 as an etching mask, thereby forming a channel hole CHH exposing the substrate 102.

[0068] The width of the channel hole CHH in the horizontal direction may decrease toward the substrate 102. The insulating pattern 114 may be a single layer or a multi-layer, which includes, for example, an oxide film, a nitride film, or a combination thereof.

[0069] A semiconductor pattern 120 that partially fills the channel hole CHH is formed by selective epitaxial growth (SEG) process using the substrate 102 exposed at the bottom of the channel hole CHH as a seed. The horizontal height where the upper surface of the semiconductor pattern 120 is located may be between the upper surface of the sacrificial layer PL closest to the substrate 102 in the sacrificial layer PL and the bottom surface of the insulating film 110 closest to the substrate 102 in the insulating film 110. The semiconductor pattern 120 may perform a channel function in a manner similar to the channel film 150. The semiconductor pattern 120 may include, for example, Si or Ge. In some embodiments, the semiconductor pattern 120 may include a semiconductor doped with impurities.

[0070] Reference Figure 5B , through the channel hole CHH, a part of each insulating film 110 is removed, and thus, a plurality of recessed spaces 110SP communicating with the channel hole CHH are formed at the same height level as the insulating film 110. Each insulating film 110 may have a recessed sidewall 110R, and the recessed sidewall 110R is farther from the center of the channel hole CHH than each sidewall PLS of the sacrificial layer PL facing the channel hole CHH. Compared with the sidewall PLS of the sacrificial layer PL, the sidewall of the insulating film 110 (i.e., the recessed sidewall 110R) may be recessed into the recessed space 110SP from the channel hole CHH. In some embodiments, a part of each insulating film 110 may be removed by a wet etching process to form the recessed space 110SP.

[0071] Reference Figure 5C, a barrier dielectric film 125 is formed to cover the exposed surfaces of the insulating film 110 and the sacrificial layer PL in the channel hole CHH. The barrier dielectric film 125 can be formed to cover the sacrificial layer PL and the insulating film 110, can extend in the third direction (Z direction) with a curved portion, and can have a first groove GR1 facing each recessed sidewall 110R of the insulating film 110. The barrier dielectric film 125 can substantially conformally cover the upper surface and a part of the bottom surface of the sacrificial layer PL, as well as the sidewall PLS and the recessed sidewall 110R of the insulating film 110.

[0072] According to the thickness of the barrier dielectric film 125, the barrier dielectric film 125 can completely fill the recessed space 110SP, as Figure 4A shown, or the barrier dielectric film 125 can incompletely fill the recessed space 110SP, and the first groove GR1 can extend into the recessed space 110SP, as Figure 4E shown.

[0073] Refer to Figure 5D , a preliminary charge storage film 130P is formed to cover the barrier dielectric film 125 in the channel hole CHH. The preliminary charge storage film 130P can be formed to cover the barrier dielectric film 125, extend in the third direction (Z direction) with a curved portion, and have a second groove GR2 corresponding to the first groove GR1. The preliminary charge storage film 130P can include, for example, a silicon nitride film. In some embodiments, the preliminary charge storage film 130P can completely fill the first groove GR1. In some embodiments, a plurality of second grooves GR2 can be formed, and the plurality of second grooves GR2 can be respectively located on the first groove GR1, as Figure 5D shown.

[0074] Refer to Figure 5E , a first covering sacrificial layer SCL1 is formed in the channel hole CHH to cover the preliminary charge storage film 130P. The first covering sacrificial layer SCL1 can be formed to cover the preliminary charge storage film 130P, extend in the third direction (Z direction) with a curved portion, and have a third groove GR3 corresponding to the second groove GR2. The first covering sacrificial layer SCL1 can include, for example, polysilicon. In some embodiments, a plurality of third grooves GR3 can be formed, and the plurality of third grooves GR3 can be respectively on the second groove GR2, as Figure 5E shown.

[0075] Refer to Fig. 5F, a second capping sacrificial layer SCL2 covering the first capping sacrificial layer SCL1 is formed in the channel hole CHH. The second capping sacrificial layer SCL2 can be formed to cover the first capping sacrificial layer SCL1, extend in the third direction (Z direction) with a bent portion, and fill the third groove GR3. The second capping sacrificial layer SCL2 can include, for example, a nitride film.

[0076] Reference Figure 5G , by anisotropically etching Fig. 5F of the second capping sacrificial layer SCL2 to form a first capping layer CVL1 filling at least a part of the third groove GR3, and the first capping layer CVL1 is a part of the second capping sacrificial layer SCL2. In the channel hole CHH, the first capping layer CVL1 can have an annular shape spaced apart from each other in the third direction (Z direction).

[0077] Reference Figure 5H and Fig.5I , a second capping layer CVL2 is formed on the first capping sacrificial layer SCL1 exposed in the channel hole CHH. The second capping layer CVL2 can be formed by oxidizing the first capping sacrificial layer SCL1. The second capping layer CVL2 can be formed by oxidizing the portion of the first capping sacrificial layer SCL1 not covered by the first capping layer CVL1, and can not be formed on the first capping layer CVL1. After forming the second capping layer CVL2, the first capping layer CVL1 is removed.

[0078] Reference Fig.5I and Figure 5J , by using the second capping layer CVL2 as an etching mask to isotropically etch the first capping sacrificial layer SCL1, a third capping layer CVL3 exposing a part of the preliminary charge storage film 130P is formed, and the third capping layer CVL3 is a part of the first capping sacrificial layer SCL1. The third capping layer CVL3 can be separated into a plurality of third capping layers CVL3 by a first recessed space RS1 of the second groove GR2 exposing the preliminary charge storage film 130P.

[0079] Reference Figure 5J to Figure 5L , after removing the second capping layer CVL2, by isotropically etching the portion of the preliminary charge storage film 130P exposed through the first recessed space RS1 of the third capping layer CVL3, a charge storage film 130 separated by a second recessed space RS2 communicating with the first recessed space RS1 is formed. In some embodiments, the second capping layer CVL2 can be removed during the isotropic etching of this portion of the preliminary charge storage film 130P, or after forming the charge storage film 130.

[0080] In the process of forming the charge storage film 130 by isotropically etching a portion of the preliminary charge storage film 130P, another portion of the preliminary charge storage film 130P may remain on the blocking dielectric film 125 in the first groove GR1 as a residual layer 130R. In some embodiments, as Figure 4A shown, a portion of the preliminary charge storage film 130P may be removed in the first groove GR1 such that the residual layer 130R no longer exists. In some embodiments, as Figure 4C shown, another portion of the preliminary charge storage film 130P may remain on the blocking dielectric film 125 in the first groove GR1 as at least two residual layers 130Ra spaced apart from each other. In some embodiments, in the process of removing this portion of the preliminary charge storage film 130P by isotropic etching, the charge storage film 130 and the residual layer 130R may be integrally formed (e.g., may be connected to each other) without separation, just like Figure 4D the charge storage film 130Rb. Referring to Figure 5M to Figure 5O , after removing the third capping layer CVL3 of Figure 5L , a tunneling dielectric film 140 covering the charge storage film 130 and the blocking dielectric film 125 is formed in the channel hole CHH. Then, after removing a portion of the blocking dielectric film 125 covering the semiconductor pattern 120 and a corresponding portion of the tunneling dielectric film 140, a channel film 150 covering the tunneling dielectric film 140 and the semiconductor pattern 120 is formed. In the process of removing this portion of the blocking dielectric film 125 covering the semiconductor pattern 120 and the corresponding portion of the tunneling dielectric film 140, a partial region of the upper surface of the semiconductor pattern 120 is removed, thereby forming a recessed surface 120R on the upper surface of the semiconductor pattern 120. Then, a buried insulating film 156 filling the channel hole CHH is formed on the channel film 150.

[0081] Referring to Figure 5P , after forming a word line cutting region WLC by removing a portion of each of the insulating film 110 and the sacrificial layer PL of Fig.5O , a plurality of word line spaces DH communicating with the word line cutting region WLC may be formed by removing the sacrificial layer PL via the word line cutting region WLC. The word line spaces DH may be filled with word line structures WS, respectively.

[0082] Then, as Figure 3 shown, an integrated circuit device 100 may be formed by forming a common source region 160, insulating spacers 170, a common source line CSL, a capping insulating film 172, a top insulating film 180, a string selection line cutting region SSLC, a cutting insulating film 184, a bit line contact hole 180H, a bit line contact pad 182, and a bit line BL.

[0083] Fig. 6A and Figure 6C , 7A to 7I , FIG. 8A to FIG. 8C , Fig. 9A , FIG. 10A to FIG. 10C , FIG. 12A to FIG. 12C , Fig.14A and Fig.16A are enlarged cross-sectional views showing methods of manufacturing integrated circuit devices according to some embodiments of the inventive concept, Figure 6B , Fig.6D , Figure 7J , Fig.8D , Fig. 9B , Fig. 10D , Fig.11 , Fig.12D , Fig.13 , Fig. 14B , Fig.15 , Fig. 16B , Fig.17 , Fig.18 , Fig.19 and Fig. 20 are enlarged cross-sectional views of integrated circuit devices according to some embodiments of the inventive concept. Specifically, FIG. 6A to FIG. 20 is Figure 3 an enlarged cross-sectional view of region P1 of Figure 3 to Figure 5P , and descriptions that are repetitive with the description of

[0084] Referring to Fig. 6A , with regard to the result of Figure 5B , a plurality of sacrificial layers PLa having circular portions PRDa at the corners are formed by removing a part of the corners of each sacrificial layer PL of Figure 5B exposed in the channel holes CHH.

[0085] Referring to Figure 6B , with regard to the result of Fig. 6A , an integrated circuit device 100a is formed by performing the process described with reference to Figures 5C to 5P .

[0086] The integrated circuit device 100a may include a plurality of circular word line structures WSa having circular portions WRDa.

[0087] Referring to Figure 6C , with regard to the result of Figure 5B , a barrier dielectric film 125a is formed to cover the surface of the sacrificial layers PLb exposed in the channel holes CHH. The barrier dielectric film 125a may be formed by oxidizing a part of the sacrificial layer PL of Figure 5B . In the process of forming the barrier dielectric film 125a, as a part of the corners of each sacrificial layer PL is consumed, sacrificial layers PLb having circular portions PRDb at the corners may be formed.

[0088] The blocking dielectric film 125a may not cover a part of the recessed sidewall 110R of the insulating film 110, but completely cover the surface of the sacrificial layer PLb in the channel hole CHH.

[0089] Reference Fig.6D , regarding Figure 6C the results of, an integrated circuit device 100a1 is formed by performing the process described in Reference Figure 5C to Figure 5P .

[0090] The integrated circuit device 100a1 may include a plurality of circular word line structures WSb having a circular portion WRDb.

[0091] Reference Fig. 7A , a preliminary charge storage film 130Pa for covering the blocking dielectric film 125 in the channel hole CHH is formed. The preliminary charge storage film 130Pa may cover the blocking dielectric film 125, extend in the third direction (Z direction) with a curved portion, and have a second groove GR2a corresponding to the first groove GR1. The thickness of the preliminary charge storage film 130Pa may be less than Figure 5D the thickness of the preliminary charge storage film 130P of Figure 5D . In some embodiments, the preliminary charge storage film 130Pa may fill a part of the first groove GR1, and the height of the second groove GR2a of the preliminary charge storage film 130Pa in the third direction (Z direction) may be greater than

[0092] Reference Figure 7B , a first covering sacrificial layer SCL1a and a second covering sacrificial layer SCL2a having the second groove GR2a are sequentially formed on the preliminary charge storage film 130Pa in the channel hole CHH. The height of the third groove GR3a in the third direction (Z direction) may be greater than Figure 5E the height of the third groove GR3 of the second covering sacrificial layer SCL2 of

[0093] Reference Figure 7C , by anisotropically etching Figure 7B the second covering sacrificial layer SCL2a of Figure 5G , a first covering layer CVL1a that fills at least a part of the third groove GR3a is formed. The first covering layer CVL1a is a part of the second covering sacrificial layer SCL2a. In some embodiments, the height of the first covering layer CVL1a in the third direction (Z direction) may be greater than

[0094] Reference Fig.7D and Fig. 7E, a second capping layer CVL2a is formed on a first capping sacrificial layer SCL1a exposed in a channel hole CHH. The second capping layer CVL2a can be formed by oxidizing the first capping sacrificial layer SCL1a and may not be formed on the first capping layer CVL1a. After forming the second capping layer CVL2a, the first capping layer CVL1a is removed.

[0095] Reference Fig. 7E and Figure 7F , a third capping layer CVL3a that is part of the first capping sacrificial layer SCL1a and exposes a part of a preliminary charge storage film 130Pa is formed by isotropically etching the first capping sacrificial layer SCL1a using the second capping layer CVL2a as an etching mask. The third capping layer CVL3a may have a first recessed space RS1a for the second groove GR2a that exposes the preliminary charge storage film 130Pa.

[0096] Reference FIG. 7F to FIG. 7H , after removing the second capping layer CVL2a, a charge storage film 130a spaced apart from each other by second recessed spaces RS2a communicating with the first recessed space RS1a is formed by isotropically etching the portion of the preliminary charge storage film 130Pa exposed through the first recessed space RS1a of the third capping layer CVL3a. In some embodiments, the second capping layer CVL2a may be removed during the isotropic etching of a portion of the preliminary charge storage film 130Pa or after forming the charge storage film 130a.

[0097] Both ends of each charge storage film 130a may have a circular structure extending toward a first groove GR1a on the blocking dielectric film 125.

[0098] Reference Fig.7I and Figure 7J , after removing Figure 7H the third capping layer CVL3a, a tunneling dielectric film 140 covering the charge storage film 130a and the blocking dielectric film 125, a channel film 150 covering the tunneling dielectric film 140 and the semiconductor pattern 120, and a buried insulating film 156 filling the channel hole CHH on the channel film 150 are sequentially formed in the channel hole CHH. Then, a word line structure WS filling the space obtained by removing the sacrificial layer PL is formed, thereby forming an integrated circuit device 100b.

[0099] Reference Fig. 8A , by performing Figure 5B the result of removing the exposed in the channel hole CHH Figure 5BA trimming process for a part of the sacrificial layer PL is used to remove a part of the end of each sacrificial layer PLc to form a plurality of sacrificial layers PLc, and each sacrificial layer PLc has a trimmed portion PTR at its end facing the channel hole CHH. The height of the trimmed portion PTR in the third direction (Z direction) can be less than the height of the other parts of the sacrificial layer PLc in the third direction (Z direction).

[0100] The recessed space 110SP defined by the bottom surface and the top surface of the sacrificial layer PLc and the recessed side wall 110R of the insulating film 110 can be greater in height in the third direction (Z direction) than Figure 5B the height of the recessed space 110SP in the third direction (Z direction).

[0101] Reference Figure 8B , a blocking dielectric film 125b is formed which has a first groove GR1b and covers the insulating film 110 and the surface of the sacrificial layer PLc exposed in the channel hole CHH.

[0102] Reference Figure 8C , by performing a process similar to the process shown in Figure 5D to Figure 5G , a preliminary charge storage film 130Pb, a first covering sacrificial layer SCL1b and a first covering layer CVL1b are sequentially formed on the blocking dielectric film 125b in the channel hole CHH.

[0103] Reference Fig.8D , by performing a process similar to the process shown in Figure 5H to Figure 5P , a charge storage film 130b, a tunneling dielectric film 140, a channel film 150 and a buried insulating film 156 are sequentially formed on the blocking dielectric film 125B. Then, a plurality of word line structures WSc are formed to fill the space obtained by removing Figure 8C the sacrificial layer PLc, thereby forming the integrated circuit device 100c. Each word line structure WSc can have a trimmed portion WTR at its end facing the channel film 150, and the height of the trimmed portion WTR in the third direction (Z direction) is less than the height of the other parts of the word line structure WSc in the third direction (Z direction).

[0104] Reference Fig. 9A , by performing a process similar to the process shown in FIG. 5A to FIG. 5M , a plurality of charge storage films 130c are formed on the blocking dielectric film 125. Compared with the process of forming Figure 5L the charge storage film 130, the charge storage film 130c can be formed by removing a relatively small amount of a part of the preliminary charge storage film 130P of Figure 5J . The second height H2a of the charge storage film 130c in the third direction (Z direction) can be greater than Figure 4A the second height H2 of the charge storage film 130c of

[0105] refer to Fig. 9B , by executing Figures 5N to 5P In a process similar to that shown in FIG. 1 , a tunnel dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially formed on the blocking dielectric film 125 and the charge storage film 130c. Then, a layer for filling the layer by removing Fig. 9B The spatial word line structure WS is obtained by the plurality of sacrificial layers PL, thereby forming the integrated circuit device 100d.

[0106] In some embodiments, a first height H1 of the word line structure WS in the third direction (Z direction) may be smaller than a second height H2 a of the charge storage film 130 c in the third direction (Z direction).

[0107] refer to Fig. 10A ,about Figure 5K As a result, a fourth cover layer CVL4 is formed on the third cover layer CVL3. The fourth cover layer CVL4 may be formed on the third cover layer CVL3 by a SEG process or a selective deposition process. The fourth cover layer CVL4 may include, for example, polysilicon.

[0108] The fourth cover layer CVL4 may have a first recessed space RS1C for exposing the second groove GR2 of the preliminary charge storage film 130P. Figure 5K The space left after the fourth cover layer CVL4 in the first recessed space RS1 shown in the figure can be reduced by forming the fourth cover layer CVL4. Figure 5K The first recessed space RS1 is shown.

[0109] refer to Fig. 10B and Fig. 10C , by isotropically etching Fig. 10A After forming a plurality of charge storage films 130d spaced apart from each other by the second recessed space RS2C communicating with the first recessed space RS1C by portions of the preliminary charge storage film 130P exposed through the first recessed space RS1C of the fourth cover layer CVL4, the third cover layer CVL3 and the fourth cover layer CVL4 are removed.

[0110] In some embodiments, the charge storage films 130 d may each have a shape in which both end portions (ie, upper and bottom surfaces thereof) are concave in the third direction (Z direction).

[0111] refer to Fig. 10D , by executing Figure 5N to Figure 5P In a similar process to that shown in FIG. 1 , a tunnel dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially formed on the blocking dielectric film 125 and the charge storage film 130d. Then, a filling film 140 is formed by removing Fig. 10C A word line structure WS of a space obtained from a sacrificial layer PL to form an integrated circuit device 100e.

[0112] Reference Fig.11 , the integrated circuit device 100f may include a charge storage film 130e. The shape of the charge storage film 130e of the integrated circuit device 100f may be different from the shape of the charge storage film 130 of the integrated circuit device 100 shown. Figure 4A shown.

[0113] In some embodiments, the height of the charge storage film 130e in the third direction (Z direction) may decrease from the channel film 150 toward the word line structure WS. For example, the height of the side wall of the charge storage film 130e facing the word line structure WS in the third direction (Z direction) may be less than the height of the side wall of the charge storage film 130e facing the channel film 150 in the third direction (Z direction).

[0114] Reference Fig. 12A and Fig. 12B , a preliminary charge storage film 130Pf covering the barrier dielectric film 125 in the channel hole CHH is formed. Compared with the preliminary charge storage film 130P of Figure 5D , the preliminary charge storage film 130Pf may have a relatively small thickness.

[0115] Then, by performing a process similar to the process shown in Figures 5E to 5M , a part of the preliminary charge storage film 130Pf is etched to form a first layer 130f1.

[0116] Reference Fig. 12C , a second layer 130f2 conformally covering the barrier dielectric film 125 and the first layer 130f1 in the channel hole CHH is formed, thereby forming a charge storage film 130f including the first layer 130f1 and the second layer 130f2. The first layer 130f1 may be surrounded by the second layer 130f2 and the barrier dielectric film 125. The second layer 130f2 may surround the upper surface, bottom surface, and side wall of the first layer 130f1 that faces the channel film 150. In some embodiments, the second layer 130f2 may extend on the upper surface, bottom surface, and side wall of the first layer 130f1 that faces the channel film 150.

[0117] The charge storage film 130f may have a stacked structure of a first layer 130f1 and a second layer 130f2 at substantially the same height level as the sacrificial layer PL, and may include only the second layer 130f2 at substantially the same height level as the insulating film 110. In other words, the second layer 130f2 may cover the blocking dielectric film 125 and the first layer 130f1, and extend in the third direction (Z direction) with a bent portion. The width of the charge storage film 130f at substantially the same horizontal height as the sacrificial layer PL in the horizontal direction may be greater than the width of the charge storage film 130f at substantially the same horizontal height as the insulating film 110 in the horizontal direction. In some embodiments, the first portion of the charge storage film 130f on the side of the sacrificial layer PL may include the first layer 130f1 and the second layer 130f2, and the second portion of the charge storage film 130f on the side of the insulating film 110 may include only the second layer 130f2, as Fig. 12C shown. Accordingly, the first width of the first portion of the charge storage film 130f in the first direction (X direction) may be wider than the second width of the second portion of the charge storage film 130f in the first direction (X direction).

[0118] In some embodiments, the first layer 130f1 and the second layer 130f2 may include the same material. In some embodiments, the first layer 130f1 and the second layer 130f2 may include different materials from each other. For example, both the first layer 130f1 and the second layer 130f2 may include any one of a silicon nitride film and polysilicon.

[0119] Reference Fig.12D , by performing a process similar to the process shown in Figure 5N to Figure 5P , a tunneling dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially formed on the blocking dielectric film 125 and the charge storage film 130f. Then, a word line structure WS is formed to fill the space obtained by removing the Fig. 12C sacrificial layer PL, thereby forming the integrated circuit device 100g.

[0120] Reference Fig.13 , the integrated circuit device 100h may include a charge storage film 130g. In the charge storage film 130g of the integrated circuit device 100h, different from the charge storage film 130f of the integrated circuit device 100g shown in Fig.12D , the portions corresponding to the word line structure WS may be spaced apart from each other.

[0121] The charge storage film 130g may include a first layer 130f1 and a second layer 130f2a. In the second layer 130f2a, different from Fig.12DUnlike the second layer 130f2 shown, portions corresponding to the word line structures WS, respectively, may be spaced apart from each other. The first layer 130f1 may be surrounded by the second layer 130f2a and the blocking dielectric film 125. The second layer 130f2a may surround the upper surface, the bottom surface, and the sidewall of the first layer 130f1, the sidewall facing the channel film 150. In some embodiments, the second layer 130f2a may extend on the upper surface, the bottom surface, and the sidewall of the first layer 130f1 facing the channel film 150.

[0122] refer to Fig.14A , relative to Figure 5M As a result, filling Figure 5M The buffer insulating film 142 is formed in a portion of the second recessed space RS2. The buffer insulating film 142 forms a buffer insulating material layer covering the blocking dielectric film 125 and the charge storage film 130 in the channel hole CHH. Then, a portion of the buffer insulating material layer is removed by anisotropic etching to remain only in the second recessed space RS2. The buffer insulating film 142 can buffer the step between the surface of the blocking dielectric film 125 and the surface of the charge storage film 130 exposed in the channel hole CHH.

[0123] refer to Fig. 14B , by executing Figure 5N to Figure 5P In a process similar to that shown in FIG. 1 , a tunnel dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially formed on the buffer insulating film 142 and the charge storage film 130. Then, a filling film 140 is formed by removing Fig.14A The sacrificial layer PL is used to obtain the spatial word line structure WS, thereby forming the integrated circuit device 100i.

[0124] refer to Fig.15 , the buffer insulating film 142 of the integrated circuit device 100j may include a second air gap 142AG therein.

[0125] refer to Fig.16A ,about Fig.14A As a result, a covering charge storage film 132 covering the charge storage film 130 and the buffer insulating film 142 is formed, thereby forming an extended charge storage film 130 h including the charge storage film 130 and the covering charge storage film 132 .

[0126] refer to Fig. 16B , by executing Figure 5N to Figure 5P In a similar process to that shown in FIG. 1 , a tunnel dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially formed on the extended charge storage film 130h. Then, a filling film 140 is formed by removing the filler film 150. Fig.16A The sacrificial layer PL is used to obtain the spatial word line structure WS, thereby forming the integrated circuit device 100k.

[0127] The charge storage film 130 and the extended charge storage film 130h covering the charge storage film 132 may correspond to Fig.12D the charge storage film 130f including the first layer 130f1 and the second layer 130f2 as shown. The integrated circuit device 100k may be similar to the integrated circuit device in Fig.12D shown in which a buffer insulating film 142 is inserted between the barrier dielectric film 125 and the second layer 130f2 in the integrated circuit device 100g.

[0128] Referring to Fig.17 , the integrated circuit device 100l may include a charge storage film 130i, and the charge storage film 130i includes a first layer 130i1 and a second layer 130i2.

[0129] In some embodiments, the first layer 130i1 and the second layer 130i2 may include the same material. In some embodiments, the first layer 130i1 and the second layer 130i2 may include different materials from each other. For example, both the first layer 130i1 and the second layer 130i2 may include any one of a silicon nitride film and polysilicon.

[0130] The second layer 130i2 may be surrounded by the first layer 130i1 and the tunneling dielectric film 140. The first layer 130i1 may surround the upper surface, the bottom surface, and the sidewall of the second layer 130i2 that faces the word line structure WS. In some embodiments, the first layer 130i1 may extend on the upper surface, the bottom surface, and the sidewall facing the word line structure WS of the second layer 130i2.

[0131] In some embodiments, regarding Figure 5D the result, the first layer 130i1 may be formed by filling the second groove GR2, forming a covering pattern covering the peripheral portion of the second groove GR2 of the preliminary charge storage film 130P, and then removing a part of the preliminary charge storage film 130P by using the covering pattern as an etching mask. The second layer 130i2 may be formed by filling the portion where the part of the preliminary charge storage film 130P has been removed.

[0132] Referring to Fig.18 , the integrated circuit device 100m may include a charge storage film 130j, and the charge storage film 130j includes a first portion 130j1 and a second portion 130j2. In some embodiments, the first portion 130j1 and the second portion 130j2 may include the same material.

[0133] The first portion 130j1 and the second portion 130j2 of the charge storage film 130j formed corresponding to one word line structure WS may be spaced apart from each other in the third direction (Z direction).

[0134] In some embodiments, regarding Figure 5L As a result, after filling the space between the filling barrier dielectric film 125 and the third capping layer CVL3, the charge storage film 130 as shown is removed to form a first portion 130j1 and a second portion 130j2. Figure 5L As shown, the charge storage film 130 is removed to form a first portion 130j1 and a second portion 130j2.

[0135] Reference Fig.19 , the integrated circuit device 100n may include a charge storage film 130k, and the charge storage film 130k includes a first portion 130k1, a second portion 130k2, and a third portion 130k3.

[0136] The first portion 130k1 and the second portion 130k2 of the charge storage film 130k formed corresponding to one word line structure WS may be spaced apart from each other in a third direction (Z direction). The third portion 130k3 may fill the space between the first portion 130k1 and the second portion 130k2. The first portion 130k1 and the second portion 130k2 may be in contact with the upper surface and the bottom surface of the third portion 130k3, respectively.

[0137] In some embodiments, the first portion 130k1 and the second portion 130k2 may be formed by a method similar to the method for the first portion 130j1 and the second portion 130j2 as shown, and the third portion 130k3 may be a portion that is not removed from the charge storage film 130 as shown. Fig.18 As shown, and the third portion 130k3 may be a portion that is not removed from the charge storage film 130 as shown. Figure 5L As shown, the charge storage film 130 is removed.

[0138] In some embodiments, the first portion 130k1, the second portion 130k2, and the third portion 130k3 may include the same material. In some embodiments, the first portion 130k1 and the second portion 130k2 may include the same material, and the third portion 130k3 may include a material different from the materials of the first portion 130k1 and the second portion 130k2.

[0139] Reference Fig. 20 , the integrated circuit device 100o may include a charge storage film 130l, and the charge storage film 130l includes a first layer 130l1 and a second layer 130l2.

[0140] In some embodiments, the first layer 130l1 and the second layer 130l2 may be formed by performing the process described in reference Figure 5D As shown, after forming a preliminary charge storage film 130 having a stacked structure of a preliminary first layer and a preliminary second layer. Figures 5E to 5M As described, the first layer 130l1 and the second layer 130l2 are formed.

[0141] In some embodiments, the first layer 130l1 and the second layer 130l2 may include the same material. In some embodiments, the first layer 130l1 and the second layer 130l2 may include different materials from each other.

[0142] The sidewall of the first layer 130l1 facing the channel film 150 and the sidewall of the second layer 130l2 facing the word line structure WS2 may be in contact with each other.

[0143] In the integrated circuit devices 100, 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h, 100i, 100j, 100k, 100l, 100m, 100n, and 100o according to the inventive concept, since the charge storage films 130, 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, 130k, and 130l are formed in the channel holes CHH and the heights and / or thicknesses of the charge storage films 130, 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h, 130i, 130j, 130k, and 130l are implemented differently, a sufficient amount of charge can be stored in the memory cells, and generation of interference between adjacent memory cells can be reduced.

[0144] Fig.21 is a cross-sectional view of an integrated circuit device according to some embodiments of the inventive concept. Fig. 22 is Fig.21 an enlarged cross-sectional view of the region P2 of. Specifically, Fig.21 is at a position corresponding to Figure 2 a cross-sectional view of the integrated circuit device at the line X1-X1'. In Fig.21 and Fig. 22 the description of, descriptions that are repetitive with the description of Figure 2 and Figure 3 may be omitted.

[0145] Referring to Figure 3 and Fig.21 the integrated circuit device 200 may include a substrate 102 having an active region AC. Each of the plurality of channel holes CHH may include a semiconductor pattern 120 in contact with the substrate 102 and partially filling the channel hole CHH, a channel film 150 in contact with the semiconductor pattern 120 and extending in a third direction (Z direction) in the channel hole CHH, a buried insulating film 156 filling an internal space of the channel film 150, and a drain region 158 in contact with the channel film 150 and filling a top inlet side of the channel hole CHH. The plurality of drain regions 158 may be insulated from each other by an insulating pattern 114.

[0146] In the channel hole CHH, a blocking dielectric film 225, a charge storage film 230, a tunneling dielectric film 140, a channel film 150, and a buried insulating film 156 are sequentially disposed, and a top inlet side of the channel hole CHH may be filled with the drain region 158.

[0147] In the channel hole CHH, the blocking dielectric film 225, the tunneling dielectric film 140, and the channel film 150 may all have a cylindrical shape. In the channel hole CHH, the charge storage film 230 may have a shape of a plurality of rings spaced apart from each other in a third direction (Z direction). The blocking dielectric film 225, the tunneling dielectric film 140, and the channel film 150 may each include a plurality of bent portions formed in a portion covering the word line structure WS and the insulating film 110.

[0148] In the process of forming the blocking dielectric film 225, the charge storage film 230, and the tunneling dielectric film 140, since a partial region of the upper surface of the semiconductor pattern 120 is removed, a recessed surface 120R may be formed on the upper surface of the semiconductor pattern 120. The channel film 150 may be in contact with the recessed surface 120R of the semiconductor pattern 120.

[0149] The word line structure WS may extend on the substrate 102 in a horizontal direction parallel to the main surface 102M along the X - Y plane, and may be arranged to be spaced apart from each other and overlap each other in a third direction (Z direction) perpendicular to the main surface 102M of the substrate 102. The insulating film 110 may extend between the word line structures WS in a horizontal direction parallel to the main surface 102M of the substrate 102. The word line structure WS and the insulating film 110 may form a stacked structure ST.

[0150] Reference Fig.21 and Fig. 22 , the insulating film 110 of the integrated circuit device 200 may have a structure that protrudes more toward the channel film 150 than the word line structure WS. The word line structure WS may have a recessed sidewall WSR that is farther from the channel film 150 than the sidewall 110 of each insulating film 110 facing the channel film 150.

[0151] The blocking dielectric film 225 may cover the word line structure WS and the insulating film 110, extend in a third direction (Z direction) with a bent portion, and have a first groove GR1c facing the recessed sidewall WSR of the word line structure WS. The blocking dielectric film 225 may substantially conformally cover the recessed sidewall WSR of the word line structure WS and the sidewall 110S of the insulating film 110. The blocking dielectric film 125 may include, for example, a silicon oxide film or a silicon oxynitride film.

[0152] In some embodiments, the blocking dielectric film 225 may completely fill the recessed space WSSP defined by the bottom surface and the top surface of the insulating film 110 and the recessed sidewalls WSR of the word line structure WS. Thus, the first groove GR1c may not extend into the recessed space WSSP. In some embodiments, the blocking dielectric film 125 may not completely fill the recessed space WSSP defined by the bottom surface and the top surface of the insulating film 110 and the recessed sidewalls WSR of the word line structure WS. Thus, the first groove GR1c may extend into the recessed space WSSP.

[0153] The charge storage film 230 may be disposed on the recessed sidewalls WSR of the word line structure WS, where the blocking dielectric film 225 is located between the charge storage film 230 and the recessed sidewalls WSR of the word line structure WS. The charge storage film 230 may include, for example, a silicon nitride film, polysilicon, or polysilicon doped with impurities. In some embodiments, the charge storage film 230 may include a charge trapping film, and the charge trapping film includes, for example, a silicon nitride film. In some embodiments, the charge storage film 230 may be a floating gate including polysilicon or polysilicon doped with impurities. In some embodiments, the first height H1 of the word line structure WS in the third direction (Z direction) may be greater than the second height H2b of the charge storage film 230 in the third direction (Z direction).

[0154] The surface of each charge storage film 230 opposite to the blocking dielectric film 225 (i.e., facing the tunneling dielectric film 140 and the channel film 150) may have a concave shape in its middle portion. For example, the surface of each charge storage film 230 facing the tunneling dielectric film 140 and the channel film 150 may have a shape that is further recessed toward the blocking dielectric film 225 in its middle portion compared to its upper and lower portions. In some embodiments, each charge storage film 230 has a first surface facing the blocking dielectric film 225 and a second surface opposite to the first surface of the charge storage film 230. The second surface of the charge storage film 230 may include a recess concave toward the blocking dielectric film 225 in its middle portion along the third direction (Z direction), as Fig. 22 shown.

[0155] Each charge storage film 230 may include a first charge storage film 232 that fills at least a portion of the first groove GR1c and a second charge storage film 234 that covers the first charge storage film 232. The width of the second charge storage film 234 in the horizontal direction (X direction or Y direction) may be greater than the width of the first charge storage film 232 in the horizontal direction (X direction or Y direction). The height of the second charge storage film 234 in the vertical direction (Z direction) may be greater than the height of the first charge storage film 232 in the third direction (Z direction). The second charge storage film 234 may cover the first charge storage film 232 and a portion of the blocking dielectric film 225. In some embodiments, as Fig. 22As shown, the width of the first charge storage film 232 in the first direction (X direction) is narrower than the width of the second charge storage film 234 in the first direction (X direction).

[0156] The tunneling dielectric film 140 may extend in the third direction (Z direction) with a curved portion and cover the blocking dielectric film 125 and the charge storage film 130. The channel film 150 may extend in the third direction (Z direction) with a curved portion to cover the tunneling dielectric film 140.

[0157] The blocking dielectric film 225, the tunneling dielectric film 140, and the channel film 150 may extend non-linearly in the third direction (Z direction). In some embodiments, the blocking dielectric film 225, the tunneling dielectric film 140, and the channel film 150 may each have a non-linear shape.

[0158] FIG. 23A to FIG. 23F is an enlarged cross-sectional view showing a method of manufacturing an integrated circuit device according to some embodiments of the inventive concept. Specifically, FIG. 23A to FIG. 23F is formed by Fig.21 The enlarged cross-sectional view of the region P2 indicated by the dotted line in shows a method of manufacturing Fig. 22 the integrated circuit device 200. In the description of FIG. 23A to FIG. 23F the description that is repetitive with Figures 5A to 5P the description may be omitted.

[0159] Referring to FIGS. 12 and Fig.23A , the insulating film 110 and the sacrificial layer PL are alternately stacked one by one on the substrate 102. After the insulating pattern 114 is formed on the top insulating film 110 in the insulating film 110, the insulating film 110 and the sacrificial layer PL are anisotropically etched by using the insulating pattern 114 as an etching mask, thereby forming a channel hole CHH exposing the substrate 102. The width of the channel hole CHH in the horizontal direction may decrease close to the substrate 102.

[0160] Referring to Fig. 23B , by removing a part of each sacrificial layer PL via the channel hole CHH, each of a plurality of recessed spaces PLSP communicating with the channel hole CHH is formed at the same height level as the corresponding sacrificial layer PL. In the recessed space PLSP, the sacrificial layer PL may have a recessed sidewall PLR, and the recessed sidewall PLR is farther from the center of the channel hole CHH than the sidewall 110S of each insulating film 110 facing the channel hole CHH. In some embodiments, a part of each sacrificial layer PL may be removed by a wet etching process to form the recessed space PLSP.

[0161] Referring to Fig.23C, a blocking dielectric film 225 is formed to cover the exposed surfaces of the insulating film 110 and the sacrificial layer PL in the channel hole CHH. The blocking dielectric film 225 can be formed to cover the sacrificial layer PL and the insulating film 110, can extend in the third direction (Z direction) with a curved portion, and can have a first groove GR1c on the sacrificial layer PL (e.g., on the recessed sidewall PLR of the sacrificial layer PL). The blocking dielectric film 225 can substantially conformally cover the upper surface and a part of the bottom surface of the insulating film 110 and the sidewall 110S and the recessed sidewall PLR of the sacrificial layer PL.

[0162] Depending on the thickness of the blocking dielectric film 225, the blocking dielectric film 225 can completely fill the recessed space PLSP, or the blocking dielectric film 225 can incompletely fill the recessed space PLSP, and the first groove GR1c can extend into the recessed space PLSP.

[0163] Reference Fig.23D and Figure 23E , a preliminary charge storage film 232P is formed in the channel hole CHH to cover the blocking dielectric film 225. The preliminary charge storage film 232P can cover the blocking dielectric film 225 and can extend in the third direction (Z direction) with a curved portion. The preliminary charge storage film 232P can include, for example, a silicon nitride film, polysilicon, or polysilicon doped with impurities.

[0164] Then, the first charge storage film 232, which is a part of the preliminary charge storage film 232P, is formed by anisotropically etching the preliminary charge storage film 232P to fill at least a part of the first groove GR1c. When viewed from the channel hole CHH, the first charge storage film 232 can have a concave surface in its middle part. For example, the first charge storage film 232 can protrude further toward the channel hole CHH from its upper and lower parts compared to its middle part.

[0165] Reference Figure 23F , a charge storage film 230 including the first charge storage film 232 and the second charge storage film 234 is formed by forming the second charge storage film 234 on the first charge storage film 232. The second charge storage film 234 can be formed by a SEG process or a selective deposition process using the first charge storage film 232 as a seed. In some embodiments, the first charge storage film 232 and the second charge storage film 234 can include the same material. In some embodiments, the first charge storage film 232 and the second charge storage film 234 can include different materials from each other. The second charge storage film 234 can include, for example, a silicon nitride film or polysilicon doped with impurities.

[0166] The second charge storage film 234 can be formed Figure 23FThe exposed surface of the first charge storage film 232 is completely covered in the shown channel hole CHH. In some embodiments, the second charge storage film 234 may also cover a portion of the surface of the blocking insulating film 225 adjacent to the first charge storage film 2. When viewed from the channel hole CHH, the second charge storage film 234 may have a surface that is concave in its middle portion. For example, the second charge storage film 234 may protrude further toward the channel hole CHH from its upper and lower portions compared to its middle portion.

[0167] Then, by performing the process described with reference to Figures 5N to 5P a tunneling dielectric film 140 covering the charge storage film 230 and the blocking dielectric film 225, a channel film 150 covering Figure 21 the tunneling dielectric film 140 and the semiconductor pattern 120, and a buried insulating film 156 filling the channel hole CHH are sequentially formed in the channel hole CHH. Next, a Figure 22 word line structure WS filling the space obtained by removing the sacrificial layer PL is formed, thereby forming the integrated circuit device 200.

[0168] Figure 24A and Figure 24B 、 Figure 25A and Figure 25B 、 Figure 26A 、 Figures 27A to 27D and Figures 28A to 28D are enlarged cross-sectional views showing a method of manufacturing an integrated circuit device according to some embodiments of the present inventive concept. Figure 24C 、 Figure 25C 、 Figure 26B 、 Figure 27E and Figure 28E are enlarged cross-sectional views of an integrated circuit device according to some embodiments of the present inventive concept. Specifically, Figures 24A to 28E is an enlarged cross-sectional view of a region P2 indicated by a dotted line in Figure 21 . In the following description, descriptions that are repetitive with the description of Figures 21 to 23F may be omitted.

[0169] Referring to Figure 24A and regarding Figure 23D the result, the first charge storage film 232a filling at least a portion of the first groove GR1c is formed by anisotropically etching the preliminary charge storage film 232P, and the first charge storage film 232a is a part of the preliminary charge storage film 232P. When viewed from the channel hole CHH, the first charge storage film 232a may have a flat surface. In other words, the sidewall of the first charge storage film 232a facing the channel hole CHH may have a flat surface.

[0170] Referring to Figure 24B, a second charge storage film 234a is formed on the first charge storage film 232a, and a charge storage film 230a including the first charge storage film 232a and the second charge storage film 234a is formed.

[0171] When viewed from the channel hole CHH, the second charge storage film 234a may have a surface that is concave in its middle portion. For example, the second charge storage film 234a may protrude further toward the channel hole CHH from the upper and lower portions compared to its middle portion.

[0172] Reference Figure 24C , by performing the process described in Reference Figures 5N to 5P , a tunneling dielectric film 140 covering the charge storage film 230a and the blocking dielectric film 225, a channel film 150 covering the Figure 21 tunneling dielectric film 140 and the semiconductor pattern 120, and a buried insulating film 156 filling the channel hole CHH are sequentially formed in the channel hole CHH. Then, a word line structure WS filling the space obtained by removing the Figure 24B sacrificial layer PL is formed, thereby forming the integrated circuit device 200a.

[0173] Reference Figure 25A , regarding the Figure 23D results, a first charge storage film 232b filling at least a part of the first groove GR1c is formed by anisotropically etching a preliminary charge storage film 232P. The first charge storage film 232b is a part of the preliminary charge storage film 232P. The first charge storage film 232b includes at least two first charge storage films 232b spaced apart from each other on the blocking dielectric film 125 in the first groove GR1c.

[0174] Reference Figure 25B , a second charge storage film 234b filling the first groove GR1c is formed on the first charge storage film 232b, thereby forming a charge storage film 230b including at least two first charge storage films 232b and the second charge storage film 234b. The second charge storage film 234b may be formed as a part formed by the SEG process or the selective deposition process from at least two first charge storage films 232b spaced apart from each other on the blocking dielectric film 125 in the first groove GR1c, and these parts are integrally bonded. In other words, an integral second charge storage film 234b may be formed on at least two first charge storage films 232b spaced apart from each other.

[0175] When viewed from the channel hole CHH, the second charge storage film 234b may have a surface that is concave in its middle portion. For example, the second charge storage film 234b may protrude further toward the channel hole CHH from the upper and lower portions compared to its middle portion.

[0176] refer to Figure 25C , by executing the reference Figures 5N to 5P In the process described above, a tunnel dielectric film 140 covering the charge storage film 230b and the blocking dielectric film 225, a tunnel dielectric film 140 covering the charge storage film 230b and the blocking dielectric film 225 are sequentially formed in the channel hole CHH. Figure 21 The tunnel dielectric film 140 and the channel film 150 of the semiconductor pattern 120 and the buried insulating film 156 filling the channel hole CHH on the channel film 150 are formed. Figure 25B The sacrificial layer PL is used to obtain the spatial word line structure WS, thereby forming the integrated circuit device 200b.

[0177] refer to Figure 26A ,about Figure 25A As a result, at least two second charge storage films 234c spaced apart from each other are formed on the at least two first charge storage films 232b, thereby forming a charge storage film 230c including the at least two first charge storage films 232b and the at least two second charge storage films 234c. The at least two second charge storage films 234c are portions that may not be merged but may be spaced apart from each other formed from the at least two first charge storage films 232b spaced apart from each other on the blocking dielectric film 125 in the first groove GR1c by the SEG process or the selective deposition process. The at least two second charge storage films 234c may not completely fill the first groove GR1c.

[0178] refer to Figure 26B , by executing the reference Figures 5N to 5P In the process described above, a tunnel dielectric film 140 covering the charge storage film 230c and the blocking dielectric film 225, a tunnel dielectric film 140 covering the charge storage film 230c and the blocking dielectric film 225 are sequentially formed in the channel hole CHH. Figure 21 The tunnel dielectric film 140 and the channel film 150 of the semiconductor pattern 120 and the buried insulating film 156 filling the channel hole CHH on the channel film 150 are formed. Then, the filling is formed by removing Figure 26A The sacrificial layer PL is used to obtain the spatial word line structure WS, thereby forming the integrated circuit device 200c.

[0179] refer to Figure 27A , through Figure 23B As a result, the exposed portion of the channel hole CHH is removed. Figure 23B A plurality of insulating films 110a are formed by trimming a portion of the surface of the insulating film 110, each of the insulating films 110a having a trimmed portion 110TR obtained by removing a portion of its end portion facing the channel hole CHH through the trimming process. The height of the trimmed portion 110TR in the third direction (Z direction) may be smaller than the height of other portions of the insulating film 110a in the third direction (Z direction).

[0180] The height of the recessed space PLSPa defined by the bottom surface and the top surface of each insulating film 110a and the recessed side walls PLR of each sacrificial layer PL in the third direction (Z direction) can be greater than Figure 23B the height of the recessed space PLSP in the third direction (Z direction) shown.

[0181] Refer to Figure 27B , and form a blocking dielectric film 225a having a first groove GR1d and covering the exposed surfaces of the insulating film 110a and the sacrificial layer PL in the channel hole CHH.

[0182] Refer to Figure 27C , and form a first charge storage film 232d that fills at least a part of the first groove GR1d by performing a process similar to the process shown in Figure 23D and Figure 23E . The height of the first charge storage film 232d in the third direction (Z direction) can be greater than Figure 23E the height of the first charge storage film 232 in the third direction (Z direction) shown.

[0183] Refer to Figure 27D , and form a second charge storage film 234d on the first charge storage film 232d, thereby forming a charge storage film 230d including the first charge storage film 232d and the second charge storage film 234d. The height of the second charge storage film 234d in the third direction (Z direction) can be greater than Figure 23F the height of the second charge storage film 234 in the third direction (Z direction) shown.

[0184] When viewed from the channel hole CHH, the second charge storage film 234d can have a surface that is concave in its middle part. For example, the second charge storage film 234d can protrude further toward the channel hole CHH from the upper and lower parts compared to its middle part.

[0185] Refer to Figure 27E , and by performing the process described in reference Figures 5N to 5P , sequentially form a tunneling dielectric film 140 that covers the charge storage film 230d and the blocking dielectric film 225a, a channel film 150 that covers Figure 21 the tunneling dielectric film 140 and the semiconductor pattern 120, and a buried insulating film 156 that fills the channel hole CHH on the channel film 150. Then, form a word line structure WS that fills the space obtained by removing Figure 27D the sacrificial layer PL, thereby forming an integrated circuit device 200d.

[0186] In some embodiments, a first height H1 of each word line structure WS in a third direction (Z direction) may be less than a second height H2c of the charge storage film 230d in the third direction (Z direction).

[0187] Reference Figure 28A , regarding Figure 27B of the result, a preliminary charge storage film 230Pe covering the blocking dielectric film 225a is formed in the channel hole CHH. The preliminary charge storage film 230Pe may cover the blocking dielectric film 225a, extend in the third direction (Z direction) with a curved portion, and have a second groove GR2d corresponding to the first groove GR1d. The preliminary charge storage film 230Pe may include, for example, a silicon nitride film.

[0188] Reference Figure 28B , by performing a process similar to that of Figure 27C and Figure 27D shown, a mask pattern layer 235 is formed, and the mask pattern layer 235 includes a first mask pattern 237 filling at least a part of the second groove GR2d and a second mask pattern 239 covering the first mask pattern 237.

[0189] Each of the first mask pattern 237 and the second mask pattern 239 can be formed by a method similar to the method of forming each charge storage film of the first charge storage film 232d of Figure 27C and Figure 27D the second charge storage film 234d. For example, after forming a preliminary mask pattern similar to the preliminary charge storage film 232P shown in Figure 23D , the first mask pattern 237 can be formed by anisotropically etching the preliminary mask pattern, or the second mask pattern 239 can be formed by a SEG process or a selective deposition process using the first mask pattern 237 as a seed. In some embodiments, the first mask pattern 237 and the second mask pattern 239 may include the same material. In some embodiments, the first mask pattern 237 and the second mask pattern 239 may include different materials from each other. Both the first mask pattern 237 and the second mask pattern 239 may include, for example, a silicon nitride film or doped polysilicon.

[0190] Reference Figure 28C and Figure 28D , by using the mask pattern layer 235 including the first mask pattern 237 and the second mask pattern 239 as an etching mask to isotropically etch Figure 28B the preliminary charge storage film 230Pe to form a charge storage film 230e that is part of the preliminary charge storage film 230Pe.

[0191] Then, the mask pattern layer 235 including the first mask pattern 237 and the second mask pattern 239 is removed.

[0192] Referring Figure 28E , by performing the process described in the referring Figures 5N to 5P , a tunneling dielectric film 140 covering the charge storage film 230e and the blocking dielectric film 225a, a channel film 150 covering the Figure 21 tunneling dielectric film 140 and the semiconductor pattern 120, and a buried insulating film 156 filling the channel hole CHH are sequentially formed in the channel hole CHH. Then, a word line structure WS filling the space obtained by removing the Figure 28D sacrificial layer PL is formed, thereby forming the integrated circuit device 200e.

[0193] In the integrated circuit devices 200, 200a, 200b, 200c, 200d, and 200e according to the inventive concept, since the charge storage films 230, 230a, 230b, 230c, 230d, and 230e are formed in the channel hole CHH and the heights and / or thicknesses of the charge storage films 230, 230a, 230b, 230c, 230d, and 230e are differently implemented, a sufficient amount of charge can be stored in the memory cell, and generation of interference between adjacent memory cells can be reduced.

[0194] Figure 29 is a plan layout view showing main regions of an integrated circuit device 500 according to some embodiments of the inventive concept.

[0195] Referring Figure 29 , the integrated circuit device 500 may include a memory cell array region 512, a first peripheral circuit region 514, a second peripheral circuit region 516, and a pad region 518.

[0196] The memory cell array region 512 may include a plurality of memory cell arrays MCA having the configuration described in the referring Figure 1 .

[0197] The first peripheral circuit region 514 and the second peripheral circuit region 516 may include control units for controlling data input to or output from the memory cell array region 512. Peripheral circuits for driving vertical memory cells included in the memory cell array region 512 may be provided in the first peripheral circuit region 514 and the second peripheral circuit region 516.

[0198] Since the first peripheral circuit region 514 is disposed to vertically overlap the memory cell array region 512, the planar size of the chip including the integrated circuit device 500 can be reduced.

[0199] In some embodiments, the peripheral circuits disposed in the first peripheral circuit region 514 may be circuits capable of processing at high speed data input to or output from the memory cell array region 512. For example, the peripheral circuits disposed in the first peripheral circuit region 514 may include page buffers, latch circuits, cache circuits, column decoders, sense amplifiers, or data input / output circuits.

[0200] The second peripheral circuit region 516 may be disposed in a region that does not overlap with the memory cell array region 512 and the first peripheral circuit region 514 and may be located at one side of the memory cell array region 512. The peripheral circuits formed in the second peripheral circuit region 516 may be, for example, row decoders. In some embodiments, different from Figure 29 the illustration, at least a part of the second peripheral circuit region 516 may be disposed under the memory cell array region 512.

[0201] The pad region 518 may be formed at the other side of the memory cell array region 512. The pad region 518 may be a region providing wirings connecting to word lines of respective vertical memory cells in the memory cell array region 512.

[0202] Figure 30A is a schematic perspective view of an integrated circuit device 600 according to some embodiments of the inventive concept. Figure 30B is Figure 30A a schematic cross-sectional view of the integrated circuit device 600. Figure 30A and Figure 30B The integrated circuit device 600 may have the same planar layout as that of the integrated circuit device 500 in Figure 29 . In Figure 30A and Figure 30B , the same reference numerals as those in Figures 1 to 4G denote the same elements, and detailed descriptions thereof are omitted.

[0203] Referring to Figure 30A and Figure 30B , the integrated circuit device 600 may include a first peripheral circuit region 514 formed at a first horizontal height of the substrate 502 and a memory cell array region 512 formed at a second horizontal height higher than the first horizontal height of the substrate 502. The term "horizontal height" used herein may represent a height in a third direction (Z direction) with respect to the substrate 502. The first horizontal height on the substrate 502 is closer to the substrate 502 than the second horizontal height.

[0204] In some embodiments, the substrate 502 may have a main surface 502M extending in a first direction (X direction) and a second direction (Y direction). The detailed description of the substrate 502 is substantially the same as that of the reference Figure 3 with respect to the description of the substrate 102.

[0205] The active region AC of the peripheral circuit may be defined by an isolation layer 504 in the substrate 502. A plurality of transistors TR forming the first peripheral circuit region 514 may be formed in the active region AC of the substrate 502. Each transistor TR may include a gate G, a gate dielectric film GD, and source / drain regions SD. Two sidewalls of the gate G may be covered by insulating spacers 106, and an etch stop layer 108 may be formed on the gate G and the insulating spacers 106. The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

[0206] A plurality of interlayer insulating films 112A, 112B, 112C, and 112D may be sequentially stacked on the etch stop layer 108. The interlayer insulating films 112A, 112B, 112C, and 112D may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0207] The first peripheral circuit region 514 may include a multilayer wiring structure 630 electrically connected to the transistors TR. The multilayer wiring structure 630 may be insulated by the interlayer insulating films 112A, 112B, 112C, and 112D.

[0208] The multilayer wiring structure 630 may include a first contact 116A, a first wiring layer 118A, a second contact 116B, a second wiring layer 118B, a third contact 116C, and a third wiring layer 118C that are sequentially stacked on the substrate 502 and electrically connected to each other. In some embodiments, the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C may each include, for example, a metal, a conductive metal nitride, a metal silicide, or a combination thereof. For example, the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C may include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide, or nickel silicide.

[0209] In Figure 30A and Figure 30B , although the multilayer wiring structure 630 is shown as having a three-layer wiring structure including the first wiring layer 118A, the second wiring layer 118B, and the third wiring layer 118C, the inventive concept is not limited to Figure 30A and Figure 30B the illustration. For example, the multilayer wiring structure 630 may have a two-layer or four-layer or more-layer multilayer wiring structure according to the layout of the first peripheral circuit region 514 or the type and arrangement of the gate G.

[0210] A semiconductor layer 520 covering the interlayer insulating films 112A, 112B, 112C, and 112D is formed on the first peripheral circuit region 514. A memory cell array region 512 is formed on the semiconductor layer 520. The memory cell array region 512 has a structure substantially the same as that of the memory cell array region of the integrated circuit device 100 described with reference to Figures 1 to 4G or a structure substantially the same as that of the memory cell array region of the integrated circuit device 200 described with reference to Figure 21 and Figure 22 and

[0211] A plurality of common source regions 572 may be formed on the semiconductor layer 520. The detailed structure of the common source region 572 is substantially the same as that of the common source region 160 described with reference to Figure 3 and

[0212] The common source region 572 may be formed by doping impurities in the semiconductor layer 520. As shown in Figure 30A and Figure 30B and

[0213] In the integrated circuit device 600, the memory cell array region 512 and the first peripheral circuit region 514 may be electrically connected to each other through at least one connection plug (not shown) extending in the third direction (Z direction). The at least one connection plug may penetrate at least a part of the interlayer insulating films 112A, 112B, 112C, and 112D forming the first peripheral circuit region 514 and the semiconductor layer 520. The wiring structure formed in the memory cell array region 512 and the wiring structure formed in the first peripheral circuit region 514 may be electrically connected to each other through the at least one connection plug.

[0214] Figure 30A and Figure 30BThe illustrated integrated circuit device 600 has a multi-layer device structure, in which semiconductor devices having a first horizontal height with different functions from each other and semiconductor devices having a second horizontal height are stacked to vertically overlap each other and are at different horizontal heights. Accordingly, in the memory cell array region 512, the number of layers of the multi-layer wiring structure formed above the plurality of common source lines CSL and the channel structures CHS can be reduced. Accordingly, the density of the wiring patterns of the multi-layer wiring structure formed in the memory cell array region 512 does not increase excessively, and the manufacturing process of the integrated circuit device can be simplified. In addition, by reducing the number of stacked metal wiring layers of the multi-layer wiring structure, the physical stress caused by the metal wiring can be reduced, and thus the warpage of the substrate can be reduced.

[0215] Figure 31 is a schematic perspective view of an integrated circuit device 700 according to some embodiments of the inventive concept. In Figure 31 , the same reference numerals as in Figures 1 to 30B denote the same elements, and their detailed descriptions are omitted.

[0216] Referring to Figure 31 , the integrated circuit device 700 may include a substrate 102, a lower stack LST having a plurality of lower word lines LWL stacked on the substrate 102 and overlapping each other in a vertical direction, and an upper stack UST having a plurality of upper word lines UWL stacked on the lower stack LST and overlapping each other in a vertical direction.

[0217] The channel structure CHS may extend on the substrate 102 to penetrate the lower stack LST and the upper stack UST in a vertical direction. The channel structure CHS may be connected to the bit line BL through the bit line contact pad 182. Both the lower stack LST and the upper stack UST may have any one of the stack structures selected from the stack structures ST shown in Figure 3 and Figure 21 . Each channel structure CHS may include any one of the channel structures selected from the channel structures CHS shown in Figure 2 , Figure 3 and Figure 21 .

[0218] The width of each lower word line LWL and each upper word line UWL in the Y direction may decrease as it moves away from the substrate 102. Accordingly, both the lower stack LST and the upper stack UST may have a cone shape. The edge portion of each lower word line LWL in the Y direction may be used as the lower contact pad CP1, and the edge portion of each upper word line UWL in the Y direction may be used as the upper contact pad CP2. Although Figure 31It is shown that both edge portions of the lower stack LST and the upper stack UST in the Y direction have a stepped structure, but the inventive concept is not limited thereto, and the direction in which the stepped structure is formed can be differently selected.

[0219] The lower word line LWL can be electrically connected to a word line driving circuit (not shown) via a plurality of lower contacts CON1 that contact the lower contact pad CP1 and a plurality of wirings 712 and 714 connected to the lower contacts CON1. The upper word line UWL can be electrically connected to a word line driving circuit (not shown) via a plurality of upper contacts CON2 that contact the upper contact pad CP2 and a plurality of wirings 722 and 724 connected to the upper contacts CON2. Among the upper word lines UWL, at least one upper word line UWL serving as a string selection line SSL can be connected to a selection line driving circuit (not shown) via a plurality of wirings 726.

[0220] In the integrated circuit device 700, a lower stack LST and an upper stack UST that overlap each other in the vertical direction are provided, so that the integration degree can be improved (for example, the integration degree can be increased).

[0221] Although the inventive concept has been specifically shown and described with reference to some embodiments of the inventive concept, it should be understood that various changes in form and detail can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, the integrated circuit device comprising: A plurality of word line structures that extend on the substrate in a horizontal direction parallel to a main surface of the substrate and overlap each other in a vertical direction perpendicular to the main surface of the substrate; A plurality of insulating films that are stacked alternately with the plurality of word line structures in the vertical direction and extend in the horizontal direction, wherein side surfaces of the plurality of word line structures and side surfaces of the plurality of insulating films define side surfaces of channel holes that extend through the plurality of word line structures and the plurality of insulating films; A blocking dielectric film that extends on the side surfaces of the channel holes; A plurality of charge storage films that are spaced apart from each other on the blocking dielectric film in the channel holes and are respectively located on the side surfaces of the plurality of word line structures, and each charge storage film of the plurality of charge storage films includes a first charge storage film and a second charge storage film that are sequentially stacked on a corresponding side surface of the side surfaces of the plurality of word line structures; and A tunneling dielectric film that is located on the blocking dielectric film and the plurality of charge storage films in the channel holes, wherein the second charge storage film includes a first surface facing the blocking dielectric film and a second surface opposite to the first surface, wherein the second surface of the second charge storage film includes a recess in an intermediate portion thereof in the vertical direction, wherein the second charge storage film has an upper portion and a lower portion that protrude further toward the channel hole than the intermediate portion, and wherein the tunneling dielectric film has curved portions that are recessed in a direction toward the channel hole and respectively correspond to the upper portion and the lower portion of the second charge storage film.

2. The integrated circuit device according to claim 1, wherein, The side surface of each insulating film of the plurality of insulating films protrudes toward the blocking dielectric film beyond the side surface of each word line structure of the plurality of word line structures.

3. The integrated circuit device according to claim 2, the integrated circuit device further comprising: A channel film that is located on the tunneling dielectric film, wherein a surface of the blocking dielectric film facing the channel film includes a plurality of grooves respectively corresponding to the plurality of word line structures, and each charge storage film of the plurality of charge storage films includes a first portion located in a corresponding groove of the plurality of grooves of the blocking dielectric film and a second portion protruding from the corresponding groove of the plurality of grooves of the blocking dielectric film.

4. The integrated circuit device according to claim 1, wherein, The second charge storage film has a greater width in the horizontal direction than the first charge storage film in the horizontal direction.

5. The integrated circuit device according to claim 1, wherein, The second charge storage film has a greater height in the vertical direction than the first charge storage film in the vertical direction.

6. The integrated circuit device according to claim 1, wherein Each charge storage film of the plurality of charge storage films has a greater height in the vertical direction than each word line structure of the plurality of word line structures in the vertical direction.

7. An integrated circuit device, the integrated circuit device comprising: A plurality of word line structures that extend on the substrate in a horizontal direction parallel to the main surface of the substrate and overlap each other in a vertical direction perpendicular to the main surface; A plurality of insulating films that are alternately stacked with the plurality of word line structures in the vertical direction and extend in the horizontal direction, wherein the side surfaces of the plurality of word line structures and the side surfaces of the plurality of insulating films define the side surfaces of channel holes that extend through the plurality of word line structures and the plurality of insulating films; A channel film that extends in the vertical direction in the channel holes; A blocking dielectric film that is located in the channel holes and extends on the side surfaces of the plurality of word line structures and the side surfaces of the plurality of insulating films in the channel holes, the blocking dielectric film includes a surface facing the channel film, and the surface includes a plurality of grooves respectively located on the side surfaces of the plurality of word line structures; and A plurality of charge storage films, wherein at least a part of each charge storage film of the plurality of charge storage films is located in a corresponding one of the plurality of grooves of the blocking dielectric film; wherein the surface of each charge storage film of the plurality of charge storage films facing the channel film has a concave shape in its middle part, and each charge storage film of the plurality of charge storage films has an upper part and a lower part that protrude further toward the channel holes compared to the middle part, and wherein the channel film has curved portions that are recessed in a direction toward the channel holes and correspond to the upper part and the lower part of each charge storage film of the plurality of charge storage films respectively.

8. The integrated circuit device according to claim 7, wherein, Each charge storage film of the plurality of charge storage films includes: A first part that is located in the corresponding one of the plurality of grooves; and A second part that protrudes from the corresponding one of the plurality of grooves of the blocking dielectric film.

9. The integrated circuit device according to claim 8, wherein, The surface of the first part facing the channel film has a concave shape in its middle part.

10. The integrated circuit device according to claim 8, wherein, The surface of the first part facing the channel film has a flat shape.

11. The integrated circuit device according to claim 8, wherein, The surface of the second part facing the channel film has a concave shape in its middle part.

12. The integrated circuit device according to claim 8, wherein, The height of the second part in the vertical direction is greater than the height of the first part in the vertical direction.

13. An integrated circuit device, the integrated circuit device includes: A plurality of word line structures that extend on the substrate in a horizontal direction parallel to the main surface of the substrate and overlap each other in a vertical direction perpendicular to the main surface; A plurality of insulating films that are alternately stacked with the plurality of word line structures in the vertical direction and extend in the horizontal direction, wherein the side surfaces of the plurality of word line structures and the side surfaces of the plurality of insulating films define the side surfaces of channel holes that extend through the plurality of word line structures and the plurality of insulating films; A channel film that extends in the vertical direction in the channel holes; A blocking dielectric film that extends in the channel hole on the sides of the plurality of word line structures and on the sides of the plurality of insulating films; At least one charge storage film that is located on the blocking dielectric film in the channel hole; and A tunneling dielectric film that extends in the channel hole on the blocking dielectric film and the at least one charge storage film, and a channel film extends on the tunneling dielectric film, wherein, for each insulating film of the plurality of insulating films, the side facing the channel film protrudes beyond the side of each word line structure of the plurality of word line structures towards the channel film, the surface of the blocking dielectric film facing the channel film includes a plurality of grooves respectively located on the sides of the plurality of word line structures, and at least a part of the at least one charge storage film is located in one of the plurality of grooves of the blocking dielectric film, wherein, the surface of the at least one charge storage film facing the channel film includes a recess in its middle part along the vertical direction, wherein, the at least one charge storage film has an upper part and a lower part that protrude further towards the channel hole compared to the middle part, and wherein, the tunneling dielectric film has curved portions that are recessed in the direction towards the channel hole and respectively correspond to the upper part and the lower part of the at least one charge storage film.

14. The integrated circuit device according to claim 13, wherein, The at least one charge storage film includes: A first part that is located in one of the plurality of grooves; and A second part that is located outside one of the plurality of grooves of the blocking dielectric film.

15. The integrated circuit device according to claim 14, wherein, The first part includes a recess in its middle part, and the recess is recessed relative to the upper part and the lower part of the first part.

16. The integrated circuit device according to claim 14, wherein, The side of the first part facing the channel film has a flat surface.

17. The integrated circuit device according to claim 14, wherein, The second part includes a recess in its middle part, and the recess is recessed relative to the upper part and the lower part of the second part.

18. The integrated circuit device according to claim 14, wherein, The first part includes at least two first parts spaced apart from each other.

19. The integrated circuit device according to claim 18, wherein, The second part includes at least two second parts respectively located on the at least two first parts.

20. A method of manufacturing an integrated circuit device, the method comprising: Forming a structure including a plurality of first films and a plurality of second films stacked alternately with the plurality of first films on a substrate; Forming a channel hole extending through the structure; Forming a plurality of recessed spaces in the channel hole by removing a part of the plurality of second films through the channel hole; Forming a blocking dielectric film in the channel hole on the plurality of first films and the plurality of second films, the blocking dielectric film including a plurality of grooves respectively located on the plurality of recessed spaces; Forming at least one charge storage film, the at least one charge storage film including a first charge storage film located in one of the plurality of grooves and a second charge storage film located on the first charge storage film; And Forming a tunneling dielectric film in the channel hole covering the at least one charge storage film and the blocking dielectric film, Among them, the surface of the second charge storage film facing the channel hole includes a recess in an intermediate portion in a vertical direction perpendicular to the main surface of the substrate. Among them, the second charge storage film has an upper portion and a lower portion that protrude further toward the channel hole than the intermediate portion, and Among them, the tunneling dielectric film has curved portions that are recessed in a direction toward the channel hole and respectively correspond to the upper portion and the lower portion of the second charge storage film.

21. The method according to claim 20, wherein, Forming the at least one charge storage film includes: Forming a preliminary charge storage film on the barrier dielectric film in the channel hole, wherein the preliminary charge storage film is located in the plurality of grooves; and Performing anisotropic etching on the preliminary charge storage film to form the first charge storage film.

22. The method according to claim 20, wherein, The second charge storage film is formed by performing a selective epitaxial growth process using the first charge storage film as a seed or by performing a selective deposition process, and Among them, at least one charge storage film includes a first portion located in one of the plurality of grooves and a second portion located outside one of the plurality of grooves of the barrier dielectric film.

23. The method according to claim 20, wherein The second charge storage film is formed to have a width larger than the width of the first charge storage film.

24. The method according to claim 20, wherein The second charge storage film is formed to have a height larger than the height of the first charge storage film.

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