Enhanced start-up circuit with jfet emulation

Abstract

An enhanced start-up circuit with JFET emulation is disclosed. A start-up circuit (100) includes an enhancement mode transistor (Q1) having a drain (D1) coupled to a start-up circuit input (102), a source (S1) coupled to a first node (104), and a gate (G1) coupled to a second node (106). The start-up circuit (100) includes a current limit circuit (112) that controls a current path between the second node (106) and a start-up circuit output node (108) based on a current sense voltage signal (VCS) representative of a current (IQ1) through the enhancement mode transistor (Q1), and a voltage regulation circuit (114) that controls a voltage (VGS) of the second node (106) to regulate a start-up circuit output voltage (VAUX) of the start-up circuit output node (108).

Description

[0001] Citation of relevant applications

[0002] Under 35 U.S.SC §119, this application claims preference and benefit to U.S. Provisional Patent Application No. 62 / 809,165, entitled “High-Voltage JFET Emulation in E-Mode GAN for Start-Up”, filed February 22, 2019, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Some circuits are designed to start up when power is applied, such as power supplies for device charging systems. In some cases, the applied power is in the form of high voltage, and the startup circuit must be capable of withstanding high voltage. High-voltage startup circuits typically include high-voltage depletion-mode transistors, such as high-voltage depletion-mode transistors or junction field-effect transistors (JFETs). Upon initial power application, the JFET or depletion-mode transistor can conduct without an auxiliary supply voltage. The JFET or depletion-mode transistor is then used to charge a capacitor until the allowable supply voltage is reached. The normally conducting transistor operates as a current source during startup, and external circuitry disables the depletion-mode transistor or JFET after startup for low-leakage normal operation. Using external depletion-mode transistors or JFETs is expensive in terms of cost and circuit area. However, integrating depletion-mode transistors or JFETs into low-mask-number, enhancement-mode, gallium nitride (GaN) fabrication processes is challenging. Summary of the Invention

[0004] A startup circuit and power conversion system are described, comprising an enhancement-mode transistor, a current-limiting circuit, and a voltage regulation circuit. The enhancement-mode transistor includes a drain, a source coupled to a first node, and a gate coupled to a second node. The current-limiting circuit controls the current path between the second node and the startup circuit output node based on a current-sensing voltage signal representing the current through the enhancement-mode transistor. The voltage regulation circuit controls the voltage of the second node to regulate the startup circuit output voltage of the startup circuit output node.

[0005] The power conversion system includes: a power input, a converter switch coupled to a switching node, a driver circuit having an output coupled to the converter switch, and a startup circuit. The startup circuit includes: a startup circuit input coupled to the power input or the switching node; and an enhancement-mode transistor coupled in a first circuit path between the startup circuit input and a startup circuit output node, the enhancement-mode transistor including a drain coupled to the startup circuit input, a source coupled to the first node, and a gate coupled to a second node. The startup circuit also includes a current-limiting circuit for controlling a second current path between the second node and the startup circuit output node based on a current-sensing voltage signal from a resistor in the first circuit path, to control an upper limit of the current in the first circuit path. The startup circuit also includes a voltage regulation circuit coupled to the startup circuit output node and the second node, and configured to control the voltage of the second node to regulate the startup circuit output voltage of the startup circuit output node.

[0006] A method is described that includes applying a rising voltage signal to the drain of an enhancement-mode transistor to turn on the enhancement-mode transistor, thereby delivering a charging current to an output node to charge a capacitor. The method further includes controlling the gate voltage of the enhancement-mode transistor to limit the charging current, blocking current flowing from the output node to the gate of the enhancement-mode transistor, and turning off the enhancement-mode transistor in response to the voltage at the output node exceeding a threshold. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a startup circuit according to one embodiment.

[0008] Figure 2 yes Figure 1 A simplified schematic diagram of the enhancement-mode gallium nitride transistor in the startup circuit.

[0009] Figure 3 This is a flowchart of a method for starting a circuit according to another embodiment.

[0010] Figure 4 This is a schematic diagram of a system with a startup circuit according to another embodiment.

[0011] Figure 5 This refers to several exemplary input voltage signals with different rise times. Figure 1 A signal diagram of an exemplary voltage in the startup circuit.

[0012] Figure 6 This is during startup and subsequent current-limiting operations. Figure 1 A signal diagram of an exemplary waveform in the startup circuit.

[0013] Figure 7 This is a schematic diagram of another exemplary startup circuit with a two-dimensional electronic gas resistor according to another embodiment.

[0014] Figure 8 This is a schematic diagram of a system with a startup circuit according to another embodiment.

[0015] Figure 9 This is a schematic diagram of a system with a startup circuit according to another embodiment, the startup circuit having a separate precharge circuit input to receive a voltage signal from an input power supply circuit.

[0016] Figure 10 This is a schematic diagram of a system with a startup circuit according to another embodiment, the startup circuit having a pre-charge circuit including a current source connected to an input power supply circuit.

[0017] Figure 11 This is a schematic diagram of a power conversion system with a startup circuit according to another embodiment. Detailed Implementation

[0018] In the accompanying drawings, similar reference numerals always refer to similar elements, and various features are not necessarily drawn to scale. The term "coupled" is used throughout the specification. This term can encompass connection, communication, or signal paths that achieve a functional relationship consistent with the description of this disclosure. For example, in a first example, if device A generates a signal to control device B to perform an action, then device A is coupled to device B via a direct connection; or in a second example, if intermediate component C does not alter the functional relationship between device A and device B such that device A controls device B via a control signal generated by device A, then device A is coupled to device B via intermediate component C.

[0019] First refer to Figure 1 and Figure 2 , Figure 1A startup circuit 100 is shown, featuring a high-voltage enhancement-type (E-type) transistor 101 (Q1) to control the startup of a host system. In one example, the startup circuit 100 is or includes an integrated circuit with pins or pads for electrical coupling to conductive features of a host printed circuit board (PCB) to create circuitry with other electronic components. In one application, the startup circuit 100 is included in a switch-mode power converter, such as a flyback converter. The transistor 101 acts as a current source during startup to establish a supply voltage for an active clamp flyback (ACF) controller, and disables the transistor 101 after startup to reduce or mitigate leakage during steady-state operation of the power converter. In one embodiment, the power converter includes a rectifier circuit or other DC power supply coupled to a first terminal of the primary winding of a transformer, and a converter switch coupled between a second terminal of the primary winding and a ground or reference node. The second terminal of the primary winding forms a switching node whose switching node voltage rises during startup in response to the initial connection of the rectifier to the AC power supply. In steady-state operation, the controller operates the switch to transfer power to the secondary transformer winding, and the secondary-side rectifier provides a DC output voltage signal to drive the load.

[0020] Figure 1 An exemplary embodiment of a high-voltage startup circuit 100 is shown. The startup circuit includes an enhancement-mode transistor Q1 (101), a current limiting circuit 112, a voltage regulating circuit 114, and a pre-charge circuit 122. The pre-charge circuit 122 includes components coupled to the startup circuit input 102 or a power node (…). Figure 1 The precharge circuit 122 includes a precharge circuit input 123 (not shown in the diagram) and a precharge circuit output coupled to the second node 106. The precharge circuit 122 includes a third transistor Q3 or a current source (e.g., shown below). Figure 10 This is coupled between the precharge circuit input 123 and the second node 106 to provide current to the second node 106. Figure 1In the example, the pre-charge circuit 122 provides charge to the gate of the enhancement-type transistor Q1 to increase the gate-source voltage VGS of the enhancement-type transistor Q1. As the gate-source voltage VGS of the enhancement-type transistor Q1 continues to rise, the current IQ1 of the transistor Q1 increases. An exemplary enhancement-type transistor 101 may be a group III-V transistor, such as a gallium nitride (GaN) enhancement-type transistor Q1. The enhancement-type transistor Q1 includes a drain D1 coupled to the startup circuit input 102, a source S1 coupled to the first node 104, and a gate G1 coupled to the second node 106. Due to the drain-gate capacitance CDG and the gate-source capacitance CGS, the increase in the drain voltage of the enhancement-type transistor Q1 can cause its gate voltage to rise. Thus, the enhancement-type transistor responds to the increase in gate charge (e.g., in response to the positive voltage slew rate of the voltage VSW at the drain of the enhancement-type transistor). The increase in gate charge may result in an increase in the gate-source voltage. When the gate-source voltage VGS of Q1 is higher than the threshold voltage of transistor Q1, transistor Q1 turns on and conducts a current IQ1 to begin charging the capacitor CAUX connected to the startup circuit output 108. The charging current generates the startup circuit output voltage VAUX at the startup circuit output node 108. The ratio CDG / CGS of the enhancement-mode transistor capacitance promotes the turn-on of the enhancement-mode transistor Q1 in response to the rising drain voltage.

[0021] Figure 1 The example also includes a pre-charge circuit 122 with a pre-charge transistor Q3 and a capacitor C1. Figure 1 In the example, capacitor C1 includes a first terminal connected to the second node 106 and a second terminal connected to the startup circuit output node 108. In other embodiments, capacitor C1 is omitted. Precharge circuit 122 provides charge to the gate G1 of enhancement-mode transistor Q1 to turn on enhancement-mode transistor Q1. Capacitor C1 is coupled between the gate of enhancement-mode transistor Q1 and startup circuit output node 108. In this embodiment, even if the rate of increase of voltage VSW at startup circuit input 102 is insufficient to turn on Q1, the rising slope of VSW at the drain of precharge circuit transistor Q3 will turn on Q3, which then charges capacitor C1 and the gate-source capacitance CGS of enhancement-mode transistor Q1, causing Q1 to turn on. The illustrated example including precharge circuit 122 enhances the ability of startup circuit 100 to turn on enhancement-mode transistor Q1 in response to rising voltage VSW at startup circuit input 102. In one example, precharge transistor Q3 is smaller than enhancement-mode transistor Q1, and Q3 can be turned on faster than Q1 by charging from rising voltage VSW. In some applications, the rate of increase of voltage VSW can be related to the frequency of the AC grid supplying power to the rectifier coupled to the startup circuit input 102 (e.g., below). Figure 11Furthermore, Q3 can be turned on even when only Q1 is not turned on. In the case where the rate of increase of voltage VSW is insufficient to create enough charge to turn on enhancement-mode transistor Q1, precharge transistor Q3 turns on to supply charge to gate G1 so that Q1 can turn on. In another embodiment, precharge circuit 122 and precharge transistor Q3 are omitted, and enhancement-mode transistor Q1 turns on in response to a rising voltage VSW at startup circuit input 102. Figure 1 Resistor R3 is shown, which is coupled to the second node 106 and the third node 124 to represent the parasitic gate-source leakage of the precharge transistor Q3.

[0022] A capacitor CAUX is connected between the startup circuit output node 108 and the reference node 110. In one example, the capacitor CAUX is charged by a current IQ1 conducted through the enhancement transistor Q1 to generate an auxiliary voltage (referred to herein as the startup circuit output voltage VAUX) at the startup circuit output node 108. In this embodiment, the reference node 110 is used for the startup circuit 100 and the host power system (e.g., below). Figure 11 The startup circuit output node 108 is connected to the main power supply voltage node (e.g., to provide the power supply voltage signal VDD) via a diode, and a separate regulator circuit regulates the main power supply voltage after the startup circuit output voltage VAUX reaches a predetermined magnitude, and provides a shutdown signal to the startup circuit 100 to turn off the enhancement-mode transistor Q1. Therefore, in this embodiment, the startup circuit output voltage VAUX is an auxiliary power supply voltage signal generated and maintained during startup operation, and the host power system uses the power supply voltage signal VDD for steady-state operation. In one example, the capacitor CAUX is external to the startup circuit 100. The capacitor CAUX maintains the startup circuit output voltage VAUX in response to the charging current IQ1 conducted by the enhancement-mode transistor Q1.

[0023] Current limiting circuit 112 (e.g., in Figure 1A current limiting circuit (labeled as a current limiter) is coupled to a first node 104, a startup circuit output node 108, and a second node 106. The current limiting circuit 112 includes a first resistor RCS having a first terminal coupled to the first node 104 and a second terminal coupled to the startup circuit output node 108. The current limiting circuit 112 also includes a second transistor Q2 having a drain directly or indirectly coupled to the second node 106, a source coupled to (e.g., connected to) the startup circuit output node 108, and a gate coupled to (e.g., connected to) the first node 104. In operation, the first terminal of the resistor RCS delivers a current-sensing voltage signal VCS to the gate of the second transistor Q2. The current-sensing voltage signal VCS causes the second transistor Q2 to control the voltage VGS at the gate G1 of the enhancement-type transistor Q1 to limit the drain-source current IQ1 of the enhancement-type transistor Q1. In one example, the current limiting circuit 112 includes a fourth transistor Q4. The fourth transistor Q4 includes a drain coupled to the third node 124, a source coupled to the output node 108 of the startup circuit, and a gate coupled to the first node 104.

[0024] In operation, the current limiting circuit 112 limits the drain-source current IQ1 of the enhancement-type transistor Q1 to an upper limit set by the impedance of the current-sensing resistor RCS. The voltage regulation circuit 114 is coupled to the startup circuit output node 108 and the second node 106. The voltage regulation circuit 114 includes a voltage-regulated output node 116, a comparator or amplifier 118 (e.g., an operational amplifier), and a reference voltage 120 that provides a non-zero reference voltage signal VREF. Furthermore, Figure 1 The exemplary startup circuit 100 includes a pre-charge circuit 122 to assist in pre-charging the second node 106. In this example, the third transistor Q3 includes a drain coupled to the drain D1 of transistor Q1, a source directly or indirectly coupled to the second node 106, and a gate coupled to the third node 124.

[0025] In one example, the current limiting circuit 112 includes a current-sensing resistor RCS coupled to the first node 104 and the startup circuit output node 108. The current limiting circuit 112 also includes a second transistor Q2 having a gate coupled to the first node 104, a drain coupled to the second node 106, and a source coupled to the startup circuit output node 108. In the illustrated example that includes a third transistor Q3 with a pre-charge circuit 122, the current limiting circuit 112 includes a fourth transistor Q4 having a gate coupled to the first node 104, a drain coupled to the third node 124, and a source coupled to the startup circuit output node 108. When the enhancement-mode transistor Q1 is turned on, the current-sensing resistor RCS provides a current-sensing voltage signal VCS proportional to the drain current IQ1 of the enhancement-mode transistor Q1. If IQ1 exceeds the desired current limit (e.g., the threshold voltage of Q2 divided by RCS(VthQ2 / RCS)), the current-sensing voltage signal VCS turns on transistor Q2 to discharge the gate G1 of transistor Q1, thereby reducing the current IQ1 of transistor Q1. The current-sensing voltage signal VCS also turns on Q4 to stop any further charging of the gate G1 of transistor Q1.

[0026] In one example, the startup circuit 100 includes a blocking circuit 126 that blocks current from the startup circuit output node 108 to the second node 106 and / or from the output node 108 to the third node 124 when the potential at the second node 106 and / or the third node 124 is lower than the potential at the startup circuit output node 108. In one example, the blocking circuit includes a first blocking transistor Q7 having a source coupled to the startup circuit output node 108, a gate coupled to the second node 106, and a drain coupled to the source of a second transistor Q2. Figure 1In the example shown, which includes a pre-charge transistor Q3, the blocking circuit also includes a second blocking transistor Q8, which has a source coupled to the output node 108 of the startup circuit, a gate coupled to the third node 124, and a drain coupled to the source of Q4. When the potential at the output node 108 of the startup circuit is greater than the potential at the second node 106, the gate-source voltage of the seventh transistor Q7 is negative. Q7 is thus turned off and prevents any current from flowing from the output node 108 of the startup circuit to the second node 106. When the potential at the output node 108 of the startup circuit is greater than the potential at the third node 124, the gate-source voltage of transistor Q8 is negative. Q8 is thus turned off and prevents any current from flowing from the output node 108 of the startup circuit to the third node 124. In one example, the enhancement-mode transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the first blocking transistor Q7, and the second blocking transistor Q8 are enhancement-mode gallium nitride (GaN) transistors. In one implementation, transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8 are enhancement-mode GaN transistors formed in a GaN die, as described below. Figure 8 Further discussion is needed.

[0027] During startup, voltage regulation circuit 114 regulates the startup circuit output voltage VAUX across capacitor CAUX. Voltage regulation circuit 114 includes comparator 118 having a non-inverting input coupled to startup circuit output node 108 and an inverting input coupled to a reference voltage signal VREF, provided by voltage source 120, referred to as reference node 110. Comparator 118 also has an output coupled to voltage regulation output node 116, which provides an output signal VSD. In operation, the VSD signal controls the gate voltages of transistors Q1 and Q3 during startup to regulate the startup circuit output voltage VAUX, and turns off transistors Q1 and Q3 to shut down startup circuit 100. The voltage regulation circuit 114 further includes: a fifth transistor Q5 having a gate coupled to the voltage regulation output node 116, a drain coupled to the second node 106, and a source coupled to the reference node 110; and a sixth transistor Q6 having a gate coupled to the voltage regulation output node 116, a drain coupled to the third node 124, and a source coupled to the reference node 110.

[0028] The voltage regulation circuit 114 also includes a fifth transistor Q5 having a drain connected to the second node 106, a source connected to the reference node 110, and a gate connected to the voltage regulation output node 116. When the shutdown voltage signal VSD rises to or above the threshold voltage of the fifth transistor Q5, the fifth transistor Q5 turns on to connect the second node 106 to the reference node 110. This reduces the gate-source voltage VGS of the enhancement-mode transistor Q1 and turns off the enhancement-mode transistor Q1. The exemplary voltage regulation circuit 114 also includes a sixth transistor Q6 having a drain connected to the third node 124, a source connected to the reference node 110, and a gate connected to the voltage regulation output node 116. The sixth transistor Q6 also turns on in response to the shutdown voltage signal VSD rising above its threshold voltage to turn off the third transistor Q3. In other embodiments where the precharge circuit 122 is omitted (e.g., below) Figure 4 In the circuit 114, the sixth transistor Q6 can also be omitted.

[0029] During operation, when the startup circuit output voltage VAUX at startup circuit output node 108 exceeds the desired value set by the reference voltage signal VREF 120, comparator 118 pulls high the shutdown signal voltage VSD at voltage regulation output node 116 to turn on the fifth transistor Q5, thereby discharging the gate G1 of enhancement-mode transistor Q1 to stop charging capacitor CAUX. The high shutdown voltage signal VSD at node 116 also turns on the sixth transistor Q6, thereby discharging the third node 124 and stopping any further charging of the gate G1 of enhancement-mode transistor Q1.

[0030] Current limiting circuit 122 and voltage regulating circuit 114 operate simultaneously to control the voltages at the second node 106 and the third node 124. If the current IQ1 of enhancement-mode transistor Q1 exceeds the upper limit set by the resistance of the sense resistor RCS and the threshold voltage of transistor Q2, current limiting circuit 122 reduces the voltage at the second node 106 by discharging capacitor C1, thereby reducing the gate-source voltage VGS of enhancement-mode transistor Q1 to reduce current IQ1 until IQ1 is within a defined limit (e.g., VthQ2 / RCS). In this way, capacitor CAUX is charged with the controlled current IQ1 of transistor Q1 during startup. When the startup circuit output voltage VAUX at startup circuit output node 108 exceeds the desired value set by the reference voltage signal VREF of reference 120, voltage regulating circuit 114 discharges the second node 106 to turn off enhancement-mode transistor Q1, thereby disconnecting the current IQ1 of transistor Q1 and thus stopping the charging of capacitor CAUX coupled to startup circuit output node 108. Voltage regulation circuit 114 also discharges third node 124 to turn off the pre-charge circuit and keeps it off to prevent any further charging of second node 106.

[0031] Figure 2 It shows Figure 1 A simplified electrical model 201 of the enhancement-mode transistors Q1 / Q3 in the startup circuit includes a drain D1 coupled to the startup circuit input 202, a gate G1 connected to the second node 206, and a source S1 connected to the power supply node 204, wherein nodes 202, 204, and 206 correspond to... Figure 1 The corresponding nodes are 102, 104, and 106. This example includes a resistor R2 connected between the drain and gate of transistor Q1 and a resistor R4 connected between the gate and source of transistor Q1 to represent the impedance path for leakage current. In one example, enhancement-mode transistor Q1 is a high-voltage GaN transistor that simulates the operation of a JFET or depletion-mode device to initially turn on transistor Q1 in response to a rising input voltage signal VSW applied at the drain D1 of the enhancement-mode transistor. In some embodiments, enhancement-mode transistor Q1 is a high-voltage GaN device with a poor Miller ratio, where the gate-to-source capacitance CGS is greater than the drain-to-gate capacitance CDG. Using enhancement-mode transistor Q1 in startup circuit 100 utilizes the poor Miller ratio to facilitate startup without an auxiliary power supply. A poor Miller ratio means that the drain-to-gate charge (defined by the drain-to-gate capacitance multiplied by the drain-to-source voltage) is greater than the gate-to-source charge (defined by the gate-to-source capacitance multiplied by the gate-to-source threshold voltage required to turn on the device).

[0032] like Figure 2 As shown, the enhancement-mode transistor Q1 has a non-zero leakage current IDG from the drain D1 to the gate G1. Furthermore, the enhancement-mode transistor Q1 has a non-zero leakage current IGS from the gate G1 to the source S1 and a non-zero leakage current IGG from the gate G1 to the ground reference. The exemplary high-voltage GaN enhancement-mode transistor Q1 simulates JFET operation during startup by utilizing the differential Miller ratio of transistor Q1. The differential Miller ratio means that the drain-to-gate charge (drain-to-gate capacitance CDG multiplied by the drain-to-source voltage) is greater than the gate-to-source charge (gate-to-source capacitance CGS multiplied by the gate-to-source threshold voltage required to turn on the device). In one example, the drain-to-source current IQ1 of the enhancement-mode transistor Q1 is C... DG *(dV DG / dt)+I DG It is greater than the total gate-source current and the gate-to-ground current (C GS *(dV GS / dt)+I GS +C GG *(dV GG / dt)+I GG ).

[0033] The enhancement-mode transistor Q1 has a drain-to-gate capacitance CDG, a gate-to-ground capacitance CGG, and a gate-to-source capacitance CGS connected as schematically indicated by the dashed lines in Figure 2 . In one example, the capacitances CDG, CGG, and CGS represent the parasitic capacitances of the enhancement-mode transistor Q1. The gate-to-source capacitance CGS of the enhancement-mode transistor Q1 is greater than the drain-to-gate capacitance CDG, and the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is less than 1000. In one example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 5. In another example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 10. In another example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 20. In another example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 100. In another example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 200. In another example, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is greater than 300.

[0034] At system startup, the poor Miller ratio caused by the ratio CGS / CDG (either alone or in further combination with the precharge circuit 122) allows the rising input voltage signal VSW to deliver a startup voltage VGS at the gate G1. Figure 1 An example of shows a first resistor R1 shown in dashed lines, which represents a parasitic leakage path from the gate to the source of the enhancement-mode transistor Q1 to simulate gate leakage. The initial gate voltage VGS rises above the threshold voltage Vt of the enhancement-mode transistor Q1. The CDG / CGS ratio does not depend on the width of a given implementation of the enhancement-mode transistor Q1. In response to the rising input voltage signal VSW at the drain D1 of the enhancement-mode transistor Q1, the startup behavior helps to turn on. In one example, the enhancement-mode transistor Q1 is a GaN transistor having a width dimension of 100,000 um, a gate-to-source capacitance CGS of 80 pF in the off state, and a gate-to-source capacitance CGS of 280 pF in the on state. In this example, the drain-to-gate capacitance CDG varies according to the drain-to-gate voltage VDG. When VGS is below Vt, the ratio of the gate-to-source capacitance CGS to the drain-to-gate capacitance CDG is less than 1000. For example, for VDG < 50 V, CDG = 8.7 pF, for 50 V < VDG < 110 V, CDG =  0.45 pF, and for 110 V < VDG, CDG = 0.23 pF. During initial startup when VGS is below Vt, the capacitance ratio CDG / CGS allows the enhancement-mode transistor Q1 to turn on in response to the voltage rise (e.g., dV / dt) of the input voltage signal VSW.

[0035] Figure 1 The exemplary startup circuit 100 also includes a blocking circuit 126. In operation, when the potential at the second node 106 and / or the third node 124 is lower than the potential at the startup circuit output node 108, the blocking circuit 126 prevents reverse current from the startup circuit output node 108 to the second node 106 or the third node 124. Figure 1 An exemplary blocking circuit 126 includes circuit components (e.g., transistors Q7 and Q8) connected between the respective sources of transistors Q2 and Q4 and the startup circuit output node 108. In another possible embodiment, the circuit component of blocking circuit 126 may be a diode, for example, having an anode connected to the respective source of transistors Q2 and Q4 and a cathode connected to the startup circuit output node 108. In yet another embodiment, the circuit component of blocking circuit 126 may be a resistor connected between the sources of transistors Q2 and Q4 and the startup circuit output node 108, respectively. In yet another possible embodiment, blocking circuit 126 may alternatively include circuit components connected to the drains of the respective transistors Q2 and Q4, for example, having a first circuit component connected between the drain of transistor Q2 and the second node 106 and a second blocking circuit component connected between the drain of transistor Q4 and the third node 124. In these embodiments, the blocking circuit component may be a resistor, a transistor, or a diode.

[0036] In one example, voltage regulation circuit 114 turns off enhancement-mode transistor Q1 in response to the startup circuit output voltage VAUX at startup circuit output node 108 exceeding a non-zero threshold set by reference voltage signal VREF. In another possible implementation, voltage regulation circuit 114 provides a feedback loop that controls (e.g., regulates) the startup circuit output voltage VAUX. In one implementation, voltage regulation circuit 114 provides on / off control to use comparator 118 to regulate the magnitude of startup circuit output voltage VAUX. In this example, regulation circuit 114 compares startup circuit output voltage VAUX with reference voltage signal VREF, and comparator 118 generates a shutdown output signal VSD, which controls charging current IQ1 to charge capacitor CAUX. In one example, when startup circuit output voltage VAUX is less than a non-zero threshold set by voltage reference 120, voltage regulation circuit 114 generates shutdown signal VSD in a first state to allow operation of transistors Q1 and Q3 to charge capacitor CAUX. In response to the start-up circuit output voltage VAUX being equal to or exceeding a non-zero threshold set by voltage reference 120, comparator 118 generates a shutdown signal VSD in the second state, which turns off Q1 and Q3 by turning on Q5 and Q6.

[0037] In one example, the voltage feedback loop is implemented using a silicon CMOS process and includes a voltage 120 and a feedback voltage divider (not shown) that provides the input voltage signal to the non-inverting (e.g., +) input of comparator 118 as a voltage signal that is part of the startup circuit output voltage VAUX. In another example, the voltage feedback loop is implemented discretely, including discrete circuit components for a reference voltage circuit, the feedback voltage divider, and the comparator. In yet another example, the voltage feedback loop is implemented integrally, for example, using an enhancement-mode GaN process (e.g., including the following...). Figure 4 The voltage references are 120, Q15, Q16, R5, and components 406, 408, and 410.

[0038] In another embodiment, comparator 118 is replaced by an amplifier (e.g., an operational amplifier) ​​having a non-inverting (+) input connected to the startup circuit output node 108 (e.g., or connected to a voltage divider coupled to output node 108) and an inverting (-) input connected to the positive terminal of voltage reference 120. In this case, the amplifier compares the startup circuit output voltage VAUX with a non-zero threshold reference voltage signal VREF. In this example, the amplifier's output is connected to voltage-regulated output node 116, and a shutdown voltage signal VSD is provided to voltage-regulated output node 116 based on the difference between the startup circuit output voltage VAUX and the non-zero reference voltage signal VREF. In this example, for example, voltage regulation circuit 114 provides linear regulation of the startup circuit output voltage VAUX during startup operation until an external regulator ( Figure 1 (Not shown in the image) The adjustment begins by being coupled to the output node 108 of the startup circuit via a diode (e.g., below). Figure 11 The supply voltage (e.g., VDD) at the power node of the power supply.

[0039] The startup circuit 100 uses an enhancement-mode transistor Q1 to provide safe startup for a high-amplitude input voltage signal VSW by incorporating simulations of JFET or depletion-mode transistor operation. During semiconductor manufacturing processes, the use of the enhancement-mode transistor Q1 avoids the additional mask required to form an integrated depletion-mode startup transistor in the process, or the need for an additional external JFET for high-voltage startup. Due to the poor Miller ratio, the enhancement-mode transistor Q1 can turn on in response to a rising input voltage signal VSW at the drain D1 without requiring an auxiliary supply voltage. The poor Miller ratio means that the drain-to-gate charge (defined by the drain-to-gate capacitance multiplied by the drain-to-source voltage) is greater than the gate-to-source charge (defined by the gate-to-source capacitance multiplied by the gate-to-source threshold voltage required to turn on the device).

[0040] The closed-loop operation of the current limiting circuit 112 facilitates safe operation to mitigate or prevent uncontrolled high inrush currents during startup, even when the drain D1 rises to a high voltage. The exemplary startup circuit 100 provides safe startup operation for a wide range of rising input voltage VSW throughout all stages of circuit startup, including the sharp edges of insertion into the host device and operation when the input voltage signal VSW is at its peak, as well as safe startup operation for slowly rising (e.g., low-slope) input voltage signals VSW, such as when the host device is inserted, when the AC line supply voltage is 0V and only low-frequency (e.g., 50Hz or 60Hz) input voltage signal VSW slopes are available for startup. In these cases, the enhancement-mode transistor Q1 conducts a drain-source current IQ1 to start the circuit 100 (JFET or depletion-mode simulation) at an initial gate-source voltage VGS of 0V. The startup circuit 100 also turns off the enhancement-mode transistor Q1 after the startup circuit output voltage VAUX has reached a predetermined threshold using the voltage regulation circuit 114.

[0041] Figure 3 A method 300 for starting a circuit is shown. In one example, method 300 can use... Figure 1 This is achieved through a startup circuit 100, which first activates in response to a rising input voltage signal VSW to charge the capacitor CAUX in charging mode, and then shuts it off using a voltage regulation circuit 114. Afterwards, the host circuit ( Figure 1 (Not shown in the diagram) can provide individual adjustment of the startup circuit output voltage VAUX. Figure 3 At position 302, method 300 includes generating a rising voltage signal (e.g., Figure 1 The voltage VSW is applied to the drain D1 of enhancement-mode transistor Q1 to turn on enhancement-mode transistor Q1. In one example, the rising voltage VSW at the drain of enhancement-mode transistor Q1 directly turns on enhancement-mode transistor Q1. In another embodiment, the rising voltage VSW turns on the precharge transistor Q3 of the precharge circuit, and the precharge circuit 122 provides the rising gate-source voltage VGS to the second node 106. Figure 3 At 304, the pre-charge circuit 122 transfers charge to the gate of the enhancement-mode transistor Q1 and the gate capacitor C1, and the enhancement-mode transistor Q1 turns on in response to the gate voltage VGS exceeding its threshold voltage (e.g., VGS > VTH1). The enhancement-mode transistor Q1 (e.g., through the first resistor RCS) delivers a charging current IQ1 to the startup circuit output node 108 to charge the capacitor CAUX. Method 300 continues at 306, where the transistor current IQ1 is less than or equal to VTH2 / RCS (where VTH2 is VTH2 / RCS). Figure 1When the threshold voltage of transistor Q2 in the current limiting circuit is exceeded, the current limiting circuit 112 controls the gate voltage VGS of enhancement-mode transistor Q1 to limit the charging current IQ1. In response to the current IQ1 exceeding VTH2 / RCS (at the threshold voltage of transistor Q2), the current limiting circuit 112 controls the gate voltage VGS of enhancement-mode transistor Q1 to limit the charging current IQ1. Figure 3 At point 306 (yes), the current limiting circuit 112 turns off the pre-charge circuit 122 at point 308, and the current limiting circuit 112 reduces the gate voltage of the enhancement-mode transistor Q1 until the transistor current IQ1 is less than or equal to VTH2 / RCS. When the startup circuit output voltage VAUX at the startup circuit output node 108 is less than Figure 1 When the reference voltage signal VREF of reference 120 is (in) Figure 3 (310 is the case here), and the voltage regulation circuit 114 continues to operate at 304-308. In one example, controlling the gate voltage VGS at 304 includes: delivering a current-sensing voltage signal VCS to the gate of the second transistor Q2 to control the current of the second transistor Q2 according to the charging current IQ1, and controlling the gate voltage VGS of the enhancement-mode transistor Q1.

[0042] At 310, voltage regulation circuit 114 determines whether the startup circuit output voltage VAUX at startup circuit output node 108 has reached or exceeded the reference voltage signal VREF. If not (yes at 310), method 300 continues closed-loop current limiting and blocking at 304 to 308 as previously described. In response to the startup circuit output voltage VAUX at startup circuit output node 108 reaching or exceeding the reference voltage signal VREF (no at 310), voltage regulation circuit 114 turns off precharge circuit 122 and turns off enhancement-mode transistor Q1 at 312. Figure 3 At point 314, the host device can start when the startup circuit output voltage VAUX at startup circuit output node 108 is at the desired value. Once the system is powered on, the high-voltage startup circuit can be used in conjunction with alternative methods to generate an auxiliary power supply voltage.

[0043] Figure 4 A system with another exemplary startup circuit 400 is shown, wherein voltage regulation is implemented integrally, for example, using an enhanced GaN process. The exemplary startup circuit 400 includes various circuits and components, generally as described above. Figure 1 The startup circuit 100 is described. The startup circuit 400 includes nodes, components, and circuits 402, 404, 406, 408, 410, 412, 414, 422, 423, 424, and 426, which generally correspond to... Figure 1 The corresponding nodes, components and circuits are 102, 104, 106, 108, 110, 112, 114, 122, 123, 124 and 126. Figure 4The startup circuit 400 includes an enhancement-mode transistor Q1, a current limiting circuit 412, a voltage regulating circuit 414, and a pre-charge circuit 422. The enhancement-mode transistor Q1 includes a drain D1 coupled to the startup circuit input 402, a source S1 coupled to the first node 404, and a gate G1 coupled to the second node 406. Figure 4 The current limiting circuit 412 is coupled to the first node 404, the output node 408 and the second node 406 to limit the enhancement transistor current IQ1, and the voltage regulation circuit 414 is coupled to the output node 408 and the second node 406.

[0044] Figure 4 The exemplary blocking circuit 426 includes a transistor Q7 connected in series with the second transistor Q2 to mitigate the current from the output node 408 to the second node 406. Figure 4 The exemplary blocking circuit 426 also includes a transistor Q8 connected in series with the fourth transistor Q4 to mitigate current from the output node 408 to the third node 424. In this example, transistor Q7 has a drain connected to the source of the second transistor Q2, a source connected to the output node 408, and a gate connected to the second node 406. Figure 4 The transistor Q8 has a drain connected to the source of the fourth transistor Q4, a source connected to the output node 408, and a gate connected to the third node 424. Figure 4 The voltage regulation circuit 414 includes a current mirror formed by transistors Q15 and Q16, with a fifth resistor R5 connected between the output node 408 and the drain of transistor Q16. Diode DREF has an anode connected to node 404 and a cathode connected to the drain of transistor Q15, and the sources of transistors Q15 and Q16 are connected to reference node 410. A hysteresis inverter 436 receives a voltage signal from the drain of transistor Q16 and provides an inverted output voltage signal to the set (S) input of RS flip-flop 438. The reset (R) input of flip-flop 438 is controlled by an enable voltage signal EN (e.g., from the host circuit). OR gate 440 is controlled by the data (Q) output of flip-flop 438 and the enable signal EN. The output of OR gate 440 provides a turn-off signal TURN OFF to the gates of transistors Q5 and Q6.

[0045] Figure 4The system includes a regulator circuit 430 connected to power node 408 to receive and ultimately regulate the power supply voltage signal VAUX across capacitor CAUX. Input node 402 receives an input voltage signal VSW as previously described, and once initial power is established, regulator 430 operates to regulate the output voltage signal VDD according to the voltage VAUX at power node 408. The system also includes a diode DAUX having an anode connected to power node 408 and a cathode connected to a second power node. A power supply capacitor CVDD is connected between the second power node and a reference node 410. Current from power node 408 to the second power node charges the power supply capacitor CVDD to generate a second power supply voltage signal VDD at the second power node. The system also includes an undervoltage lockout circuit 432 (UVLO) that monitors the second power supply voltage signal VDD. In one example, in response to the second power supply voltage signal VDD reaching a predetermined threshold level, the lockout circuit 432 provides a status signal PWR_GD (e.g., "Power Good") at output 434. In one example, the status signal PWR_GD has a first state (e.g., at or near the voltage of reference node 410) in response to the second power supply voltage signal VDD being below a predetermined threshold level, and has a different second state (e.g., active high) in response to the second power supply voltage signal VDD being above the predetermined threshold level.

[0046] Also refer to Figure 5 and Figure 6 , Figure 4 One embodiment of the startup circuit 400 charges the capacitor CAUX to the target voltage level within an input voltage rise time ranging from 1 μs to 10 ms. This is suitable for use with Figure 4 The input voltage signal VSW is activated, and the rise time of the input voltage signal VSW is slower than the rise time of the grid frequency. Figure 5 The diagram shows an analog waveform including graph 500, which has VSW curves 501, 502, 503 and 504 for the rise time of the input voltage signal, which increases from 1 μs (curve 501) to 10 ms (curve 504), respectively. Figure 5 The graph 510 includes gate-source voltage curves 511, 512, 513 and 514, which show the enhancement-mode transistor gate-source voltage VGS with rise times from 1 μs to 10 ms corresponding to the respective VSW curves 501, 502, 503 and 504. Figure 5 The curve 520 in the figure shows the output node voltage curves 521, 522, 523 and 524 corresponding to the VSW curves 501, 502, 503 and 504 in the curve 500, with rise times from 1 μs to 10 ms.

[0047] Figure 6 Graphs 600, 610, and 620 are shown, illustrating the operation of the current limiting circuit 112 for an input voltage signal VSW (curve 601 in graph 600) with a rise time of 1 ms. Curve 611 in graph 610 shows the gate voltage VG of the enhancement-mode transistor at node 406, which initially rises rapidly via Q3 (422) due to the pre-charge circuit. The current limiting circuit 112 keeps the gate-source voltage VGS of the enhancement-mode transistor Q1 constant. Therefore, the capacitor CAUX (410) is charged with a constant current. Curve 612 shows the startup circuit output voltage VAUX, illustrating the current-limited charging of the capacitor CAUX from the drain-source current IQ1 of the enhancement-mode transistor Q1. Graph 620 includes curve 621, which shows the current-sensing voltage signal VCS across the resistor RCS, which rises rapidly and then gradually decreases during the current-limited charging operation of the startup circuit 400. When the startup circuit output voltage VAUX reaches its target level at time T1, the voltage regulation circuit 414 pulls down the second node 406 and the third node 424 to terminate the startup charging. During operation, once the voltage regulation circuit 414 detects the threshold level of the startup circuit output voltage VAUX, the external regulator circuit 430 begins to regulate the startup circuit output voltage VAUX, and the voltage regulation circuit 414 turns on the enhancement-mode transistor Q1, thereby causing the current-sensing voltage signal curve 621 (VCS) to decrease.

[0048] Figure 7 This is a schematic diagram of another exemplary startup circuit 700, which includes nodes, components, and circuits 701, 702, 704, 706, 708, 710, 712, 714, 716, 718, 720, 722, 723, 724, and 726, which generally correspond to Figure 1 The corresponding nodes, components, and circuits are 101, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 123, 124, and 126. (As shown above...) Figure 1As described in the example, the startup circuit 700 includes an enhancement-mode transistor Q1, a current-limiting circuit 712, a voltage-regulating circuit 714, a pre-charge circuit 722, and a blocking circuit 726. The startup circuit 700 additionally includes a resistor R6 (which can be implemented as a two-dimensional electron gas (2DEG) resistor) having a first terminal coupled to the drain D1 of the enhancement-mode transistor Q1 at the startup circuit input 702 and a second terminal connected to the third node 724. The inclusion of resistor R6 improves robustness by providing a quiescent current for startup, particularly for startup even under the slow switching rate and / or high leakage current of the GaN enhancement-mode transistor Q1. In one example, the 2DEG resistor R6 is sized to conduct approximately 50 μA (e.g., 10 MΩ) at saturation. In another embodiment, resistor R6 is replaced by a current source connected between the drain D1 of the enhancement-mode transistor Q1 and the third node 724 to provide a controlled current to the third node 724 and the gate of the third transistor Q3.

[0049] Figure 8 An exemplary system implemented as a multi-chip module (MCM) is shown, the exemplary system including a startup circuit 800, the startup circuit including generally corresponding to Figure 1 The corresponding nodes, components, and circuits 102, 104, 106, 108, 110, 112, 114, 122, 123, 124, and 126, and the nodes, components, and circuits 802, 804, 806, 808, 810, 812, 814, 822, 823, 824, and 826, and generally corresponding to Figure 4 The corresponding nodes, components, and circuits 430, 432, and 434 are 830, 832, and 834. The startup circuit 800 includes an enhancement-mode transistor Q1, a current-limiting circuit 812, a voltage regulation circuit 814, a pre-charge circuit 822, and a blocking circuit 826. In one embodiment, the enhancement-mode transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the first blocking transistor Q7, and the second blocking transistor Q8 are gallium nitride GaN transistors in a first GaN die 801. In this example, the voltage source (e.g., Figure 7 The 720 and comparator 718 are located in the second silicon die 830. In one example, the startup circuit 800 is implemented as a dedicated startup integrated circuit. Figure 8 The exemplary implementation does not include the above-described combination. Figure 7 The resistor R6 is described, but such a resistor can be included in different implementations. In this example, the startup circuit 800 is implemented as a first chip, and the voltage regulation circuit (e.g., Figure 7A portion of circuit 714 is implemented in silicon as a regulator chip 830 with an output pin or pad that provides a turn-off signal TURN OFF to a corresponding input pin or pad of the startup circuit 800. Furthermore, in this embodiment, the regulator circuit silicon die 830 includes an input pin or pad connected to an output node to receive, for example, the startup circuit output voltage VAUX from a corresponding output pin or pad of the startup circuit 800, which may be at the PCB level or in a package level within a multi-chip module. Figure 8 In the example, voltage regulation is performed by the regulator circuit chip 830, for example using an internal feedback voltage divider and bandgap reference for the startup circuit output voltage VAUX, to generate a turn-off signal TURN OFF via a comparator.

[0050] Also refer to Figure 9 and Figure 10 In some examples, the startup system has two high-voltage nodes. The first high-voltage node supplies power to the pre-charge circuit 122 ( Figure 1 The first high-voltage node provides input to the second high-voltage node, and the second high-voltage node provides input to the enhancement-mode transistor Q1. In various embodiments, the high-voltage node can be connected to a static high-voltage supply voltage (e.g., VIN) or to a switching node (e.g., VSW). In an exemplary startup circuit with a pre-charge circuit (e.g., circuit 122 above), there are four possible configurations. Figure 9 An exemplary system is shown, comprising a startup circuit 900, which includes nodes, components, and circuits 901, 902, 904, 906, 908, 910, 912, 914, 922, 923, 924, and 926, generally corresponding to Figure 1 The corresponding nodes, components, and circuits are 101, 102, 104, 106, 108, 110, 112, 114, 122, 123, 124, and 126. In this example, the input power supply circuit 942 is connected to a separate input node 923 of the precharge circuit 922. The drain of the precharge circuit transistor Q3 is connected to the switching node voltage signal VSW. The drain D1 of the enhancement-mode transistor Q1 is coupled to the startup circuit input 902. In one example, the startup circuit input 902 is coupled to the quiescent input voltage signal VIN (e.g., a DC input voltage). In another embodiment, the startup circuit input 902 and the drain D1 of the enhancement-mode transistor Q1 are coupled to the switching node voltage signal VSW.

[0051] Figure 10 Another exemplary system is shown, which includes a startup circuit 1000, the startup circuit including components generally corresponding to... Figure 1The corresponding nodes, components, and circuits 101, 102, 104, 106, 108, 110, 112, 114, 122, 123, and 126, and the nodes, components, and circuits 1001, 1002, 1004, 1006, 1008, 1010, 1012, 1014, 1022, 1023, and 1026, and generally corresponding to Figure 9 The corresponding nodes, components, and circuits 942 and 923 are 1042 and 1023. In this example, the precharge circuit 1022 includes a current source 1050 connected between the input power supply circuit 1042 at the precharge circuit input node 1023 and the second node 1006. In response to the applied voltage signal VIN, the current source 1050 provides a gate current at the second node 1006 to the gate G1 of the enhancement-mode transistor Q1 to turn on the transistor Q1 and thus start it up. Figure 10 The static precharge circuit shown does not require dynamic triggering of the switching node voltage VSW; instead, it can be connected to the static power node. One implementation connects both device Q1 and the precharge current source to VIN. The precharge circuit can be implemented in two ways, as follows: Figure 9 and Figure 10 As shown. In Figure 1 In the exemplary pre-charge circuit 122, the pre-charge transistor Q3 is dynamically turned on in response to the positive voltage slew rate at the drain (e.g., the rising switching node voltage VSW). Figure 9 In the example, the precharge transistor Q3 in circuit 922 turns on in response to a positive slew rate caused by the rising input voltage signal VIN from input power supply circuit 942. Figure 10 In one example, the precharge circuit 1022 includes a high-voltage precharge current source 1050 that provides static startup to turn on the enhancement transistor Q1.

[0052] Figure 11 A power conversion system 1100 according to another embodiment is shown, having a flyback DC-to-DC switching converter and the aforementioned startup circuit 100. The power conversion system 1100 includes an AC input 1101 configured to be coupled to an AC input source, in this case, the AC input source being an AC input voltage V. AC A single-phase power supply. The flyback converter includes components coupled to the startup circuit input (e.g., the above). Figure 1The switching node 1102 of the AC input 1101 is also included. The power conversion system 1100 further includes a diode bridge rectifier 1104 having a first node and a second node coupled to the AC input 1101. The diode bridge rectifier 1104 also includes a third node coupled to a ground reference node (e.g., reference node 110 mentioned above), and a power input 1106 providing a DC input voltage signal VIN across a capacitor 1108. The flyback switching converter receives the DC input voltage signal VIN and converts the input voltage into an isolated DC output voltage signal V0. OUT To drive a load (not shown). An exemplary flyback converter includes a transformer 1110 having a primary winding 1111 and a secondary winding 1112. A first terminal or node of the primary winding 1111 is coupled to an input voltage signal VIN at a power input 1106, and a second terminal or node of the primary winding 1111 is coupled to a switching node 1102. A first (e.g., low-side) converter switch 1114 (e.g., a high-voltage n-channel MOSFET or other high-voltage transistor) includes a drain coupled to the switching node 1102, a source 1116 coupled to a reference node 110 via a resistor, and a gate. The flyback converter also includes a second (e.g., high-side) converter switch 1118, which includes a source coupled to the switching node 1102, a drain coupled to the power input 1106 via a capacitor 1119, and a gate. The first converter switch 1114 and the second converter switch 1118 are controlled by pulse width modulation (PWM) switch control signals provided by the switch driver circuit 1120 to their respective gates to control the current through the primary winding 1111 of the transformer 1110.

[0053] The flyback converter includes an isolated secondary-side output circuit coupled to the secondary winding 1112 of a transformer. A secondary-side switch 1122 includes a drain coupled to the lower terminal of the secondary winding 1112, a source coupled to the lower output terminal 1128 via a resistor 1125, and a gate. A capacitor 1124 includes a first terminal coupled to the upper terminal of the secondary winding 1112 and an upper output terminal 1126. A second terminal of the capacitor 1124 is coupled to the source of the secondary-side switch 1122 and to both the output and reference. The gate of the secondary-side switch 1122 is coupled to a switching rectifier controller 1130 to regulate the output voltage across the capacitor 1124. An exemplary flyback converter also includes sensing the output voltage V at output terminals 1126 and 1128. OUT The constant current / constant voltage compensator circuit 1132. The compensator circuit 1132 provides a signal to the optocoupler circuit 1134 to provide the output voltage feedback signal FB to the primary-side controller 1140.

[0054] In one example, the primary-side controller 1140 is an active clamp feedback (ACF) controller that receives a feedback signal FB and generates a high pulse width modulation control signal PWMH and a low pulse width modulation control signal PWML to the driver 1122 to regulate the output voltage V at output terminals 1126 and 1128. OUT In this example, controller 1140 includes a regulator (e.g., the above). Figure 4 The regulators 430 and UVLO 432 in the circuit regulate the power supply voltage VDD supplied to the driver circuit 1120. Figure 11 As further shown, the startup circuit 100 is coupled to the switching node 1102 (e.g., in...). Figure 1 The startup circuit input 102 is located in the startup circuit, and the startup circuit output node 108 generates the startup circuit output voltage VAUX. The startup circuit output node 1108 is coupled to a power supply voltage terminal or node via an auctioneering diode, which provides the power supply voltage VDD to power the controller 1140 and the driver circuit 1120. The controller 1140 receives a voltage sensing signal VS from a resistor divider circuit, which is formed by a first resistor 1141 and a second resistor 1142 coupled in series between the startup circuit output node 108 and the reference node 110. In this example, the power conversion system 1100 also includes an auxiliary secondary winding 1143 of a transformer 1110, which provides power to the startup circuit output node 108 after the startup circuit 100 is turned off, so as to maintain the power supply voltage VDD during steady-state operation when the controller 1140 switches the primary side switches 1114 and 1118 during DC-DC converter operation. As described above, the enhancement transistor Q1 of the startup circuit 100 acts as a current source during startup to establish the power supply voltage VAUX for the ACF controller, and during steady-state operation of the power converter, the startup circuit 100 is disabled after the voltage VAUX is individually regulated by the regulator 430 to reduce or mitigate leakage.

[0055] The examples above are merely illustrative of several possible implementations of various aspects of this disclosure, and equivalent substitutions and / or modifications will arise in the minds of others skilled in the art upon reading and understanding this specification and the accompanying drawings. Modifications to the examples are possible within the scope of the claims, and other implementations are also possible.

Claims

1. A startup circuit, comprising: Start-up circuit input; Start-up circuit output; A first transistor, the first transistor comprising: The first current terminal coupled to the input of the starting circuit; Second current terminal; and First control terminal; A current limiting circuit, the current limiting circuit comprising: A resistor having a first terminal coupled to the second current terminal and a second terminal coupled to the output of the startup circuit, the resistor being configured to generate a current-sensing voltage signal representing the current through the first circuit path of the first transistor; and A second transistor having a third current terminal coupled to the first control terminal, a fourth current terminal coupled to the output of the startup circuit, and a second control terminal coupled to the second current terminal, wherein the second transistor is configured to discharge the first control terminal when turned on; and A voltage regulation circuit is coupled to the start-up circuit output and the first control terminal, and is configured to control the voltage of the first control terminal to regulate the start-up circuit output voltage at the start-up circuit output.

2. The startup circuit according to claim 1 further includes a pre-charging circuit, the pre-charging circuit comprising: The pre-charge circuit input is coupled to the start-up circuit input or the power supply terminal; The pre-charge circuit output is coupled to the first control terminal; as well as A third transistor or current source is coupled between the precharge circuit input and the first control terminal to provide current to the first control terminal.

3. The startup circuit according to claim 2, wherein: The pre-charge circuit includes the third transistor, which has a fifth current terminal coupled to the input of the pre-charge circuit, a sixth current terminal coupled to the output of the pre-charge circuit, and a third control terminal. The current limiting circuit includes a fourth transistor having a seventh current terminal coupled to the third control terminal, an eighth current terminal coupled to the output of the startup circuit, and a fourth control terminal coupled to the second current terminal. The fourth transistor is configured to turn on in response to the current sensing voltage signal exceeding a first threshold to stop the pre-charge circuit from charging the control terminal of the first transistor. as well as The second transistor can be configured to turn on in response to the current-sensing voltage signal exceeding a first threshold to discharge the control terminal of the first transistor.

4. The starting circuit according to claim 3 further includes a blocking circuit, the blocking circuit comprising: A first blocking transistor has a ninth current terminal coupled to the first control terminal, a tenth current terminal coupled to the output of the startup circuit, and a fifth control terminal coupled to the first control terminal. as well as The second blocking transistor has an eleventh current terminal coupled to the third control terminal, a twelfth current terminal coupled to the output of the startup circuit, and a sixth control terminal coupled to the third control terminal.

5. The starting circuit according to claim 4, wherein the voltage regulation circuit comprises: A voltage source having an output configured to provide a reference voltage signal; A comparator having: The non-inverting input coupled to the output of the startup circuit; The output of the voltage source is coupled to receive the inverted input of the reference voltage signal; as well as Output; The fifth transistor includes a seventh control terminal coupled to the output of the comparator, a thirteenth current terminal coupled to the first control terminal, and a fourteenth current terminal coupled to the reference node. as well as The sixth transistor includes an eighth control terminal coupled to the output of the comparator, a fifteenth current terminal coupled to the third control terminal, and a sixteenth current terminal coupled to the reference node.

6. The startup circuit according to claim 5, wherein: The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the first blocking transistor, and the second blocking transistor are gallium nitride transistors in the first die; and The voltage source and the comparator are located in the second die.

7. The startup circuit according to claim 4, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the first blocking transistor, and the second blocking transistor are gallium nitride transistors.

8. The startup circuit according to claim 1 further includes a blocking circuit, the blocking circuit including a blocking transistor having a fifth current terminal coupled to the first control terminal, a sixth current terminal coupled to the output of the startup circuit, and a third control terminal coupled to the first control terminal.

9. The startup circuit according to claim 1, wherein the first current terminal is the drain of the first transistor, the second current terminal is the source of the first transistor, and the control terminal is the gate of the first transistor, wherein the first transistor has a drain-to-gate capacitance and a gate-to-source capacitance, the gate-to-source capacitance being greater than the drain-to-gate capacitance, and the ratio of the gate-to-source capacitance to the drain-to-gate capacitance being less than 1000.

10. The startup circuit according to claim 9, wherein the ratio of the gate-to-source capacitance to the drain-to-gate capacitance is greater than 5.

11. A startup circuit, comprising: Start-up circuit input; Start-up circuit output; A first transistor is coupled in a first circuit path between the input of the startup circuit and the output of the startup circuit, and the first transistor includes a first current terminal, a second current terminal and a first control terminal coupled to the input of the startup circuit. A current limiting circuit is configured to control the current in the first circuit path by discharging the first control terminal in response to a current sensing voltage signal representing the current in the first circuit path exceeding a specific threshold. as well as Voltage regulation circuit, the voltage regulation circuit comprising: The comparator has: a non-inverting input coupled to the output of the startup circuit, an inverting input adapted to receive a reference voltage signal, and an output; as well as The second transistor includes a second control terminal coupled to the output of the comparator, a third current terminal coupled to the first control terminal, and a fourth current terminal coupled to the reference node.

12. The startup circuit according to claim 11, further comprising a pre-charging circuit, the pre-charging circuit comprising: The pre-charge circuit input is coupled to the start-up circuit input or the power supply terminal; The pre-charge circuit output is coupled to the first control terminal; as well as A third transistor or current source is coupled between the precharge circuit input and the first control terminal to provide current to the first control terminal.

13. The startup circuit according to claim 12, wherein: The third transistor has a fifth current terminal coupled to the input of the precharge circuit, a sixth current terminal coupled to the output of the precharge circuit, and a third control terminal. as well as The current limiting circuit includes a fourth transistor having a seventh current terminal coupled to the third control terminal, an eighth current terminal coupled to the output of the startup circuit, and a fourth control terminal coupled to the second current terminal.

14. The startup circuit of claim 13, wherein the voltage regulation circuit further comprises a fifth transistor having a fifth control terminal coupled to the output of the comparator, a ninth current terminal coupled to the third control terminal, and a tenth current terminal coupled to the reference node.

15. The startup circuit of claim 11 further includes a blocking circuit, the blocking circuit including a blocking transistor having a source coupled to the output of the startup circuit, a gate coupled to the first control terminal, and a drain coupled to the first control terminal.

16. The startup circuit of claim 11, wherein the first current terminal is the drain of the first transistor, the second current terminal is the source of the first transistor, and the control terminal is the gate of the first transistor, wherein the first transistor has a drain-to-gate capacitance and a gate-to-source capacitance, the gate-to-source capacitance being greater than the drain-to-gate capacitance, and the ratio of the gate-to-source capacitance to the drain-to-gate capacitance being less than 1000.

17. The startup circuit of claim 11, wherein the current limiting circuit comprises: A resistor having a first terminal coupled to the second current terminal and a second terminal coupled to the output of the startup circuit, so as to generate the current sensing voltage signal; as well as The sixth transistor has a drain coupled to the first control terminal, a source coupled to the output of the startup circuit, and a gate coupled to the second current terminal.

18. A power conversion system, comprising: Power input; A converter switch coupled to the switch terminal; A driver circuit having an output coupled to the control terminal of the converter switch; as well as Start-up circuit, the start-up circuit comprising: A startup circuit input, which is coupled to one of the power input and the switch terminal. A first transistor, coupled in a first circuit path between the input and output of the startup circuit, includes a first current terminal, a second current terminal, and a first control terminal coupled to the input of the startup circuit. A current limiting circuit, configured to control the current in the first circuit path by discharging the first control terminal in response to a current-sensing voltage signal representing the current in the first circuit path exceeding a specific threshold, and A voltage regulation circuit is coupled to the start-up circuit output and the first control terminal, and is configured to control the voltage of the first control terminal to regulate the start-up circuit output voltage at the start-up circuit output.

19. The power conversion system of claim 18, wherein the current limiting circuit comprises: A resistor having a first terminal coupled to the second current terminal and a second terminal coupled to the output of the startup circuit, so as to generate the current sensing voltage signal; as well as The second transistor has a third current terminal coupled to the first control terminal, a fourth current terminal coupled to the output of the startup circuit, and a second control terminal coupled to the second current terminal.

20. The power conversion system of claim 18, wherein the voltage regulation circuit comprises: A voltage source having an output configured to provide a reference voltage signal; A comparator having: The non-inverting input coupled to the output of the startup circuit; The output of the voltage source is coupled to receive the inverted input of the reference voltage signal; as well as Output; as well as The third transistor includes a third control terminal coupled to the output of the comparator, a fifth current terminal coupled to the first control terminal, and a sixth current terminal coupled to the reference node.

21. A startup circuit suitable for coupling to an input voltage power supply and operable to supply an output voltage at an output terminal, the startup circuit comprising: A first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal being adapted to be coupled to the input voltage power supply and the second current terminal being coupled to the output terminal; A pre-charge circuit having a first terminal, a second terminal, and a third terminal, the second terminal being adapted to be coupled to the input voltage power supply, and the third terminal being coupled to the first control terminal; A current limiter coupled to the precharge circuit, the first control terminal and the second current terminal, and configured to control the current in the first transistor by discharging the first control terminal in response to a current sensing voltage signal representing the current in the first transistor exceeding a specific threshold. The second transistor has a second control terminal, a third current terminal and a fourth current terminal, the third current terminal being coupled to the precharge circuit, and the second transistor being configurable to receive a control signal at the second control terminal; as well as A third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal being coupled to the first control terminal, the third transistor being configured to receive the control signal at the third control terminal.

22. The startup circuit of claim 21, wherein the startup circuit is implemented in a power converter.

23. The startup circuit of claim 21, wherein the startup circuit is implemented on a separate semiconductor substrate.

24. The startup circuit of claim 21, wherein the startup circuit is implemented on a separate GaN substrate.

25. The startup circuit of claim 21, wherein the first transistor is implemented using an enhancement-mode transistor.

26. The startup circuit of claim 21, wherein the pre-charge circuit comprises: A fourth transistor having a fourth control terminal, a seventh current terminal and an eighth current terminal, the fourth control terminal being coupled to the third current terminal and the current limiter, the seventh current terminal being coupled to the first current terminal, and the eighth current terminal being coupled to the first control terminal.

27. The startup circuit of claim 21, wherein the current limiter comprises: A resistor, the resistor being coupled between the second current terminal and the output terminal; A fifth transistor having a fifth control terminal, a ninth current terminal and a tenth current terminal, the fifth control terminal being coupled to the second current terminal and the ninth current terminal being coupled to a pre-charge circuit; as well as A sixth transistor having a sixth control terminal, an eleventh current terminal and a twelfth current terminal, the sixth control terminal being coupled to the second current terminal and the eleventh current terminal being coupled to the first control terminal.

28. The startup circuit of claim 21, wherein the capacitor is coupled between the output terminal and ground.

29. The startup circuit of claim 21, wherein the second transistor and the third transistor are included in a voltage regulation circuit.

30. A startup circuit adapted to be coupled to an input voltage power supply and operable to supply an output voltage at an output terminal, the startup circuit comprising: A first transistor having a first control terminal, a first current terminal, and a second current terminal, the first current terminal being adapted to be coupled to the input voltage power supply, and the second current terminal being coupled to the output terminal; A pre-charge circuit having a first terminal, a second terminal, and a third terminal, the second terminal being adapted to be coupled to the input voltage power supply, and the third terminal being coupled to the first control terminal; as well as A current limiter is coupled to the precharge circuit, the first control terminal, and the second current terminal, and is configured to control the current in the first circuit path by discharging the first control terminal in response to a current-sensing voltage signal representing the current in the first circuit path of the first transistor exceeding a specific threshold.

31. The startup circuit according to claim 30, comprising a voltage regulation circuit coupled to the first terminal, the first control terminal and the output terminal of the pre-charge circuit.

32. The startup circuit of claim 30, wherein the first transistor is implemented using an enhancement-mode transistor.

33. The startup circuit according to claim 31, wherein the pre-charge circuit comprises: The second transistor has a second control terminal, a third current terminal and a fourth current terminal, the second control terminal being coupled to the voltage regulation circuit and the current limiter, the third current terminal being coupled to the first current terminal, and the fourth current terminal being coupled to the first control terminal.

34. The startup circuit of claim 30, wherein the current limiter comprises: A resistor, the resistor being coupled between the second current terminal and the output terminal; A third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the third control terminal being coupled to the second current terminal and the sixth current terminal being coupled to the pre-charge circuit and the first control terminal; as well as A fourth transistor having a fourth control terminal, a seventh current terminal and an eighth current terminal, the fourth control terminal being coupled to the second current terminal and the seventh current terminal being coupled to the precharge circuit.

35. The startup circuit of claim 30, wherein the capacitor is coupled between the output terminal and ground.

36. The startup circuit of claim 31, wherein the voltage regulation circuit includes a trigger coupled to the output terminal via an inverter.

37. The startup circuit of claim 30, wherein the first transistor is fabricated on a GaN substrate.

38. The startup circuit of claim 30, wherein the pre-charge circuit includes a current source.

Images