Integrated circuit device

Abstract

An integrated circuit device includes a channel structure extending from a substrate in a vertical direction, a memory cell string disposed along the plurality of channel structures, gate lines spaced apart from each other in the vertical direction and including an erase control line and a string select line, and drive transistors including an erase control drive transistor connected to the erase control line and a string select drive transistor connected to the string select line.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0023287, filed with the Korean Intellectual Property Office on February 27, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present inventive concept generally relates to integrated circuit devices. More particularly, the present inventive concept relates to integrated circuit devices including vertical memory devices. Background art

[0004] Modern integrated circuit devices require increasingly large data storage capacities while maintaining relatively small physical sizes. This combined set of requirements demands increasingly high integration densities. Vertical memory devices provide memory cells stacked on a substrate in a vertical direction. To increase the data storage capacity of a vertical memory device, the number of stacked memory cells must be increased while maintaining efficient read, write, and / or erase operations. Summary of the invention

[0005] Embodiments of the present inventive concept provide integrated circuit devices in which the number of stacked memory cells can be increased but controlled.

[0006] According to an aspect of the present inventive concept, there is provided an integrated circuit device including: a plurality of channel structures extending from a main surface of a substrate in a vertical direction; a plurality of memory cell strings disposed along the plurality of channel structures in the vertical direction, wherein each memory cell string includes a plurality of memory cells connected in series; a plurality of gate lines spaced apart from each other in the vertical direction and including an erase control line and a string selection line; and a plurality of driving transistors including an erase control driving transistor connected to the erase control line and a string selection driving transistor connected to the string selection line, wherein at least two of the plurality of gate lines spaced apart from each other in a horizontal direction with respect to the main surface of the substrate are commonly connected to one of the plurality of driving transistors.

[0007] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a channel structure extending from a substrate in a vertical direction; bit lines respectively connected to the channel structure and extending in a first horizontal direction; a gate electrode vertically stacked on the substrate, crossing the channel structure, having a stepped pattern, and extending in a second horizontal direction above the substrate; and an erase control driving transistor and at least two string selection driving transistors. At least two of the gate electrodes respectively serve as erase control lines, at least two other of the gate electrodes respectively serve as string selection lines, the erase control lines and the string selection lines are spaced apart from each other in the first horizontal direction, the erase control lines are commonly connected to the erase control driving transistor, and each of the string selection lines is respectively connected to one of the at least two string selection driving transistors.

[0008] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a channel structure extending from a substrate in a vertical direction; a memory cell string disposed along the channel structure in the vertical direction, wherein each of the memory cell strings includes memory cells connected in series; a gate electrode spaced apart from each other in the vertical direction, crossing the channel structure, and extending in a second horizontal direction above the substrate; and driving transistors including an erase control driving transistor and a string selection driving transistor, wherein the gate electrode includes a word line, an erase control line, and a string selection line, at least two of the erase control lines are spaced apart from each other in a first horizontal direction and commonly connected to one erase control driving transistor, and at least two of the string selection lines are spaced apart from each other in the first horizontal direction and respectively connected to the at least two string selection driving transistors.

[0009] According to another aspect of the inventive concept, there is provided an integrated circuit device including: a plurality of channel structures extending from a substrate in a vertical direction with respect to a main surface of the substrate; at least two memory cell strings having a plurality of memory cells, a string selection transistor, and an erase control transistor, wherein the plurality of memory cells, the string selection transistor, and the erase control transistor are connected in series along at least two of the plurality of channel structures; and at least two erase control lines connected to the erase control transistors of each of the at least two memory cell strings and spaced apart from each other in a horizontal direction, wherein the erase control transistors of each of the at least two memory cell strings perform an erase operation through one erase control driving transistor commonly connected to the at least two erase control lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the inventive concept can be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing main components of an integrated circuit device according to an embodiment of the inventive concept;

[0012] Figure 2A is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0013] Figure 2B and Figure 2C is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0014] Figure 3A is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0015] Figure 3B is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0016] Figure 4A is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0017] Figure 4B and Figure 4C is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0018] Figure 5 、 Figure 6 and Figure 7 are corresponding equivalent circuit diagrams of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0019] Figure 8 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0020] Figure 9A 、 Figure 9B 、 Figure 9C 、 Figure 9D and Figure 9E are Figure 8 corresponding cross-sectional views of the dashed region IX of the integrated circuit device shown in;

[0021] Figure 10A is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0022] Figure 10B is a plan view showing main components of an integrated circuit device according to an embodiment of the inventive concept;

[0023] Figure 10C is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept;

[0024] Figure 11 is an equivalent circuit diagram of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0025] Figure 12 and Figure 13 are cross-sectional views of an integrated circuit device according to an embodiment of the inventive concept, respectively;

[0026] Figure 14 and Figure 15 are corresponding equivalent circuit diagrams of a memory cell array of an integrated circuit device according to an embodiment of the inventive concept;

[0027] Figure 16 、 Figure 17 and Figure 18 are corresponding cross-sectional views of an integrated circuit device according to an embodiment of the inventive concept; and

[0028] Figure 19 is a cross-sectional view of an integrated circuit device according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0029] Figure 1 is a plan view showing an integrated circuit device 1 according to an embodiment of the inventive concept. Figure 2A is an equivalent circuit diagram of a memory cell array (MCA) of an integrated circuit device 1 according to an embodiment of the inventive concept. Figure 2B and Figure 2C are cross-sectional views of an integrated circuit device 1 according to an embodiment of the inventive concept, respectively, where Figure 2B is a cross-sectional view taken along a bit line BL and Figure 2C is a cross-sectional view taken along a common connection wiring 190X for electrically connecting (hereinafter referred to as "connecting") an erase control line ECL.

[0030] Embodiments of the inventive concept generally relate to an integrated circuit including a vertically configured memory cell array MCA. Thus, Figure 1 、 Figure 2A 、 Figure 2B and Figure 2CThe integrated circuit device 1 shown is a vertical NAND (VNAND) flash memory device having a vertical channel structure. In this regard, those skilled in the art will recognize that the terms "vertical" and "horizontal" are used to describe the relative spatial orientation of the constituent components and features. For example, the main surface of the substrate can serve as a convenient geometric reference according to which various coordinate "directions" (e.g., X, Y, and Z directions) are defined, where one of these directions (e.g., the Z direction) is identified as the vertical direction, and the other directions (e.g., the X direction and the Y direction) are identified as the orthogonally related horizontal directions. However, such relative spatial orientations and general geometric relationships are merely descriptive in nature.

[0031] By using the main upper horizontal surface 110M of the main substrate 110 as a reference, as Figure 2A and Figure 2B shown, the memory cell array MCA can be understood to include a plurality of memory cell strings MS extending vertically from the substrate 110 in the vertical direction. In certain embodiments of the inventive concept, the plurality of memory cell strings MS may be respectively disposed on the substrate 110 along a plurality of vertically extending channel structures 150.

[0032] Each of the plurality of memory cell strings MS may include a series-connected arrangement of: at least one ground selection transistor GST, a plurality of memory cells MC, at least one string selection transistor SST, and at least one erase control transistor ECT. Here, each of the plurality of memory cells MC may be used to store single-bit data or multi-bit data, where word lines WL are respectively connected to the corresponding memory cells MC and may be used to at least partially control the operation of the memory cells MC.

[0033] The gate terminal of the ground selection transistor GST may be connected to the ground selection line GSL, and the source terminal of the ground selection transistor GST may be connected to the common source line CSL. The gate terminal of the string selection transistor SST may be connected to the string selection line SSL, the source terminal of the string selection transistor SST may be connected to the drain terminal of the memory cell MC, and the drain terminal of the string selection transistor SST may be connected to the bit line BL through the source terminal of the erase control transistor ECT. The gate terminal of the erase control transistor ECT may be connected to the erase control line ECL, the source terminal of the erase control transistor ECT may be connected to the drain terminal of the string selection transistor SST, and the drain terminal of the erase control transistor ECT may be connected to the common connection wiring 190X.

[0034] Considering the above examples, it should be noted that each memory cell string MS may include: a ground selection transistor GST, a string selection transistor SST, and an erase control transistor ECT. Alternatively, each memory cell string MS may include a plurality of ground selection transistors GST, a plurality of string selection transistors SST, and a plurality of erase control transistors ECT. Alternatively, each memory cell string MS may omit the ground selection transistor GST. However, these are merely examples of options, and various memory cell strings may be used in various embodiments of the present inventive concept.

[0035] When a signal is applied to the gate terminal of the string selection transistor SST through the string selection line SSL, the signal applied through the bit line BL is provided to the plurality of memory cells MC. Thus, a data write operation can be performed. When a signal is applied to the gate terminal of the erase control transistor ECT through the erase control line ECL, a gate-induced drain leakage (GIDL) current generated by the erase control transistor ECT can be used to perform an erase operation on the plurality of memory cells MC. In this regard, it should be noted that the erase operation can be performed cell block by cell block using the GIDL current.

[0036] Referring to Figure 1 , the substrate 110 can be conceptually divided into a memory cell region CR, a connection region IR, and a peripheral circuit region PR. The substrate 110 may include a semiconductor material, such as a Group IV semiconductor, a III-V compound semiconductor, or a II-VI oxide semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or Si-Ge. The substrate 110 may be provided as a bulk wafer or an epitaxial layer. In another embodiment, the substrate 110 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0037] Here, a memory cell array MCA may be provided in the memory cell region CR, and a plurality of driving transistors TR for driving the memory cell array MCA may be provided in the peripheral circuit region PR.

[0038] Assuming that the upper surface 110M of the substrate 110 is defined by a first horizontal direction (i.e., the X direction) and a second horizontal direction (i.e., the Y direction), the memory cell region CR, the connection region IR, and the peripheral circuit region may be understood to extend sequentially along the substrate 110 in the second horizontal direction. That is, the peripheral circuit region PR may be spaced apart by the intervening connection region IR in the second horizontal direction.

[0039] Referring to Figure 1 , Figure 2A , Figure 2B and Figure 2C, a plurality of gate electrodes 120 may be formed on a substrate 110, extend in a second horizontal direction, and be spaced apart from each other in a vertical direction. Here, the plurality of gate electrodes 120 may extend across the substrate 110 in the second horizontal direction and extend upward in the vertical direction in a stepped arrangement along the second horizontal direction.

[0040] In certain embodiments of the inventive concept, the plurality of gate electrodes 120 may correspond to at least one ground selection line GSL, a plurality of word lines WL, at least one string selection line SSL, and at least one erase control line ECL configured for a memory cell string MS. For example, at least one gate electrode 120a may be disposed at the bottom of a memory cell array MCA and may serve as the ground selection line GSL, at least one gate electrode 120d may be disposed at the top of the memory cell array MCA and may serve as the erase control line ECL, at least one gate electrode 120c may be disposed below at least one gate electrode 120d and may serve as the string selection line SSL, and a plurality of remaining gate electrodes 120b may serve as corresponding word lines WL.

[0041] In the foregoing examples and throughout the following description, certain geometric or spatial relative terms may be used with respect to a previously assumed descriptive relationship, such as "above", "below", "topmost", "bottommost", "upward", "downward", "above", and "beneath". For example, considering a defined vertical relationship or direction, one component may be considered above or below another component.

[0042] In the foregoing examples, among the plurality of gate electrodes 120, in order to distinguish the plurality of gate electrodes 120b serving as word lines WL from the gate electrodes 120a, 120c, and 120d serving as the ground selection line GSL, the string selection line SSL, and the erase control line ECL, the plurality of gate electrodes 120b serving as word lines WL may hereinafter be referred to as "word lines", and the gate electrodes 120a, 120c, and 120d serving as the ground selection line GSL, the string selection line SSL, and the erase control line ECL may hereinafter be referred to as "gate lines". Thus, it can be understood that the plurality of gate electrodes 120 may include a plurality of word lines and a plurality of gate lines.

[0043] The possible inclusion and the use of one or more dummy lines are also contemplated in certain embodiments of the inventive concept. For example, one or more of the plurality of gate electrodes 120 (e.g., word line 120b, string selection line SSL 120c, and / or erase control line ECL 120d) may serve as a dummy line. (See, for example, component 120e below) Figures 8 to 13 in.

[0044] In other embodiments (see, for example, with respect to below Figures 4A to 7In the described example), among the plurality of gate electrodes 120, at least one gate electrode 120d-U in the uppermost (or position) and at least one gate electrode 120d-D in the lowermost portion can be used as an upper erase control line ECL-U and a lower erase control line ECL-D. Alternatively, in other embodiments such as Figure 16 , Figure 17 and Figure 18 as shown, when the plurality of gate electrodes 120 include at least two stacks ST1 and ST2, at least one gate electrode 120d-U in the uppermost portion of each of the stacks ST1 and ST2 can be used as each of the erase control lines ECL-U1 and ECL-U2 of the upper erase control line. In some embodiments, at least one gate electrode 120d-D in the uppermost portion of each of the stacks ST1 and ST2 can be used as each of the erase control lines ECL-D1 and ECL-D2 of the lower erase control line.

[0045] As Figure 2B and Figure 2C shown, the insulating layer 130 can be disposed between the substrate 110 and the lowermost gate electrode 120a and between each of the plurality of gate electrodes 120. In addition, the insulating layer 130 can be disposed on the gate electrode 120d in the uppermost portion.

[0046] A plurality of word line cut regions WLC can be provided in the substrate 110 and extend in the second horizontal direction, wherein the plurality of gate electrodes 120 are disposed between adjacent word line cut regions WLC to configure a block. A pair of adjacent word line cut regions WLC can limit the width of the plurality of gate electrodes 120 in the first horizontal direction. An intermediate word line cut region WLCA can be (optionally) disposed between the pair of word line cut regions WLC in the second horizontal direction.

[0047] A plurality of common source lines 140 vertically overlapping the plurality of word line cut regions WLC can be disposed on the substrate 110 in the second horizontal direction. In addition, a plurality of intermediate common source lines 140A vertically overlapping the intermediate word line cut region WLCA can be disposed on the substrate 110 in the second horizontal direction. Insulating spacers 142 can be disposed on opposite sidewalls of each of the common source lines 140 and the intermediate common source lines 140A. For example, the insulating spacers 142 can be disposed between each of the common source lines 140 and the gate electrode 120 and between each of the intermediate common source lines 140A and the gate electrode 120. In certain embodiments of the present inventive concept, the plurality of common source lines 140 and the plurality of common source lines 140A can extend below the main surface 110M of the substrate 110M 110.

[0048] Multiple common source regions 144 may be selectively disposed in the substrate 100 below the multiple common source lines 140 in the second horizontal direction. The multiple common source regions 144 may be impurity regions doped with n-type impurities at a high density. The multiple common source regions 144 may be respectively used as source regions for supplying charges to memory cells. The multiple common source regions 144 may overlap with the multiple word line cut regions WLC.

[0049] Each of the multiple channel structures 150 may vertically extend upward through the memory cell region CR from the main surface 110M of the substrate 110 through the multiple gate electrodes 120 in the Z direction. Here, the channel structures 150 may be spaced apart from each other at a predetermined interval in the first horizontal direction, the second direction, and / or some diagonal (e.g., a combination of the first horizontal direction and the second horizontal direction) directions. Thus, in some embodiments of the inventive concept, the multiple channel structures 150 may be arranged in a zigzag or staggered pattern.

[0050] The multiple channel structures 150 may be respectively disposed in the channel holes 150H that extend through the gate electrodes 120, the insulating layer 130, and the interlayer insulating layer 170. The gate insulating layer 152 and the channel layer 154 may be sequentially disposed on the inner walls of each of the channel holes 150H. The buried insulating layer 156 may be disposed on the channel layer 154 to fill the space in each of the channel holes 150H.

[0051] The conductive plugs 158 that contact the channel layer 154 and close the upper openings of each of the channel holes 150H may be disposed on each of the channel holes 150H. In some embodiments, the conductive plugs 158 may include a semiconductor material doped with impurities at a high concentration, and the channel layer 154 may include a semiconductor material not doped with impurities or doped with impurities at a lower density than the conductive plugs 158. In other embodiments, the buried insulating layer 156 is omitted, and the channel layer 154 may have the form of columns filling the remaining portions of each of the channel holes 150H. Although not shown, the integrated circuit device 1 may further include dummy channel structures for ensuring structural stability in the process of manufacturing the integrated circuit device 1. The dummy channel structures may have a structure similar to that of each of the multiple channel structures 150.

[0052] The gate insulating layer 152 may include a blocking dielectric layer 152a, a charge storage layer 152b, and a tunneling dielectric layer 152c that are sequentially formed from each of the plurality of gate electrodes 120 to the channel layer 154. The blocking dielectric layer 152a may include silicon oxide, silicon nitride, or a metal oxide having a dielectric constant greater than that of silicon oxide. The metal oxide may be hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination of the above oxides. The charge storage layer 152b may include polysilicon or polysilicon doped with impurities. In some embodiments, the charge storage layer 152b may be a charge trapping layer formed of silicon nitride, boron nitride, or boron silicon nitride. The tunneling dielectric layer 152c may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, or tantalum oxide.

[0053] Each of at least two gate electrodes 120c and 120d in the uppermost part may be divided into at least two lines by the string isolation insulating layer 160. For example, the string select line cutting region SLC may extend between the word line cutting region WLC and the middle word line cutting region WLCA or extend in the second horizontal direction between a pair of word line cutting regions WLC, and the string isolation insulating layer 160 may be disposed in the string select line cutting region SLC. Accordingly, the width of each of the erase control line ECL and the string select line SSL in the first horizontal direction may be less than the width of the word line WL in the first horizontal direction. The width of each of the erase control line ECL and the string select line SSL in the first horizontal direction may be less than 1 / 2 of the width of the word line WL in the first horizontal direction. For example, two physically separated (or separate) erase control lines ECL and / or two physically separated string select lines SSL may be provided with respect to the width of the word line WL in the first horizontal direction.

[0054] In some embodiments, the first width of each erase control line ECL in the first horizontal direction and the second width of each string select line SSL in the first horizontal direction may be equal. However, when the string isolation insulating layer 160 gradually shrinks and thus the string isolation insulating layer 160 extends to the substrate 110 and the width of the string isolation insulating layer 160 in the first horizontal direction gradually decreases, the width of the erase control line ECL in the first horizontal direction may be slightly greater than the width of the string select line SSL in the first horizontal direction.

[0055] In some embodiments of the inventive concept, a plurality of bit lines BL may be spaced apart from each other at uniform intervals in a second horizontal direction and may extend in a first horizontal direction. The plurality of bit lines BL may be connected to a plurality of channel structures 150. For example, the plurality of bit lines BL and the plurality of channel structures 150 may be connected through conductive studs 184 disposed on conductive plugs 158 of the plurality of channel structures 150 and upper conductive vias 188 disposed between the conductive studs 184 and the plurality of bit lines BL. In some embodiments, a pair of adjacent bit lines BL may be alternately connected through the plurality of channel structures 150, the conductive studs 184, and the upper conductive vias 188. However, the inventive concept is not limited thereto. The plurality of channel structures 150 and the plurality of bit lines BL may be connected through various methods of an arrangement method that considers the horizontal widths of the plurality of channel structures 150, each of the plurality of channel structures, and / or the horizontal widths of each of the plurality of bit lines BL.

[0056] The plurality of gate electrodes 120 and the plurality of driving transistors TR may be connected through a plurality of connection wirings 190. The plurality of gate electrodes 120 and the plurality of connection wirings 190 may be connected through lower conductive vias 182 disposed on a part of the plurality of gate electrodes 120 connected to a connection region IR and conductive studs 184 disposed between the lower conductive vias 182 and the plurality of connection wirings 190.

[0057] The plurality of driving transistors TR may be initially connected to the plurality of gate electrodes 120. The plurality of driving transistors TR and the plurality of gate electrodes 120 may be connected only through a conductive path, such as the lower conductive vias 182, the conductive studs 184, the plurality of connection wirings 190, or conductive via plugs (not shown) for connecting the plurality of connection wirings 190 to the plurality of driving transistors TR.

[0058] In the connection region IR, one end of the stepped gate electrode 120 may be referred to as a pad layer connected to the lower conductive via 182. The resulting heights of the plurality of lower conductive vias 182 formed on the pad layer of the plurality of gate electrodes 120 in a vertical direction may vary according to the relative vertical positions of the plurality of gate electrodes 120. The plurality of connection wirings 190 may extend from the pad layer of the plurality of gate electrodes 120 to the plurality of driving transistors TR.

[0059] The plurality of connection wirings 190 may include: a common connection wiring 190X, an extended connection wiring 190E, a serial connection wiring 190S, and a gate connection wiring 190W. The common connection wiring 190X and the extended connection wiring 190E may be connected to an erase control line ECL, the serial connection wiring 190S may be connected to a string select line SSL, and the gate connection wiring 190W may be connected to a word line WL or a ground select line CSL.

[0060] A plurality of driving transistors TR may include a word line driving transistor TR-W connected to a word line WL, a string selection driving transistor TR-S connected to a string selection line SSL, and an erase control driving transistor TR-E connected to an erase control line ECL.

[0061] The word line driving transistor TR-W may be connected to the word line WL through a gate connection wiring 190W. In Figure 1 the figure, for clarity of description, only a single word line driving transistor TR-W and a single gate connection wiring 190W are shown. However, the integrated circuit device 1 may include a plurality of word line driving transistors TR-W and a plurality of gate connection wirings 190W, and the plurality of word line driving transistors TR-W and the plurality of gate connection wirings 190W are respectively connected to a plurality of word lines WL disposed at different heights in the vertical direction.

[0062] The driving transistor TR may further include a ground selection driving transistor connected to a ground selection line GSL, and the plurality of connection wirings 190 may further include a ground selection connection wiring for connecting the ground selection driving transistor to the ground selection line GSL. However, since the ground selection connection wiring and the ground selection driving transistor connected to the ground selection line GSL are similar to the gate connection wiring 190W and the word line driving transistor TR-W connected to the word line WL, the ground selection connection wiring and the ground selection driving transistor will not be described or repeatedly described.

[0063] The string selection driving transistor TR-S may be connected to the string selection line SSL through a string connection wiring 190S. The integrated circuit device 1 may include a plurality of string connection wirings 190S and a plurality of string selection driving transistors TR-S, and the plurality of string connection wirings 190S and the plurality of string selection driving transistors TR-S are respectively connected to a plurality of physically separated string selection lines SSL.

[0064] The erase control driving transistor TR-E may be connected to a plurality of erase control lines ECL through a common connection wiring 190X and an extension connection wiring 190E. The common connection wiring 190X and the extension connection wiring 190E may be referred to as erase control connection wirings.

[0065] The gate connection wiring 190W, the string connection wiring 190S, and the extension connection wiring 190E may extend in a first horizontal direction and / or a second horizontal direction. However, Figure 1 the layout configurations (e.g., layout design, geometry, or shape) of the gate connection wiring 190W, the string connection wiring 190S, and the extension connection wiring 190E shown in the figure are examples.

[0066] A plurality of physically separated string select lines SSL are respectively connected to a plurality of string select drive transistors TR-S through physically separated string connection wirings 190S. At least two of the physically separated plurality of erase control lines ECL can be connected to an erase control drive transistor TR-E through an erase control connection wiring. That is, a common connection wiring 190X and an extended connection wiring 190E can be connected to each other. The common connection wiring 190X extending in a first horizontal direction (the direction in which the bit lines extend) can be connected to at least two erase control lines ECL. That is, the common connection wiring 190X extends in the first horizontal direction and connects at least two of the erase control lines ECL in the erase control connection wiring. For example, the common connection wiring 190X can extend along one end of each of the plurality of erase control lines ECL in the first horizontal direction on a connection region IR (that is, on a pad layer), and can connect the plurality of erase control lines ECL in a block.

[0067] For example, the number of string select drive transistors TR-S corresponding to the physically separated string select lines SS1 can be greater than the number of erase control drive transistors TR-G corresponding to the physically separated erase control lines ECL.

[0068] Since integrated circuit devices such as Figure 1 、 Figure 2A 、 Figure 2B and Figure 2C shown in include a plurality of string select drive transistors TR-S for individually driving a plurality of string select transistors SST, such integrated circuit devices can individually operate a plurality of memory cell strings MS. Therefore, in order to simultaneously drive at least two of the plurality of erase control transistors ECT, the integrated circuit device can include a common connection wiring 190X that connects at least two erase control lines ECL and extends in the first horizontal direction, and an extended connection wiring 190E for connecting the common connection wiring 190X to the erase control drive transistor TR-G.

[0069] With this configuration, the number of erase control connection wirings including the common connection wiring 190X and the extended connection wiring 190E can be minimized. The layout area required for the connection wiring 190 and the layout area occupied by the erase control drive transistor TR-G can be minimized. Therefore, it is possible to more easily and efficiently control the plurality of memory cells MC of the integrated circuit device 1 according to an embodiment of the inventive concept without correspondingly increasing the layout area occupied by the integrated circuit device.

[0070] Figure 3AIt is an equivalent circuit diagram of a memory cell array of an integrated circuit device 1a according to an embodiment of the inventive concept. Figure 3B It is a cross-sectional view of the integrated circuit device 1a taken along a common connection wiring 190Xa for connecting an erase control line ECL. Here, the un-described portions of the integrated circuit device 1a may be the same as those of the integrated circuit device 1 previously described with respect to Figure 1 , Figure 2A , Figure 2B and Figure 2C in terms of configuration and operation.

[0071] Referring to Figure 3A and Figure 3B , the integrated circuit device 1a may include a plurality of connection wirings 190a, where the plurality of connection wirings 190a includes a common connection wiring 190Xa, an extended connection wiring (190E in reference to Figure 1 ), a string connection wiring 190S, and a gate connection wiring 190W. The common connection wiring 190Xa and the extended connection wiring 190E may be connected to the erase control line ECL, the string connection wiring 190X may be connected to the string selection line SSL, and the gate connection wiring 190W may be connected to the word line WL or the ground selection line CSL. The common connection wiring 190Xa and the extended connection wiring 190E may be referred to as erase control connection wirings.

[0072] The common connection wiring 190Xa extending in a first horizontal direction (the direction in which the bit line BL extends, as shown in Figure 1 ) may be connected to at least two erase control lines ECL. That is, the common connection wiring 190Xa extending in the first horizontal direction may be connected to at least two erase control lines ECL among the erase control connection wirings. For example, a plurality of common connection wirings 190Xa extend in the first horizontal direction and may be connected to at least two erase control lines ECL among the plurality of erase control lines ECL in a block.

[0073] Previously, the common connection wiring 190X described with respect to Figure 1 , Figure 2A , Figure 2B and Figure 2C could be connected to a plurality of erase control lines ECL in a block. However, in Figure 3A and Figure 3B , each of at least two physically separated common connection wirings 190Xa in the first horizontal direction may be connected to at least two different erase control lines ECL among the plurality of erase control lines ECL in a block.

[0074] In addition, at least two physically separated common connection wirings 190Xa in the first horizontal direction may be respectively connected to at least two erase control driving transistors (see, for example,Figure 1 in component TR-E).

[0075] Figure 4A is an equivalent circuit diagram of a memory cell array of an integrated circuit device 2 or 2a according to an embodiment of the inventive concept. Figure 4B and Figure 4C are corresponding cross-sectional views of integrated circuit devices 2 and 2a taken along a common connection wiring 190X for connecting an upper erase control electrode ECL-U. Here, the un-described portions of integrated circuit devices 2 and 2a may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 3B (including Figure 1 and Figure 3B ).

[0076] Referring to Figure 4A , Figure 4B and Figure 4C , each of the integrated circuit devices 2 and 2a may include a plurality of gate electrodes 120. Each of the plurality of memory cell strings MS may include a lower erase control transistor ECT-D, a ground selection transistor GST, a plurality of memory cells MC, a string selection transistor SST, and an upper erase control transistor ECT-U, which are connected in series with each other. In an exemplary embodiment, the plurality of gate electrodes 120 may correspond to at least one lower erase control line ECL-D, at least one ground selection line GSL, a plurality of word lines WL, at least one string selection line SSL, and at least one upper erase control line ECL-U that configure the memory cell string MS. The gate terminal of the upper erase control transistor ECT-U may be connected to the upper erase control line ECL-U, and the gate terminal of the lower erase control transistor ECT-D may be connected to the lower erase control line ECL-D. The upper erase control line ECL-U and the upper erase control transistor ECT-U may be the same as the erase control line ECL and the erase control transistor ECT described with reference to Figures 1 to 3B .

[0077] For example, at least one of the bottom-most gate electrodes 120d-D or 120d-Da serves as at least one lower erasure control line ECL-D, at least one gate electrode 120a above the at least one gate electrode 120d-D or 120d-Da serving as the at least one lower erasure control line ECL-D serves as a ground selection line GSL, at least one gate electrode 120d-U in the uppermost portion serves as an upper erasure control line ECL-U, at least one gate electrode 120c below the at least one gate electrode 120d-U serving as the upper erasure control line ECL-U in the uppermost portion serves as a string selection line SSL, and a plurality of remaining gate electrodes 120b can serve as word lines WL.

[0078] Each of at least two gate electrodes 120c and 120d-U in the uppermost portion can be divided into at least two lines in a plane by a string isolation insulating layer 160. For example, a string selection line cutting region SLC can extend in a second horizontal direction between a word line cutting region WLC and an intermediate word line cutting region WLCA or between a pair of word line cutting regions WLC, and the string isolation insulating layer 160 can be disposed in the string selection line cutting region SLC. Accordingly, the width of each of the upper erasure control line ECL-U and the string selection line SSL in a first horizontal direction can be less than the width of the word line WL in the first horizontal direction. The width of each of the upper erasure control line ECL-U and the string selection line SSL in the first horizontal direction can be less than 1 / 2 of the width of the word line WL in the first horizontal direction. For example, two physically separated upper erasure control lines ECL-U and two physically separated string selection lines SSL can be provided within the width of one word line WL in the first horizontal direction.

[0079] Reference Figure 4B The width of at least one gate electrode 120d-D in the bottom-most portion of the integrated circuit device 2 can be the same as the width of at least two gate electrodes 120a and 120b above the at least one gate electrode 120d-D in the bottom-most portion. For example, one physically separated lower erasure control line ECL-D can be provided within the width of one word line WL in the first horizontal direction.

[0080] However, when the word line cutting region WLC and / or the intermediate word line cutting region WLCA extend toward the substrate 110 and the width of the word line cutting region WLC and / or the intermediate word line cutting region WLCA in the first horizontal direction gradually decreases and thus the word line cutting region WLC and / or the intermediate word line cutting region WLCA gradually shrinks, the width of the lower erasure control line ECL-D in the first horizontal direction can be slightly greater than the width of the word line WL in the first horizontal direction.

[0081] Reference Figure 4C, at least one gate electrode 120d-Da in the lowermost part of the integrated circuit device 2a may be divided into at least two lines in a plane. The width of the lower erasure control line ECL-D in the first horizontal direction may be smaller than the width of the word line WL in the first horizontal direction. The width of the lower erasure control line ECL-D in the first horizontal direction may be smaller than 1 / 2 of the width of the word line WL in the first horizontal direction. For example, two physically separated lower erasure control lines ECL-D may be provided within the width of one word line WL in the first horizontal direction.

[0082] Reference Figure 4A , Figure 4B and Figure 4C , the common connection wiring 190X extending in the first horizontal direction may be connected to a plurality of upper erasure control lines ECL-U in a block. A plurality of lower erasure control lines ECL-D in a block may be connected to each other. In some embodiments, a plurality of lower erasure control lines ECL-D in a block may be connected to the common connection wiring 190X for connecting a plurality of upper erasure control lines ECL-U in a block through similar connection wiring. In other embodiments, a plurality of lower erasure control lines ECL-D in a block may be connected through a conductive region formed in the substrate 100.

[0083] The number of connected upper erasure control transistors ECT-U may be equal to the number of connected lower erasure control transistors ECT-D.

[0084] For example, Figure 4B the integrated circuit device 2 shown in is connected to four physically separated upper erasure control lines ECL-U in the horizontal direction and may be connected to two physically separated lower erasure control lines ECL-D in the horizontal direction. The number of lower erasure control transistors ECT-D connected to one physically separated lower erasure control line ECL-D may be twice the number of upper erasure control transistors ECT-U connected to one physically separated upper erasure control line ECL-U.

[0085] For example, Figure 4C the integrated circuit device 2a shown in is connected to four physically separated upper erasure control lines ECL-U in the horizontal direction and may be connected to four physically separated lower erasure control lines ECL-D in the horizontal direction. The number of lower erasure control transistors ECT-D connected to one physically separated lower erasure control line ECL-D may be equal to the number of upper erasure control transistors ECT-U connected to one physically separated upper erasure control line ECL-U.

[0086] Figure 5 , Figure 6 and Figure 7It is the corresponding equivalent circuit diagram of the memory cell arrays of the integrated circuit devices 2b, 2c, and 2d according to an embodiment of the inventive concept.

[0087] Referring to Figure 5 , in the integrated circuit device 2b, the number of connected upper erase control transistors ECT-U can be greater than the number of connected lower erase control transistors ECT-D. For example, the number of connected upper erase control transistors ECT-U can be twice the number of connected lower erase control transistors ECT-D or not less than twice the number of connected lower erase control transistors ECT-D.

[0088] For example, like Figure 4A and Figure 4B the upper erase control line ECL-U of each integrated circuit device in the integrated circuit devices 2 and 2a shown in Figure 5 the upper erase control line ECL-U in one block of the integrated circuit device 2b shown in Figure 4A is physically divided into four upper erase control lines ECL-U in the horizontal direction, and the four physically separated upper erase control lines ECL-U can be connected. For example, like Figure 5 the lower erase control line ECL-D of the integrated circuit device 2 shown in Figure 4B the lower erase control line ECL-D in one block of the integrated circuit device 2b shown in Figure 5 is physically divided into two lower erase control lines ECL-D in the horizontal direction, and the two physically separated lower erase control lines ECL-D are connected, or like

[0089] Referring to Figure 6 , in the integrated circuit device 2c, the number of connected upper erase control transistors ECT-U can be less than the number of connected lower erase control transistors ECT-D. For example, the number of connected lower erase control transistors ECT-D can be twice the number of connected upper erase control transistors ECT-U or not less than twice the number of connected upper erase control transistors ECT-U.

[0090] For example, like Figure 3A and Figure 3B the upper erase control line ECL-U in the integrated circuit device 1a shown in Figure 6In a block of the integrated circuit device 2c shown, the upper erase control line ECL-U is physically divided into four upper erase control lines ECL-U in the horizontal direction, and the four physically separated upper erase control lines ECL-U can be connected in pairs.

[0091] For example, like the lower erase control line ECL-D of the integrated circuit device 2 shown in Figure 4A the lower erase control line ECL-D in a block of the integrated circuit device 2c shown in Figure 6 is physically divided into two lower erase control lines ECL-D in the horizontal direction, and the two physically separated lower erase control lines ECL-D can be connected, or like the lower erase control line ECL-D of the integrated circuit device 2a shown in Figure 4B the lower erase control line ECL-D in a block of the integrated circuit device 2c shown in Figure 6 is physically divided into four lower erase control lines ECL-D in the horizontal direction, and the four physically separated lower erase control lines ECL-D can be connected in pairs.

[0092] Referring to Figure 7 in the integrated circuit device 2d, the number of connected upper erase control transistors ECT-U can be equal to the number of connected lower erase control transistors ECT-D.

[0093] For example, like the upper erase control line ECL-U in the integrated circuit device 1a shown in Figure 3A and Figure 3B the upper erase control line ECL-U in a block of the integrated circuit device 2d shown in Figure 7 is physically divided into four upper erase control lines ECL-U in the horizontal direction, and the four physically separated upper erase control lines ECL-U can be connected in pairs.

[0094] For example, like the lower erase control line ECL-D of the integrated circuit device 2 shown in Figure 4A the lower erase control line ECL-D in a block of the integrated circuit device 2d shown in Figure 7 is physically divided into two lower erase control lines ECL-D in the horizontal direction, and the two physically separated lower erase control lines ECL-D are not connected, or like the lower erase control line ECL-D of the integrated circuit device 2a shown in Figure 4B the lower erase control line ECL-D in a block of the integrated circuit device 2d shown in Figure 7 is physically divided into four lower erase control lines ECL-D in the horizontal direction, and the four physically separated lower erase control lines ECL-D can be connected in pairs.

[0095] Figure 8 FIG. 0 is a cross-sectional view of an integrated circuit device 3 according to an embodiment of the inventive concept taken along a bit line BL. Here, un-described portions of the integrated circuit device 3 may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 7 (including Figure 1 and Figure 7 ).

[0096] Referring to Figure 8 , the integrated circuit device 3 may include a plurality of gate electrodes 120. At least one gate electrode 120a in the lowermost portion serves as a ground selection line GSL, at least one gate electrode 120d in the uppermost portion serves as an erase control line ECL, at least one gate electrode 120c below at least one gate electrode 120d serving as the erase control line ECL in the uppermost portion serves as a string selection line SSL, at least one gate electrode 120e below at least one gate electrode 120c serving as the string selection line SSL in the uppermost portion may be a dummy word line DWL, and a plurality of remaining gate electrodes 120b may serve as word lines WL.

[0097] In this regard, the dummy word line DWL may be disposed between the string selection line SSL and the word line WL to reduce electrical interference between the string selection line SSL and the word line WL. Alternatively or additionally, the dummy word line DWL may be disposed between the string selection line SSL and the erase control line ECL (e.g., the uppermost portion of the plurality of gate electrodes 120).

[0098] Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E are corresponding cross-sectional views taken along a dashed line region IX of the integrated circuit device 3 shown in Figure 8 .

[0099] Referring to Figure 9A , a channel structure 150 may be disposed in a channel hole 150H. A gate insulating layer 152 and a channel layer 154 may be sequentially disposed on an inner wall of the channel hole 150H such that a buried insulating layer 156 fills a remaining space of the channel hole 150H. A conductive plug 158 contacting the channel layer 154 and covering an entrance of the channel hole 150H may be disposed on the channel hole 150H.

[0100] The gate insulating layer 152 may include a barrier dielectric layer 152a, a charge storage layer 152b, and a tunneling dielectric layer 152c sequentially formed on the gate electrode 120 toward the channel layer 154.

[0101] The uppermost end of the gate insulating layer 152 may be disposed at the same height as the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d. The uppermost end of the gate insulating layer 152 and the uppermost end of the channel layer 154 may be disposed at the same height. The lowermost end of the conductive plug 158 may be disposed at the same height as the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d, or at a height lower than the height of the upper surface.

[0102] Reference Figure 9B , the uppermost end of the gate insulating layer 152 may be disposed at a height higher than the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d. The uppermost end of the channel layer 154 may be disposed at a height lower than the height of the uppermost end of the gate insulating layer 152. The lowermost end of the conductive plug 158 may be disposed at the same height as the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d, or at a height lower than the height of the upper surface.

[0103] Reference Figure 9C , the uppermost end of the gate insulating layer 152 may be disposed at a height higher than the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d. The lowermost end of the conductive plug 158 may be disposed at the same height as the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d, or at a height lower than the height of the upper surface.

[0104] Reference Figure 9D , the gate insulating layer 152 may include a barrier dielectric layer 152a, a charge storage layer 152b, a tunneling dielectric layer 152c, and a gate dielectric layer 152d.

[0105] The uppermost end of each of the barrier dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c may be disposed at a height between the height of the lower surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d, and the height of the upper surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120c. The gate dielectric layer 152d may face the side surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d. The thickness of the gate dielectric layer 152d facing the side surface of the uppermost one of the plurality of gate electrodes 120, i.e., the gate electrode 120d, may be less than a second width W2, where the second width W2 is the sum of the widths of the barrier dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c in the horizontal direction.

[0106] That is, among the plurality of gate electrodes 120, the first width W1, which is the thickness of the gate insulating layer 152 facing the side surface of the uppermost gate electrode 120d (e.g., the erase control line ECL), may be smaller than the second thickness W2, which is the thickness of the gate insulating layer 152 facing the side surfaces of the remaining gate electrodes 120 (e.g., the string selection line SSL, the dummy word line DWL, and the word line WL).

[0107] Reference Figure 9E , the gate insulating layer 152 may include a blocking dielectric layer 152a, a charge storage layer 152b, a tunneling dielectric layer 152c, and a gate dielectric layer 152d.

[0108] The uppermost end of each of the blocking dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c may be disposed at a height between the height of the upper surface of the word line WL in the uppermost of the plurality of gate electrodes 120 and the height of the lower surface of the dummy word line DWL. The gate dielectric layer 152d may face the side surfaces of the erase control line ECL, the string selection line SSL, and the dummy word line DWL among the plurality of gate electrodes 120. The first width W1a of the gate dielectric layer 152d in the horizontal direction may be smaller than the second width W2a, where the first width W1a is the thickness of the gate dielectric layer 152d facing the side surfaces of the erase control line ECL, the string selection line SSL, and the dummy word line DWL, and the second width W2a is the sum of the widths of the blocking dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c in the horizontal direction.

[0109] In some embodiments, the uppermost end of each of the blocking dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c may be disposed at a height between the height of the upper surface of the dummy word line DWL and the height of the lower surface of the string selection line SSL. That is, the gate dielectric layer 152d faces the side surfaces of the erase control line ECL and the string selection line SSL, and the blocking dielectric layer 152a, the charge storage layer 152b, and the tunneling dielectric layer 152c may face the side surfaces of the word line WL and the dummy word line DWL.

[0110] In Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E (hereinafter, Figures 9A to 9E (including Figure 9A and Figure 9E )) in each of the figures, one erase control line ECL, one string selection line SSL, and one dummy word line DWL are respectively shown. However, the scope of the inventive concept is not limited thereto. At least one of the erase control line ECL, the string selection line SSL, and the dummy word line DWL may include a plurality of lines. In this case, respectively in Figures 9A to 9EThe upper surface, lower surface, and side surfaces of the erase control line ECL shown in the figure can define the upper surface of the erase control line ECL in the uppermost side among the plurality of erase control lines ECL, the lower surface of the erase control line ECL in the lowermost side, and the side surfaces of the plurality of erase control lines ECL. The upper surface, lower surface, and side surfaces of the string select line SSL can define the upper surface of the string select line SSL in the uppermost side among the plurality of string select lines SSL, the lower surface of the string select line SSL in the lowermost side, and the side surfaces of the plurality of string select lines SSL, respectively. The upper surface, lower surface, and side surfaces of the dummy word line DWL can define the upper surface of the dummy word line DWL in the uppermost side among the plurality of dummy word lines DWL, the lower surface of the dummy word line DWL in the lowermost side, and the side surfaces of the plurality of dummy word lines DWL, respectively.

[0111] Figure 10A is an equivalent circuit diagram of a memory cell array of an integrated circuit device 4 according to an embodiment of the inventive concept. Figure 10B is a plan view further showing the integrated circuit device 4, and Figure 10C is a cross-sectional view of the integrated circuit device 4 taken along a second common connection wiring 190X2 for connecting the second erase control electrode ECL2. Here, the un-described part of the integrated circuit device 4 may be similar in configuration and operation to one or more integrated circuit devices previously described with respect to Figures 1 to 9E (including Figure 1 and Figure 9E ).

[0112] Referring to Figure 10A , Figure 10B and Figure 10C , the integrated circuit device 4 includes at least two erase control lines ECL, at least one string select line SSL, at least one dummy word line DWL, a plurality of word lines WL, and at least one ground select line GSL. However, the integrated circuit device 4 may include at least two string select lines SSL, and in some embodiments, the integrated circuit device 4 may include at least two dummy word lines DWL.

[0113] At least two erasure control lines ECL may be at least two of the uppermost gate electrodes 120 among the plurality of gate electrodes 120. For example, the at least two erasure control lines ECL may include a first erasure control line ECL1 and a second erasure control line ECL2. The first erasure control line ECL1 is a gate electrode 120d among the second uppermost of the plurality of gate electrodes 120, and the second erasure control line ECL2 is a gate electrode 120d among the uppermost of the plurality of gate electrodes 120. Among the plurality of gate electrodes 120, the first erasure control line ECL1 (i.e., the gate electrode 120d among the second uppermost) may extend farther from the memory cell region CR in the second horizontal direction than the second erasure control line ECL2 (i.e., the gate electrode 120d among the uppermost). That is, one end of the first erasure control line ECL1 facing the peripheral circuit region PR may extend farther outward from the memory cell region CR than one end of the second erasure control line ECL2.

[0114] The plurality of connection wirings 190 may include a first common connection wiring 190X1, a second common connection wiring 190X2, a first string connection wiring 190S1, a second string connection wiring 190S2, and a gate connection wiring 190W.

[0115] The first common connection wiring 190X1 and the second common connection wiring 190X2 may be connected to the first erasure control line ECL1 and the second erasure control line ECL2, respectively. The first string connection wiring 190S1 and the second string connection wiring 190S2 may be connected to the first string select line SSL1 and the second string select line SSL2, respectively. The gate connection wiring 190W may be connected to the word line WL or the ground select line GSL.

[0116] In Figure 10B the first string connection wiring 190S1 connected to the first string select line SSL1 is not shown. However, it will be apparent to those skilled in the art that, like the second string connection wiring 190S2, the first string connection wiring 190S1 may connect the second string select line SSL2 to the second string select driving transistor TR-S, or share the second string connection wiring 190S2 connected to the second string select line SSL2, where the second string select line SSL2 overlaps in the vertical direction and may be connected to the string select driving transistor TR-S.

[0117] The number of first erasure control transistors ECT1 connected through the first common connection wiring 190X1 may be equal to the number of second erasure control transistors ECT2 connected through the second common connection wiring 190X2. For example, the first common connection wiring 190X1 and the second common connection wiring 190X2 extend in the first horizontal direction and may be connected to a plurality of first erasure control lines ECL1 and a plurality of second erasure control lines ECL2 in one block.

[0118] The number of the first erasure control transistor ECT1 and the second erasure control transistor ECT2 that can be connected to the first common connection wiring 190X1 and the second common connection wiring 190X2 can be greater than the number of the first string selection transistor SST1 and the second string selection transistor SST2 connected through the first string selection line SSL1 and the second string selection line SSL2.

[0119] Figure 11 is an equivalent circuit diagram of a memory cell array of an integrated circuit device 4a according to an embodiment of the inventive concept. Here, the un-described part of the integrated circuit device 4a may be similar to one or more of the integrated circuit devices described previously with respect to Figures 1 to 10C (including Figure 1 and Figure 10C ).

[0120] Referring to Figure 11 , the integrated circuit device 4a includes at least two erasure control lines ECL, at least one string selection line SSL, a plurality of word lines WL, and at least one ground selection line GSL. In some embodiments, the integrated circuit device 4a may include at least two string selection lines SSL.

[0121] At least two erasure control lines ECL may be at least two of the uppermost gate electrodes 120d among the plurality of gate electrodes 120. For example, at least two erasure control lines ECL may include a first erasure control line ECL1 and a second erasure control line ECL2, the first erasure control line ECL1 being the gate electrode 120d among the second uppermost ones among the plurality of gate electrodes 120, and the second erasure control line ECL2 being the gate electrode 120d among the uppermost ones among the plurality of gate electrodes 120.

[0122] The plurality of connection wirings 190 may include a first common connection wiring 190X1a, a second common connection wiring 190X2, a first string connection wiring 190S1, a second string connection wiring 190S2, and a gate connection wiring 190W. The layout configuration of the first common connection wiring 190X1a may be similar to the layout configuration of the common connection wiring 190Xa shown in Figure 3B , and the layout configuration of the second common connection wiring 190X2 may be similar to the layout configuration of the common connection wiring 190X shown in Figure 2C .

[0123] The number of first erase control transistors ECT1 connected through the first common connection wiring 190X1a may be less than the number of second erase control transistors ECT2 connected through the second common connection wiring 190X2. For example, the first common connection wiring 190X1a extending in the first horizontal direction may be a plurality of first common connection wirings 190X1a and may be connected to at least two of the plurality of first erase control lines ECL1 in a block. The second common connection wiring 190X2 extending in the first horizontal direction may be connected to the plurality of second erase control lines ECL2 in a block.

[0124] The number of first erase control transistors ECT1 and second erase control transistors ECT2 connected through the first common connection wiring 190X1a and the second common connection wiring 190X2 may be greater than the number of first string selection transistors SST1 and second string selection transistors SST2 connected through the first string selection line SSL1 and the second string selection line SSL2.

[0125] Figure 12 FIG. is a cross-sectional view of an integrated circuit device 5 according to an embodiment of the inventive concept taken along a common connection wiring 190X for connecting an erase control electrode ECLa. Here, the un-described portions of the integrated circuit device 5 may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 11 (including Figure 1 and Figure 11 ).

[0126] Reference Figure 12 , the integrated circuit device 5 includes at least one erase control line ECLa, at least two string selection lines SSL, at least one dummy word line DWL, a plurality of word lines WL, and at least one ground selection line GSL. In some embodiments, the integrated circuit device 5 may include at least two dummy word lines DWL.

[0127] A first thickness T1 associated with the thickness of the erase control line ECLa may be greater than a second thickness T2 associated with the thickness of the string selection line SSL, a third thickness T3 associated with the thickness of the dummy word line DWL, and / or a fourth thickness T4 associated with the thickness of the gate line. In some embodiments, a fifth thickness T5 associated with the thickness of the ground selection line GSL may be greater than the second thickness T2, the third thickness T3, and / or the fourth thickness T4. In some embodiments, the first thickness T1 may be greater than or equal to the fifth thickness T5.

[0128] Figure 13 FIG. is a cross-sectional view of an integrated circuit device 6 according to an embodiment of the inventive concept. Here, the un-described portions of the integrated circuit device 6 may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 12 (includingFigure 1 and Figure 12 ) one or more similar to those described in the integrated circuit device.

[0129] Refer to Figure 13 , the integrated circuit device 6 includes at least one erase control line ECL, at least one string selection line SSL, at least two dummy word lines DWL, a plurality of word lines WL, and at least one ground selection line GSL.

[0130] The at least two dummy word lines DWL may include a first dummy word line DWL1 disposed between at least one erase control line ECL and at least one string selection line SSL, and a second dummy word line DWL2 disposed above at least one erase control line ECL. In some embodiments, the at least two dummy word lines DWL may further include a third dummy word line disposed between at least one string selection line SSL and the plurality of word lines WL.

[0131] A first thickness T1 associated with the thickness of the erase control line ECLa may be greater than a second thickness T2 associated with the thickness of the string selection line SSL, a third thickness T3 associated with the thickness of the dummy word line DWL, and / or a fourth thickness T4 associated with the thickness of the gate line. In some embodiments, a fifth thickness T5 associated with the thickness of the ground selection line GSL may be greater than the second thickness T2, the third thickness T3, and / or the fourth thickness T4. In some embodiments, the first thickness T1 may be greater than or equal to the fifth thickness T5.

[0132] Figure 14 is an equivalent circuit diagram of a memory cell array of an integrated circuit device 7 according to an embodiment of the inventive concept. Here, the un-described part of the integrated circuit device 7 may be similar to one or more of the integrated circuit devices previously described with respect to Figures 1 to 13 (including Figure 1 and Figure 13 ) one or more similar to those described in the integrated circuit device.

[0133] Refer to Figure 14 , the integrated circuit device 7 includes at least two blocks, and the at least two blocks include a first block BK1 and a second block BK2.

[0134] The plurality of connection wirings 190b may include a common connection wiring 190Xb, a string connection wiring 190S, and a gate connection wiring 190W. The common connection wiring 190Xb may connect the erase control lines ECL in different blocks (i.e., the erase control line ECL in the first block BK1 and the erase control line ECL in the second block BK2). For example, the common connection wiring 190Xb may connect the erase control transistor ECT in the first block BK1 and the erase control transistor ECT in the second block BK2.

[0135] Figure 15 is an equivalent circuit diagram of a memory cell array of an integrated circuit device 8 according to an embodiment of the inventive concept. Here, parts not described of the integrated circuit device 8 may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 14 (including Figure 1 and Figure 14 ).

[0136] Referring to Figure 15 , the integrated circuit device 8 includes at least two blocks, the two blocks including a common block BK-N and a spare block BK-S. The spare block BK-S may have at least two sub-blocks, the at least two sub-blocks including a first sub-block BK-S1 and a second sub-block BK-S2. When a defect occurs in one of a plurality of memory cell strings MS in the common block BK-N, the spare block BK-S may provide a memory cell string MS to replace the memory cell string MS having the defect.

[0137] The common connection wiring 190X of the common block BK-N may connect a plurality of erase control transistors ECT as shown in Figures 1 to 2C . On the other hand, the common connection wiring 190Xa of the spare block BK-S may be a plurality of common connection wirings 190Xa and may connect at least two of a plurality of erase control transistors ECT in the spare block BK-S. For example, one of the plurality of common connection wirings 190Xa of the spare block BK-S connects all of the erase control transistors ECT among the plurality of erase control transistors ECT in the first sub-block BK-S1, and another one of the plurality of common connection wirings 190Xa of the spare block BK-S may connect all of the erase control transistors ECT among the plurality of erase control transistors ECT in the first sub-block BK-S1.

[0138] Figure 16 , Figure 17 and Figure 18 are respective cross-sectional views of integrated circuit devices 9, 9a, and 9b according to embodiments of the inventive concept. Here, parts not described of the integrated circuit devices 9, 9a, and 9b may be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 15 (including Figure 1 and Figure 15 ).

[0139] Referring to Figure 16 , Figure 17 and Figure 18, Each of the integrated circuit devices 9, 9a, and 9b includes a plurality of stacks, and the plurality of stacks include a first stack structure ST1 in the lower part and a second stack structure ST2 in the upper part.

[0140] In each of the integrated circuit devices 9, 9a, and 9b, after a plurality of gate electrodes 120 and a plurality of channel holes 150H of the first stack structure ST1 are previously formed, a plurality of gate electrodes 120 and a plurality of channel holes 150H of the second stack structure ST2 can be formed on the first stack structure ST1. In some embodiments, the gate insulating layer 152, the channel layer 154, and the buried insulating layer 156 included in each of the plurality of channel structures 150 can be integrated in each of the plurality of channel holes 150H of the first stack structure ST1 and each of the plurality of channel holes 150H of the second stack structure ST2. In some embodiments, the gate insulating layer 152, the channel layer 154, and the buried insulating layer 156 included in each of the plurality of channel structures 150 can be respectively formed in each of the plurality of channel holes 150H of the first stack structure ST1 and each of the plurality of channel holes 150H of the second stack structure ST2.

[0141] Each of the plurality of channel holes 150H of the first stack structure ST1 and each of the plurality of channel holes 150H of the second stack structure ST2 can be gradually narrowed such that the width in the horizontal direction decreases from the upper part to the lower part. Each of the plurality of channel holes 150H has a step difference at the boundary between the first stack structure ST1 and the second stack structure ST2. For example, the width of the uppermost end of each of the plurality of channel holes 150H of the first stack structure ST1 in the horizontal direction can be greater than the width of the lowermost end of each of the plurality of channel holes 150H of the second stack structure ST2.

[0142] Reference Figure 16 , In the integrated circuit device 9, the gate insulating layer 152, the channel layer 154, and the buried insulating layer 156 included in each of the plurality of channel structures 150 of the first stack structure ST1 and each of the plurality of channel structures 150 of the second stack structure ST2 can be directly connected.

[0143] The first stack structure ST1 can have an upper erase control line ECL-U1 and an upper erase control line ECL-U2. That is, the first stack structure ST1 can have a ground selection line GSL and can not have a string selection line SSL, and the second stack structure ST2 can have a string selection line SSL and can not have a ground selection line GSL.

[0144] The number of upper erasure control lines ECL-U2 provided in the second stacked structure ST2 in the first horizontal direction may be equal to the number of string select lines SSL, and may be greater than the number of upper erasure control lines ECL-U1 of the first stacked structure ST1.

[0145] Reference Figure 17 , in the integrated circuit device 9a, the connection conductive plug 158M may be provided between the plurality of channel structures 150 of the first stacked structure ST1 and the plurality of channel structures 150 of the second stacked structure ST2. For example, the connection conductive plug 158M may include the same material as the conductive plug 158.

[0146] The first stacked structure ST1 may have an upper erasure control line ECL-U1 and a lower erasure control line ECL-D1. The second stacked structure ST2 may have an upper erasure control line ECL-U2 and a lower erasure control line ECL-D2. That is, the first stacked structure ST1 may have a ground select line GSL and may not have a string select line SSL, and the second stacked structure ST2 may have a string select line SSL and may not have a ground select line GSL.

[0147] In the integrated circuit device 9a, the number of upper erasure control lines ECL-U2 provided in the second stacked structure ST2 in the first horizontal direction may be equal to the number of string select lines SSL, and may be greater than the number of lower erasure control lines ECL-D2 of the second stacked structure ST2, the number of upper erasure control lines ECL-U1 of the first stacked structure ST1, and the number of lower erasure control lines ECL-D1 of the first stacked structure ST1. For example, the number of upper erasure control lines ECL-U2 of the second stacked structure ST2 may be twice the number of lower erasure control lines ECL-D2 of the second stacked structure ST2, the number of upper erasure control lines ECL-U1 of the first stacked structure ST1, and the number of lower erasure control lines ECL-D1 of the first stacked structure ST1. In some embodiments, the number of upper erasure control lines ECL-U2 provided in the second stacked structure ST2 in the first horizontal direction may be equal to the number of upper erasure control lines ECL-U1 of the first stacked structure ST1.

[0148] Reference Figure 18, in the integrated circuit device 9b, the number of upper erase control lines ECL-U2 arranged in the first horizontal direction of the second stack structure ST2 and the number of lower erase control lines ECL-D1 of the first stack structure ST1 can be equal to the number of string select lines SSL and can be greater than the number of lower erase control lines ECL-D2 of the second stack structure ST2 and the number of upper erase control lines ECL-U1 of the first stack structure ST1. For example, the number of upper erase control lines ECL-U2 of the second stack structure ST2 and the number of lower erase control lines ECL-D1 of the first stack structure ST1 can be twice the number of lower erase control lines ECL-D2 of the second stack structure ST2 and the number of upper erase control lines ECL-U1 of the first stack structure ST1.

[0149] In some embodiments, the number of lower erase control lines ECL-D1 arranged in the first horizontal direction of the first stack structure ST1 can be equal to the number of ground select lines GSL. In some embodiments, the number of upper erase control lines ECL-U2 arranged in the first horizontal direction of the second stack structure ST2 can be equal to the number of upper erase control lines ECL-U1 of the first stack structure ST1.

[0150] Figure 19 is a cross-sectional view of an integrated circuit device 10 according to an embodiment of the inventive concept. Here, the un-described parts of the integrated circuit device 10 can be similar in configuration and operation to one or more of the integrated circuit devices previously described with respect to Figures 1 to 18 (including Figure 1 and Figure 18 ).

[0151] Refer to Figure 19 , the integrated circuit device 10 includes a peripheral circuit region 514 formed on a substrate 502 at a first height, and a memory cell array region 512 formed on the substrate 502 at a second height higher than the first height. Here, the term "height" represents the relative height above the substrate 502 in the vertical direction, where in the illustrated example, the first height is closer to the substrate 502 than the second height.

[0152] In some embodiments, the substrate 502 can have a main surface 502M extending in a first horizontal direction and a second horizontal direction. In certain embodiments, the substrate 502 can be similar to the substrate 110 referred to in Figure 2A , Figure 2B and Figure 2C .

[0153] The peripheral circuit active area AC may be defined by an isolation layer 504 on the substrate 502. A plurality of transistors TR may be configured in the peripheral circuit region 514 of the peripheral circuit active area AC of the substrate 502. Each of the plurality of transistors TR may include a gate G, a gate dielectric layer GD, and a source / drain region SD. Both sidewalls of the gate G may be covered with an insulating spacer 106. An etch stop layer 108 may be formed on the gate G and the insulating spacer 106. The etch stop layer 108 may include an insulating material such as silicon nitride or silicon oxynitride.

[0154] A plurality of interlayer insulating layers 114A, 114B, 114C, and 114D may be sequentially stacked on the etch stop layer 108. The plurality of interlayer insulating layers 114A, 114B, 114C, and 114D may include silicon oxide and silicon oxynitride. The peripheral circuit region 514 includes a multilayer wiring structure 630 connected to a plurality of transistors TR. The multilayer wiring structure 630 may be insulated by a plurality of interlayer insulating layers 114A, 114B, 114C, and 114D.

[0155] The multilayer wiring structure 630 may include a first contact 116A, a first wiring layer 118A, a second contact 116B, a second wiring layer 118B, a third contact 116C, and a third wiring layer 118C that are sequentially stacked on the substrate 502 and connected to one another.

[0156] A semiconductor layer 520 covering the plurality of interlayer insulating layers 114A, 114B, 114C, and 114D is formed on the peripheral circuit region 514. A memory cell array region 512 is formed on the semiconductor layer 520. The memory cell array region 512 has the same structure as previously described. Figures 1 to 19 The configuration of the memory cell array area MCA of each of the integrated circuit devices 1, 1a, 2, 2a, 2b, 2c, 2d, 3, 4, 4a, 5, 6, 7, 8, 9, 9a and 9b is the same.

[0157] In the integrated circuit device 10, the memory cell array region 512 and the peripheral circuit region 514 may be connected through at least one connection plug 195, wherein the at least one connection plug 195 vertically extends upward through the filling insulating layer 172. For example, the common connection wiring 190X of the memory cell array region 512 may be connected to the peripheral circuit region 514 through at least one connection plug 195. At least one connection plug 195 may be connected to the multi-layer wiring structure 630. For example, at least one connection plug 195 may be connected to the third wiring layer 118C.

[0158] The integrated circuit device 10 has a multi-layer device structure in which a first-height semiconductor device and a second-height semiconductor device having different functions are stacked to vertically overlap at different heights. Accordingly, it is possible to prevent the density of the wiring patterns configuring the multi-layer wiring structure 630 from excessively increasing in the memory cell array region 512 and simplify the manufacturing process of the integrated circuit device. Further, by reducing the number of metal wiring layers of the stack having the multi-layer wiring structure, it is possible to reduce physical stress caused by the metal wiring and prevent the substrate from being bent.

[0159] Although the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device, comprising: a plurality of channel structures extending from a main surface of a substrate in a vertical direction; a plurality of memory cell strings disposed along the plurality of channel structures in the vertical direction, wherein each memory cell string includes a plurality of memory cells connected in series; a plurality of gate lines spaced apart from each other in the vertical direction and including an erase control line and a string select line; and a plurality of driving transistors, including an erase control driving transistor connected to the erase control line and a string select driving transistor connected to the string select line, wherein at least two gate lines of the plurality of gate lines spaced apart from each other in a horizontal direction with respect to the main surface of the substrate are commonly connected to one driving transistor of the plurality of driving transistors.

2. The integrated circuit device according to claim 1, wherein at least two erase control lines are spaced apart from each other in the horizontal direction and are commonly connected through a common connection wiring extending in the horizontal direction.

3. The integrated circuit device according to claim 2, further comprising: a plurality of bit lines, the plurality of bit lines being respectively connected to the plurality of memory cell strings, extending in the horizontal direction, and disposed at a height different from that of the common connection wiring.

4. The integrated circuit device according to claim 2, further comprising: at least two blocks, including a first block and a second block, wherein the common connection wiring commonly connects the erase control lines of the first block to the erase control lines of the second block.

5. The integrated circuit device according to claim 1, wherein the thickness of at least one of the erase control lines is greater than the thickness of at least one of the string select lines.

6. The integrated circuit device according to claim 1, further comprising: a plurality of word lines respectively connected to the plurality of memory cell strings, wherein the width of each of the plurality of word lines in the horizontal direction is at least twice the width of each of the plurality of gate lines.

7. The integrated circuit device according to claim 6, wherein each of the plurality of channel structures includes a gate insulating layer that contacts at least one of the plurality of gate lines and at least one of the plurality of word lines, and a first portion of a side surface of the gate insulating layer facing the erase control line has a thickness less than a second portion of a side surface of the gate insulating layer facing the plurality of word lines.

8. The integrated circuit device according to claim 6, wherein each of the plurality of channel structures includes a gate insulating layer that contacts at least one of the plurality of gate lines and at least one of the plurality of word lines, and a first portion of a side surface of the gate insulating layer contacting the erase control line has a thickness less than a second portion of a side surface of the gate insulating layer contacting the string select line.

9. The integrated circuit device according to claim 6, wherein each of the plurality of channel structures includes a gate insulating layer that contacts at least one of the plurality of gate lines and at least one of the plurality of word lines, and a thickness of a first portion of the side surface of the gate insulating layer that contacts the string selection line is less than a thickness of a second portion of the side surface of the gate insulating layer that contacts at least one of the plurality of word lines.

10. The integrated circuit device according to claim 6, wherein each of the plurality of channel structures includes a gate insulating layer and a channel layer disposed on the gate insulating layer, the gate insulating layer contacts at least one of the plurality of gate lines and at least one of the plurality of word lines, and a height at which an uppermost end of the channel layer is disposed is less than or equal to a height at which an uppermost end of the gate insulating layer is disposed.

11. The integrated circuit device according to claim 1, wherein at least two erase control lines spaced apart from each other in the horizontal direction are commonly connected to one erase control driving transistor, and each of at least two string selection lines spaced apart from each other in the horizontal direction is connected to one of at least two string selection driving transistors.

12. The integrated circuit device according to claim 1, wherein at least one of the erase control lines and one of the string selection lines are spaced apart from each other in the vertical direction.

13. An integrated circuit device, comprising: channel structures extending from a substrate in a vertical direction; bit lines respectively connected to the channel structures and extending in a first horizontal direction; gate electrodes vertically stacked on the substrate, crossing the channel structures, having a stepped pattern, and extending in a second horizontal direction above the substrate; and an erase control driving transistor and at least two string selection driving transistors, wherein at least two of the gate electrodes respectively serve as erase control lines, at least two other of the gate electrodes respectively serve as string selection lines, the erase control lines and the string selection lines are spaced apart from each other in the first horizontal direction, the erase control lines are commonly connected to the erase control driving transistor, and each of the string selection lines is respectively connected to one of the at least two string selection driving transistors.

14. The integrated circuit device according to claim 13, further comprising: common connection wirings extending from one end of each of at least two erase control lines in the first horizontal direction, wherein the at least two erase control lines are commonly connected through the common connection wirings.

15. The integrated circuit device according to claim 14, wherein the bit lines extend in the first horizontal direction at a height different from a height of the common connection wirings.

16. The integrated circuit device according to claim 13, wherein the gate electrodes other than the at least two gate electrodes serving as erase control lines and the at least another two gate electrodes serving as string selection lines among the gate electrodes serve as word lines, and the width in the first horizontal direction of each of the at least two erase control lines and the at least two string selection lines is less than half of the width in the first horizontal direction of each word line among the word lines.

17. An integrated circuit device, comprising: a channel structure extending from a substrate in a vertical direction; a memory cell string disposed along the channel structure in the vertical direction, wherein each memory cell string among the memory cell strings includes memory cells connected in series; gate electrodes spaced apart from each other in the vertical direction, crossing the channel structure, and extending in a second horizontal direction above the substrate; and drive transistors, including an erase control drive transistor and a string selection drive transistor, wherein the gate electrodes include word lines, erase control lines, and string selection lines, at least two of the erase control lines are spaced apart from each other in a first horizontal direction and commonly connected to one erase control drive transistor, and at least two of the string selection lines are spaced apart from each other in the first horizontal direction and respectively connected to at least two of the string selection drive transistors among the string selection drive transistors.

18. The integrated circuit device according to claim 17, wherein the width in the first horizontal direction of each word line among the word lines is at least twice the width in the first horizontal direction of each of the erase control lines and the string selection lines.

19. The integrated circuit device according to claim 17, wherein a common connection wiring commonly connects the at least two erase control lines to one erase control drive transistor.

20. The integrated circuit device according to claim 19, wherein the common connection wiring extends from a stepped end of the erase control line in the first horizontal direction.

21. An integrated circuit device, comprising: a plurality of channel structures extending from the substrate in a vertical direction with respect to a main surface of the substrate; at least two memory cell strings having a plurality of memory cells, string selection transistors, and erase control transistors, wherein the plurality of memory cells, string selection transistors, and erase control transistors are connected in series along at least two of the plurality of channel structures; and at least two erase control lines connected to the erase control transistors of each of the at least two memory cell strings and spaced apart from each other in a horizontal direction, wherein the erase control transistors of each of the at least two memory cell strings perform an erase operation through one erase control drive transistor commonly connected to the at least two erase control lines.

22. The integrated circuit device according to claim 21, further comprising: At least two string selection lines, each connected to a string selection transistor of each of the at least two memory cell strings and spaced apart from each other in the horizontal direction, wherein the string selection transistors of each of the at least two memory cell strings are driven by at least two string selection driving transistors respectively connected to the at least two string selection lines.

23. The integrated circuit device according to claim 21, wherein the erase control transistor performs an erase operation by gate-induced drain leakage (GIDL) current.

24. The integrated circuit device according to claim 21, further comprising: bit lines, connected to the at least two memory cell strings and extending in the horizontal direction, wherein the at least two erase control lines are commonly connected through a common connection wiring extending in the horizontal direction at a height different from the height of the bit lines.

25. The integrated circuit device according to claim 21, further comprising: word lines, combined with memory cells at the same height in each of the at least two memory cell strings, and the width of the word lines in the horizontal direction is at least twice the width of each of the at least two erase control lines in the horizontal direction.

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