A pacing switching circuit, a pacing switching device and an implantable cardiac pacemaker

Abstract

The present application belongs to the technical field of medical devices, and provides a pacing switching circuit, a pacing switching device, and an implantable cardiac pacemaker, which are connected to a first electrode and a second electrode through an electrocardiogram acquisition circuit to receive an electrocardiogram acquisition signal, and a switching circuit is used to connect the pacing circuit and the first electrode and the second electrode, and the switching state of the switching circuit is controlled by a switch control signal, thereby controlling the output state of the pacing pulse signal, thereby integrating the pacing circuit and the electrocardiogram acquisition circuit into the same circuit, and performing instant switching as needed, thereby solving the problems of large size, very complex circuit structure, and high power consumption of existing pacemaker circuits.

Description

Technical Field

[0001] The present application belongs to the technical field of medical devices, and in particular, relates to a pacing switching circuit, a pacing switching device and an implantable cardiac pacemaker. Background Art

[0002] Pacemakers can significantly improve the quality of life of heart patients, especially those with bradycardia, and prolong their lifespan. Since pacemakers are implantable devices that need to be implanted in the body when used, the size of the pacemaker determines the patient's basic feeling. A small size can make the patient feel more natural and comfortable. In addition to size, there is another more important indicator for implanted medical devices, which is lifespan, that is, the power consumption of the pacemaker. A pacemaker with lower power consumption has a longer lifespan and can work longer at the same energy. In this way, patients do not have to worry about the pacemaker running out of energy, and avoid the risk of re-implanting the pacemaker due to energy exhaustion, which not only saves money but also eliminates many problems caused by re-surgery.

[0003] However, existing pacemaker circuits usually set up the pacing circuit and the ECG acquisition circuit independently, which has the problems of large size, very complex circuit structure and high power consumption. Summary of the invention

[0004] The purpose of the present application is to provide a pacing switching circuit, a pacing switching device and an implantable cardiac pacemaker, aiming to solve the problems of large size, complex circuit structure and high power consumption of existing pacemaker circuits.

[0005] A first aspect of an embodiment of the present application provides a pacing switching circuit, comprising:

[0006] a first electrode;

[0007] a second electrode;

[0008] A pacing circuit, used for providing a pacing pulse signal and a switch control signal;

[0009] a switch circuit, connected to the first electrode, the second electrode and the pacing circuit, respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the output state of the pacing pulse signal according to the switch control signal; and

[0010] The ECG acquisition circuit is connected to the first electrode and the second electrode respectively, and is used to receive the ECG acquisition signals output by the first electrode and the second electrode.

[0011] Optionally, the switch circuit includes:

[0012] a first switch unit, connected to the pacing circuit and the first electrode respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the connection state between the pacing circuit and the first electrode according to the switch control signal;

[0013] The second switch unit is connected to the pacing circuit and the first electrode respectively, and is used to receive the pacing pulse signal and the switch control signal, and control the connection state between the pacing circuit and the second electrode according to the switch control signal.

[0014] Optionally, the first switching unit is a first transistor, the input end of the first transistor is connected to the pacing pulse signal output end of the pacing circuit, the control end of the first transistor is connected to the switch control signal output end of the pacing circuit, and the output end of the first transistor is connected to the first electrode.

[0015] Optionally, the second switching unit is a second transistor, the input end of the second transistor is connected to the ground end of the pacing circuit, the control end of the second transistor is connected to the switch control signal output end of the pacing circuit, and the output end of the second transistor is connected to the second electrode.

[0016] Optionally, the ECG acquisition circuit includes:

[0017] a common-mode signal following unit, connected to the first electrode and the second electrode respectively, for receiving the ECG acquisition signals output by the first electrode and the second electrode, and generating a reference voltage signal according to the ECG acquisition signals;

[0018] The common mode amplifying unit is respectively connected to the common mode signal following unit, the first electrode and the second electrode, and is used to amplify the ECG acquisition signal and perform common mode suppression processing on the ECG acquisition signal according to the reference voltage signal.

[0019] Optionally, the common-mode signal following unit includes: a first differential amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor;

[0020] The first end of the first resistor is connected to the first electrode, the first end of the second resistor is connected to the second electrode, the second end of the first resistor, the second end of the second resistor and the first end of the third resistor are connected in common, the second end of the third resistor is connected to the first input end of the first differential amplifier, the second input end of the first differential amplifier, the output end of the first differential amplifier, the first end of the fourth resistor and the first end of the fifth resistor are connected in common to form a reference voltage signal output end of the common-mode signal following unit and are connected to the common-mode amplification unit, the second end of the fifth resistor is grounded, and the second end of the fourth resistor is connected to a working power supply.

[0021] Optionally, the common-mode amplification unit includes: a second differential amplifier, a third differential amplifier, a fourth differential amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor;

[0022] The first input terminal of the second differential amplifier is connected to the first electrode, the first input terminal of the third differential amplifier is connected to the second electrode, the second input terminal of the second differential amplifier, the first end of the sixth resistor and the first end of the seventh resistor are connected in common, the second input terminal of the third differential amplifier, the second end of the seventh resistor and the first end of the eighth resistor are connected in common, the second end of the sixth resistor, the output terminal of the second differential amplifier and the first end of the tenth resistor are connected in common, the second end of the eighth resistor, the output terminal of the third differential amplifier and the first end of the ninth resistor are connected in common, the second end of the ninth resistor, the first end of the twelfth resistor and the first input terminal of the fourth differential amplifier are connected in common, the second end of the twelfth resistor is connected to the common-mode signal following unit, the second end of the tenth resistor, the first end of the eleventh resistor and the second input terminal of the fourth differential amplifier are connected in common, and the second end of the eleventh resistor is connected in common with the output terminal of the fourth differential amplifier to form the output terminal of the common-mode amplification unit.

[0023] Optionally, the pacing switching circuit further includes:

[0024] A control circuit, connected to the pacing circuit and the ECG acquisition circuit respectively, for receiving the ECG acquisition signal and sending a control signal to the pacing circuit according to the ECG acquisition signal;

[0025] Wherein, the pacing circuit generates the pacing pulse signal and the switch control signal according to the control signal.

[0026] A second aspect of an embodiment of the present application further provides a pacing switching device, comprising a pacing switching circuit as described in any one of the above items.

[0027] A third aspect of the embodiments of the present application also provides an implantable cardiac pacemaker, comprising a pacing switching circuit as described in any one of the above items.

[0028] In the pacing switching circuit, pacing switching device and implantable cardiac pacemaker provided in the embodiments of the present application, an ECG acquisition circuit is connected to the first electrode and the second electrode to receive an ECG acquisition signal, and a switching circuit is used to connect the pacing circuit and the first electrode and the second electrode. The switching state of the switching circuit is controlled by a switch control signal, thereby controlling the output state of the pacing pulse signal, thereby integrating the pacing circuit and the ECG acquisition circuit into the same circuit, and performing instant switching as needed, thereby solving the problems of large size, complex circuit structure and high power consumption of existing pacemaker circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of a pacing switching circuit provided in one embodiment of the present application;

[0030] Figure 2 A schematic diagram of the structure of a pacing switching circuit provided in another embodiment of the present application;

[0031] Figure 3 A schematic diagram of the structure of an ECG acquisition circuit provided in one embodiment of the present application;

[0032] Figure 4 A schematic diagram of the structure of a pacing switching circuit provided in another embodiment of the present application;

[0033] Figure 5 A schematic diagram of the structure of a pacing circuit provided for one embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0035] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0036] A first aspect of an embodiment of the present application provides a pacing switching circuit, which includes a first electrode 11, a second electrode 12, a pacing circuit 20, a switching circuit 30 and an ECG acquisition circuit 40; wherein the pacing circuit 20 is used to provide a pacing pulse signal and a switch control signal; the switching circuit 30 is respectively connected to the first electrode 11, the second electrode 12 and the pacing circuit 20, for receiving the pacing pulse signal and the switch control signal, and controlling the output state of the pacing pulse signal according to the switch control signal; the ECG acquisition circuit 40 is respectively connected to the first electrode 11 and the second electrode 12, for receiving the ECG acquisition signals output by the first electrode 11 and the second electrode 12.

[0037] In this embodiment, the first input end of the switch circuit 30 is connected to the pacing pulse signal output end of the pacing circuit 20, the second input end of the switch circuit 30 is connected to the ground end of the pacing circuit 20, the first output end of the switch circuit 30 is connected to the first electrode 11, and the second output end of the switch circuit 30 is connected to the second electrode 12, wherein the switch control signal is used to control the connection state between the first input end and the first output end, and the connection state between the second input end and the second output end. In a specific application, the grounding state of the second electrode 12 is controlled by the switch circuit 30, so that the ECG acquisition circuit 40 can introduce a differential circuit, thereby increasing its common mode rejection ratio. For example, in the non-pacing state, the second electrode 12 is disconnected from the ground end as an anode electrode, and the second output end is in a high impedance state. The preamplifier of the ECG acquisition circuit 40 can use a differential circuit, which increases the common mode rejection ratio of the ECG acquisition circuit 40. The higher the common mode rejection ratio, the stronger the 50Hz power frequency interference suppression capability, and the better the quality of the ECG waveform collected.

[0038] In one embodiment, see Figure 2 As shown, the switch circuit 30 includes a first switch unit 31 and a second switch unit 32; wherein the first switch unit 31 is connected to the pacing circuit 20 and the first electrode 11, respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the connection state between the pacing circuit 20 and the first electrode 11 according to the switch control signal; the second switch unit 32 is connected to the pacing circuit 20 and the first electrode 11, respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the connection state between the pacing circuit 20 and the second electrode 12 according to the switch control signal.

[0039] In this embodiment, the first switch unit 31 is provided between the pacing circuit 20 and the first electrode 11, and the second switch unit 32 is provided between the pacing circuit 20 and the second electrode 12. The pacing circuit 20 controls the on and off of the first switch unit 31 and the second switch unit 32 by outputting a switch control signal. For example, in the pacing state, the switch circuit 30 is turned on by sending a corresponding switch control signal, so that a pacing pulse signal is sent to the second electrode 12 through the pacing circuit 20.

[0040] Furthermore, a switch circuit 30 can be provided between the ECG acquisition circuit 40 and the first electrode 11 and the second electrode 12, and controlled by the same switch control signal, so that only one of the two switch circuits 30 is turned on at the same time, thereby avoiding the influence of the pacing pulse signal sent in the pacing state on the ECG acquisition circuit 40.

[0041] In one embodiment, see Figure 2 As shown, the first switch unit 31 is a first transistor T1, the input end of the first transistor T1 is connected to the pacing pulse signal output end of the pacing circuit 20, the control end of the first transistor T1 is connected to the switch control signal output end of the pacing circuit 20, and the output end of the first transistor T1 is connected to the first electrode 11.

[0042] In one embodiment, see Figure 2 As shown, the second switch unit 32 is a second transistor T2, the input end of the second transistor T2 is connected to the ground end of the pacing circuit 20, the control end of the second transistor T2 is connected to the switch control signal output end of the pacing circuit 20, and the output end of the second transistor T2 is connected to the second electrode 12.

[0043] In this embodiment, the pacing switching circuit includes a pacing output state and an ECG acquisition state. When the pacing switching circuit operates in the pacing output state, the first transistor T1 and the second transistor T2 are turned on, and the pacing pulse signal is output to the first electrode 11 and the second electrode 12. When the pacing switching circuit operates in the ECG acquisition state, the first transistor T1 and the second transistor T2 are turned off, and the pacing circuit 20 is disconnected from the first electrode 11 and the second electrode 12, thereby not affecting the normal operation of the ECG acquisition circuit 40.

[0044] In one embodiment, see Figure 3As shown, the ECG acquisition circuit 40 includes a common-mode signal following unit 41 and a common-mode amplifying unit 42; the common-mode signal following unit 41 is respectively connected to the first electrode 11 and the second electrode 12, and is used to receive the ECG acquisition signals output by the first electrode 11 and the second electrode 12, and generate a reference voltage signal according to the ECG acquisition signals; the common-mode amplifying unit 42 is respectively connected to the common-mode signal following unit 41, the first electrode 11 and the second electrode 12, and is used to amplify the ECG acquisition signals, and perform common-mode suppression processing on the ECG acquisition signals according to the reference voltage signal.

[0045] In this embodiment, the amplitude of the common-mode signal is reduced by the common-mode signal following unit 41, thereby improving the common-mode rejection ratio. Specifically, the common-mode signal following unit 41 generates a reference voltage signal based on the signal collected by the first electrode 11 and the second electrode 12, and superimposes the reference voltage signal on the reference signal source of the common-mode amplification unit 42. When the common-mode signal changes, the reference voltage signal also changes, thereby indirectly reducing the amplitude of the common-mode voltage.

[0046] In one embodiment, see Figure 3 As shown, the common-mode signal following unit 41 includes: a first differential amplifier U1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; the first end of the first resistor R1 is connected to the first electrode 11, the first end of the second resistor R2 is connected to the second electrode 12, the second end of the first resistor R1, the second end of the second resistor R2 and the first end of the third resistor R3 are connected in common, the second end of the third resistor R3 is connected to the first input end of the first differential amplifier U1, the second input end of the first differential amplifier U1, the output end of the first differential amplifier U1, the first end of the fourth resistor R4 and the first end of the fifth resistor R5 are connected in common to form a reference voltage signal output end of the common-mode signal following unit 41 connected to the common-mode amplification unit 42, the second end of the fifth resistor R5 is grounded, and the second end of the fourth resistor R4 is connected to the working power supply.

[0047] In this embodiment, the voltage of the input common-mode signal is between the first resistor R1 and the second resistor R2. After passing through the first differential amplifier U1, the common-mode voltage is superimposed on the reference signal source of the common-mode amplification unit 42 of the single power supply. When the common-mode signal changes, the reference voltage signal also changes, thereby indirectly reducing the amplitude of the common-mode voltage.

[0048] In one embodiment, see Figure 3As shown, the common-mode amplification unit 42 includes: a second differential amplifier U2, a third differential amplifier U3, a fourth differential amplifier U4, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12; a first input end of the second differential amplifier U2 is connected to the first electrode 11, a first input end of the third differential amplifier U3 is connected to the second electrode 12, a second input end of the second differential amplifier U2, a first end of the sixth resistor R6 and a first end of the seventh resistor R7 are connected in common, a second input end of the third differential amplifier U3, a second end of the seventh resistor R7 and a first end of the eighth resistor R8 are connected in common, and the sixth resistor R 6, the output end of the second differential amplifier U2 and the first end of the tenth resistor R10 are connected together, the second end of the eighth resistor R8, the output end of the third differential amplifier U3 and the first end of the ninth resistor R9 are connected together, the second end of the ninth resistor R9, the first end of the twelfth resistor R12 and the first input end of the fourth differential amplifier U4 are connected together, the second end of the twelfth resistor R12 is connected to the common-mode signal following unit 41, the second end of the tenth resistor R10, the first end of the eleventh resistor R11 and the second input end of the fourth differential amplifier U4 are connected together, and the second end of the eleventh resistor R11 and the output end of the fourth differential amplifier U4 are connected together to form the output end of the common-mode amplification unit 42.

[0049] In this embodiment, the reference voltage signal Vref output by the common-mode signal follower unit 41 is superimposed on the reference voltage source of the first input terminal of the fourth differential amplifier U4, so that the signal of the first input terminal of the fourth differential amplifier U4 changes with the change of the common-mode signal, thereby indirectly reducing the amplitude of the common-mode voltage.

[0050] In one embodiment, see Figure 4 As shown, the pacing switching circuit also includes: a control circuit 50, which is respectively connected to the pacing circuit 20 and the ECG acquisition circuit 40, for receiving the ECG acquisition signal and sending a control signal to the pacing circuit 20 according to the ECG acquisition signal; wherein the pacing circuit 20 generates the pacing pulse signal and the switch control signal according to the control signal.

[0051] In this embodiment, when the pacing switching circuit is in the ECG acquisition state, the control circuit 50 receives the ECG acquisition signal and analyzes the ECG acquisition signal, for example, to determine whether the ECG acquisition signal is within a preset threshold range. If not, the pacing switching circuit is in the pacing output state, by outputting the pacing signal to the pacing circuit 20 and outputting the switch control signal to the switch circuit 30, the pacing pulse signal is output to the heart through the first electrode 11 and the second electrode 12, thereby stimulating the heart to beat.

[0052] In one embodiment, Figure 5 For a schematic diagram of the circuit structure of the pacing circuit 20 provided in this embodiment, see Figure 5 As shown, the pacing circuit 20 includes: a fifth differential amplifier U5, a sixth differential amplifier U6, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and a sixteenth resistor R16; wherein, the first end of the thirteenth resistor R13 is connected to the control circuit 50, the second end of the thirteenth resistor R13, the first end of the fifteenth resistor R15 and the second input end of the fifth differential amplifier U5 are connected in common, the first input end of the fifth differential amplifier U5 is connected to the first end of the fourteenth resistor R14, the second end of the fourteenth resistor R14 is grounded, the power supply end of the fifth differential amplifier U5 is connected to the first power supply, the ground end of the fifth differential amplifier U5 is connected to the second power supply, the output end of the fifth differential amplifier U5, the second end of the fifteenth resistor R15 and the first end of the sixteenth resistor R16 are connected in common, the second end of the sixteenth resistor R16 is connected to the first input end of the sixth differential amplifier U6, and the output end of the sixth differential amplifier U6 and the second input end of the sixth differential amplifier U6 are connected in common to the switch circuit 30.

[0053] In this embodiment, when the pacing switching circuit operates in the pacing output state, the pacing circuit 20 amplifies the pacing output signal sent by the control circuit 50 and outputs a corresponding pacing pulse signal, and the control circuit 50 sends a corresponding switch control signal to control the switching circuit 30 to be turned on, thereby outputting the pacing pulse signal to the first electrode 11 and the second electrode 12 to stimulate the heart.

[0054] Furthermore, after a preset time interval, the control circuit 50 sends a corresponding switch control signal to turn off the switch circuit 30, and collects ECG signals from the heart through the ECG acquisition circuit 40. If the ECG signals are within a preset threshold range, the pacing pulse signal is stopped from being output, and the pacing switching circuit enters the ECG acquisition state.

[0055] In one embodiment, the control circuit 50 is further used to adjust the working clock frequency according to the collected ECG signal to reduce the power consumption of the control circuit. The control circuit 50 adjusts the working clock frequency according to the collected ECG signal including:

[0056] Step 1: The control circuit 50 is initialized and reduces the operating frequency to a first preset threshold frequency to enter a sleep mode.

[0057] In this embodiment, the control circuit 50 enters a main cycle process after initialization. The first step of the main cycle process is to reduce the operating frequency to a first preset threshold frequency so that the control circuit 50 enters a sleep mode.

[0058] When the ECG acquisition circuit 40 is interrupted from sampling regularly, the control circuit 50 enters the response of interrupting the reading of the ECG acquisition circuit 40. The response first wakes up the control circuit 50 to enter the working mode, then reads the ECG data and saves it in the buffer, and the sampling number is increased by one, and finally exits the loop. After the control circuit 50 is awakened, step 2 of the main loop is performed.

[0059] Step 2, determine whether the sampling period of the ECG signal is over, if not, continue to execute step 1, if yes, increase the operating frequency of the control circuit 50 to the second preset threshold frequency, and store the collected ECG data into the memory.

[0060] In this embodiment, it is mainly to determine whether the sampling period of the ECG signal is ended. If not, continue to execute step 1. If it is ended, step 21 can be executed, that is, increasing the operating frequency of the control circuit 50 to the second preset threshold frequency and storing the collected ECG data in the memory.

[0061] The memory may be a large-capacity flash (flash memory) or an SD card (secure digital card).

[0062] Step 3, judging whether the ECG signal in the acquisition period is abnormal according to the ECG data, if so, adjusting the clock frequency of the control circuit 50 to a preset high frequency, if not, adjusting the clock frequency of the control circuit 50 to a preset low frequency.

[0063] In this embodiment, the control circuit 50 can evaluate the ECG signal based on the ECG signal evaluation algorithm. If it is abnormal, a complicated ECG processing algorithm under a high-frequency clock is used. If it is normal, a simple ECG algorithm under a low-frequency clock is used.

[0064] In this embodiment, by adding a step of evaluating the quality of the ECG signal, the process of evaluating the quality of the ECG signal is run at a low clock frequency. When the quality of the ECG signal is evaluated to be normal, the ECG signal is processed using a simple ECG algorithm with a low clock frequency, and when an abnormality is found, the ECG signal is processed using a complicated ECG algorithm running at a high clock frequency, thereby reducing the operation time of the control circuit 50 and thus reducing power consumption.

[0065] Furthermore, in this embodiment, the control circuit 50 also adds a method for controlling the clock frequency, so that tasks with more calculations and storage use a high clock frequency, and tasks with more IO operations use a low clock frequency, thereby reducing power consumption by changing the clock frequency.

[0066] Furthermore, if the control circuit 50 determines that the ECG signal is abnormal, it can also drive an alarm module such as an LED light or a buzzer to send out an alarm signal.

[0067] Furthermore, if the control circuit 50 determines that the ECG signal is abnormal, it can also drive the switch circuit 30 to conduct, so as to control the pacing circuit 20 to output a pacing pulse signal.

[0068] A second aspect of an embodiment of the present application further provides a pacing switching device, comprising a pacing switching circuit as described in any one of the above items.

[0069] A third aspect of the embodiments of the present application also provides an implantable cardiac pacemaker, comprising a pacing switching circuit as described in any one of the above items.

[0070] In the pacing switching circuit, pacing switching device and implantable cardiac pacemaker provided in the embodiments of the present application, an ECG acquisition circuit is connected to the first electrode and the second electrode to receive an ECG acquisition signal, and a switching circuit is used to connect the pacing circuit and the first electrode and the second electrode. The switching state of the switching circuit is controlled by a switch control signal, thereby controlling the output state of the pacing pulse signal, thereby integrating the pacing circuit and the ECG acquisition circuit into the same circuit, and performing instant switching as needed, thereby solving the problems of large size, complex circuit structure and high power consumption of existing pacemaker circuits.

[0071] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A pacing switching circuit, characterized in that: include: a first electrode; a second electrode; A pacing circuit, used for providing a pacing pulse signal and a switch control signal; a switch circuit, connected to the first electrode, the second electrode and the pacing circuit respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the output state of the pacing pulse signal according to the switch control signal; as well as An ECG acquisition circuit, connected to the first electrode and the second electrode respectively, and used for receiving ECG acquisition signals output by the first electrode and the second electrode; The switch circuit is also used to control the grounding state of the second electrode; The electrocardiogram acquisition circuit comprises: A common-mode signal following unit, connected to the first electrode and the second electrode respectively, for receiving the ECG acquisition signals output by the first electrode and the second electrode, and generating a reference voltage signal according to the ECG acquisition signals; The common mode amplifying unit is respectively connected to the common mode signal following unit, the first electrode and the second electrode, and is used to amplify the ECG acquisition signal and perform common mode suppression processing on the ECG acquisition signal according to the reference voltage signal.

2. The pacing switching circuit according to claim 1, characterized in that: The switch circuit comprises: a first switch unit, connected to the pacing circuit and the first electrode respectively, for receiving the pacing pulse signal and the switch control signal, and controlling the connection state between the pacing circuit and the first electrode according to the switch control signal; The second switch unit is connected to the pacing circuit and the first electrode respectively, and is used to receive the pacing pulse signal and the switch control signal, and control the connection state between the pacing circuit and the second electrode according to the switch control signal.

3. The pacing switching circuit according to claim 2, characterized in that: The first switch unit is a first transistor, the input end of the first transistor is connected to the pacing pulse signal output end of the pacing circuit, the control end of the first transistor is connected to the switch control signal output end of the pacing circuit, and the output end of the first transistor is connected to the first electrode.

4. The pacing switching circuit according to claim 2, characterized in that: The second switch unit is a second transistor, the input end of the second transistor is connected to the ground end of the pacing circuit, the control end of the second transistor is connected to the switch control signal output end of the pacing circuit, and the output end of the second transistor is connected to the second electrode.

5. The pacing switching circuit according to claim 1, characterized in that: The common-mode signal following unit includes: a first differential amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The first end of the first resistor is connected to the first electrode, the first end of the second resistor is connected to the second electrode, the second end of the first resistor, the second end of the second resistor and the first end of the third resistor are connected in common, the second end of the third resistor is connected to the first input end of the first differential amplifier, the second input end of the first differential amplifier, the output end of the first differential amplifier, the first end of the fourth resistor and the first end of the fifth resistor are connected in common to form a reference voltage signal output end of the common-mode signal following unit and are connected to the common-mode amplification unit, the second end of the fifth resistor is grounded, and the second end of the fourth resistor is connected to a working power supply.

6. The pacing switching circuit according to claim 1, characterized in that: The common-mode amplification unit includes: a second differential amplifier, a third differential amplifier, a fourth differential amplifier, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor and a twelfth resistor; The first input terminal of the second differential amplifier is connected to the first electrode, the first input terminal of the third differential amplifier is connected to the second electrode, the second input terminal of the second differential amplifier, the first end of the sixth resistor and the first end of the seventh resistor are connected in common, the second input terminal of the third differential amplifier, the second end of the seventh resistor and the first end of the eighth resistor are connected in common, the second end of the sixth resistor, the output terminal of the second differential amplifier and the first end of the tenth resistor are connected in common, the second end of the eighth resistor, the output terminal of the third differential amplifier and the first end of the ninth resistor are connected in common, the second end of the ninth resistor, the first end of the twelfth resistor and the first input terminal of the fourth differential amplifier are connected in common, the second end of the twelfth resistor is connected to the common-mode signal following unit, the second end of the tenth resistor, the first end of the eleventh resistor and the second input terminal of the fourth differential amplifier are connected in common, and the second end of the eleventh resistor is connected in common with the output terminal of the fourth differential amplifier to form the output terminal of the common-mode amplification unit.

7. The pacing switching circuit according to claim 1, characterized in that: The pacing switching circuit also includes: A control circuit, connected to the pacing circuit and the ECG acquisition circuit respectively, for receiving the ECG acquisition signal and sending a control signal to the pacing circuit according to the ECG acquisition signal; Wherein, the pacing circuit generates the pacing pulse signal and the switch control signal according to the control signal.

8. A pacing switching device, characterized in that: Comprising a pacing switching circuit as described in any one of claims 1-7.

9. An implantable cardiac pacemaker, characterized in that: Comprising a pacing switching circuit as described in any one of claims 1-7.

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