A two-way handshake communication circuit and method between single-chip microcomputers

Abstract

The present invention discloses a bidirectional handshake communication circuit and method between single-chip microcomputers, comprising single-chip microcomputer A, single-chip microcomputer B, a first D flip-flop, a second D flip-flop and a third D flip-flop, wherein the single-chip microcomputer A is respectively connected to the input end of the first D flip-flop, the input end of the second D flip-flop and the input end of the third D flip-flop, the output end of the first D flip-flop, the output end of the second D flip-flop and the output end of the third D flip-flop are all connected to the single-chip microcomputer B, and the output end of the third D flip-flop is also connected to the single-chip microcomputer A; the beneficial effects of the present invention are: 1. Through the bidirectional handshake mechanism, it is ensured that the upper computer is in a waiting state when the lower computer executes the instruction, thereby avoiding communication conflicts. 2. The communication logic is optimized, and it is simple and convenient to use. 3. There is no need to monopolize the parallel port resources of the single-chip microcomputer, and the time-sharing multiplexing of the parallel port is supported. 4. It supports mounting multiple slaves, and the slaves can work synchronously without conflicting with each other.

Description

Technical Field

[0001] The invention relates to the technical field of single-chip computers, and in particular to a two-way handshake communication circuit and method between single-chip computers. Background Art

[0002] In some complex projects, two or more microcontrollers are often needed to jointly realize the target function, which requires the realization of communication function between microcontrollers. In some cases (such as when the information density of transmission is small, or the time compactness requirement is not high), the target function can be realized through conventional UART, RS232 / 485, I2C, SPI and other mature communication protocols; however, when the information density of transmission is large, the instruction execution time is long, and the system operation speed requirement is high, conventional communication protocols alone often cause communication conflicts between microcontrollers, thus failing to meet the use requirements.

[0003] Prior art, such as the single-chip full-duplex communication device and communication method with application number 201210178802.2: this solution uses only two IO ports for communication, and its principle is similar to using the IO port to simulate the conventional UART port, and communicates by outputting and receiving serial waveforms. The problem is that since it uses the IO port to simulate the conventional UART port, in order to ensure stability, its communication speed is inevitably limited. In the example of this patent, a communication cycle is about 10ms. This communication rate is sufficient for simple communication, but it is far from enough for a large number of frequent communications. In addition, this solution does not solve the problem of communication conflicts. Summary of the invention

[0004] The object of the present invention is to provide a two-way handshake communication circuit and method between single-chip microcomputers to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A bidirectional handshake communication circuit between single-chip microcomputers comprises single-chip microcomputer A, single-chip microcomputer B, a first D flip-flop, a second D flip-flop and a third D flip-flop, wherein the single-chip microcomputer A is connected to the input end of the first D flip-flop, the input end of the second D flip-flop and the input end of the third D flip-flop respectively, the output end of the first D flip-flop, the output end of the second D flip-flop and the output end of the third D flip-flop are all connected to the single-chip microcomputer B, and the output end of the third D flip-flop is also connected to the single-chip microcomputer A.

[0007] As a further technical solution of the present invention: the single chip computer A is connected to the first D flip-flop via a parallel port bus.

[0008] As a further technical solution of the present invention: the single chip microcomputer A is connected to the second D flip-flop via a parallel port bus.

[0009] As a further technical solution of the present invention: the single chip microcomputer A is connected to a third D flip-flop via a WR interface and a CS interface.

[0010] As a further technical solution of the present invention: the single chip microcomputer A is a data sending end, and the single chip microcomputer B is a data receiving end.

[0011] A two-way handshake communication method between single-chip computers, with the following specific steps: the CS chip selection signal of single-chip computer A is set low and applied to the D end of the third D flip-flop, and the single-chip computer A detects the BUSY pin. If it is 1, step 4 is executed; if it is 0, the single-chip computer A waits, and the single-chip computer A sends the address and data to the D end of the first D flip-flop through the parallel port bus, and then A sends a WR signal, and the address and data are latched to the Q end of the first D flip-flop; at the same time, the chip selection signal WR is latched to the Q end of the third D flip-flop, so that BUSY=0, if the single-chip computer B is in an idle state at this time, after querying BUSY=0, the data of the Q end of the first D flip-flop can be read, and a CLEAR pulse is sent after the reading is completed, and BUSY is reset to 1 through the SET function of the third D flip-flop, indicating that the data has been read, and then related instructions are executed according to the read data; if the single-chip computer B is in a busy state at this time, wait for it to end the busy state before executing this operation.

[0012] As a further technical solution of the present invention: in the initial state, BUSY=1, WR=1, CS=1, CLEAR=1.

[0013] Compared with the prior art, the beneficial effects of the present invention are: 1. Through the two-way handshake mechanism, it is ensured that when the lower computer executes the instruction, the upper computer is in a waiting state, thereby avoiding communication conflicts. 2. The communication logic is optimized, the logic complexity during use is greatly reduced, and it is simple and convenient to use. 3. Since WR is actually a chip select signal, this circuit does not need to monopolize the parallel port resources of the single-chip microcomputer, and supports time-sharing multiplexing of the parallel port. In addition, the function of querying whether the instruction on the B side has been executed can also be realized by relying only on the IO ports of the single-chip microcomputers A and B. However, compared with the communication method of the pure IO port, the advantages of this method are also: 4. It supports mounting multiple slaves, and the slaves can work synchronously without conflict. 5. Due to the use of a D flip-flop, the primary data can be latched, so that the entire communication process has almost no redundant waiting time, thereby improving the efficiency of data transmission. 6. The number of handshakes required is small, the logic is simple and clear, and it is easy to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the hardware connection framework of the present invention. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] See also Figure 1 Embodiment 1: A bidirectional handshake communication circuit between single-chip microcomputers, including single-chip microcomputer A, single-chip microcomputer B, a first D flip-flop, a second D flip-flop and a third D flip-flop, wherein the single-chip microcomputer A is respectively connected to the input end of the first D flip-flop, the input end of the second D flip-flop and the input end of the third D flip-flop, the output end of the first D flip-flop, the output end of the second D flip-flop and the output end of the third D flip-flop are all connected to the single-chip microcomputer B, and the output end of the third D flip-flop is also connected to the single-chip microcomputer A. Single-chip microcomputer A is connected to the first D flip-flop through a parallel port bus. Single-chip microcomputer A is connected to the second D flip-flop through a parallel port bus. Single-chip microcomputer A is connected to the third D flip-flop through a WR interface and a CS interface. Single-chip microcomputer A is a data sending end, and single-chip microcomputer B is a data receiving end. The first D flip-flop and the second D flip-flop do not have RS function, and the third D flip-flop has RS function (but the R end is pulled high, that is, the R function is never effective). WR, CS, BUSY at the single-chip microcomputer A end and CLEAR, BUSY at the single-chip microcomputer B end are ordinary IO ports.

[0017] The invention also discloses a two-way handshake communication method between single-chip computers. The circuit is adopted, and the specific steps are as follows: in the initial (idle) state, BUSY=1, WR=1, CS=1, CLEAR=1, the CS chip selection signal of single-chip computer A is set low and applied to the D end of the third D flip-flop, the single-chip computer A detects the BUSY pin, if it is 1, then execute step 4; if it is 0, then wait, the single-chip computer A sends the address and data to the D end of the first D flip-flop through the parallel port bus, and then A sends a WR signal, the address and data are latched to the Q end of the first D flip-flop; at the same time, the chip selection signal WR is latched to the Q end of the third D flip-flop, so that BUSY=0, if the single-chip computer B is in the idle state at this time, after querying BUSY=0, the data of the Q end of the first D flip-flop can be read, and a CLEAR pulse is sent after the reading is completed, and BUSY is reset to 1 through the SET function of the third D flip-flop, indicating that the data has been read, and then the relevant instructions are executed according to the read data; if the single-chip computer B is in the busy state at this time, wait for it to end the busy state before executing this operation.

[0018] in: Figure 1The BUSY signal shown in the figure is used as the input of both microcontrollers A and B. When BUSY = 0, it means that the B terminal has received the current instruction, allowing the A terminal to send the next instruction. Figure 1 After the B end shown in the figure receives the instruction, the CLEAR signal sent is only a pulse. After the pulse ends, the BUSY of the B end changes from 0 to 1, and then the B end starts to execute the instruction. Figure 1 The CLEAR shown in is equivalent to the flag that the B end takes the instruction. According to the logic, if the previous instruction has not been executed, the B end will not take the next instruction, and the A end will not continue to send instructions, thus avoiding communication conflicts.

[0019] During the entire communication process, the work of clearing the busy state of the B end is completed through the CLEAR~SD signal of the B end, and there is no need to change the level of CS. Therefore, the CS signal only needs to be set low during the entire communication process, thereby realizing the actual chip select function.

[0020] The entire communication process has a first-level cache, that is, while the B end is executing instruction 1, the Q end has prepared instruction 2, and the A end is ready to send instruction 3. The specific communication timing process is as follows:

[0021] A terminal outputs instruction 1 and sends WR → instruction 1 is latched to Q terminal, BUSY is cleared to 0 → B terminal detects BUSY = 0 signal, takes instruction 1 and sends CLEAR pulse, sets BUSY to 1 → A terminal detects BUSY = 1, outputs instruction 2 and sends WR → instruction 2 is latched to Q terminal, BUSY is cleared to 0 → B terminal is still processing instruction 1 → A terminal detects BUSY = 0, continues to wait → B terminal completes instruction 1 → B terminal takes instruction 2 and sends CLEAR pulse, sets BUSY to 1 → A terminal detects BUSY = 1, outputs instruction 3 and sends WR → instruction 3 is latched to Q terminal, BUSY is cleared to 0 → B terminal is still processing instruction 1 → A terminal detects BUSY = 0, continues to wait →......

[0022] After the A terminal sends WR, it is ready for the next instruction. The status changes of the A, B, and Q terminals are as follows:

[0023]

[0024] Embodiment 2, based on embodiment 1, the present invention supports multiple single-chip microcomputers and only requires a chip select signal.

[0025] Embodiment 3, based on the communication logic of embodiment 1, does not use the D flip-flop, but only uses the IO port of the microcontroller, and can also achieve similar functions, but this method does not support multiple slaves and cannot latch data.

[0026] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0027] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A two-way handshake communication circuit between single-chip microcomputers, comprising single-chip microcomputer A, single-chip microcomputer B, a first D flip-flop, a second D flip-flop and a third D flip-flop, characterized in that: The single-chip microcomputer A transmits the address signal and the data signal to the D1~D8 ports of the first D flip-flop and the D1~D8 ports of the second D flip-flop respectively through two parallel ports. The / WR port of the single-chip microcomputer A is also connected to the CP port of the first D flip-flop, the CP port of the second D flip-flop and the CP port of the third D flip-flop respectively. The / CS port of the single-chip microcomputer A is connected to the D port of the third D flip-flop. The first D flip-flop and the Q1~Q8 ports transmit the address signal to the parallel port bus of the single-chip microcomputer B. The second D flip-flop and the Q1~Q8 ports transmit the address signal to the parallel port bus of the single-chip microcomputer B. The / SD port of the third D flip-flop is connected to the / CLEAR port of the single-chip microcomputer B. The Q port of the third D flip-flop is connected to the / BUSY port of the single-chip microcomputer A and the / BUSY port of the single-chip microcomputer B. The single-chip microcomputer A is a data sending end, and the single-chip microcomputer B is a data receiving end.

2. A two-way handshake communication method between single-chip microcomputers, characterized in that: The circuit described in claim 1 is adopted, and the specific steps are as follows: the CS chip select signal of the single-chip microcomputer A is set low and applied to the D end of the third D flip-flop. The single-chip microcomputer A detects the BUSY pin. If it is 1, step 4 is executed; if it is 0, it waits, and the single-chip microcomputer A sends the address and data to the D end of the first D flip-flop and 2 through the parallel port bus, and then A sends a WR signal, and the address and data are latched into the Q end of the first D flip-flop and 2; at the same time, the chip select signal WR is latched to the Q end of the third D flip-flop 3, so that BUSY=0, if the single-chip microcomputer B is in an idle state at this time, after querying BUSY=0, the data of the Q end of the first D flip-flop and 2 can be read, and a CLEAR pulse is sent after the reading is completed, and BUSY is reset to 1 through the SET function of the D flip-flop 3, indicating that the data has been read, and then the relevant instructions are executed according to the read data; if the single-chip microcomputer B is in a busy state at this time, wait for it to end the busy state before performing this operation.

3. A two-way handshake communication method between single-chip computers according to claim 2, characterized in that: In the initial state, BUSY=1, WR=1, CS=1, CLEAR=1.

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