Memory and method of forming the same

Abstract

The present invention provides a memory and a method for forming the same. A first partitioned array is defined by a bit line and an insulating line, and after the bit line and the insulating line are formed, a second partitioned array corresponding to the first partitioned array is further defined by an isolation layer, so that a node contact window can be defined by combining the first partitioned array and the second partitioned array, and then a node contact structure can be filled in the node contact window in a self-aligned manner. Therefore, for the memory and the method for forming the same provided by the present invention, when preparing the node contact structure, it is not necessary to perform a patterning process on the conductive material used to form the node contact structure. Thus, the etching process in the patterning process of the hard conductive material can be omitted, which is beneficial to improving the pattern accuracy of the formed node contact structure, and polymers can also be avoided from being generated, preventing polymers from adhering to the node contact structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a memory and a method for forming the same. Background Art

[0002] A memory, such as a Dynamic Random Access Memory (DRAM), generally includes a storage capacitor and a storage transistor electrically connected to the storage capacitor. The storage capacitor is used to store charges representing stored information, and the storage transistor can be electrically connected to the storage capacitor through a node contact structure.

[0003] Among them, the preparation method of the node contact structure generally includes:

[0004] First, deposit a conductive material layer on a substrate, and form a mask layer on the conductive material layer to define a pattern of the node contact structure by using the mask layer.

[0005] Next, etch the conductive material layer using the mask layer as a mask to copy the pattern in the mask layer into the conductive material layer, thereby forming the node contact structure.

[0006] Finally, remove the mask layer, and fill an isolation portion between adjacent node contact structures to isolate adjacent node contact structures from each other.

[0007] However, it should be noted that in the above preparation method, on the one hand, the conductive material used to form the node contact structure usually has a relatively large hardness, so the etching rate of the conductive material layer is relatively low during the etching process, and a relatively large lateral etching phenomenon will also occur, which will affect the morphology of the formed node contact structure. On the other hand, when etching the conductive material layer using the mask layer as a mask, by-products such as polymers are often generated, and the by-products are easily attached to the surface of the node contact structure, which will increase the contact resistance between the formed node contact structure and the subsequently formed storage capacitor. Summary of the Invention

[0008] The purpose of the present invention is to provide a memory to improve the morphology of the node contact structure in the memory.

[0009] To solve the above technical problems, the present invention provides a memory, including:

[0010] A substrate in which at least one active region is formed;

[0011] A plurality of bit lines and a plurality of insulating lines formed on the substrate, and the bit lines and the insulating lines intersect to define a first grid array;

[0012] An isolation layer is formed on the bit line and the insulating line. The isolation layer has a second sub-grid array pattern. The pattern of the second sub-grid array of the isolation layer corresponds to the pattern of the first sub-grid array in position, and each second sub-grid in the second sub-grid array is vertically connected to each first sub-grid in the first sub-grid array to form a node contact window; and,

[0013] A node contact structure is filled in the node contact window, and the top surface of the node contact structure is higher than the top surfaces of the bit line and the insulating line.

[0014] Optionally, the top surfaces of the bit line and the insulating line are flush.

[0015] Optionally, the isolation layer includes: a first isolation portion formed on the top surface of the bit line, and a second isolation portion formed on the top surface of the insulating line; wherein, the width dimension of the first isolation portion in the direction perpendicular to the extension direction of the bit line is smaller than the width dimension of the bit line, and the width dimension of the second isolation portion in the direction perpendicular to the extension direction of the insulating line is smaller than the width dimension of the insulating line.

[0016] Optionally, the node contact structure includes a first contact portion and a second contact portion. The first contact portion is filled at the bottom of the first sub-grid, and the second contact portion is formed above the first contact portion and fills from the first sub-grid upward to the second sub-grid.

[0017] Optionally, the node contact structure further includes an intermediate conductive layer. The intermediate conductive layer covers the top surface of the first contact portion, and also covers the side walls of the first sub-grid above the first contact portion and the side walls of the second sub-grid; and, the second contact portion is filled in the space surrounded by the intermediate conductive layer so that the intermediate conductive layer covers the bottom and side walls of the second contact portion.

[0018] Optionally, the memory has a device region and a peripheral region, and at least one active region is formed in the device region, and the peripheral region is formed outside the device region; and, a transistor device, an interlayer dielectric layer, and a conductive plug are formed in the peripheral region. The interlayer dielectric layer covers the side walls and the top surface of the gate structure of the transistor device, and the conductive plug penetrates through the interlayer dielectric layer to be electrically connected to the transistor device.

[0019] Optionally, the interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer coats the sidewalls of the gate structure, and the top surface of the first interlayer dielectric layer is flush with the top surface of the bit line. The second interlayer dielectric layer covers the top surface of the first interlayer dielectric layer and the top surface of the gate structure, and the top surface of the second interlayer dielectric layer is flush with the top surface of the isolation layer.

[0020] In addition, the present invention also provides a method for forming a memory, including:

[0021] Providing a substrate in which at least one active region is formed;

[0022] Forming a bit line and an insulating line on the substrate, the bit line and the insulating line intersecting to define a first grid array;

[0023] Filling a sacrificial layer in each first grid of the first grid array;

[0024] Forming an isolation material layer on the substrate, the isolation material layer covering the bit line, the insulating line, and the sacrificial layer;

[0025] Patterning the isolation material layer to form an isolation layer having a pattern of a second grid array, the pattern of the second grid array of the isolation layer corresponding to the pattern position of the first grid array, so that the isolation layer covers the bit line and the insulating line, and each first grid in the first grid array communicates with each second grid in the second grid array up and down to form a node contact window; and,

[0026] Removing the sacrificial layer and filling a node contact structure in the node contact window, the top surface of the node contact portion not being lower than the top surfaces of the bit line and the insulating line.

[0027] Optionally, after forming the bit line and the insulating line and before filling the sacrificial layer, it further includes: forming a first contact portion at the bottom of the first grid in the first grid array to electrically connect the first contact portion to the active region.

[0028] Optionally, after removing the sacrificial layer, filling a second contact portion of the node contact structure in the node contact window, the second contact portion being filled from the first grid upward to the second grid.

[0029] Optionally, after removing the sacrificial layer and before filling the second contact portion, the method further includes: forming an intermediate conductive layer in the node contact window, the intermediate conductive layer covering the top surface of the first contact portion and also covering the sidewalls of the first partition above the first contact portion and the sidewalls of the second partition; and filling the second contact portion in the space surrounded by the intermediate conductive layer, so that the intermediate conductive layer covers the bottom and sidewalls of the second contact portion.

[0030] Optionally, the memory has a device region and a peripheral region, and the at least one active region is formed in the device region, and the peripheral region is formed outside the device region;

[0031] Wherein, when forming the bit line, the method further includes: forming a gate structure of a transistor device on the substrate in the peripheral region;

[0032] And when forming the insulating line, the method further includes: forming a first interlayer dielectric layer in the peripheral region, the first interlayer dielectric layer covering the outer sidewalls of the gate structure;

[0033] And when forming the isolation layer, the method further includes: forming a second interlayer dielectric layer in the peripheral region, the second interlayer dielectric layer covering the first interlayer dielectric layer and the gate structure.

[0034] In the memory and its forming method provided by the present invention, a first partition array is defined by using a bit line and an insulating line, and a second partition array corresponding to the first partition array is defined by using an isolation layer. Thus, a node contact window can be further defined by combining the first partition array and the second partition array. Based on this, a node contact structure can be filled in the node contact window in a self-aligned manner.

[0035] It should be recognized that since the memory provided by the present invention can form a node contact structure in a self-aligned manner without performing a patterning process on the conductive material used to form the node contact structure. In this way, the etching process in the patterning process of the harder conductive material can be omitted, which is beneficial to improving the pattern accuracy of the formed node contact structure. And since there is no need to perform a patterning process, polymers can be avoided from being generated, preventing polymers from adhering to the node contact structure. Description of the Drawings

[0036] Figure 1a It is a top view of a memory in an embodiment of the present invention, showing a first partition array of a node contact window;

[0037] Figure 1b It is a top view of a memory in an embodiment of the present invention, showing a second partition array of a node contact window;

[0038] Figure 2 The figure shows a cross-sectional view of a node contact window in a memory according to an embodiment of the present invention;

[0039] Figure 3 The figure shows a cross-sectional view of a node contact window filled with a node contact structure in a memory according to an embodiment of the present invention;

[0040] Figure 4 The figure shows a schematic structural view of a peripheral region of a memory according to an embodiment of the present invention;

[0041] Figure 5 The figure shows a schematic flow chart of a method for forming a memory according to an embodiment of the present invention;

[0042] Figures 6a to 6e The figure shows a schematic structural view of a method for forming a memory according to an embodiment of the present invention during its preparation process.

[0043] Among them, the reference numerals are as follows:

[0044] 100 - Substrate;

[0045] 101 - First source / drain region; 102 - Second source / drain region;

[0046] 200 - Bit line;

[0047] 210 - Bit line conductive part; 220 - Bit line shielding layer;

[0048] 230 - Isolation sidewall;

[0049] 300 - Insulating wire;

[0050] 310 - Insulating segment

[0051] 400 - Isolation layer;

[0052] 410 - First isolation part; 420 - Second isolation part;

[0053] 500 - Node contact structure;

[0054] 510 - First contact part; 520 - Second contact part;

[0055] 530 - First intermediate conductive layer; 540 - Second intermediate conductive layer;

[0056] 610 - Spacer insulating layer; 620 - Sacrificial layer;

[0057] 700 - Gate structure;

[0058] 710 - Gate conductive part; 720 - Gate shielding layer;

[0059] 800 - Interlayer dielectric layer;

[0060] 810 - The first interlayer dielectric layer; 820 - The second interlayer dielectric layer;

[0061] 910 - The first conductive plug; 920 - The second conductive plug;

[0062] AA - Active region;

[0063] WL - Word line;

[0064] G1 - The first grid; G2 - The second grid. Detailed implementation manners

[0065] The memory proposed by the present invention and the method for forming the same will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0066] Figure 1a This is a top view of a memory in an embodiment of the present invention, showing a first grid array of node contact windows. Figure 1b This is a top view of a memory in an embodiment of the present invention, showing a second grid array of node contact windows. Figure 2 This is a cross-sectional view of a memory in an embodiment of the present invention, showing node contact windows. Figure 3 This is a cross-sectional view of a memory in an embodiment of the present invention, showing node contact windows filled with node contact structures.

[0067] Combined with Figures 1a to 1b 、 Figure 2 and Figure 3 As shown, the memory includes a substrate 100 and a bit line 200, an insulating line 300, an isolation layer 400, and a node contact structure 500 formed on the substrate 100.

[0068] Specifically, a plurality of active regions AA are formed in the substrate 100. A first source / drain region 101 and a second source / drain region 102 are formed in the plurality of active regions AA, for example, to form a memory transistor. Among them, adjacent active regions AA can be separated from each other by a trench isolation structure, for example.

[0069] Furthermore, a plurality of word lines WL are also formed in the substrate 100. The word lines WL extend along a first direction (X direction) and intersect with the corresponding active regions AA, and the portions of the word lines WL that intersect with the active regions AA are located between the first source / drain region 101 and the second source / drain region 102, for forming the gate structure of the memory transistor.

[0070] Continue to refer to Figure 1a and Figures 1b to 3 As shown, multiple bit lines 200 in the memory are formed on the substrate 100. Among them, the bit lines 200 extend along the second direction (Y direction) and intersect the corresponding active regions AA spatially. The portion of the bit line 200 that intersects the active region AA constitutes a bit line contact portion, for example, and the bit line contact portion is electrically connected to the active region AA. In this embodiment, the bit line contact portion is electrically connected to the second source / drain region 102 of the active region AA.

[0071] In addition, the bit line contact portion of the bit line 200 that intersects the active region AA is further embedded into the substrate 100. That is, the bottom of the bit line contact portion is lower than the top surface of the substrate. In this way, the bit line contact portion of the bit line 200 can be in full contact with the second source / drain region 102, reducing the contact resistance between the bit line 200 and the second source / drain region 102.

[0072] Focus on referring to Figure 2 As shown, the bit line 200 includes a bit line conductive portion 210, a bit line shielding layer 220, and an isolation sidewall 230. Among them, the bit line conductive portion 210 is formed on the substrate 100 and is electrically connected to the corresponding active region AA; the bit line shielding layer 220 covers the top surface of the bit line conductive portion 210; and the isolation sidewall 230 covers the sidewall of the bit line conductive portion 210. That is, by using the bit line shielding layer 220 and the isolation sidewall 230, electrical isolation of the bit line conductive portion 210 is achieved, and then an insulating partition line can be formed to define a node contact window.

[0073] Furthermore, the bit line conductive portion 210 of the bit line 200 may have multiple conductive layers stacked in sequence. For example, in this embodiment, the bit line conductive portion 210 includes a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence from bottom to top. The material of the first conductive layer includes doped polysilicon, for example, the material of the second conductive layer includes titanium nitride, and the material of the third conductive layer includes tungsten.

[0074] Continue to refer to Figure 2 As shown, the isolation sidewall 230 covers the sidewall of the bit line conductive portion 210 and also covers the sidewall of the bit line shielding layer 220. Among them, the isolation sidewall 230 may include multiple stacked structures that sequentially cover the sidewall of the bit line conductive portion 210.

[0075] Continue to combine with Figure 1a and Figure 2As shown, the insulating line 300 is formed on the surface of the substrate 100, and the extending direction of the insulating line 300 is different from that of the bit line 200, so that the insulating line 300 and the bit line 200 can intersect on the top surface of the substrate 100 to define a node contact window. In this embodiment, the extending direction of the insulating line 300 is the same as that of the word line WL, both extending along the first direction (X direction), and the insulating line 300 is formed directly above the word line WL.

[0076] Specifically, the insulating line 300 intersects with the bit line 200 to define a first segmentation array, and the first segmentation array has a plurality of first segments G1. In this embodiment, each first source / drain region 101 corresponds to a first segment G1. It can be considered that the first segment G1 of the first segmentation array is used to form the lower trench portion of the node contact window.

[0077] Furthermore, the top surfaces of the bit line 200 and the insulating line 300 are flush. For example, when forming the insulating line 300 in combination with a planarization process, the bit line 200 can be used as a polishing stop layer. In this embodiment, the top surface of the insulating line 300 is flush with the top surface of the bit line shielding layer 220 of the bit line 200.

[0078] With key reference to Figure 1a As shown, in this embodiment, the insulating line 300 includes a plurality of insulating segments 310 arranged in sequence along the first direction and separated from each other. The insulating segments 310 also extend along the extending direction of the insulating line (i.e., the insulating segments 310 also extend along the first direction), and the insulating segments 310 are formed between adjacent bit lines 200, so that the two end portions of the insulating segments 310 are respectively connected to adjacent bit lines 200, thereby the insulating segments 310 and the adjacent bit lines 200 can surround the first segment G1 to form the lower trench portion of the node contact window.

[0079] With key reference to Figure 2 and Figure 3 As shown, the lower trench portion of the node contact window further extends into the substrate 100, so that a larger area of the active region AA can be exposed in the node contact window (i.e., at least part of the active region AA is exposed in the node contact window). And by making the bottom of the node contact window lower than the top surface of the substrate, thus, it is beneficial to realize the electrical connection between the node contact portion 500 filled in the node contact window and the active region AA. In this embodiment, the first source / drain region 101 in the active region AA is exposed in the node contact window.

[0080] Continue to refer to Figures 1b to 3As shown, the isolation layer 400 is formed on the bit line 200 and the insulating line 300. Specifically, the isolation layer 400 has a second divided grid array pattern. The pattern of the second divided grid array of the isolation layer 400 corresponds to the pattern of the first divided grid array in position, and each second divided grid G2 in the second divided grid array is in one-to-one correspondence and communication with each first divided grid G1 in the first divided grid array to form a node contact window. It can be considered that the first divided grid G1 in the first divided grid array constitutes the lower groove part of the node contact window, and the second divided grid G2 in the second divided grid array constitutes the upper groove part of the node contact window.

[0081] For key reference Figure 1b and Figure 2 As shown, the isolation layer 400 includes: a first isolation part 410 formed on the top surface of the bit line 200, and a second isolation part 420 formed on the top surface of the insulating line 300. It can be understood that the first isolation part 410 and the second isolation part 420 of the isolation layer 400 are connected to each other to surround the second divided grid G2. Or, it can also be understood that the first isolation part 410 extends along the second direction (Y direction) corresponding to the bit line 200, the second isolation part 420 extends along the first direction (X direction) corresponding to the insulating line 300, and the first isolation part 410 and the second isolation part 420 intersect, thereby defining the second divided grid array.

[0082] In a further embodiment, the width dimension of the first isolation part 410 in the isolation layer 400 in the direction perpendicular to the extension direction of the bit line is smaller than the width dimension of the bit line 200, and the width dimension of the second isolation part 420 in the isolation layer 400 in the direction perpendicular to the extension direction of the insulating line is smaller than the width dimension of the insulating line 300. At this time, that is, the opening size of the second divided grid G2 in the defined second divided grid array is made larger than the opening size of the first divided grid G1 in the first divided grid array.

[0083] That is, in this embodiment, the node contact window has an upper-wide and lower-narrow structure. Furthermore, the node contact structure 500 filled in the node contact window can also correspondingly present an upper-wide and lower-narrow structure. In this way, it is beneficial to increase the contact area between the node contact structure 500 and the storage capacitor (not shown in the figure) above it and reduce the contact resistance between devices.

[0084] For key reference Figure 3 As shown, the node contact structure 500 includes a first contact part 510 and a second contact part 520 stacked in sequence from bottom to top. Among them, the material of the first contact part 510 includes, for example, polysilicon, and the material of the second contact part 520 includes, for example, tungsten.

[0085] Further, the first contact portion 510 is filled at the bottom of the node contact window. Specifically, the first contact portion 510 is filled at the bottom of the first grid G1 to be directly electrically connected to the active region AA. As described above, the bottom of the node contact window is embedded in the substrate 100. Therefore, the first contact portion 510 is correspondingly also embedded in the substrate 100, and the top surface of the first contact portion 510 is higher than the top surface of the substrate 100 and lower than the top surfaces of the bit line 200 and the insulating line 300.

[0086] In addition, the second contact portion 520 is filled in the space in the node contact window that is higher than the first contact portion 510, and the top surface of the second contact portion 520 is flush with the top surface of the isolation layer 400. In this embodiment, the second contact portion 520 fills upward from the first grid G1 into the second grid G2, and correspondingly, the second contact portion 520 has a structure that is wider at the top and narrower at the bottom.

[0087] Continue to refer to Figure 3 As shown, the node contact structure 500 further includes an intermediate conductive layer. The intermediate conductive layer covers the top surface of the first contact portion 510, and also covers the side walls of the insulating line 300 and the side walls of the isolation layer 400. In this embodiment, the top of the intermediate conductive layer is also coplanar with the top of the isolation layer 400.

[0088] Specifically, the intermediate conductive layer includes a first intermediate conductive layer 530 and a second intermediate conductive layer 540, and the second contact portion 520 is formed on the second intermediate conductive layer 540.

[0089] Among them, the first intermediate conductive layer 530 is formed on the top surface of the first contact portion 510, and the first intermediate conductive layer 530 is, for example, a metal silicide layer (for example, the first intermediate conductive layer 530 can specifically be a cobalt metal silicide layer). By providing the metal silicide layer, the contact resistance between the first contact portion 510 and the conductive material above it can be effectively reduced.

[0090] In addition, the second intermediate conductive layer 540 covers the top surface of the first intermediate conductive layer 530, and the second intermediate conductive layer 540 also covers the side walls of the first grid G1 that are higher than the first intermediate conductive layer 530 and the side walls of the second grid G2. Based on this, the second contact portion 520 is filled in the space surrounded by the second intermediate conductive layer 540, that is, there is a second intermediate conductive layer 540 between the second contact portion 520 and the side walls of the first grid G1, and between the second contact portion 520 and the side walls of the second grid G2.

[0091] In this embodiment, the second intermediate conductive layer 540 covers the sidewalls of the insulating wire 300 and the sidewalls of the isolation layer 400, and the top of the second intermediate conductive layer 540 and the top of the isolation layer 400 are coplanar.

[0092] In a specific embodiment, the memory has a device region and a peripheral region. Also, as described above, the active region AA is formed in the device region, and the peripheral region is disposed outside the device region.

[0093] Figure 4 FIG. is a schematic structural diagram of the peripheral region of a memory in an embodiment of the present invention. As Figure 4 shown, at least one transistor device is formed in the peripheral region. Only two transistor devices are schematically shown in the appendix of this embodiment. Figure 4

[0094] In this embodiment, an interlayer dielectric layer 800 is further formed in the peripheral region. The interlayer dielectric layer 800 covers the sidewalls and the top surface of the gate structure 700 of the transistor device. Wherein, the gate structure 700 includes a gate conductive portion 710 and a gate shielding layer 720 covering the top surface of the gate conductive portion 710. In addition, the transistor device further includes source / drain regions (not shown in the figure) formed in the substrate 100.

[0095] In an alternative solution, the gate structure 700 of the transistor device can be formed simultaneously with the bit line 200, and the top surface of the gate structure 700 and the top surface of the bit line 200 are flush. Based on this, the gate conductive portion 710 in the gate structure 700 can also correspondingly include a first conductive layer, a second conductive layer, and a third conductive layer. Also, the gate shielding layer 720 and the bit line shielding layer 220 in the bit line 200 can be formed of the same material, for example, both include silicon nitride.

[0096] Continue to refer to Figure 4 shown, the interlayer dielectric layer 800 includes a first interlayer dielectric layer 810 and a second interlayer dielectric layer 820. The first interlayer dielectric layer 810 covers the sidewalls of the gate structure 700, and the second interlayer dielectric layer 820 covers the top surface of the first interlayer dielectric layer 810 and the top surface of the gate structure 700.

[0097] In this embodiment, the top surface of the first interlayer dielectric layer 810 is flush with the top surface of the gate structure 700 (correspondingly, the first interlayer dielectric layer 810 is flush with the top surfaces of the bit line 200 and the insulating wire 300). Also, the top surface of the second interlayer dielectric layer 820 is flush with the top surface of the isolation layer 400.

[0098] ​In a further embodiment, the memory further includes a plurality of conductive plugs that penetrate the interlayer dielectric layer 800 for electrical connection to the transistor device.

[0099] In this embodiment, the plurality of conductive plugs include a first conductive plug 910 for electrically connecting to the gate structure 700 and a second conductive plug 920 for electrically connecting to the source / drain region. Specifically, the first conductive plug 910 penetrates the second interlayer dielectric layer 820 and, in this embodiment, further penetrates the gate shielding layer 720 of the gate structure to extend to the gate conductive portion 710, thereby electrically connecting the first conductive plug 910 to the gate conductive portion 710. Also, the second conductive plug 920 penetrates the second interlayer dielectric layer 820 and the first interlayer dielectric layer 810 in sequence to extend to the substrate, thereby electrically connecting the second conductive plug 920 to the source / drain region.

[0100] Furthermore, the width dimension of the portion of the first conductive plug 910 located in the second interlayer dielectric layer 820 is greater than the width dimension of the portion of the first conductive plug 910 located in the gate shielding layer 720. Also, the width dimension of the portion of the second conductive plug 920 located in the second interlayer dielectric layer 820 is greater than the width dimension of the portion of the second conductive plug 920 located in the first interlayer dielectric layer 810.

[0101] Based on the memory described above, the method for forming the memory will be described in detail below with reference to the accompanying drawings. Figure 5 It is a schematic flowchart of the method for forming the memory in an embodiment of the present invention. Figures 6a to 6e It is a schematic structural diagram of the method for forming the memory in an embodiment of the present invention during its manufacturing process.

[0102] In step S100, specifically referring to Figure 6a as shown, a substrate 100 is provided, and a plurality of active regions AA are formed in the substrate 100.

[0103] Among them, a plurality of trench isolation structures may be formed in the substrate 100 first to define the plurality of active regions AA. Also, the first source / drain region S / D1 and the second source / drain region S / D2 in the active region AA may be formed by an ion implantation process.

[0104] Continuing to refer to what is shown in 6a, the memory has a device region and a peripheral region, and Figure 6a the cross-sectional schematic diagrams in the aa' and bb' directions correspond to the schematic structural diagrams in a part of the device region. Also, transistor devices may be further formed in the peripheral region in subsequent processes.

[0105] In step S200, continue to refer to Figure 6a As shown, bit lines 200 and insulating lines 300 are formed on the substrate 100. The bit lines 200 and the insulating lines 300 intersect to define a first grid array. In this embodiment, each of the first source / drain regions 101 corresponds to a first grid G1.

[0106] Specifically, in this embodiment, the bit lines 200 can be preferentially formed on the substrate 100, and then the insulating lines 300 are formed on the substrate 100. Further, the top surfaces of the bit lines 200 and the insulating lines 300 can be made flush, so that in subsequent processes, it is beneficial to form an isolation layer on the top surfaces of the bit lines 200 and the insulating lines 300, improving the pattern accuracy of the formed isolation layer.

[0107] Among them, the bit lines 200 extend continuously along a second direction. And, the insulating lines 300 include a plurality of insulating segments 310 arranged in sequence along a first direction, and each of the insulating segments 310 also extends along the first direction between adjacent bit lines 200 to connect with the bit lines 200, thereby surrounding the first grid G1 in the first grid array. It can be understood that the insulating lines 300 extend discontinuously along the first direction, and there is a bit line 200 between adjacent insulating segments 310 in the same insulating line 300. And, the first grid G1 in the first grid array is used to form the lower trench portion of the node contact window.

[0108] In this embodiment, the pattern of the first grid array defined by the bit lines 200 and the insulating lines 300 can also be used to further etch the substrate 100 of the first source / drain region 101, so that the lower trench portion of the node contact window is embedded in the substrate 100.

[0109] In an alternative solution, specifically refer to Figure 6b As shown, after forming the lower trench portion of the node contact window, a first contact portion 510 of the node contact structure can be directly formed in the lower trench portion to be electrically connected to the active region AA. And, the top surface of the first contact portion 510 is lower than the top surfaces of the bit lines 200 and the insulating lines 300, that is, the first contact portion 510 fills the bottom of the first grid G1.

[0110] Further, after forming the first contact portion 510, the method further includes: forming a spacer insulating layer 610 on the sidewalls of the first partition G1 that are higher than the first contact portion 510. That is, the spacer insulating layer 610 correspondingly covers the sidewalls of the bit line 200 that are higher than the first contact portion 510 and the sidewalls of the insulating line 300 that are higher than the first contact portion 510. Wherein, the top of the spacer insulating layer 610 may be coplanar with the top of the insulating line 300 and correspondingly coplanar with the top of the bit line 200.

[0111] In this embodiment, by forming the spacer insulating layer 610, it can be used to protect the bit line 200 and the insulating line 300, and prevent the sidewalls of the bit line 200 and the insulating line 300 from being damaged in subsequent processes.

[0112] Continue to refer to Figure 6b As shown, after forming the first contact portion 510, a first intermediate conductive layer 530 may also be formed on the top surface of the first contact portion 510.

[0113] Wherein, the material of the first contact portion 510 includes, for example, polysilicon, and the first intermediate conductive layer 530 is, for example, a metal silicide layer. Based on this, the method for forming the first intermediate conductive layer 530 includes, for example: First, deposit a metal layer on the substrate 100, the metal layer covering the top surface of the first contact portion 510 and covering the bit line 200 and the insulating line 300; then, perform a thermal annealing process to cause the metal in the metal layer to react with the polysilicon in the first contact portion 510, thereby self-aligning to form the metal silicide layer on the top surface of the first contact portion 510; then, remove the unreacted portion of the metal layer.

[0114] In addition, in step S200, a gate structure 700 and a first interlayer dielectric layer 810 are also formed on the substrate 100 in the peripheral region, and the first interlayer dielectric layer 810 covers the outer sidewalls of the gate structure 700. Wherein, the gate structure 700 may be formed simultaneously with the bit line 200, and the first interlayer dielectric layer 810 may be formed simultaneously with the insulating line 300, and the top surface of the first interlayer dielectric layer 810 may be further flush with the top surface of the gate structure 700.

[0115] In step S300, specifically referring to Figure 6c As shown, fill the sacrificial layer 620 in each of the first partitions G1 of the first partition array. In this embodiment, the sacrificial layer 620 is formed above the first intermediate conductive layer 530.

[0116] As described above, the top surfaces of the bit line 200 and the insulating line 300 are flush. Based on this, the sacrificial layer 620 can be filled in the first grid G1 in an aligned manner through a planarization process, and then a flat top surface can be formed by the bit line 200, the insulating line 300, and the sacrificial layer 620. In this way, it is beneficial to improve the pattern accuracy of the isolation layer formed subsequently.

[0117] In step S400, an isolation material layer is formed on the substrate 100, and the isolation material layer covers the bit line 200, the insulating line 300, and the sacrificial layer 620. Specifically, the isolation material layer is formed on the flat top surface formed by the bit line 200, the insulating line 300, and the sacrificial layer 620. At this time, the isolation material layer also has a corresponding flat top surface.

[0118] In step S500, specifically referring to Figure 6c As shown, the isolation material layer is patterned to form an isolation layer 400 having a second grid array pattern, and the pattern of the second grid array of the isolation layer 400 corresponds to the pattern position of the first grid array.

[0119] Specifically, when patterning the isolation material layer, the portion of the isolation material layer covering the bit line 200 and the insulating line 300 is retained (in this embodiment, the isolation layer 400 includes a first isolation portion 410 corresponding to the top surface of the bit line 200 and a second isolation portion 420 corresponding to the top surface of the insulating line 300), so that the second grid G2 of the second grid array of the isolation layer 400 communicates with the first grid G1 in the first grid array up and down to form a node contact window.

[0120] It should be noted that since the isolation material layer is formed on a flat surface, the isolation material layer correspondingly has a flat top surface. Based on this, when performing a patterning process on the isolation material layer (for example, including a photolithography process and an etching process), it is beneficial to improve the accuracy of the photolithography process and the etching process, and further beneficial to ensure the pattern accuracy of the formed isolation layer 400.

[0121] Continuing to refer to Figure 6c As shown, in this embodiment, the width dimension of the first isolation portion 410 of the isolation layer 400 can also be made smaller than the width dimension of the bit line 200, and the width dimension of the second isolation portion 420 of the isolation layer 400 can be made smaller than the width dimension of the insulating line 300, so that the opening dimension of the second grid G2 of the second grid array is larger than the opening dimension of the first grid G1 of the first grid array.

[0122] In an alternative embodiment, while forming the isolation layer 400, a second interlayer dielectric layer 820 can also be formed in the peripheral region on the first interlayer dielectric layer 810 and the gate structure 700. In this embodiment, the second interlayer dielectric layer 820 is further a patterned second interlayer dielectric layer 820.

[0123] Among them, the second interlayer dielectric layer 820 and the isolation layer 400 are formed simultaneously. For example, when depositing the isolation material layer, the isolation material layer also covers the first interlayer dielectric layer 810 and the gate structure 700, and when patterning the isolation material layer, the portion of the isolation material layer located in the peripheral region is also patterned to form the patterned second interlayer dielectric layer 820.

[0124] In this embodiment, a plurality of upper openings are formed in the patterned second interlayer dielectric layer 820, and the plurality of upper openings correspond to the gate structure 700 and the source / drain regions of the transistor device. Specifically, the plurality of upper openings include a first upper opening corresponding to the gate structure and a second upper opening corresponding to the source / drain region.

[0125] In step S600, specifically referring to Figure 6d and Figure 6e as shown, the sacrificial layer is removed to vacate the node contact window, and the second contact portion 520 is filled in the node contact window to form the node contact structure 500.

[0126] In this embodiment, after removing the sacrificial layer, the first intermediate conductive layer 530 is exposed. Moreover, when removing the sacrificial layer, the spacer insulating layer 610 can be used to protect the sidewalls of the bit line 200 and the insulating line 300 to prevent the bit line 200 and the insulating line 300 from being eroded.

[0127] Furthermore, the second contact portion 520 is filled from the first partition G1 upward into the second partition G2 so that the top surface of the second contact portion 520 is not lower than the top surfaces of the bit line 200 and the insulating line 300. Among them, the second contact portion 520 can be self-aligned and filled in the node contact window by combining a planarization process, for example.

[0128] In addition, continue to refer to Figure 6dAs shown, in step S600, it further includes etching the portion of the gate shielding layer 720 exposed to the first upper opening to form a first lower opening in the gate shielding layer 720. The first lower opening and the first upper opening are vertically connected and expose the gate conductive portion 710. Further, it further etches the portion of the first interlayer dielectric layer 810 exposed to the second upper opening to form a second lower opening in the first interlayer dielectric layer 810. The second upper opening and the first lower opening are vertically connected and expose the substrate 100.

[0129] Based on this, in this embodiment, when filling the second contact portion 520 into the node contact window, conductive plugs are also filled in the interlayer dielectric layer in the peripheral area. Specifically, a first conductive plug 910 is filled in the first lower opening and the first upper opening so that the first conductive plug 910 is electrically connected to the gate conductive portion 710 of the gate structure; and a second conductive plug 920 is filled in the second lower opening and the second upper opening so that the second conductive plug 920 is electrically connected to the source / drain region.

[0130] Focus on Figure 6e As shown, in an alternative solution, before filling the second contact portion 520, it further includes: forming a second intermediate conductive layer 540 in the node contact window. Specifically, the second intermediate conductive layer 540 covers the top surface of the first intermediate conductive layer 530, and also covers the sidewalls of the bit line 200 above the first intermediate conductive layer 530, the sidewalls of the insulating line 300 above the first intermediate conductive layer 530, and the sidewall of the isolation layer 400. In this embodiment, the second intermediate conductive layer 540 conformally covers the spacer insulating layer 610 and continuously extends upward to cover the sidewall of the isolation layer 400. That is, the second intermediate conductive layer 540 covers the top surface of the first intermediate conductive layer 530, and also covers the sidewalls of the node contact window above the first intermediate conductive layer 530.

[0131] Based on this, the second contact portion 520 can be filled in the space surrounded by the second intermediate conductive layer 540. That is, equivalently, there is the second intermediate conductive layer 540 between the second contact portion 520 and the bit line 200, between the second contact portion 520 and the insulating line 300, and between the second contact portion 520 and the isolation layer 400.

[0132] It should be noted that if the material of the second contact portion 520 includes a metal material (for example, including tungsten), then by coating the periphery of the second contact portion 520 with the second intermediate conductive layer 540, the metal in the second contact portion 520 can be prevented from diffusing into the adjacent insulating material by using the second intermediate conductive layer 540. Among them, the material of the second intermediate conductive layer 540 includes, for example, at least one of titanium and titanium nitride.

[0133] In summary, in the memory and its forming method provided in this embodiment, after forming the lower trench portion of the bit line and the insulating line to define the node contact window, the upper trench portion of the node contact window is continuously defined by the isolation layer, so that the top of the formed node contact window is higher than the top surface of the bit line to meet the height requirement of the node contact structure. In this way, the node contact structure can be filled in the node contact window in a self-aligned manner. Compared with the traditional method of forming the node contact structure by a patterning process, in this embodiment, it is not necessary to perform a patterning process on the conductive material of the node contact structure, avoiding the problem that the etching difficulty increases due to the large hardness of the conductive material of the node contact structure in the traditional process, which in turn affects the pattern accuracy of the node contact structure. At the same time, the memory and its forming method provided in this embodiment also overcome the phenomenon that polymers are easily generated and attached to the node contact structure during the patterning process in the traditional process.

[0134] In a further solution provided in this embodiment, an intermediate conductive layer can also be covered on at least the sidewalls of the node contact window, so that there is an intermediate conductive layer between the second contact portion of the node contact structure and the node contact window. Based on this, when the material of the second contact portion includes a metal, the intermediate conductive layer can be used to block the metal in the second contact portion from diffusing into the adjacent insulating material, which is beneficial to improving the overall performance of the memory.

[0135] It should be noted that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the disclosed technical content, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

[0136] It should also be understood that unless otherwise specifically stated or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship between each component, element, step, etc.

[0137] It should also be recognized that the terminology described herein is only used to describe specific embodiments and is not intended to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include sub-steps as well as sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A memory, characterized in that, Including: A substrate in which at least one active region is formed, and a first source / drain region and a second source / drain region are formed in the active region; A plurality of bit lines and a plurality of insulating lines are formed on the substrate, and the bit lines and the insulating lines intersect to define a first partitioned array; An isolation layer is formed on the bit lines and the insulating lines. The isolation layer has a second partitioned array pattern. The pattern of the second partitioned array of the isolation layer corresponds to the pattern of the first partitioned array in position, and each second partition in the second partitioned array communicates with each first partition in the first partitioned array up and down to form a node contact window; and A node contact structure is filled in the node contact window, and the top surface of the node contact structure is higher than the top surfaces of the bit lines and the insulating lines; The isolation layer includes: a first isolation portion formed on the top surface of the bit line, and a second isolation portion formed on the top surface of the insulating line; wherein, the width dimension of the first isolation portion in the direction perpendicular to the extension direction of the bit line is smaller than the width dimension of the bit line, and the width dimension of the second isolation portion in the direction perpendicular to the extension direction of the insulating line is smaller than the width dimension of the insulating line.

2. The memory according to claim 1, characterized in that, The top surfaces of the bit lines and the insulating lines are flush.

3. The memory according to claim 1, characterized in that, The insulating line includes a plurality of insulating segments arranged in sequence along a first direction, and the bit line extends continuously along a second direction; and, the insulating segments are formed between adjacent bit lines and extend along the first direction, and the two end portions of the insulating segments are respectively connected to adjacent bit lines to surround the first partition by the insulating segments and the adjacent bit lines.

4. The memory according to claim 1, characterized in that, The node contact structure includes a first contact portion and a second contact portion. The first contact portion is filled at the bottom of the first partition, and the second contact portion is formed above the first contact portion and is filled from the first partition upward to the second partition.

5. The memory according to claim 4, characterized in that, The node contact structure further includes an intermediate conductive layer that covers the top surface of the first contact portion and also covers the sidewalls of the insulating line and the sidewalls of the isolation layer.

6. The memory according to claim 5, characterized in that, The top of the intermediate conductive layer and the top of the isolation layer are coplanar.

7. The memory according to claim 5, characterized in that, The memory further includes a spacer insulating layer that covers the sidewalls of the insulating line, and the intermediate conductive layer covers the spacer insulating layer and extends continuously upward to cover the sidewalls of the isolation layer.

8. The memory according to claim 7, characterized in that, The top of the spacer insulating layer and the top of the insulating line are coplanar.

9. The memory according to claim 5, characterized in that, The second contact portion is filled in the space surrounded by the intermediate conductive layer so that the intermediate conductive layer covers the bottom and the sidewalls of the second contact portion.

10. The memory according to claim 1, characterized in that, The memory has a device region and a peripheral region, and the at least one active region is formed in the device region, and the peripheral region is formed outside the device region; and A transistor device, an interlayer dielectric layer, and a conductive plug are formed in the peripheral region. The interlayer dielectric layer covers the sidewalls and the top surface of the gate structure of the transistor device, and the conductive plug penetrates through the interlayer dielectric layer to be electrically connected to the transistor device.

11. The memory according to claim 10, characterized in that, The interlayer dielectric layer includes a first interlayer dielectric layer and a second interlayer dielectric layer. The first interlayer dielectric layer coats the sidewalls of the gate structure, and the top surface of the first interlayer dielectric layer is flush with the top surface of the bit line. Also, the second interlayer dielectric layer covers the top surface of the first interlayer dielectric layer and the top surface of the gate structure, and the top surface of the second interlayer dielectric layer is flush with the top surface of the isolation layer.

12. A method for forming a memory, characterized in that, Comprising: Providing a substrate in which at least one active region is formed; Forming a bit line and an insulating line on the substrate, the bit line and the insulating line intersecting to define a first grid array; Filling a sacrificial layer in each first grid of the first grid array; Forming an isolation material layer on the substrate, the isolation material layer covering the bit line, the insulating line, and the sacrificial layer; Patterning the isolation material layer to form an isolation layer having a second grid array pattern, the pattern of the second grid array of the isolation layer corresponding to the pattern position of the first grid array, so that the isolation layer covers the bit line and the insulating line, and each first grid in the first grid array communicates with each second grid in the second grid array up and down to form a node contact window; and, Removing the sacrificial layer and filling a node contact structure in the node contact window, the top surface of the node contact structure not being lower than the top surfaces of the bit line and the insulating line.

13. The method for forming a memory according to claim 12, characterized in that, After forming the bit line and the insulating line and before filling the sacrificial layer, it further includes: Forming a first contact portion at the bottom of the first grid in the first grid array to electrically connect the first contact portion and the active region.

14. The method for forming a memory according to claim 13, characterized in that, After removing the sacrificial layer, filling a second contact portion of the node contact structure in the node contact window, the second contact portion filling from the first grid upward to the second grid.

15. The method for forming a memory according to claim 14, wherein, After removing the sacrificial layer and before filling the second contact portion, it further includes: forming an intermediate conductive layer in the node contact window, the intermediate conductive layer covering the top surface of the first contact portion and also covering the sidewalls of the insulating line and the sidewalls of the isolation layer; And, the second contact portion is filled in the space surrounded by the intermediate conductive layer so that the intermediate conductive layer coats the bottom and the sidewalls of the second contact portion.

16. The method for forming a memory according to claim 12, wherein, The memory has a device region and a peripheral region, and the at least one active region is formed in the device region, and the peripheral region is formed outside the device region; Wherein, when forming the bit line, it further includes: forming a gate structure of a transistor device on the substrate in the peripheral region; And, when forming the insulating line, it further includes: forming a first interlayer dielectric layer in the peripheral region, the first interlayer dielectric layer covering the outer sidewalls of the gate structure; And, when forming the isolation layer, it further includes: forming a second interlayer dielectric layer in the peripheral region, the second interlayer dielectric layer covering the first interlayer dielectric layer and the gate structure.

Images