Semiconductor structure

Abstract

The present invention provides a semiconductor structure, wherein the semiconductor structure has a groove located between adjacent contact pads, and an insulating filling layer filled in the groove is composed of at least two insulating parts, so that the internal stress of the insulating material in the groove can be more effectively relieved, which is conducive to improving the problem of damage to the adjacent semiconductor device due to the high-intensity internal stress of the insulating material in the groove.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] For semiconductor processes, internal stress has a significant impact on the reliability of semiconductor devices. In particular, with the continuous development of semiconductor technology, the size of semiconductor devices continues to shrink, and the impact of internal stress in semiconductor structures on semiconductor devices is becoming more and more obvious. Generally speaking, the internal stress generated by the material filled in the groove during the high-temperature process is greater, which is more likely to affect adjacent semiconductor devices. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor structure to solve the problem that the semiconductor device is easily damaged due to high-intensity internal stress in the existing semiconductor structure.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor structure, comprising:

[0005] A substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed in the substrate, and the interlayer dielectric layer covers the semiconductor device;

[0006] at least two interconnect structures, the interconnect structures comprising contact plugs and contact pads, the contact plugs penetrating the interlayer dielectric layer and extending to the semiconductor device, the contact pads covering the tops of the contact plugs and extending to cover a portion of the top surface of the interlayer dielectric layer; and

[0007] a groove located between adjacent contact pads, the groove further extending downward and stopping in the interlayer dielectric layer; and,

[0008] The insulating filling layer is filled in the groove, and the insulating filling layer includes at least two insulating parts.

[0009] Optionally, the insulating filling layer includes at least two first insulating parts, the two first insulating parts cover two opposite side walls of the groove, and the two first insulating parts define a recess in the middle area of ​​the groove; and the semiconductor structure also includes a covering layer, the covering layer covers the contact pad and the insulating filling layer, and fills the recess.

[0010] Optionally, the bottom of the depression extends to the bottom of the groove, the covering layer fills the depression and extends to the bottom of the groove, and a cavity is formed in a portion of the covering layer corresponding to the depression.

[0011] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the shielding layer; wherein the groove extends downward from between adjacent contact pads to the shielding layer in the height direction, and the groove extends laterally from the shielding layer to the sidewall structure in the width direction, and the depth value of the groove is not greater than the height value of the gate conductive layer, and the width dimension of the groove is greater than the width dimension of the gate conductive layer.

[0012] Optionally, the insulating filling layer also includes a second insulating part, which covers the bottom of the groove, and a gap is formed between the second insulating part and the first insulating part, and the gap extends from the corner where the bottom wall and the side wall of the groove are interconnected toward the direction of the recess.

[0013] Optionally, the bottom of the recess extends to the second insulating portion, and the gap is connected to the recess, and the covering layer fills the recess and closes the opening of the first gap.

[0014] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the shielding layer; wherein the groove extends downward from between adjacent contact pads to the shielding layer in the height direction, the groove extends laterally from the shielding layer to the sidewall structure in the width direction, and the depth of the groove is not greater than the height of the gate conductive layer.

[0015] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the shielding layer;

[0016] The groove extends downward from between adjacent contact pads to the shielding layer in the height direction, and extends laterally from the shielding layer to the sidewall structure in the width direction, and the depth of the groove is greater than the height of the gate conductive layer.

[0017] Optionally, a gap is also formed in a portion of the covering layer corresponding to the recess.

[0018] Optionally, a gap is formed between the two first insulating parts in a middle area of ​​the groove, and the gap extends along the height direction below the depression.

[0019] Optionally, the covering layer fills the recess and closes the top opening of the gap.

[0020] Optionally, the semiconductor device includes a gate conductive layer formed on the top surface of the substrate, and a first source / drain region and a second source / drain region formed in the substrate, the first source / drain region and the second source / drain region are respectively located on both sides of the gate conductive layer; wherein the interconnection structure is respectively arranged on the first source / drain region and the second source / drain region, and the contact pad corresponding to the first source / drain region and the contact pad corresponding to the second source / drain region respectively extend laterally from both sides of the gate conductive layer in a direction toward the gate conductive layer.

[0021] Optionally, the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the sidewalls of the shielding layer; wherein the contact pad corresponding to the first source / drain region and the contact pad corresponding to the second source / drain region extend laterally from both sides of the gate conductive layer to the sidewall structure respectively.

[0022] Optionally, the groove extends laterally from the shielding layer to the sidewall structure in the width direction, and the groove extends downward from between adjacent contact pads to the shielding layer in the height direction.

[0023] In the semiconductor structure provided by the present invention, there is a groove located between adjacent contact pads, and the groove is filled with an insulating filling layer to separate adjacent contact pads. In addition, the insulating filling layer filled in the groove is composed of at least two insulating parts. Compared with only using a larger volume of insulating material to fill the groove, the present invention uses at least two insulating parts to fill the groove, which can more effectively relieve the internal stress of the insulating material in the groove, thereby improving the problem of damage to the adjacent semiconductor device due to the high-intensity internal stress of the insulating material in the groove.

[0024] Furthermore, the insulating material filled in the groove can be formed with gaps (for example, gaps can be formed between adjacent insulating parts). In this way, the gaps can be used to release the stress of the insulating material, further reducing the internal stress of the insulating material filled in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a semiconductor structure in Embodiment 1 of the present invention;

[0026] Figure 2 is a schematic diagram of a semiconductor structure in a second embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a semiconductor structure in Embodiment 3 of the present invention;

[0028] Figure 4It is a schematic diagram of a semiconductor structure in Embodiment 4 of the present invention.

[0029] The reference numerals are as follows:

[0030] 100-substrate;

[0031] 110-first source / drain region;

[0032] 120- a second source / drain region;

[0033] 200-gate conductive layer;

[0034] 210- first conductive layer;

[0035] 220- second conductive layer;

[0036] 230- third conductive layer;

[0037] 300-interconnection structure;

[0038] 310-contact plug;

[0039] 320-contact pad;

[0040] 400-interlayer dielectric layer;

[0041] 410- shielding layer;

[0042] 420-isolation side wall;

[0043] 430-isolation dielectric layer;

[0044] 500-insulation filling layer;

[0045] 500a-depression;

[0046] 510- first insulating portion;

[0047] 520- second insulating portion;

[0048] 510a-first gap;

[0049] 520a-second gap;

[0050] 600-covering layer;

[0051] 600a-Gap. DETAILED DESCRIPTION

[0052] The semiconductor structure proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0053] Embodiment 1

[0054] Figure 1 is a schematic diagram of a semiconductor structure in Embodiment 1 of the present invention, such as Figure 1 As shown, the semiconductor structure comprises:

[0055] A substrate 100, wherein at least one semiconductor device and an interlayer dielectric layer 400 are formed in the substrate 100, and the interlayer dielectric layer 400 covers the semiconductor device;

[0056] at least two interconnect structures 300, the interconnect structures 300 comprising contact plugs 310 and contact pads 320, the contact plugs 310 penetrating the interlayer dielectric layer 400 and extending to the semiconductor device, the contact pads 320 covering the top of the contact plugs 310 and extending to cover a portion of the top surface of the interlayer dielectric layer 400; and,

[0057] A groove between adjacent contact pads 320 of a bit line, wherein the groove further extends downward and stops in the interlayer dielectric layer 400; and,

[0058] An insulating filling layer is filled in the groove, and the insulating filling layer includes at least two insulating parts (for example, Figure 1 Two first insulating parts 510 shown in FIG.

[0059] The groove is formed by, for example, etching the interlayer dielectric layer 400 using adjacent contact pads 320 as a mask, thereby ensuring that adjacent contact pads 320 are separated from each other and avoiding the problem of electrical connection between adjacent contact pads due to residual conductive material when preparing the contact pads 320.

[0060] Furthermore, in this embodiment, the insulating filling layer filled in the groove is composed of at least two insulating parts. It should be noted that, compared with filling the groove with only one insulating part with a larger volume, filling the groove with multiple insulating parts will be more conducive to achieving stress release of the insulating material in the groove. Among them, each insulating part in the insulating filling layer can be formed of the same material, for example, the material of each insulating part includes silicon nitride or silicon oxide.

[0061] Continue to refer Figure 1 As shown, the insulating filling layer includes at least two first insulating parts 510, and the two first insulating parts 510 cover two opposite side walls of the groove. In this embodiment, the first insulating part 510 also covers the side wall of the contact pad 320 exposed to the groove.

[0062] Furthermore, the two first insulating parts 510 can define a recess 500a in the middle area of ​​the groove. Specifically, the two opposite first insulating parts 510 extend from the two opposite side walls of the groove to the middle area of ​​the groove, and the recess 500a is defined by the boundaries of the two first insulating parts 510. In this embodiment, the top of the recess 500a is not higher than the top of the groove.

[0063] Continue to refer Figure 1 As shown, the semiconductor structure further includes a capping layer 600 , and the capping layer 600 covers the contact pad 320 and the insulating filling layer, and fills the recess 500 a .

[0064] In this embodiment, the bottom of the depression 500a also extends to the bottom of the groove, that is, the two first insulating parts 510 are separated from each other by the depression 500a located in the middle area. Based on this, the cover layer 600 fills the depression 500a and can extend to the bottom of the groove.

[0065] It should be noted that the depression 500a is located in the spatial region of the groove, and the cover layer 600 fills the depression 500a. Based on this, it can be considered that the cover layer 600 at least partially fills the groove. Therefore, in the groove of this embodiment, not only the insulating filling layer (including the two first insulating parts 510) is filled, but also part of the cover layer 600 is filled, so that the groove is filled with at least three insulating parts.

[0066] The cover layer 600 can be formed of the same material as the insulating filling layer, for example, both can be made of silicon nitride. By forming the cover layer 600 with the same material as the insulating filling layer, the insulating filling layer and the cover layer 600 have the same or similar thermal expansion coefficients, thereby avoiding the problem of increased internal stress caused by the difference in thermal expansion between different materials.

[0067] In an optional solution, a gap 600a may be further formed in the portion of the covering layer 600 corresponding to the recess 500a.

[0068] Specifically, the width of the recess 500a is at least partially determined by the spacing between the two first insulating parts 510, and the first insulating part 510 is filled in the groove, so that the spacing between the two first insulating parts 510 is smaller, and the width of the defined recess 500a is correspondingly smaller. In addition, the recess 500a extends downward to the bottom of the groove in the depth direction, so the depth value of the recess 500a corresponds to the depth value of the groove. In this way, the depth-to-width ratio of the recess 500a can be made larger, so when the cover layer 600 fills the recess 500a, it is easy to form the gap 600a in the portion corresponding to the recess 500a.

[0069] In this embodiment, a pit is formed in the bottom of the groove corresponding to the depression 500a, so that the depth of the depression 500a can be further increased. For example, the bottom of the depression 500a can be made lower than the bottom of the first insulating portion 510. In this way, the depth-to-width ratio of the depression 500a is increased, which is more conducive to forming the gap 600a in the cover layer 600.

[0070] It should be noted that, since a gap is formed in the insulating material corresponding to the groove (i.e., a gap 600a is formed in the portion of the cover layer 600 corresponding to the groove), the gap 600a can be used to further release the stress of the insulating material filled in the groove. For example, when a high-temperature process is performed on the semiconductor structure, the insulating material in the groove can release the stress by using the gap 600a, thereby avoiding the problem that the insulating material in the groove squeezes other components due to high-intensity stress and causes damage to other components.

[0071] In particular, when the groove is formed directly above the semiconductor device, the high-intensity internal stress of the insulating material filled in the groove may damage the semiconductor device. Figure 1 As shown, in this embodiment, the insulating filling layer and the cover layer 600 filled in the groove are formed directly above the semiconductor device.

[0072] Continue to refer Figure 1 As shown, in this embodiment, the semiconductor device includes, for example, a transistor. The transistor includes a gate conductive layer 200 formed on the top surface of the substrate 100, and a first source / drain region 110 and a second source / drain region 120 formed in the substrate 100, wherein the first source / drain region 110 and the second source / drain region 120 are respectively located on both sides of the gate conductive layer 200.

[0073] In this embodiment, the gate conductive layer 200 includes a stacked first conductive layer 210, a second conductive layer 220, and a third conductive layer 230. The material of the first conductive layer 210 includes, for example, polysilicon, the material of the second conductive layer 220 includes, for example, titanium nitride, and the material of the third conductive layer 230 includes, for example, tungsten.

[0074] The interconnection structure 300 is respectively disposed on the first source / drain region 110 and the second source / drain region 120. Specifically, the contact plug 310 corresponding to the first source / drain region and the contact plug 310 corresponding to the second source / drain region are respectively formed on both sides of the gate conductive layer 200, and vertically extend to the first source / drain region 110 and the second source / drain region 120 of the substrate 100, so as to be electrically connected to the first source / drain region 110 and the second source / drain region 120. And, the contact pad 320 corresponding to the first source / drain region and the contact pad 320 corresponding to the second source / drain region extend laterally from both sides of the gate conductive layer 200 in a direction toward the gate conductive layer 200.

[0075] Furthermore, the interlayer dielectric layer 400 includes a shielding layer 410 covering the top surface of the gate conductive layer 200 , and an isolation spacer 420 covering the sidewalls of the gate conductive layer 200 and the sidewalls of the shielding layer 410 .

[0076] Specifically, the isolation sidewall 420 is, for example, a stacked structure that sequentially covers the gate conductive layer 200. In this embodiment, the isolation sidewall 420 includes a first isolation layer, a second isolation layer, and a third isolation layer that sequentially cover the gate conductive layer 200 from the inside to the outside. The first isolation layer and the third isolation layer can be formed of the same material, for example, both include silicon oxide, and the material of the second isolation layer includes, for example, silicon nitride, thereby forming an isolation sidewall 420 of an ONO structure. In addition, the material of the shielding layer 410 can also include silicon nitride.

[0077] In this embodiment, the two contact pads 320 corresponding to the first source / drain region 110 and the second source / drain region 120 extend laterally from both sides of the gate conductive layer 200 to the top of the isolation spacer 420 in the direction toward the gate conductive layer 200. Based on this, the groove located between adjacent contact pads 320 extends laterally from the shielding layer 410 to the isolation spacer 420 in the width direction. In this embodiment, the groove extends laterally to the second isolation layer of the isolation spacer 420 in the width direction, and accordingly, the width dimension of the groove is greater than the width dimension of the gate conductive layer 220.

[0078] Furthermore, the groove extends downward from between adjacent contact pads 320 to the shielding layer 410 and the isolation spacer 420 in the height direction. The depth value H2 of the groove may be no greater than the height value H1 of the semiconductor device above the top surface of the substrate. In this embodiment, the depth value H2 of the groove is no greater than the height value H1 of the gate conductive layer 200.

[0079] As described above, the width of the groove is greater than the width of the gate conductive layer 200. Therefore, it can be considered that in this embodiment, the depth-to-width ratio of the groove is small, so that two first insulating portions 510 separated from each other can be formed in the groove, and the two first insulating portions 510 can be separated from each other by the larger recess 500a. In this embodiment, the bottom of the recess 500a further extends downward into the shielding layer 410, so that the portion of the shielding layer 410 corresponding to the recess 500a is further sunken.

[0080] Furthermore, the outer edge boundary of the first insulating portion 510 correspondingly exceeds the outer edge boundary of the gate conductive layer 200 and covers the sidewalls of the contact pad 320 and the isolation spacer 410 exposed in the groove.

[0081] Continue to refer Figure 1 As shown, the interlayer dielectric layer 400 further includes an isolation dielectric layer 430 . The isolation dielectric layer 430 is formed at the periphery of the isolation sidewall 420 away from the gate conductive layer 200 , and the conductive plug 310 penetrates the isolation dielectric layer 430 .

[0082] In addition, it should be noted that, in this embodiment, a gap 600a is formed in the portion of the cover layer 600 corresponding to the recess 500a. However, in other embodiments, a gap may be formed between the cover layer 600 and the insulating filling layer, for example, a gap may be formed between the cover layer 600 and the first insulating portion 510.

[0083] Embodiment 2

[0084] The difference from the first embodiment is that, in this embodiment, the insulating filling layer further includes a second insulating portion covering the bottom of the groove.

[0085] Figure 2 is a schematic diagram of a semiconductor structure in the second embodiment of the present invention, such as Figure 2 As shown, in this embodiment, the insulating filling layer 500 includes two first insulating parts 510 and a second insulating part 520 , wherein the first insulating part 510 covers the sidewall of the groove, and the second insulating part 520 covers the bottom of the groove.

[0086] Further, a gap (i.e., a first gap 510a) is formed between the second insulating portion 520 and the first insulating portion 510, and the first gap 510a between the first insulating portion 510 and the second insulating portion 520 extends from the corner where the bottom wall and the side wall of the groove are connected to each other toward the direction of the recess 500a. The first gap 510a, for example, extends obliquely upward from the corner. In this embodiment, the first gap 510a is formed between the two first insulating portions 510 and the second insulating portion 520 to relieve the internal stress of the insulating filling layer 500.

[0087] Continue to refer Figure 2 As shown, the bottom of the recess 500a further extends downward into the second insulating portion 520, that is, a pit is formed in the second insulating portion 520 corresponding to the portion between the two first insulating portions 510. In this way, the first gap 510a and the recess 500a can be connected to each other. In this embodiment, the first gap 510a is connected to the recess 500a on the side wall of the recess 500a, that is, the opening position of the first gap 510a exposed in the recess 500a is higher than the bottom position of the recess 500a.

[0088] The opening size of the recess 500a is larger than the opening size of the first gap 510a. Furthermore, the cover layer 600 fills the recess 500a and closes the opening of the first gap 510a, so that the first gap 510a between the first insulating part 510 and the second insulating part 520 can be retained.

[0089] It should be noted that, in this embodiment, the groove extends transversely from the shielding layer 410 to the first isolation layer of the isolation sidewall 420 in the width direction. Also, the depth value H2 of the groove is not greater than the height value H1 of the gate conductive layer 200, and the recess 500a does not extend to the bottom of the groove, so that the depth value of the recess 500a is smaller accordingly. Therefore, compared with the first embodiment, the depth-to-width ratio of the recess 500a in this embodiment is smaller, and at this time, for example, no gap is formed in the portion of the cover layer 600 corresponding to the recess 500a.

[0090] Embodiment 3

[0091] The difference from the second embodiment is that, in this embodiment, the depth value H2 of the groove is greater than the height value H1 of the gate conductive layer, so that the groove has a larger aspect ratio and the aspect ratio of the depression can be increased accordingly, so that a gap can also be formed in the part of the cover layer corresponding to the depression.

[0092] Figure 3is a schematic diagram of a semiconductor structure in Embodiment 3 of the present invention, such as Figure 3 As shown, in this embodiment, the depth of the groove extending downward in the shielding layer 410 in the height direction is lower, so that the depth value H2 of the groove is greater than the height value of the gate conductive layer H1, thereby making the groove have a larger aspect ratio.

[0093] Accordingly, the depression 500a between the two first insulating parts 510 can have a larger aspect ratio. In this way, the portion of the cover layer 600 filled in the depression 500a can form a gap 600a. Similar to the first embodiment, the bottom of the depression 500a can further extend into the second insulating part 520, thereby facilitating further increasing the aspect ratio of the depression 500a.

[0094] That is, in this embodiment, for grooves with a larger aspect ratio, the filled insulating material can include two first insulating parts 510, a second insulating part 520 and a partial covering layer 600, and a gap 510a is formed between adjacent first insulating parts 510 and second insulating parts 520, and a gap 600a is also formed in the part of the covering layer 600 filled in the groove, thereby further improving the stress resistance of the insulating material filled in the groove.

[0095] Embodiment 4

[0096] The difference from the third embodiment is that in this embodiment, the recess does not extend to the second insulating portion, and the two first insulating portions are close to each other in the middle area of ​​the recess and a gap is formed.

[0097] Figure 4 is a schematic diagram of a semiconductor structure in a fourth embodiment of the present invention, such as Figure 4 As shown, a gap (i.e., a second gap 520a) is also formed between the two first insulating parts 510, and the second gap 520a located between the two first insulating parts 510 extends along the height direction below the recess 500a. That is, the top of the second gap 520a is connected to the recess 500a.

[0098] In this embodiment, the gap between the first insulating portion 510 and the second insulating portion 520 (ie, the first gap 510 a ) extends obliquely upward from the corner of the groove and communicates with the bottom of the second gap 520 a .

[0099] Continue to refer Figure 4As shown, the cover layer 600 fills the recess 500a and closes the top opening of the second gap 520a. That is, the second gap 520a between the two first insulating parts 510 and the first gap 510a between the first insulating part 510 and the second insulating part 520 can be retained to achieve stress release of the insulating material filled in the groove.

[0100] It should be noted that, compared with the third embodiment, the recess 500a in this embodiment does not extend downward to the second insulating portion 520, so that the recess 500a has a smaller aspect ratio, and further, no gap is formed in the portion of the cover layer 600 corresponding to the recess 600a.

[0101] To sum up, in the semiconductor structure as described above, the insulating filling layer filled in the groove includes at least two insulating parts. Compared with using only one larger insulating material to fill the groove, using multiple insulating parts to fill the groove will be more conducive to achieving stress release of the insulating material filled in the groove, thereby alleviating the problem of the insulating material filled in the groove damaging adjacent semiconductor devices due to high-intensity internal stress.

[0102] Furthermore, the insulating material filled in the groove can be formed with gaps (for example, gaps are formed between adjacent insulating parts). In this way, the gaps can be used to further release the stress of each insulating part, thereby more effectively relieving the internal stress of the insulating material in the groove.

[0103] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0104] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0105] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0106] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, wherein at least one semiconductor device and an interlayer dielectric layer are formed in the substrate, and the interlayer dielectric layer covers the semiconductor device; at least two interconnect structures, the interconnect structures comprising contact plugs and contact pads, the contact plugs penetrating the interlayer dielectric layer and extending to the semiconductor device, the contact pads covering the tops of the contact plugs and extending to cover a portion of the top surface of the interlayer dielectric layer; as well as, A groove located between adjacent contact pads, the groove further extending downward and stopping in the interlayer dielectric layer; as well as, an insulating filling layer, filled in the groove, and comprising at least two insulating parts; The semiconductor device includes a gate conductive layer formed on the top surface of the substrate and a first source / drain region and a second source / drain region formed in the substrate, the first source / drain region and the second source / drain region are respectively located on both sides of the gate conductive layer, the interlayer dielectric layer includes a shielding layer covering the top surface of the gate conductive layer and a sidewall structure covering the sidewalls of the gate conductive layer and the shielding layer, the groove extends downward from between adjacent contact pads to the shielding layer in the height direction, and the groove extends laterally from the shielding layer to the sidewall structure in the width direction.

2. The semiconductor structure according to claim 1, wherein: The insulating filling layer comprises at least two first insulating parts, the two first insulating parts cover two opposite side walls of the groove, and the two first insulating parts define a middle area recessed in the groove; Furthermore, the semiconductor structure further includes a capping layer, wherein the capping layer covers the contact pad and the insulating filling layer and fills the recess.

3. The semiconductor structure according to claim 2, wherein: The bottom of the depression extends to the bottom of the groove, the covering layer fills the depression and extends to the bottom of the groove, and a gap is formed in a portion of the covering layer corresponding to the depression.

4. The semiconductor structure according to claim 2, wherein: The depth of the groove is not greater than the height of the gate conductive layer, and the width of the groove is greater than the width of the gate conductive layer.

5. The semiconductor structure according to claim 2, wherein: The insulating filling layer also includes a second insulating portion, which covers the bottom of the groove, and a gap is formed between the second insulating portion and the first insulating portion, and the gap extends from the corner where the bottom wall and the side wall of the groove are connected to each other toward the direction of the recess.

6. The semiconductor structure according to claim 5, characterized in that The bottom of the recess extends to the second insulating portion and connects the gap with the recess, and the covering layer fills the recess and closes the opening of the gap.

7. The semiconductor structure according to claim 5, characterized in that The depth of the groove is not greater than the height of the gate conductive layer.

8. The semiconductor structure according to claim 7, wherein: No void is formed in a portion of the cover layer corresponding to the recess.

9. The semiconductor structure according to claim 5, characterized in that The depth of the groove is greater than the height of the gate conductive layer.

10. The semiconductor structure according to claim 9, wherein: A gap is formed in a portion of the cover layer corresponding to the recess.

11. The semiconductor structure according to claim 2, wherein: A gap is formed between the two first insulating parts in a middle area of ​​the groove, and the gap extends along a height direction below the depression.

12. The semiconductor structure according to claim 11, wherein: The cover layer fills the recess and closes the top opening of the void.

13. The semiconductor structure according to claim 1, wherein: The interconnection structure is respectively arranged on the first source / drain region and the second source / drain region, and the contact pad corresponding to the first source / drain region and the contact pad corresponding to the second source / drain region extend laterally from both sides of the gate conductive layer toward the gate conductive layer.

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