Integrated chip and method of forming an integrated chip

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a phase change material disposed over a bottom electrode, and the phase change material is configured to change from a crystalline structure to an amorphous structure when the temperature changes. A top electrode is disposed over the upper surface of the phase change material. A hard mask is over the top electrode. A via is in electrical contact with the top surface of the top electrode. Further, a maximum width of the upper surface of the phase change material is less than a maximum width of the bottom surface of the phase change material. Wherein a bottom surface of the hard mask directly contacts the top surface of the top electrode, and wherein the bottom surface of the hard mask is narrower than the top surface of the top electrode.

Description

Technical Field

[0001] The present disclosure relates to phase change random access memory devices and methods of manufacturing the same. Background Art

[0002] Many modern electronic devices include electronic memory configured to store data. The electronic memory may be volatile or non-volatile memory. Volatile memory stores data while power is supplied, and non-volatile memory is capable of storing data when power is removed. Phase change random access memory (PCRAM) devices are a type of non-volatile memory and are promising candidates for next-generation non-volatile electronic memory because, compared to other commonly used non-volatile memories, PCRAM devices offer faster speed and lower power consumption while maintaining a low manufacturing cost. Summary of the Invention

[0003] One aspect of the present disclosure provides an integrated wafer including: a phase change material, a top electrode, and a via. The phase change material is disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure when the temperature changes. The top electrode is disposed over an upper surface of the phase change material. The via is in electrical contact with a top surface of the top electrode. Wherein, a maximum width of the upper surface of the phase change material is less than a maximum width of the bottom surface of the phase change material.

[0004] Another aspect of the present disclosure provides an integrated wafer including: a phase change material, a top electrode, a hard mask, and a via. The phase change material is disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure when the temperature changes. The top electrode is disposed over an upper surface of the phase change material. The hard mask is over the top electrode. The via is in electrical contact with a top surface of the top electrode. Wherein, a maximum width of the upper surface of the phase change material is less than a maximum width of the bottom surface of the phase change material. Wherein a bottom surface of the hard mask directly contacts the top surface of the top electrode, and wherein the bottom surface of the hard mask is narrower than the top surface of the top electrode.

[0005] Another aspect of the present disclosure provides an integrated wafer including: a phase change material, a top electrode, a polymer coating, and a hard mask. The phase change material is disposed over a bottom electrode and configured to change the structure of the phase change material between a substantially crystalline structure and a substantially amorphous structure when the temperature changes, wherein the phase change material has a topmost surface and a bottommost surface, and wherein a maximum width of the topmost surface is less than a maximum width of the bottommost surface. The top electrode is over the phase change material. The polymer coating is on an outer sidewall of the phase change material, wherein the polymer coating separates the phase change material from an interlayer dielectric layer. The hard mask is configured over the top electrode, wherein the polymer coating covers a top surface and an outer sidewall of the hard mask, and wherein a via extends through the polymer coating and the hard mask to directly contact the top electrode.

[0006] Another aspect of the present disclosure provides an integrated wafer, comprising: a phase change material layer, a top electrode, a hard mask, a via hole, and a polymer coating. The phase change material layer is disposed above the bottom electrode and configured to change its structure between a crystalline structure and an amorphous structure when the temperature changes, wherein the phase change material layer has a topmost surface and a bottommost surface, and wherein the maximum width of the topmost surface is smaller than the maximum width of the bottommost surface. The top surface is above the phase change material layer. The hard mask is disposed above the top electrode. The via hole electrically extends through the hard mask to contact the top surface of the top electrode. The polymer coating is on the outer sidewalls of the phase change material layer, the top electrode, and the hard mask. Wherein the phase change material layer has an upper peripheral portion that is higher than the bottom surface of the top electrode and lower than the top surface of the top electrode.

[0007] Another aspect of the present disclosure provides a method of forming an integrated wafer, comprising: depositing a phase change material layer above a bottom electrode, wherein the phase change material layer is configured to change the degree of crystallization when the temperature changes; depositing a top electrode layer above the phase change material layer; depositing a hard mask layer above the top electrode layer; patterning the top electrode layer and the hard mask layer to remove the outsides of the top electrode layer and expose the outsides of the phase change material layer; and performing isotropic etching to remove portions of the phase change material layer that are not covered by the top electrode layer and the mask layer, wherein the isotropic etching removes these portions of the phase change material layer faster than it removes these outsides of the top electrode layer and the mask layer.

[0008] Another aspect of the present disclosure provides a method of forming an integrated wafer, comprising: depositing a phase change material layer above a bottom electrode, wherein the phase change material layer is configured to change the degree of crystallization when the temperature changes; depositing a top electrode layer above the phase change material layer; patterning the top electrode layer to remove the outsides of the top electrode layer and expose the outsides of the phase change material; and performing isotropic etching using an inert gas selective to the phase change material layer, wherein the isotropic etching comprises a first step followed by a second step, wherein the first step is performed at a first pressure, and wherein the second step is performed at a second pressure, the second pressure being less than the first pressure.

[0009] Another aspect of the present disclosure provides a method of forming an integrated wafer, comprising: forming a phase change material layer above a bottom electrode; forming a top electrode layer above the phase change material layer; forming a hard mask layer above the top electrode layer; patterning the top electrode layer and the hard mask layer to expose the outsides of the phase change material layer; performing isotropic etching selective to the phase change material layer, wherein the isotropic etching comprises a plurality of cycles, and wherein each cycle comprises a first step performed at a first pressure followed by a second step performed at a second pressure, the second pressure being different from the first pressure; and forming a polymer coating above the hard mask layer, the top electrode layer, and the phase change material layer. Description of the Drawings

[0010] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figures 1A to 1C Illustrate some embodiments of an integrated chip having a phase change random access memory (PCRAM) device, the device including a trapezoidal structure and a polymer coating;

[0012] Figures 2A to 2B Illustrate some embodiments of an integrated chip having a phase change random access memory device including a trapezoidal structure;

[0013] Figures 3 to 15 Illustrate a cross-sectional view of some embodiments of a method of forming an integrated chip having a phase change random access memory device, the phase change random access memory device including a trapezoidal structure and a polymer coating;

[0014] Figure 16 Illustrate a flowchart of some embodiments of a method of forming an integrated chip having a phase change random access memory device, the phase change random access memory device including a trapezoidal structure and a polymer coating.

[0015]

Description of Symbols

[0016] 100A1: Cross-sectional view

[0017] 100A2: Top view

[0018] 100B: Cross-sectional view

[0019] 100C: Cross-sectional view

[0020] 101: Phase change random access memory cell

[0021] 102: Substrate

[0022] 104: Transistor

[0023] 104a: Source / drain region

[0024] 104b: Source / drain region

[0025] 104c: Conductive gate

[0026] 104d: Gate oxide layer

[0027] 106: Dielectric structure

[0028] 106a: Lower part

[0029] 106b: Upper part

[0030] 108: Through hole

[0031] 109: Interconnection layer

[0032] 110: Interconnecting wire

[0033] 112: Insulating layer

[0034] 114: Bottom electrode

[0035] 116: Barrier layer

[0036] 118: Phase change material layer

[0037] 118s: Outer sidewall

[0038] 118t: Topmost surface

[0039] 120: Top electrode

[0040] 120b: Bottommost surface

[0041] 120t: Top surface

[0042] 122: Hard mask

[0043] 122t: Top surface

[0044] 124: Polymer coating

[0045] 126: Through hole

[0046] 127: Encapsulation layer

[0047] 128: Etch stop layer

[0048] 130: Upper peripheral part

[0049] 140: Wire

[0050] 200A: Cross-sectional view

[0051] 200B: Top view

[0052] 300: Cross-sectional view

[0053] 400: Cross-sectional view

[0054] 428: Etch stop material

[0055] 500: Cross-sectional view

[0056] 512: Insulating material

[0057] 600: Cross-sectional view

[0058] 602: Opening

[0059] 700: Cross-sectional view

[0060] 800: Cross-sectional view

[0061] 818: Deposited phase change material layer

[0062] 820: Top electrode layer

[0063] 822: Hard mask layer

[0064] 900: Cross-sectional view

[0065] 902: Organic mask

[0066] 904: Photoresist

[0067] 1000: Cross-sectional view

[0068] 1002: Organic mask

[0069] 1022: Hard mask

[0070] 1020: Top electrode

[0071] 1100: Cross-sectional view

[0072] 1200A: Cross-sectional view

[0073] 1200B: Cross-sectional view

[0074] 1200C: Cross-sectional view

[0075] 1202: Isotropic etching

[0076] 1218: Preliminary phase change material layer

[0077] 1220: Preliminary top electrode

[0078] 1222: Preliminary hard mask

[0079] 1300A: Cross-sectional view

[0080] 1300B1: Cross-sectional view

[0081] 1300B2: Top view

[0082] 1302: Line

[0083] 1400: Cross-sectional view

[0084] 1406: Upper interlayer dielectric layer

[0085] 1500: Cross-sectional view

[0086] 1600: Method

[0087] 1602: Action

[0088] 1604: Action

[0089] 1606: Action

[0090] 1608: Action

[0091] 1610: Action

[0092] 1612: Action

[0093] 1614: Action

[0094] 1616: Action

[0095] 2218: Intermediate phase change material layer

[0096] 2220: Intermediate top electrode

[0097] 2222: Intermediate hard mask

[0098] A: Arrow

[0099] B - B’: Line

[0100] C: Angle

[0101] D: Angle

[0102] E: Angle

[0103] d 1 : Distance

[0104] W b : Bottom surface

[0105] W t : Top surface Detailed implementation manners

[0106] The subsequent disclosures provide many different implementation manners or embodiments to implement different features of the provided subject matter. The following describes specific embodiments of components and configurations to simplify the present disclosure. These are of course only embodiments and are not intended to be limiting. For example, in the subsequent description, forming a first feature above a second feature or on top of the second feature may include an embodiment where the first and second features are formed in direct contact, and may also include an embodiment where additional features may be formed between the first and second features, so the first and second features may not be in direct contact. In addition, the present disclosure may repeat numerals and / or letters in various embodiments. Such repetition is for simplicity and clarity and does not imply a relationship between the various embodiments and / or configurations discussed.

[0107] In addition, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, may be used herein to facilitate describing the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or otherwise), and the spatially relative terms used herein may be interpreted accordingly.

[0108] A phase change random access memory (PCRAM) device includes a phase change material (PCM) layer disposed between a top electrode and a bottom electrode. The phase change material layer includes a structure that changes phase based on, for example, a temperature change program. These phases may be substantially crystalline, amorphous, or in between. For example, when heated to a very high temperature, the phase change material layer has an amorphous structure and remains amorphous when rapidly cooled. When heated to an intermediate temperature, the phase change material layer may form a crystalline structure and remains crystalline when cooled. Heating of the phase change material layer may be performed via Joule heating. Joule heating involves heat generated during the flow of an electric current through a conductive material. When an electric current flows through the bottom electrode susceptible to Joule heating, the temperature of the phase change material layer increases. When the phase of the phase change material layer changes from crystalline to amorphous, for example, due to a heating and cooling program, the resistance of the phase change material layer changes from a low resistance to a high resistance. The high or low resistance of the phase change material layer corresponds to the bit value of data storage.

[0109] A phase change random access memory device may be fabricated by forming a phase change material layer over a bottom electrode. Subsequently, a top electrode is formed over the phase change material layer, and then a hard mask is formed over the top electrode. The hard mask and the top electrode layer are patterned. Using the hard mask and the top electrode as a mask, the phase change material layer is then patterned such that the hard mask, the top electrode, and the phase change material layer have substantially the same width.

[0110] The phase change material layer is often patterned using dry etching (e.g., halogen gas etching), where the halogen gas reacts with the sidewalls of the phase change material layer and damages the sidewalls of the phase change material layer. If the phase change material layer already has damaged sidewalls, the heat dissipation path may become non-linear. The heat dissipation path is the distance between the heat source (bottom electrode) and the interface between the sidewalls of the phase change material layer and the surrounding layer (e.g., encapsulation layer or interlayer dielectric (ILD) layer). Additionally, the sidewalls of the phase change material layer are often substantially vertical, resulting in a long heat dissipation path. Having a longer and non-linear heat dissipation path reduces the heat confinement within the phase change material layer. When the heat confinement is poor, the time and / or current required to change and maintain the phase of the phase change material layer increases, resulting in an increase in the switching speed and / or power consumption of the phase change random access memory device, respectively. Increasing the switching speed of the phase change random access memory device has a negative impact on the control of the phase change random access memory device.

[0111] In the present disclosure, a method and structure for manufacturing a phase change random access memory device are proposed to produce a highly controllable phase change random access memory device with fast switching speed and low power consumption. The new manufacturing method uses isotropic etching, which has high selectivity for the phase change material layer and eliminates damage to the sidewalls. Additionally, the isotropic etching results in a new structure of the phase change random access memory device that includes a phase change material layer having a trapezoidal-like structure. Further, the new method and structure may include a polymer coating over the outer sidewalls of the phase change material layer, the polymer coating configured to confine heat within the phase change material layer. The new manufacturing method and the corresponding phase change random access memory structure reduce the heat dissipation path, suppress heat dissipation, and thus increase the heat confinement within the phase change material layer, thereby providing a reliable phase change random access memory device with low power consumption.

[0112] Figure 1A Cross-sectional views 100A1 and corresponding top views 100A2 of some embodiments of an integrated wafer including phase change random access memory cells are shown.

[0113] The integrated wafer in cross-sectional view 100A1 includes phase change random access memory cells 101 disposed over a substrate 102. The phase change random access memory cells 101 include a phase change material (PCM) layer 118, which is separated from the substrate 102 by one or more lower interconnect layers 109 embedded within a lower portion 106a of a dielectric structure 106. The dielectric structure 106 often includes one or more interlayer dielectric (ILD) layers. In many embodiments, the one or more lower interconnect layers 109 include via holes 108 and interconnect lines 110, the via holes 108 and interconnect lines 110 configured to connect a bottom electrode 114 of the phase change random access memory cells 101 to a transistor 104 within the substrate 102.

[0114] The bottom electrode 114 may be embedded in an insulating layer 112 having one or more stacked dielectric materials. In some embodiments, the bottom electrode 114 is separated from the insulating layer 112 by a barrier layer 116 (e.g., a diffusion barrier layer). The phase change random access memory cell 101 further includes a phase change material layer 118 and a top electrode 120, the phase change material layer 118 is disposed on the bottom electrode 114, and the top electrode 120 is interposed between the phase change material layer 118 and the hard mask 122.

[0115] In some embodiments, a polymer coating 124 is disposed on the phase change material layer 118, the top electrode 120, and the hard mask 122. In some embodiments, the polymer coating 124 may also cover and contact the top surface of the insulating layer 112. Thus, the polymer coating 124 separates the phase change material layer 118 from the upper portion 106b of the dielectric structure 106. Due to the bias-free deposition process, the polymer coating 124 may have a uniform thickness over its entire length. The polymer coating 124 may include a material having a thermal conductivity lower than that of the phase change material layer 118 to inhibit heat dissipation and promote heat confinement within the phase change material layer 118. By promoting heat confinement, less joule heating is required to write data to the phase change random access memory cell 101, thereby allowing the phase change random access memory cell 101 to have low power consumption. In many embodiments, a via 126 extends through the upper portion 106b of the dielectric structure 106, the top of the polymer coating 124, and the top of the hard mask 122 to directly contact the top surface of the top electrode 120.

[0116] In many embodiments, the phase change material layer 118 has a trapezoid-like shape, where the top surface of the phase change material layer 118 is narrower than the bottom surface of the phase change material layer 118. The top surface and the bottom surface of the phase change material layer 118 may be connected via the slanted outer sidewalls 118s. Additionally, due to the residual effect of etching the phase change material layer 118, the top electrode 120 and the hard mask 122 may exhibit a trapezoid-like shape. In many embodiments, since the sidewalls of the hard mask 122 are directly exposed to the etching, the sidewalls of the hard mask 122 meet the top surface of the hard mask 122 with rounded corners. In some embodiments, the size of the bottom surface of the top electrode 120 may be equal to the size of the top surface of the phase change material layer 118. In other embodiments (not shown), the top surface of the phase change material layer 118 may be wider than the bottom surface of the top electrode 120. The trapezoid-like shaped phase change material layer 118 reduces the heat dissipation path, which is the distance between the bottom electrode 114 and the outer sidewalls of the phase change material layer 118. Arrow A shows one example of many heat dissipation paths. By reducing the heat dissipation path and increasing the thermal confinement within the phase change random access memory device, the reset (RESET) current of the phase change random access memory device is reduced, further reducing the power consumption of the phase change random access memory cell 101.

[0117] The top view 100A2 is illustrated by the section line B - B' of the sectional view 100A1. Line 140 shows the corresponding boundary of the polymer coating 124 between the sectional view 100A1 and the top view 100A2.

[0118] As shown, the lower portion of the via 126 is surrounded by the hard mask 122. Additionally, the polymer coating 124 surrounds the hard mask 122. In some embodiments, the hard mask 122 and the polymer coating 124 may have a circular shape. In other embodiments (not shown), the hard mask 122 and the polymer coating 124 may have different shapes (e.g., rectangular, square, etc.). Although the top electrode 120 is not visible in the top view 100A2 due to the upper portion 106b of the dielectric structure 106, the protruding bottom surface 120b of the top electrode 120 is shown. In some embodiments, due to the trapezoid-like shape of the top electrode 120, the diameter of the protruding bottom surface 120b of the top electrode 120 is larger than the diameter of the hard mask 122. In such embodiments, the polymer coating 124 may have sidewalls directly located above the protruding bottom surface 120b of the top electrode 120. In some additional embodiments (not shown), the polymer coating 124 may have sidewalls directly located above the top surface of the top electrode 120.

[0119] Figure 1B Illustrated Figure 1A is the enlarged sectional view 100B of the phase change random access memory cell 101.

[0120] In many embodiments, the phase change material layer 118 comprises a chalcogenide material, which is an alloy comprising a Group VI element in combination with a Group IV and / or Group V element. The phase change material layer 118 may comprise, for example, Ge 2 Sb 2 Te 5 (GST), ScSbTe, GeTe, InSb, Sb 2 Te 3 、Sb 70 Te 30 、GaSb, InSbTe, GaSeTe, SnSbTe 4 、InSbGe, AgInSbTe, Te 81 Ge 15 Sb 2 S 2 、GeSbTe, SnSbTe, GeSbSe, GeSbTe, etc. In many embodiments, the bottom surface and the top surface of the phase change material layer 118 are substantially planar. The bottom surface of the phase change material layer 118 meets the outer sidewall 118s of the phase change material layer 118 at an angle C. In order to achieve sufficient thermal confinement to reduce power consumption, the angle C may be an acute angle. For example, in some embodiments, in order to achieve sufficient thermal confinement to reduce power consumption, the angle C may range between about 45 degrees and about 75 degrees. In some additional embodiments, in order to achieve sufficient thermal confinement to reduce power consumption, the angle C may range between about 45 degrees and about 60 degrees. In some embodiments, the outer sidewall 118s of the phase change material layer 118 is substantially linear from a cross-sectional view, as shown in cross-sectional view 100B.

[0121] In some embodiments, the maximum width of the bottom surface W b of the phase change material layer 118 may range between about 100 nanometers and about 200 nanometers, and the maximum width of the top surface W t of the phase change material layer 118 may range between about 40 nanometers and about 100 nanometers. Further, in some embodiments, the height of the phase change material layer 118 may range between about 20 nanometers and about 40 nanometers. In order to achieve sufficient thermal confinement to reduce power consumption, the ratio of the maximum width of the bottom surface W b to the maximum width of the top surface W t may range between about 0.2 and about 0.5. In some embodiments, the power consumption is reduced due to a reduction of up to about 20% in the reset current. In some embodiments, the reset current may range between about 0.73 milliamps and about 0.80 milliamps.

[0122] In many embodiments, the polymer coating 124 is a carbonaceous material having a lower thermal conductivity than the material of the phase change material layer 118. In some embodiments, the polymer coating 124 comprises carbon and hydrogen. For example, the polymer coating may be CH x polymer, where x ranges between 2 and 4. In some embodiments, the thickness of the polymer coating 124 may range between about 10 angstroms and about 15 angstroms.

[0123] Furthermore, in some embodiments (not shown), the phase change random access memory cell 101 may be inverted such that the top surface W t of the phase change material layer 118 is wider than the bottom surface W b of the phase change material layer 118. When the phase change random access memory cell 101 is inverted, the bias voltages applied to the top electrode 120 and the bottom electrode 114 are also inverted to effectively heat the phase change material layer 118.

[0124] Figure 1C Shows Figure 1A a cross-sectional view 100C of another embodiment of the phase change random access memory cell 101.

[0125] In addition to the upper peripheral portion 130 of the phase change material layer 118, Figure 1C Contains Figure 1B the same features as the cross-sectional view 100B. Due to the redeposition effect in the etching of the phase change material layer 118, the upper peripheral portion 130 may be included in some embodiments. The upper peripheral portion 130 extends above the interface where the top electrode 120 contacts the phase change material layer 118. In some embodiments, when the phase change material layer 118 includes the upper peripheral portion 130, the topmost surface 118t of the phase change material layer 118 is higher than the bottommost surface 120b of the top electrode 120, and the distance between the topmost surface 118t and the bottommost surface 120b is d 1 . In some embodiments, the distance d 1 may be less than the height of the top electrode 120. In some embodiments (not shown), the distance d 1 may be greater than the height of the top electrode 120. In some embodiments, the top electrode 120 may have a height ranging between about 100 angstroms and about 300 angstroms.

[0126] Figure 2A Shows a cross-sectional view 200A of another embodiment of an integrated chip including a phase change random access memory cell.

[0127] Figure 2A Contains features similar to Figure 1A except that Figure 2A it does not include a polymer coating (Figure 1A (124). In addition, the embodiment in the cross-sectional view 200A includes an etch stop layer 128 interposed between the insulating layer 112 and the interconnect line 110. The etch stop layer 128 separates the lower portion 106a of the dielectric structure 106 from the upper portion 106b of the dielectric structure 106. The bottom electrode 114 and the barrier layer 116 extend through the etch stop layer 128 such that the bottom electrode 114 is coupled to the interconnect line 110. In addition, in some embodiments, the insulating layer 112 has substantially the same width as the bottom surface of the phase change material layer 118. In other embodiments, the insulating layer 112 may extend beyond the opposite sides of the phase change material layer 118. Similar to Figure 1A the phase change material layer 118 in the cross-sectional view 100A1, the phase change material layer 118 in the cross-sectional view 200A has a trapezoidal shape to suppress heat dissipation via a relatively short heat dissipation path (e.g., the heat dissipation path is shorter than that of a phase change material layer with a rectangular cross-sectional shape).

[0128] In addition, there may be a lattice mismatch at the boundary between the outer sidewalls 118s of the phase change material layer 118 and the surrounding layers. In some embodiments, the surrounding layer may be the dielectric structure 106, while in other embodiments, the surrounding layer may be the encapsulation layer 127. In some embodiments, the encapsulation layer 127 may separate the dielectric structure from the phase change material layer 118. The encapsulation layer 127 may include silicon nitride, silicon oxide, etc. The dielectric structure 106 may contain nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxides (e.g., carbon-doped oxide, SiCOH), or similar compounds. In some embodiments, the encapsulation layer 127 and the dielectric structure 106 contain the same material, while in other embodiments, the encapsulation layer 127 and the dielectric structure 106 contain different materials. In some embodiments, the lattice mismatch between the phase change material layer 118 and the encapsulation layer 127 may be caused by the etching used during the patterning of the phase change material layer 118. The lattice mismatch suppresses heat dissipation via phonon transport, promotes heat confinement within the phase change material layer 118, thereby reducing the power consumption of the phase change random access memory cell.

[0129] Figure 2B Some embodiments of an integrated wafer including phase change random access memory cells are illustrated, a top view 200B along Figure 2A line B-B'.

[0130] The top view 200B does not include Figure 2Athe dielectric structure 106 or the encapsulation layer 127. As shown, the lower part of the via 126 is surrounded by the hard mask 122. In addition, from the top view 200B, when the dielectric structure 106 is ignored, the top electrode 120 and the phase change material layer 118 are visible because of their trapezoidal shape.

[0131] Figures 3 to 15 Cross-sectional views 300 to 1500 illustrate some embodiments of a method of forming an integrated wafer having phase change random access memory cells. Although Figures 3 to 15 this is a description of a method, it should be understood that Figures 3 to 15 the structures disclosed herein are not limited to such a method, but may be separate structures independent of this method.

[0132] As Figure 3 shown in the cross-sectional view 300, a substrate 102 is provided. In various embodiments, the substrate 102 may comprise any type of semiconductor body (e.g., silicon / complementary metal oxide semiconductor (CMOS) body, SiGe, SOI, etc.), such as a semiconductor wafer or one or more die on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or associated therewith.

[0133] A transistor 104 is formed within the substrate 102, including a conductive gate 104c on the substrate 102, and the conductive gate 104c is interposed between doped source / drain regions 104a / 104b. A gate oxide layer 104d is disposed between the substrate 102 and the conductive gate 104c. Then, one or more lower interconnect layers 109 including vias 108 and interconnect lines 110 are formed on the transistor 104 and within the lower part 106a of the dielectric structure. The interconnect vias 108 and interconnect lines 110 often comprise a conductive metal, such as tungsten, copper, etc. One or more interconnect layers 109 are often formed using a damascene process (e.g., a single damascene process or a dual damascene process). One or more interconnect layers 109 are coupled to one of the source / drain regions 104a / 104b.

[0134] As Figure 4 shown in the cross-sectional view 400, in some embodiments, an etch stop material 428 is deposited on the interconnect line 110 and the lower part 106a of the dielectric structure. The etch stop material 428 may be deposited via a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the etch stop material 428 may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), etc. In some embodiments, the etch stop material 428 may have a height ranging from about 10 nanometers to about 30 nanometers.

[0135] As Figure 5As shown in the cross-sectional view 500, an insulating material 512 is deposited over the etch stop material 428. The insulating material 512 may be deposited via a vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the insulating material 512 comprises the same material as the lower portion 106a of the dielectric structure. In other embodiments, the insulating material 512 may be a silicon-rich oxide, while the lower portion 106a of the dielectric structure comprises a different dielectric material, e.g., a nitride (silicon nitride), a carbide (e.g., silicon carbide), etc. In some embodiments, the insulating material 512 may have a height ranging between approximately 30 nanometers and approximately 60 nanometers.

[0136] As Figure 6 shown in the cross-sectional view 600, the insulating material ( Figure 5 of 512) and the etch stop material ( Figure 5 of 428) are patterned via lithography and etching to form openings 602 in the insulating layer 112 and the etch stop layer 128. The openings 602 extend through the etch stop layer 128 to expose a portion of the interconnect 110. In some embodiments, the openings 602 may be at least 40 nanometers wide. Due to residual etch effects, the openings 602 may also have tapered sidewalls.

[0137] As Figure 7 shown in the cross-sectional view 700, a bottom electrode 114 is formed within the opening ( Figure 6 of 602) in the insulating layer 112. The bottom electrode 114 comprises a conductive material capable of joule heating. The bottom electrode 114 may comprise copper, titanium nitride, tantalum nitride, etc. The bottom electrode 114 may be surrounded by a barrier layer 116 to prevent diffusion into the insulating layer 112. The barrier layer 116 may comprise, for example, tantalum, tantalum nitride, or titanium nitride. In many embodiments, the bottom electrode 114 is deposited over the insulating layer 112 to fill the opening 602. A deposition process and / or an electroplating process (e.g., electroplating, electroless plating, etc.) may be used to form the bottom electrode 114. Then, a planarization process (e.g., a chemical mechanical planarization process) may be performed to remove the excess material of the bottom electrode 114 such that the upper surface of the bottom electrode 114 is substantially planar and such that the upper surface of the insulating layer 112 is uncovered.

[0138] As Figure 8As shown in the cross-sectional view 800, a deposited phase change material (PCM) layer 818, a top electrode layer 820, and a hard mask layer 822 are sequentially deposited over the bottom electrode 114 and the insulating layer 112. Accordingly, the deposited phase change material layer 818 separates the top electrode layer 820 from the bottom electrode 114. The deposited phase change material layer 818 may be deposited via physical vapor deposition (PVD) or sputtering. In some embodiments, the deposited phase change material layer 818 may have a height ranging between approximately 250 angstroms and approximately 350 angstroms. The top electrode layer 820 comprises a conductive material such as copper, aluminum copper, titanium nitride, tantalum nitride, etc. In some embodiments, the top electrode layer 820 may have a height ranging between approximately 150 angstroms and approximately 200 angstroms. The hard mask layer 822 is deposited over the top electrode layer 820. The hard mask layer 822 may comprise silicon, oxide, silicon nitride, silicon oxynitride, silicon carbide, etc. In some embodiments, the hard mask layer 822 may have a height ranging between approximately 350 angstroms and approximately 400 angstroms.

[0139] As Figure 9 shown in the cross-sectional view 900, an organic mask 902 and a covering photoresist 904 are deposited over the hard mask layer 822. In many embodiments, the photoresist 904 and the organic mask 902 are deposited using a spin coating process, a deposition process, etc. The organic mask 902 may be a bottom anti-reflective coating (BARC), an anti-reflective coating (ARC), a bottom photoresist coating, etc. The photoresist 904 comprises a photosensitive material. Using photolithography, the photoresist 904 is patterned to cover the central portions of the hard mask layer 822 and the top electrode layer 820. After patterning, the photoresist 904 is directly above the bottom electrode 114, as shown in the cross-sectional view 900. In many embodiments, the photoresist 904 is patterned to be wider than the bottom electrode 114. Accordingly, in most embodiments, the photoresist 904 has a width greater than 40 nanometers. In some embodiments, the organic mask 902 may have a height ranging between approximately 250 angstroms to approximately 450 angstroms, and the photoresist 904 may have a height ranging between approximately 1200 angstroms and approximately 1300 angstroms.

[0140] As Figure 10 shown in the cross-sectional view 1000, according to the photoresist 904, the top electrode layer ( Figure 9 of 820), and the hard mask layer ( Figure 9 of 822), in the organic mask ( Figure 9On the 902), a three-step etching process is performed to form a patterned organic mask 1002, followed by a patterned hard mask 1022, and then a patterned top electrode 1020, respectively. The etching process is carried out within a process chamber and may use a plasma etchant. In some embodiments, the plasma etchant may be formed as a transformer coupled plasma (TCP) via a transformer coupled plasma source. In other embodiments, the plasma etchant may be formed as a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), etc.

[0141] In the first step of the etching process, for the organic mask ( Figure 9 of 902), a patterned organic mask 1002 is formed according to the photoresist 904. In some embodiments, the first step of the etching process is carried out at a pressure ranging from about 1 millitorr to about 100 millitorr within the process chamber. In some embodiments, the first step of the etching process may use a plasma etchant formed via a transformer coupled plasma source at a power ranging from about 200 watts to about 800 watts. In some embodiments, a bias voltage is applied to a wafer chuck (not shown), and the wafer chuck is configured to hold the substrate 102. In many embodiments, the bias voltage used ranges from about 100 volts to about 500 volts. In various embodiments, the etching gas used in the first step of the etching process may include the following: oxygen, with a flow rate ranging from about 1 standard cubic centimeter per minute to about 20 standard cubic centimeters per minute; chlorine, with a flow rate ranging from about 5 standard cubic centimeters per minute to about 50 standard cubic centimeters per minute; helium, with a flow rate ranging from about 100 standard cubic centimeters per minute to about 300 standard cubic centimeters per minute; and / or CH 2 F 2 gas, with a flow rate ranging from about 10 standard cubic centimeters per minute to about 100 standard cubic centimeters per minute.

[0142] In the second step of the etching process, for the hard mask layer ( Figure 9 of 822), a patterned hard mask 1022 is formed according to the photoresist 904. In some embodiments, the second step of the etching process is carried out at a pressure ranging from about 1 millitorr to about 100 millitorr. In some embodiments, the power of the transformer coupled plasma source is set at a power ranging from about 200 watts to about 1000 watts. In some embodiments, the bias voltage is set to a voltage ranging from about 100 volts to about 700 volts. In various embodiments, the etching gas used in the second step of the etching process may contain the following: SF 6, whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 80 standard cubic centimeters per minute; CF 4 , whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 50 standard cubic centimeters per minute; helium, whose flow rate ranges between approximately 100 standard cubic centimeters per minute and approximately 300 standard cubic centimeters per minute; and / or CH 2 F 2 gas, whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 100 standard cubic centimeters per minute.

[0143] The third and final step in the etching process is for the top electrode layer ( Figure 9 of 820), to form the patterned top electrode 1020. In some embodiments, the third step of the etching process is carried out at a pressure ranging between approximately 1 millitorr and approximately 100 millitorr. In some embodiments, the transformer-coupled plasma source power is set to a power ranging between approximately 200 watts and approximately 1000 watts. In some embodiments, the bias voltage is set to a voltage ranging from approximately 100 volts to approximately 900 volts. In various embodiments, the etching gas used in the third step of the etching process may include the following: chlorine gas, whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 200 standard cubic centimeters per minute; CF 4 , whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 100 standard cubic centimeters per minute; argon gas, whose flow rate ranges between approximately 50 standard cubic centimeters per minute and approximately 500 standard cubic centimeters per minute; and / or HBr gas, whose flow rate ranges between approximately 10 standard cubic centimeters per minute and approximately 100 standard cubic centimeters per minute.

[0144] As Figure 11 shown in the cross-sectional view 1100, the photoresist ( Figure 10 of 904) and the patterned organic mask ( Figure 10 of 1002) are stripped, leaving the patterned top electrode 1020 and the patterned hard mask 1022. The deposited phase change material layer 818 is wider than the patterned top electrode 1020 and the patterned hard mask 1022.

[0145] As Figure 12A shown in the cross-sectional view 1200A of, in the deposited phase change material layer ( Figure 11Isotropic etching 1202 is performed on the 818). In some embodiments, isotropic etching 1202 is performed at a pressure ranging from about 1 millitorr to about 100 millitorr. In some embodiments, the transformer-coupled plasma source power is set to a power ranging from about 100 watts and about 800 watts. In some embodiments, the bias voltage is set to a voltage ranging from about 100 volts to about 800 volts. In various embodiments, the etching gas used in isotropic etching 1202 may include the following: argon, with a flow rate ranging from about 50 standard cubic centimeters per minute and about 1000 standard cubic centimeters per minute; nitrogen, with a flow rate ranging from about 20 standard cubic centimeters per minute and about 5000 standard cubic centimeters per minute; and / or helium, with a flow rate ranging from about 100 standard cubic centimeters per minute and about 2000 standard cubic centimeters per minute.

[0146] Isotropic etching 1202 undergoes a series of cycles or pulses to vary the pressure within the process chamber such that the pressure is between a high pressure and a low pressure. A single "cycle" includes a high pressure step followed by a low pressure step. In some embodiments, isotropic etching 1202 may undergo up to 10 cycles or more. The number of cycles and parameters of isotropic etching 1202 depend on the desired final shape of the deposited phase change material layer 818 to achieve sufficient thermal confinement within the phase change material layer 818 to reduce power consumption. The high pressure cycle includes, for example, introducing pure argon at high pressure in the process chamber up to a pressure of about 100 millitorr. The high pressure cycle etches and removes material from the sidewalls of the deposited phase change material layer 818. The low pressure cycle uses a low pressure, as low as about 1 millitorr, and utilizes, for example, heavy argon ion bombardment. The low pressure cycle may result in re-deposition of the phase change material on the sidewalls of the phase change random access memory structure. This is because the phase change material is a polymer or polymer-like material and does not evaporate during etching. However, in many embodiments, the high pressure cycle etches the phase change material faster than the low pressure cycle re-deposits the phase change material such that there is substantially no deposition of the phase change material on the sidewalls. In many embodiments, the low pressure step often utilizes a low enough pressure to effectively inhibit re-deposition of the phase change material.

[0147] Figure 12ACross-sectional view 1200A is an exemplary view of a phase change random access memory structure during an early stage of isotropic etching 1202. Cross-sectional view 1200A shows a preliminary phase change material layer 1218, a preliminary top electrode 1220, and a preliminary hard mask 1222. The preliminary phase change material layer 1218 has a bottom surface that is wider than the top surface. The outer sidewalls of the preliminary phase change material layer 1218 are inclined and connect the bottom surface to the top surface. In some embodiments, the outer sidewalls of the preliminary phase change material layer 1218 are non-linear when viewed in cross-section. In other embodiments, as in cross-sectional view 100B, the outer sidewalls of the preliminary phase change material layer 1218 are substantially linear. The top surface of the preliminary phase change material layer 1218 is substantially centered above the bottom surface of the preliminary phase change material layer 1218. The preliminary hard mask 1222 has angled upper corners. In other embodiments, the preliminary hard mask 1222 may have rounded upper corners. In some embodiments, the preliminary hard mask 1222 is substantially free of a patterned hard mask 1022 that is different from Figure 11 the patterned hard mask 1022.

[0148] In many embodiments, isotropic etching 1202 may include argon and have a high selectivity for the deposited phase change material layer 818. In other embodiments, a different inert gas may be used instead of argon. Inert gases are used because they do not react and damage the sidewalls of the deposited phase change material layer 818. For example, in some embodiments, the selectivity ratio of the patterned hard mask 1022 to the patterned top electrode 1020 to the deposited phase change material layer 818 is approximately 1:2:5.

[0149] As Figure 12B shown in cross-sectional view 1200B, an exemplary embodiment from isotropic etching 1202 is shown during a mid-stage later than Figure 12A cross-sectional view 1200A but still during the occurrence of isotropic etching 1202. The width of the intermediate phase change material layer 2218 has decreased, and the upper surface of the insulating layer 112 is exposed. The intermediate phase change material layer 2218 may have non-linear outer sidewalls. The intermediate top electrode 2220 has inclined or rounded upper corners. Due to the residual effect of isotropic etching 1202, a portion of the intermediate hard mask 2222 has been removed, and the intermediate hard mask 2222 begins to exhibit a shape more like a trapezoid than the shape of the preliminary hard mask 1222. The upper surface of the intermediate phase change material layer 2218 is wider than the bottom surface of the intermediate top electrode 2220.

[0150] As Figure 12C shown in cross-sectional view 1200C, for some embodiments, the phase change material layer 118, the top electrode 120, and the hard mask 122 after completion of isotropic etching 1202 are shown. The phase change material layer 118 generally has a shape as Figure 12CThe shape shown is trapezoidal and has a topmost surface that is substantially flush with the bottommost surface of the top electrode 120. In some embodiments, after the isotropic etch 1202, the topmost surface of the phase change material layer 118 is wider than the bottommost surface of the top electrode 120. The phase change material layer 118 may have non-linear outer sidewalls 118s as viewed in a cross-sectional view, such as shown in cross-sectional view 1200C. The bottom surface of the phase change material layer 118 meets the outer sidewalls 118s of the phase change material layer 118 at an angle C. In various embodiments, the angle C may range between approximately 45 degrees and approximately 75 degrees. The top electrode 120 may have outer sidewalls that meet the bottom surface of the top electrode 120 at an angle D. The hard mask 122 may have outer sidewalls that meet the bottom surface of the hard mask 122 at an angle E. In some embodiments, the angles C, D, and E are substantially the same. In other embodiments, as shown in cross-sectional view 1200C, the angles D and E may each be less than the angle C.

[0151] In addition, in some embodiments, the phase change material layer 118 may have a substantially uniform lattice structure throughout the trapezoidal-like shape, with no damage on the outermost sidewalls of the phase change material layer 118. In some embodiments, the phase change material layer 118 may have an upper surface that is wider than the bottom surface of the top electrode 120. In other embodiments, the low-pressure step of the isotropic etch 1202 redeposits the phase change material faster than the high-pressure step of the isotropic etch 1202 etches the phase change material, resulting in a phase change material layer 118 having an upper peripheral portion 130 as Figure 1C shown.

[0152] As Figure 13A shown in cross-sectional view 1300A of, a polymer coating 124 is deposited over the hard mask 122, the top electrode 120, and the phase change material layer 118. The polymer coating 124 may comprise a carbon-like material and has a lower thermal conductivity than the material of the phase change material layer 118. Thus, the polymer coating 124 promotes heat confinement within the phase change material layer 118. For example, the polymer coating 124 may be a CH x polymer, where x ranges between 2 and 4.

[0153] In some embodiments, CH 4, argon, and / or helium plasma is used to deposit a polymer coating 124 in-situ with isotropic etching. In some embodiments, the flow rate of the plasma may range between approximately 50 standard cubic centimeters per minute and approximately 500 standard cubic centimeters per minute. In some embodiments, the transformer-coupled plasma source power may range between approximately 100 watts and approximately 800 watts. In some embodiments, no bias is applied so that the thickness of the polymer coating 124 is substantially equal along its entire length. In some embodiments, the thickness of the polymer coating 124 ranges between approximately 1 nanometer and approximately 3 nanometers.

[0154] As Figure 13B shown in the cross-sectional view 1300B1 of Figure 13A an alternative embodiment of the cross-sectional view 1300A of Figures 12A to 12C wherein the hard mask 122 has a bottom surface 122b that is narrower than the top surface 120t of the top electrode 120. The cross-sectional view 1300B1 may be the result of the hard mask 122 having a faster removal rate than the top electrode 120 during the isotropic etching of

[0155] Figure 13BThe top view 1300B2 corresponds to an image taken using an imaging tool (e.g., SEM, TEM, etc.). As shown in the top view 1300B2, due to the small thickness of the polymer coating 124 (between about 1 nanometer and about 3 nanometers), the portion of the polymer coating 124 disposed above the underlying horizontal surface may not be visible using the imaging tool, while the portion of the polymer coating 124 disposed along the vertically extending surface may be visible. For example, in some embodiments, from the top view 1300B2, the polymer coating 124 may appear as two rings because the polymer coating 124 along the sidewalls of the hard mask 122, the top electrode 120, and / or the phase change material 118 may appear thicker from the perspective of the top view 1300B2 compared to the polymer coating 124 on the top surface 122t of the hard mask 122 and the top surface 120t of the top electrode 120. For example, in some embodiments, the polymer coating 124 on the top surface 120t of the top electrode 120 may be too thin to appear in the top view 1300B2. Thus, although the top surface 120t of the top electrode 120 is covered by the polymer coating 124 as shown in the cross-sectional view 1300B1, the top surface 120t of the top electrode 120 may be visible in the top view 1300B2, between the two rings of the polymer coating 124. Similarly, although the top surface 122t of the hard mask 122 is covered by the polymer coating 124, the top surface 122t of the hard mask 122 may be visible in the top view 1300B2 because the polymer coating 124 covering the top surface 122t of the hard mask 122 appears too thin from the perspective of the top view 1300B2. For these same reasons, in some embodiments, although the insulating layer 112 is covered by the polymer coating 124, the insulating layer 112 may be visible from the top view 1300B2. In other embodiments, from the perspective of the top view 1300B2, the polymer coating 124 may appear as more than two rings.

[0156] As Figure 14As shown in the cross-sectional view 1400, an upper interlayer dielectric (ILD) layer 1406 is disposed over the polymer coating 124. In some embodiments, an encapsulation layer 127 is disposed over the polymer coating 124 before depositing the upper interlayer dielectric layer 1406 such that the encapsulation layer 127 separates the polymer coating 124 from the upper interlayer dielectric layer 1406. The encapsulation layer 127 may include silicon nitride, silicon oxide, etc. In some embodiments, the upper interlayer dielectric layer 1406 may be deposited via physical vapor deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, etc.). The upper interlayer dielectric layer 1406 may include the same materials as the lower portion 106a of the dielectric structure, such as nitrides (e.g., silicon nitride, silicon oxynitride), carbides (e.g., silicon carbide), oxides (e.g., silicon oxide), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant oxides (e.g., carbon-doped oxide, SiCOH), or similar materials.

[0157] As Figure 15 shown in the cross-sectional view 1500, the patterned upper interlayer dielectric layer ( Figure 14 1406 of) is formed to form the upper portion 106b of the dielectric structure. The upper portion 106b of the dielectric structure is patterned to form an opening for the via 126. Additionally, the encapsulation layer 127, the polymer coating 124, and the hard mask 122 are patterned for the via 126 such that the via 126 is deposited over the upper portion 106b of the dielectric structure to contact the top electrode 120. A deposition process and / or an electroplating process (e.g., electroplating, electroless plating, etc.) may be used to deposit the via 126. The via 126 may include a conductive metal such as copper, tungsten, etc.

[0158] Figure 16 FIG. 1600 is a flow chart illustrating some embodiments of a method for forming an integrated wafer having a phase change random access memory device.

[0159] Although the method 1600 is shown and described below as a series of acts or events, it should be understood that the illustrated order of such acts or events should not be construed in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events not shown and / or described herein. Additionally, not all of the acts shown may be required to implement one or more aspects or embodiments described herein. Further, one or more of the acts described herein may be performed in one or more separate acts and / or phases.

[0160] At 1602, a phase change material (PCM) layer is deposited over the bottom electrode.

[0161] At 1604, a top electrode layer is deposited over the phase change material layer.

[0162] At 16:06, a hard mask layer is deposited over the top electrode layer. Figure 8 A cross-sectional view 800 corresponding to some embodiments of operations 1602, 1604, and 1606 is shown.

[0163] At 16:08, the top electrode layer and the hard mask layer are patterned to expose the exterior of the phase change material layer. Figure 10 A cross-sectional view 1000 corresponding to some embodiments of operation 1608 is shown.

[0164] At 16:10, an isotropic etch selective to the phase change material layer is performed. The isotropic etch comprises a plurality of cycles. Each cycle includes a first step at high pressure followed by a second step at low pressure. The isotropic etch is performed until the phase change material layer has a trapezoidal shape. Figures 12A to 12C Cross-sectional views 1200A to 1200C corresponding to some embodiments of operation 1610 are shown.

[0165] At 16:12, a polymer coating is deposited over the hard mask, the top electrode, and the phase change material layer. Figure 13A And Figure 13B Cross-sectional views 1300A and 1300B1 corresponding to various embodiments of operation 1612 are shown.

[0166] At 16:14, an interlayer dielectric layer is deposited over the polymer coating. Figure 14 A cross-sectional view 1400 corresponding to some embodiments of operation 1614 is shown.

[0167] At 16:16, a via is formed that passes through the interlayer dielectric layer, the polymer coating, and the hard mask to contact the top electrode. Figure 15 A cross-sectional view 1500 corresponding to some embodiments of operation 1616 is shown.

[0168] Accordingly, the present disclosure relates to a method of manufacturing a phase change random access memory device that reduces the heat dissipation path by forming a trapezoidal-shaped phase change material and increases the thermal confinement within the phase change material and suppresses heat dissipation by reducing the thermal conductivity at the phase change material boundary with a polymer coating. This method provides phase change random access memory cells with low power consumption.

[0169] Accordingly, in some embodiments, the present disclosure relates to an integrated wafer comprising: a phase change material disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure when the temperature changes; a top electrode disposed over an upper surface of the phase change material; a via in electrical contact with a top surface of the top electrode; and wherein a maximum width of the upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material.

[0170] In other embodiments, the present disclosure relates to an integrated wafer, comprising: a phase change material disposed over a bottom electrode and configured to change its structure between a substantially crystalline structure and a substantially amorphous structure when the temperature changes, wherein the phase change material has a topmost surface and a bottommost surface, and wherein the maximum width of the topmost surface is less than the maximum width of the bottommost surface; a top electrode over the phase change material; and a polymer coating on the outer sidewalls of the phase change material, wherein the polymer coating separates the phase change material from the interlayer dielectric layer.

[0171] In still other embodiments, the present disclosure relates to a method of forming an integrated wafer, comprising: depositing a phase change material layer over a bottom electrode, wherein the phase change material layer is configured to change the degree of crystallization when the temperature changes; depositing a top electrode layer over the phase change material layer; patterning the top electrode layer to remove the exterior of the top electrode layer and expose the exterior of the phase change material layer; and performing an isotropic etch using an inert gas selective to the phase change material layer, wherein the isotropic etch comprises a first step followed by a second step, wherein the first step is performed at a first pressure and the second step is performed at a second pressure less than the first pressure.

[0172] Some embodiments of the present disclosure provide an integrated wafer, comprising: a phase change material, a top electrode, and a via. The phase change material is disposed over a bottom electrode and configured to change from a crystalline structure to an amorphous structure when the temperature changes. The top electrode is disposed over the upper surface of the phase change material. The via is in electrical contact with the top surface of the top electrode. Wherein, the maximum width of the upper surface of the phase change material is less than the maximum width of the bottom surface of the phase change material.

[0173] In the integrated wafer of some embodiments, the outermost sidewalls of the phase change material meet the bottom surface of the phase change material at an acute angle.

[0174] In the integrated wafer of some embodiments, the acute angle ranges between about 45 degrees and about 75 degrees.

[0175] In the integrated wafer of some embodiments, the phase change material has an upper peripheral portion having a topmost surface that is higher than the bottom surface of the top electrode and directly contacts the outer sidewalls of the top electrode.

[0176] In the integrated wafer of some embodiments, the ratio of the maximum width of the top surface of the phase change material to the maximum width of the bottom surface of the phase change material ranges between about 0.2 and about 0.5.

[0177] In the integrated wafer of some embodiments, further comprising: a polymer coating on the outer sidewalls of the phase change material, wherein the polymer coating has a thermal conductivity lower than that of the phase change material.

[0178] In some embodiments of the integrated wafer, it further includes: a packaging layer and a dielectric structure. The packaging layer is disposed on the polymer coating; the dielectric structure laterally surrounds the phase change material and extends above the top electrode, wherein the packaging layer separates the polymer coating from the dielectric structure.

[0179] In some embodiments of the integrated wafer, the polymer coating includes carbon and hydrogen.

[0180] Some embodiments of the present disclosure provide an integrated wafer including: a phase change material, a top electrode, and a polymer coating. The phase change material is disposed above the bottom electrode and is configured to change the structure of the phase change material between a substantially crystalline structure and a substantially amorphous structure when the temperature changes, wherein the phase change material has a topmost surface and a bottommost surface, and wherein the maximum width of the topmost surface is less than the maximum width of the bottommost surface. The top electrode is above the phase change material. The polymer coating is on the outer sidewall of the phase change material, wherein the polymer coating separates the phase change material from the interlayer dielectric layer.

[0181] In some embodiments of the integrated wafer, it further includes: a hard mask disposed above the top electrode, wherein the polymer covers the outer sidewall and the top surface of the hard mask, and wherein a via extends through the polymer coating and the hard mask to directly contact the top electrode.

[0182] In some embodiments of the integrated wafer, the thermal conductivity of the phase change material is greater than the thermal conductivity of the polymer coating.

[0183] In some embodiments of the integrated wafer, the maximum width of the top surface of the top electrode is less than the maximum width of the bottom surface of the top electrode.

[0184] In some embodiments of the integrated wafer, the outer sidewall of the phase change material meets the bottommost surface at a first angle, and the first angle ranges between approximately 45 degrees and approximately 75 degrees.

[0185] In some embodiments of the integrated wafer, the outer sidewall of the top electrode meets the bottom surface of the top electrode at a second angle, and the second angle is equal to the first angle.

[0186] Some embodiments of the present disclosure provide a method of forming an integrated wafer, comprising: depositing a phase change material layer over a bottom electrode, wherein the phase change material layer is configured to change the degree of crystallization when the temperature changes; depositing a top electrode layer over the phase change material layer; patterning the top electrode layer to remove the exterior of the top electrode layer and expose the exterior of the phase change material; and performing isotropic etching using an inert gas selective to the phase change material layer, wherein the isotropic etching comprises a first step followed by a second step, wherein the first step is performed at a first pressure and the second step is performed at a second pressure, and the second pressure is less than the first pressure.

[0187] In the method of some embodiments, it further comprises: depositing a hard mask layer over the top electrode layer; and depositing a polymer coating over the hard mask layer, the top electrode layer, and the phase change material layer, wherein the polymer coating is deposited in-situ with the isotropic etching.

[0188] In the method of some embodiments, wherein the polymer coating comprises carbon and hydrogen, and wherein the polymer coating has a lower thermal conductivity compared to the phase change material layer.

[0189] In the method of some embodiments, wherein after performing the isotropic etching, the bottommost surface of the phase change material layer is wider than the topmost surface of the phase change material layer.

[0190] In the method of some embodiments, wherein the isotropic etching is repeated multiple times until the phase change material layer presents a trapezoidal shape.

[0191] In the method of some embodiments, wherein after performing the isotropic etching, the phase change material layer has a top surface that is higher than the bottom surface of the top electrode layer.

[0192] The features of several embodiments have been outlined above so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they may readily use the present disclosure as a basis for the design and modification of other processes and structures to achieve the same purposes as the embodiments introduced herein, or to achieve the same benefits. Those skilled in the art should also understand that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated chip, characterized in that, comprising: a phase change material disposed on a bottom electrode and configured to change from a crystalline structure to an amorphous structure when the temperature changes; a top electrode disposed on an upper surface of the phase change material; a hard mask above the top electrode; a via hole electrically contacting a top surface of the top electrode; and a polymer coating on an outer sidewall of the phase change material, on an outer sidewall of the top electrode, and on an outer sidewall and the top surface of the hard mask layer, wherein the thickness of the polymer coating is not greater than 3 nanometers; wherein, a maximum width of an upper surface of the phase change material is less than a maximum width of a bottom surface of the phase change material, wherein a bottom surface of the hard mask directly contacts the top surface of the top electrode; and wherein the bottom surface of the hard mask is narrower than the top surface of the top electrode.

2. The integrated chip according to claim 1, characterized in that, a outermost sidewall of the phase change material joins the bottom surface of the phase change material at an acute angle.

3. The integrated chip according to claim 2, characterized in that, the acute angle ranges between 45 degrees and 75 degrees.

4. The integrated chip according to claim 1, characterized in that, the phase change material has an upper peripheral portion, the upper peripheral portion has a topmost surface, the topmost surface is higher than a bottom surface of the top electrode and directly contacts an outer sidewall of the top electrode.

5. The integrated chip according to claim 1, characterized in that, a ratio of the maximum width of the top surface of the phase change material to the maximum width of the bottom surface of the phase change material ranges between 0.2 and 0.

5.

6. The integrated chip according to claim 1, characterized in that: wherein the polymer coating has a thermal conductivity lower than that of the phase change material.

7. The integrated chip according to claim 6, characterized in that, the polymer coating directly contacts the top surface of the top electrode.

8. The integrated chip according to claim 6, characterized in that, further comprising: a packaging layer disposed on the polymer coating; and a dielectric structure laterally surrounding the phase change material and extending above the top electrode, wherein the packaging layer separates the polymer coating from the dielectric structure.

9. The integrated chip according to claim 8, characterized in that, the packaging layer comprises a material different from the polymer coating.

10. The integrated chip according to claim 6, characterized in that, the polymer coating comprises carbon and hydrogen.

11. An integrated chip, characterized in that, comprising: a phase change material disposed on a bottom electrode, and configured to change the structure of the phase change material between a substantially crystalline structure and a substantially amorphous structure when the temperature changes, wherein the phase change material has a topmost surface and a bottommost surface, and wherein a maximum width of the topmost surface is less than a maximum width of the bottommost surface; a top electrode above the phase change material, a polymer coating on an outer sidewall of the phase change material and on an outer sidewall of the top electrode, wherein the polymer coating separates the phase change material from an interlayer dielectric layer; and A hard mask disposed above the top electrode, wherein the polymer coating covers a top surface and an outer sidewall of the hard mask, and wherein a through hole extends through the polymer coating and the hard mask to directly contact the top electrode; wherein the thickness of the polymer coating is not greater than 3 nanometers.

12. The integrated wafer according to claim 11, wherein, a thermal conductivity of the phase change material is greater than a thermal conductivity of the polymer coating.

13. The integrated wafer according to claim 11, wherein, a maximum width of a top surface of the top electrode is less than a maximum width of a bottom surface of the top electrode.

14. The integrated wafer according to claim 11, wherein, an outer sidewall of the phase change material meets the bottommost surface at a first angle, and the first angle ranges between 45 degrees and 75 degrees.

15. The integrated wafer according to claim 14, wherein, an outer sidewall of the top electrode meets a bottom surface of the top electrode at a second angle, and wherein the second angle is equal to the first angle.

16. An integrated wafer, wherein, comprising: a phase change material layer disposed above a bottom electrode and configured to change its structure between a crystalline structure and an amorphous structure when the temperature changes, wherein the phase change material layer has a topmost surface and a bottommost surface, and wherein a maximum width of the topmost surface is less than a maximum width of the bottommost surface; a top electrode above the phase change material layer; a hard mask disposed above the top electrode; a through hole electrically extending through the hard mask to contact a top surface of the top electrode; and a polymer coating on outer sidewalls of the phase change material layer, the top electrode, and the hard mask, wherein the thickness of the polymer coating is not greater than 3 nanometers; wherein the phase change material layer has an upper peripheral portion that is higher than a bottom surface of the top electrode and lower than a top surface of the top electrode.

17. The integrated wafer according to claim 16, wherein, the polymer coating comprises carbon and hydrogen.

18. The integrated wafer according to claim 16, wherein, the polymer coating has a lower thermal conductivity than the phase change material layer.

19. The integrated wafer according to claim 16, wherein, the top surface of the top electrode is narrower than the bottom surface of the top electrode; and wherein the hard mask has a top surface that is narrower than a bottom surface of the hard mask.

20. The integrated wafer according to claim 19, wherein, the outer sidewalls of the hard mask meet the top surface of the hard mask at a plurality of rounded corners.

21. A method of forming an integrated wafer, wherein, comprising: depositing a phase change material layer above a bottom electrode, wherein the phase change material layer is configured to change the degree of crystallization when the temperature changes; depositing a top electrode layer above the phase change material layer; depositing a hard mask layer above the top electrode layer; patterning the top electrode layer and the hard mask layer to remove the exteriors of the top electrode layer and expose the exteriors of the phase change material layer; and An isotropic etch is performed to remove portions of the phase change material layer not covered by the top electrode layer and the hard mask layer, wherein the isotropic etch removes the portions of the phase change material layer faster than removing the outer portions of the top electrode layer and the outer portions of the hard mask layer, the isotropic etch is a dry etch, wherein the isotropic etch comprises a first step followed by a second step, wherein the first step is performed at a first pressure, and wherein the second step is performed at a second pressure less than the first pressure.

22. The method for forming an integrated wafer as claimed in claim 21, It is characterized in that The isotropic etch removes the outer portions of the top electrode layer faster than the top electrode layer.

23. The method for forming an integrated wafer as claimed in claim 21, It is characterized in that The isotropic etching uses an inert gas.

24. The method for forming an integrated wafer as claimed in claim 21, It is characterized in that Also includes: forming an upper dielectric layer over the hard mask layer; patterning the upper dielectric layer and the hard mask layer to form an opening in the upper dielectric layer and the hard mask layer, the opening exposing an upper surface of the top electrode layer; as well as A via is formed within the opening to directly contact the upper surface of the top electrode layer.

25. The method for forming an integrated wafer as claimed in claim 24, It is characterized in that Also includes: forming a polymer coating over the hard mask layer, the phase change material layer, and the top electrode layer before forming the upper dielectric layer, Wherein when the upper dielectric layer is patterned, multiple portions of the polymer coating are patterned.

26. The method for forming an integrated wafer as claimed in claim 21, It is characterized in that The first step and the second step are repeated multiple times until the phase change material layer presents a trapezoidal shape, wherein an upper surface of the phase change material layer is narrower than a lower surface of the phase change material layer.

27. A method of forming an integrated wafer, It is characterized in that Include: depositing a phase change material layer over a bottom electrode, wherein the phase change material layer is configured to change a degree of crystallinity when temperature changes; depositing a top electrode layer above the phase change material layer; patterning the top electrode layer to remove outer portions of the top electrode layer and expose outer portions of the phase change material; as well as An isotropic etch is performed using an inert gas selective to the phase change material layer, wherein the isotropic etch comprises a first step followed by a second step, wherein the first step is performed at a first pressure, and wherein the second step is performed at a second pressure that is less than the first pressure.

28. The method for forming an integrated wafer as claimed in claim 27, It is characterized in that A bottommost surface of the phase change material layer is wider than a topmost surface of the phase change material layer.

29. The method for forming an integrated wafer as claimed in claim 27, It is characterized in that The isotropic etching is repeated for multiple times until the phase change material layer presents a trapezoidal shape.

30. The method for forming an integrated wafer as claimed in claim 27, It is characterized in that After performing such anisotropic etching, the phase change material layer has a topmost surface that is higher than a bottom surface of the top electrode layer.

31. The method of forming an integrated wafer according to claim 27, wherein, further comprising: depositing a hard mask layer over the top electrode layer; and patterning the hard mask layer to remove the outsides of the hard mask layer and expose the outsides of the phase change material layer, wherein after the anisotropic etching, a bottom surface of the hard mask layer directly contacts a top surface of the top electrode layer, and wherein the bottom surface of the hard mask layer is narrower than the top surface of the top electrode layer.

32. The method of forming an integrated wafer according to claim 27, wherein, further comprising: depositing a hard mask layer over the top electrode layer; and depositing a polymer coating over the hard mask layer, the top electrode layer, and the phase change material layer, wherein the polymer coating is deposited in situ with the anisotropic etching.

33. The method of forming an integrated wafer according to claim 32, wherein, the polymer coating comprises carbon and hydrogen, and wherein the polymer coating has a thermal conductivity lower than that of the phase change material layer.

34. A method of forming an integrated wafer, wherein, comprising: forming a phase change material layer over a bottom electrode; forming a top electrode layer over the phase change material layer; forming a hard mask layer over the top electrode layer; patterning the top electrode layer and the hard mask layer to expose the outsides of the phase change material layer; performing an anisotropic etching selective to the phase change material layer, wherein the anisotropic etching comprises a plurality of cycles, and wherein each cycle comprises a first step performed at a first pressure, followed by a second step performed at a second pressure, the second pressure being different from the first pressure; and forming a polymer coating over the hard mask layer, the top electrode layer, and the phase change material layer.

35. The method of forming an integrated wafer according to claim 34, wherein, after the anisotropic etching, a topmost surface of the phase change material layer is narrower than a bottommost surface of the phase change material layer.

36. The method of forming an integrated wafer according to claim 34, wherein, further comprising: forming a packaging layer over the polymer coating, wherein the packaging layer comprises a material different from the polymer coating.

37. The method of forming an integrated wafer according to claim 34, wherein, further comprising: forming a through hole through the polymer coating and the hard mask layer to contact the top electrode layer.

38. The method of forming an integrated wafer according to claim 34, wherein, the first pressure is greater than the second pressure.

39. The method of forming an integrated wafer according to claim 34, wherein, the anisotropic etching removes the phase change material layer faster than it removes the hard mask layer.

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