Data storage devices and systems

Abstract

A data storage device is provided. The data storage device includes: a first functional block of a device controller, which is configured to receive user data and perform a first data process; a first buffer memory, which is connected to the first functional block and is configured to store the user data that has undergone the first data process as first processed data; a second functional block of the device controller, which is configured to receive a data write command determined based on the first processed data; and a non-volatile memory, which is connected to the second functional block and is configured to receive and store the data stored in the first buffer memory. The user data is provided to the first functional block before the data write command is provided to the second functional block.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of Korean Patent Application No. 10-2019-0025059 filed on March 5, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to data storage devices and systems. More specifically, example embodiments relate to data storage devices and systems that improve data processing effects and reduce processor overhead. Background Art

[0004] As technology continues to develop, the amount of data to be managed and stored continues to increase. In addition, it is difficult to store large amounts of data as raw data.

[0005] Therefore, there is a need for an efficient and economical data storage method that is performed by processing raw data. However, with the development of technology, the development of data processing is also complex and diverse. Many operations are required to perform complex data processing, and when a single processor performs many operations, overhead occurs in the processor and latency increases.

[0006] Therefore, there is a need for a method or system for efficiently managing data by performing complex data processing while maintaining the processor overhead at an appropriate level. Summary of the invention

[0007] One or more example embodiments provide a data processing apparatus and system that perform efficient data processing.

[0008] One or more example embodiments also provide a data processing apparatus and system that performs data processing with reduced latency.

[0009] According to one aspect of an example embodiment, there is provided a data storage device, comprising: a device controller configured to implement a first functional block and a second functional block, the second functional block being configured to perform a function independent of the first functional block; a first buffer memory connected to the first functional block; a second buffer memory connected to the second functional block and configured to interface with another device outside the data storage device; and a nonvolatile memory connected to the first functional block. The first functional block and the second functional block are connected to each other and configured to directly exchange data; and the first functional block is configured to receive first processed data from the second functional block according to a data write command and write the first processed data to the nonvolatile memory.

[0010] According to an aspect of an example embodiment, there is provided a data storage device, comprising: a first functional block of a device controller configured to receive user data and perform first data processing to generate first processed data; a first buffer memory connected to the first functional block and configured to store the first processed data; a second functional block of the device controller configured to receive a data write command determined based on the first processed data; and a nonvolatile memory connected to the second functional block and configured to receive and store the data stored in the first buffer memory. Before providing the data write command corresponding to the first processed data to the second functional block, user data corresponding to the first processed data is provided to the first functional block.

[0011] According to an aspect of an example embodiment, there is provided a data storage system, comprising: a host processor configured to generate a data write command and a data read command; and a data storage device comprising a device controller configured to communicate with the host processor. The device controller is configured to receive user data before receiving the data write command from the host processor, the device controller is configured to provide first processed data to the host processor based on the data read command, and the first processed data is data generated by the device controller and the host processor based on the user data.

[0012] The various aspects are not limited to those described herein. The above and other aspects will become more apparent to those of ordinary skill in the art by referring to the detailed description given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a diagram illustrating a data storage system according to one or more example embodiments.

[0014] Figure 2 is a diagram illustrating a first data path according to one or more example embodiments.

[0015] Figure 3 and Figure 4 is a diagram illustrating a second data path according to one or more example embodiments.

[0016] Figure 5 is a flowchart illustrating a data writing operation of a data storage system according to one or more example embodiments.

[0017] Figure 6 , Figure 7 and Figure 8 is a diagram illustrating a data write operation of a data storage system according to one or more example embodiments.

[0018] Fig. 9is a flowchart illustrating a data read operation of a data storage system according to one or more example embodiments.

[0019] Fig.10 and Fig.11 is a diagram illustrating a data read operation of a data storage system according to one or more example embodiments.

[0020] Fig.12 is a flowchart illustrating a data read operation of a data storage system according to one or more example embodiments.

[0021] Fig.13 and Fig.14 is a diagram illustrating a data read operation of a data storage system according to one or more example embodiments.

[0022] Fig.15 is a diagram illustrating a data read operation of a data storage system according to one or more example embodiments. DETAILED DESCRIPTION

[0023] Figure 1 is a diagram illustrating a data storage system according to one or more example embodiments.

[0024] Reference Figure 1 , a data storage system according to one or more example embodiments includes a data storage device 100, a host 200, and a system bus 300. For example, the data storage system may be implemented in a personal computer (PC), a workstation, a data center, an Internet data center (IDC), a storage area network (SAN), a network attached storage (NAS), or a mobile computing device. However, example embodiments are not limited thereto.

[0025] For example, the mobile computing device may be implemented as a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a drone, an RFID device, or an e-book. However, example embodiments are not limited thereto.

[0026] The host 200 may be connected to the data storage device 100 via a system bus 300. The system bus 300 may be, for example, Universal Flash Storage (UFS), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), Embedded MultiMediaCard (eMMC), Fibre Channel (FC), Advanced Technology Attachment (ATA), Integrated Drive Electronics (IDE), Universal Serial Bus (USB), IEEE 1394 FireWire, etc. However, example embodiments are not limited thereto, and the system bus 300 may be an interface that allows data to be transmitted and received between the host 200 and the data storage device 100.

[0027] Hereinafter, for convenience of explanation, the system bus 300 will be described as PCIe. However, example embodiments are not limited thereto, and any data storage system using any interface (including the above-described electrical interface) may be used.

[0028] According to one or more example embodiments, the data storage device 100 may include a device controller 110, a controller memory 120, and a non-volatile memory 130. The device controller 110 may execute a program code for controlling the data storage device 100. For example, the device controller 110 may execute a program code for performing a data write operation and a data read operation in response to a request from the host 200. In another example, the device controller 110 may execute a program code for performing a background operation (e.g., a garbage collection operation) on the non-volatile memory 130. In another example, the device controller 110 may perform data processing on data to be written to the non-volatile memory 130 or data to be read from the non-volatile memory 130.

[0029] The device controller 110 may include a central processing unit (CPU), a graphic processing unit (GPU), an application processor (AP), a micro processing unit (MPU), etc., but example embodiments are not limited thereto.

[0030] The device controller 110 may include a first functional block 112 and a second functional block 114. The first functional block 112 and the second functional block 114 may mean functional blocks that perform functions independent of each other. The first functional block 112 and the second functional block 114 may be implemented as hardware, firmware, software, or a combination thereof, respectively. The first functional block 112 and the second functional block 114 may be interconnected to directly exchange data without using a bus (e.g., a system bus 300). For example, the device controller 110 is connected to an endpoint (EP) of PCIe, and the first functional block 112 and the second functional block 114 may be interconnected via a bridge in the endpoint of PCIe. However, example embodiments are not limited thereto.

[0031] The controller memory 120 may be a memory for temporarily storing data. The controller memory 120 may include a first buffer memory 122 and a second buffer memory 124. Figure 1 It is shown that both the first buffer memory 122 and the second buffer memory 124 are included in the controller memory 120, but this is for convenience of description, and example embodiments are not limited thereto. For example, the first buffer memory 122 and the second buffer memory 124 may be implemented as different regions of the same memory device, or may be implemented as physically different memory devices. In addition, although Figure 1 The controller memory 120 is illustrated as a separate constituent element different from the device controller 110 , but example embodiments are not limited thereto. For example, the controller memory 120 may be included in the device controller 110 .

[0032] Access to the first buffer memory 122 from the outside of the data storage device 100 (i.e., the host 200) is not allowed. On the other hand, access to the second buffer memory 124 from the host 200 is allowed. In other words, the second buffer memory 124 is exposed to the outside of the data storage device 100, but the first buffer memory 122 is not exposed to the outside of the data storage device 100. Although Figure 1 The second buffer memory 124 is shown to be exposed to the host 200 via the system bus 300, but this is only for ease of explanation and example embodiments are not limited thereto. For example, the host 200 and the second buffer memory 124 may be directly connected, and the second buffer memory 124 may be interfaced with the host 200. Additional description on this point will be referred to later. Figure 3 and Figure 4 supply.

[0033] The controller memory 120 (ie, the first buffer memory 122 and the second buffer memory 124 ) may be implemented as a static random access memory (SRAM), a fast static RAM (fast SRAM), and / or a dynamic RAM (DRAM). However, example embodiments are not limited thereto.

[0034] The nonvolatile memory 130 is a memory in which data is semi-permanently stored. The nonvolatile memory 130 may include at least one of a flash memory, a resistive RAM (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), a ferroelectric memory (FRAM), and a spin injection magnetization reversal memory (spin STT-RAM), but example embodiments are not limited thereto.

[0035] According to one or more example embodiments, the first functional block 112, the first buffer memory 122, and the non-volatile memory 130 may form a first data path ( Figure 2 P1). Figure 2 For illustrative purposes only.

[0036] Figure 2 is a diagram illustrating a first data path according to one or more example embodiments.

[0037] Reference Figure 2 , the first functional block 112 may be connected to the first buffer memory 122. In addition, the first functional block 112 may be connected to the nonvolatile memory 130.

[0038] In other words, the first functional block 112, the first buffer memory 122, and the non-volatile memory 130 may form a first data path P1 to which data is transmitted. For example, the first data path P1 may be implemented as a non-volatile memory express (NVMe) interface.

[0039] According to one or more example embodiments, the first functional block 112 may be configured to drive firmware or software for controlling the nonvolatile memory 130. For example, the first functional block 112 may provide a chip enable signal, a write enable signal, a read enable signal, etc. to the nonvolatile memory 130. The first functional block 112 may control input / output of data to and from the first buffer memory 122 and the nonvolatile memory 130. For example, when a garbage collection operation is performed on the nonvolatile memory 130, the first functional block 112 reads data from the nonvolatile memory 130 and outputs the data to the first buffer memory 122. The first functional block 112 may apply an erase voltage to a specific memory block of the nonvolatile memory 130, or may write the data stored in the first buffer memory 122 to the nonvolatile memory 130 again. In another example, in response to a data read request from the host 200 , the first function block 112 may temporarily store data read from the nonvolatile memory 130 in the first buffer memory 122 , and may provide the data to the host 200 .

[0040] According to one or more example embodiments, the first buffer memory 122 may store data requiring security (e.g., encryption code, mapping data, etc.). In this regard, the first buffer memory 122 is configured not to be exposed to the outside of the data storage device 100. As described above, the host 200 may not access the first buffer memory 122, and may not directly read or change the data stored in the first buffer memory 122.

[0041] Refer again Figure 1, the second functional block 114 and the second buffer memory 124 can form a second data path ( Figure 3 and Figure 4 P2). Figure 3 and Figure 4 An exemplary description is given.

[0042] Figure 3 and Figure 4 is an exemplary diagram for illustrating a second data path according to one or more example embodiments.

[0043] Reference Figure 3 , the second functional block 114 may be connected to the second buffer memory 124. In other words, the second functional block 114 and the second buffer memory 124 may be connected to each other to form a second data path P2.

[0044] According to one or more example embodiments, the second functional block 114 may perform a first data processing on the received data. The second functional block 114 may include at least one of a data compression engine 301, a data encryption engine 302, a data scanning (search) engine 303, a data filtering engine 304, a data hashing engine 305, and a neural network engine 306. The second functional block 114 may use one or more of the data compression engine 301, the data encryption engine 302, the data scanning (search) engine 303, the data filtering engine 304, the data hashing engine 305, and the neural network engine 306 to perform the first data processing. For example, the first data processing may include at least one function of data compression or decompression, data encryption or decryption, data scanning (search), data filtering, and data hashing. In addition, the first data processing may include performing deep learning training.

[0045] According to one or more example embodiments, the data subjected to the first data processing by the second functional block 114 may be provided to the second buffer memory 124. In other words, the second buffer memory 124 may store the result data of the first data processing. In addition, the second buffer memory 124 may also store the intermediate data of the first data processing. For example, the second functional block 114 may use the data compression engine 301 to compress the received data. At this time, the compressed data or the intermediate data may be stored in the second buffer memory 124.

[0046] As described above, the second buffer memory 124 may allow access from outside the data storage device 100 (ie, the host 200). According to one or more example embodiments, Figure 3 As shown, the host 200 may access the second buffer memory 124 through direct memory access (DMA). According to one or more example embodiments, as shown in FIG. Figure 4As shown, the host 200 may access the second buffer memory 124 through the system bus 300. According to one or more example embodiments, the host 200 may access the second buffer memory 124 to perform a second data process on data stored in the second buffer memory 124. Specific examples will be described later.

[0047] Refer again Figure 1 , the host 200 may include a host processor 210 and a host memory 220. The host processor 210 may be connected to the host memory 220. The host processor 210 may include a CPU, a GPU, an AP, an MPU, etc., but example embodiments are not limited thereto. In addition, the host memory 220 may be implemented as a static RAM (SRAM), a fast static RAM (fast SRAM), and / or a dynamic RAM (DRAM), but example embodiments are not limited thereto.

[0048] The host processor 210 may control the data storage device 100. For example, the host processor 210 may generate a data write command and provide it to the first functional block 112. In another example, the host processor 210 may provide data stored in the host memory 220 to the second functional block 114. In addition, the host processor 210 may access the second buffer memory 124 of the data storage device 100 to perform data processing (e.g., second data processing) on ​​the data stored in the second buffer memory 124. The functions performed by the host processor 210 may be implemented via hardware, firmware, software, or a combination thereof, respectively.

[0049] Reference Figures 1 to 4 , from the perspective of the host 200, the first data path P1 and the second data path P2 are independent of each other. However, because the first functional block 112 and the second functional block 114 are connected to each other, direct data exchange between the first data path P1 and the second data path P2 can be enabled. In other words, the first data path P1 and the second data path P2 can exchange data with each other without using the system bus 300. In other words, data can be exchanged between the first data path P1 and the second data path P2 without using the system bus 300, and the delay of data transmission / reception can be reduced. Figures 5 to 8 A data writing operation using the first data path P1 and the second data path P2 is described.

[0050] Figure 5 is an exemplary flow chart illustrating a data writing operation of a data storage system according to one or more example embodiments. Figures 6 to 8 is an exemplary diagram illustrating a data write operation of a data storage system according to one or more example embodiments.

[0051] Reference Figure 1 , Figure 5 and Figure 6 , before the host processor 210 generates a data write command (or request), the host processor 210 may provide the first user data UD_1 to the data storage device 100. For example, the second function block 114 of the data storage device 100 may receive the first user data UD_1 from the host 200 (S510). The second function block 114 may perform a first data process on the received first user data UD_1. As described above, the second function block 114 may use at least one of the data compression engine 301, the data encryption engine 302, the data scanning (searching) engine 303, the data filtering engine 304, the data hash engine 305, and the neural network engine 306 included in the second function block 114 to perform the first data process. For example, the second function block 114 may use the data compression engine 301 to perform a data compression process on the received first user data UD_1.

[0052] For ease of description, the first user data UD_1 subjected to the first data processing by the second function block 114 is defined as the first processed data PD_1. For example, the first processed data PD_1 may represent the first user data UD_1 subjected to data compression processing. In other words, the second function block 114 may generate the first processed data PD_1 using the first user data UD_1. The generated first processed data PD_1 may be stored in the second buffer memory 124 (S520).

[0053] Although Figure 6 It is shown that the first user data UD_1 received from the host 200 is directly provided to the second function block 114 to generate the first processed data PD_1, but the example embodiments are not limited thereto. For example, the first user data UD_1 received from the host 200 may be temporarily stored in the second buffer memory 124, and the second function block 114 may read the first user data UD_1 from the second buffer memory 124 to generate the first processed data PD_1. Those skilled in the art will appreciate that various data storage systems may be implemented by modifying or adopting the example embodiments described herein.

[0054] Reference Figure 1 , Figure 5 and Figure 7, the host processor 210 can access the second buffer memory 124. The host processor 210 can perform a second data processing on the first processed data PD_1 stored in the second buffer memory 124. The second data processing can be a data processing at a stage after the first data processing. For example, if the first data processing is a data compression process, the second data processing can be a packing process of the compressed data. For example, the data compressed and segmented by the first data processing (i.e., the first processed data PD_1) is packed by the second data processing and can be changed into a data page with continuous valid values. For ease of explanation, the first processed data PD_1 that has been subjected to the second data processing by the host processor 210 is defined as the second processed data PD_2. In other words, the host processor 210 can generate the second processed data PD_2 using the first processed data PD_1 stored in the second buffer memory 124 (S530).

[0055] According to one or more example embodiments, when the host processor 210 generates the second processed data PD_2, the first metadata MD_1 may be stored in the host memory 220. The first metadata MD_1 may be, for example, size information and offset information about the first processed data PD_1. When performing the third data processing, the first metadata MD_1 may be used. The specific content thereof will be described later.

[0056] although Figure 7 It is described that the first metadata MD_1 is stored in the host memory 220 separately from the second processed data PD_2, but example embodiments are not limited thereto. According to one or more example embodiments, the first metadata MD_1 may also be stored in the second buffer memory 124 instead of the host memory 220. According to one or more example embodiments, the second processed data PD_2 may include the first metadata MD_1. For example, when the host processor 210 generates the second processed data PD_2 using the first processed data PD_1, size information about the first processed data PD_1, etc. may be included in the second processed data PD_2 (see Fig.11 ). Those skilled in the art will appreciate that the first metadata MD_1 may be managed in various ways.

[0057] According to one or more example embodiments, when the host processor 210 generates the second processed data PD_2, the host processor 210 may generate a data write command using the second processed data PD_2. The host processor 210 may provide the generated data write command to the device controller 110. In other words, the data storage device 100 may receive the first user data UD_1 before receiving the data write command from the host 200.

[0058] Reference Figures 1 to 5 and Figure 8 , the device controller 110 may receive a data write command regarding the second processed data PD_2 (S540). When the device controller 110 receives the data write command regarding the second processed data PD_2, the device controller 110 reads the second processed data PD_2 via the second data path P2, and may store the second processed data PD_2 in the non-volatile memory 130 through the first data path P1 (S550). In other words, when the device controller 110 receives the data write command regarding the second processed data, the device controller 110 may read the second processed data PD_2 stored in the second buffer memory 124 using the second function block 114. Subsequently, the second processed data PD_2 may be directly provided from the second function block 114 to the first function block 112 without passing through the system bus 300. The first function block 112 may receive the second processed data PD_2 from the second function block 114. The first function block 112 may provide and store the received second processed data PD_2 to the non-volatile memory 130. At this time, address information (or mapping information) regarding a location of the nonvolatile memory 130 storing the second processed data PD_2 and the like may be stored in the first buffer memory 122 as second metadata MD_2.

[0059] According to one or more example embodiments, the first data processing may be performed by the device controller 110, and the second data processing may be performed by the host processor 210. That is, data processing of data to be written to the data storage device 100 may be allocated to the device controller 110 and the host processor 210, thereby reducing operation overheads of the device controller 110 and the host processor 210.

[0060] In addition, the device controller 110 may have relatively low performance compared to the host processor 210. Therefore, when only the device controller 110 is used, relatively complex data processing may not be implemented. However, according to one or more example embodiments, by implementing processing such as simple operations in the device controller 110, and by implementing processing such as complex operations or metadata management in the host processor 210, more complex and efficient data processing can be implemented. In addition, as described above, since the first function block 112 and the second function block 114 are connected to each other to enable direct data exchange, the delay associated with the data exchange can also be effectively reduced.

[0061] Fig. 9 is an exemplary flow chart illustrating a data read operation of a data storage system according to one or more example embodiments. Fig.10 and Fig.11 is an exemplary diagram illustrating a data read operation of a data storage system according to one or more example embodiments.

[0062] Reference Figure 1 , Fig. 9 and Fig.10 , the host processor 210 may provide a data read command associated with the second processed data PD_2 to the device controller 110. The device controller 110 may receive the data read command associated with the second processed data PD_2 (S910).

[0063] The second processed data PD_2 stored in the nonvolatile memory 130 is read through the first data path P1 and can be stored in the second buffer memory 124 via the second data path P2. In other words, the first function block 112 that has received the data read command can read the second processed data PD_2 from the nonvolatile memory 130 by referring to the second metadata MD_2 in the first buffer memory 122. At this time, the second processed data PD_2 may include the first metadata MD_1. The first function block 112 may directly provide the read second processed data PD_2 to the second function block 114. The second function block 114 may perform a third data process on the provided second processed data PD_2. For ease of description, the second processed data PD_2 that has been subjected to the third data process by the second function block 114 is defined as the third processed data PD_3. In other words, the second function block 114 may generate the third processed data PD_3 using the second processed data PD_2 (S920). According to one or more example embodiments, the second function block 114 may refer to the first metadata MD_1 included in the second processed data PD_2 to generate the third processed data PD_3. The third processed data PD_3 may be stored in the second buffer memory 124. Assuming that the second processed data PD_2 is compressed data, the third processed data PD_3 may be, for example, decompressed data.

[0064] Reference Figure 1 , Fig. 9 and Fig.11 , the third processed data PD_3 may be provided from the second function block 114 to the first function block 112. In response to the data read command from the host 200, the first function block 112 may provide the provided third processed data PD_3 to the host 200 (S930).

[0065] Fig.12 is an exemplary flow chart illustrating a data read operation of a data storage system according to one or more example embodiments. Fig.13 and Fig.14 is an exemplary diagram illustrating a data read operation of a data storage system according to one or more example embodiments. For ease of explanation, repeated or similar contents will be omitted or briefly described.

[0066] Reference Figure 1 and Figure 12 to Figure 14 , the first function block 112 may receive a data read command related to the second processed data PD_2 from the host processor 210 (S1210). The first function block 112 reads the second processed data PD_2 stored in the nonvolatile memory 130 via the first data path P1, and may provide the second processed data PD_2 to the host 200 (S1220). In other words, the first function block 112 reads the second processed data PD_2 with reference to the second metadata MD_2 stored in the first buffer memory 122, and may provide the read second processed data PD_2 to the host processor 210. The host processor 210 may store the provided second processed data PD_2 in the host memory 220. The host processor 210 may perform a third data process on the second processed data PD_2 with reference to the first metadata MD_1 stored in the host memory 220. In other words, the host processor 210 may generate the third processed data PD_3 using the second processed data PD_2 (S1230).

[0067] For example, the second processed data PD_2 may be data compressed at a compression ratio of x:1, and the maximum data read speed of the system bus 300 may be y (bytes / second). According to one or more example embodiments, the third data processing (e.g., decompression processing) may be performed by the host processor 210. At this time, in the second processed data PD_2 provided to the host 200, because the data compressed to x:1 is read at a speed of y (bytes / second), when the decompression processing is performed in the host processor 210, the maximum speed at which the host 200 reads data may be x*y (bytes / second). In other words, the data storage system according to one or more example embodiments may read data at a speed further improved than the maximum data read speed physically provided by the system bus 300.

[0068] Fig.15 is an exemplary diagram illustrating a data read operation of a data storage system according to one or more example embodiments. For ease of explanation, repeated or similar contents will be omitted or briefly described.

[0069] Reference Figure 1 , Fig.12 , Fig.13 and Fig.15, the host 200 may further include a processing module 1510. For example, the processing module 1510 may be implemented using hardware components. The processing module 1510 may be a module different from the host processor 210. The processing module 1510 may access the host memory 220. According to one or more example embodiments, the processing module 1510 may perform a third data process on the data stored in the host memory 220. In other words, the processing module 1510 different from the host processor 210 may generate the third processed data PD_3 using the second processed data PD_2. That is, the host processor 210 may receive the second processed data PD_2 from the data storage device 100 and store it in the host memory 220. Subsequently, the processing module 1510 may generate the third processed data PD_3 with reference to the first metadata MD_1 stored in the host memory 220.

[0070] According to one or more example embodiments, the third data process may be performed by a module (ie, the processing module 1510) different from the host processor 210. Therefore, the overhead of the host processor 210 may be reduced.

[0071] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the present disclosure.

Claims

1. A data storage device, comprising: a device controller configured to implement a first functional block and a second functional block, the second functional block being configured to perform a function independent of the first functional block; a first buffer memory connected to the first functional block; a second buffer memory connected to the second functional block and configured to interface with another device external to the data storage device; and a nonvolatile memory connected to the first functional block, wherein the first functional block and the second functional block are connected to each other and are configured to directly exchange data, The first functional block is configured to receive first processed data from the second functional block according to a data write command, and write the first processed data into the non-volatile memory, The second functional block is configured to receive user data and generate second processed data by performing first data processing based on the user data, wherein the first processed data is generated by the other device outside the data storage device based on the second processed data, and Wherein, the data write command is generated based on the first processed data.

2. The data storage device according to claim 1, wherein: The first buffer memory is not configured to interface with the other device external to the data storage device.

3. The data storage device according to claim 1, wherein: The second functional block is configured to store the second processed data in the second buffer memory.

4. The data storage device according to claim 1, wherein: The second buffer memory is configured to store the first processed data, and wherein the second functional block is configured to read the first processed data from the second buffer memory and provide the first processed data directly to the first functional block.

5. The data storage device according to claim 1, wherein: The first functional block is configured to read the first processed data from the nonvolatile memory according to a data read command and provide the first processed data to the second functional block.

6. The data storage device according to claim 5, wherein: The second functional block is configured to perform third data processing based on the first processed data to generate third processed data.

7. The data storage device according to claim 1, wherein: The first functional block is configured to read the first processed data from the nonvolatile memory according to a data read command and provide the first processed data to the outside of the data storage device.

8. The data storage device according to claim 1, wherein: The first functional block, the first buffer memory and the non-volatile memory are connected via a non-volatile memory fast interface.

9. The data storage device according to claim 1, wherein: The first function block and the second function block are connected via a bridge in an endpoint of a peripheral component interconnect express.

10. The data storage device according to claim 1, wherein: The second functional block includes at least one of a data compression engine, a data encryption engine, a data scanning engine, a data filtering engine, a data hash engine and a neural network engine.

11. A data storage device, comprising: a first functional block of the device controller configured to receive user data and perform first data processing to generate first processed data; a first buffer memory connected to the first functional block and configured to store the user data subjected to the first data processing as the first processed data; a second functional block of the device controller configured to receive a data write command determined based on the first processed data; and a nonvolatile memory connected to the second functional block and configured to receive and store the data stored in the first buffer memory, Before providing the data write command corresponding to the first processing data to the second functional block, the user data corresponding to the first processing data is provided to the first functional block.

12. The data storage device according to claim 11, wherein: The first function block and the second function block are connected to each other and are configured to directly exchange data.

13. The data storage device according to claim 11, wherein: The first buffer memory is configured to interface with another device external to the data storage device.

14. The data storage device according to claim 11, wherein: The first buffer memory is configured to store second processed data, and wherein the second processed data is generated based on the first processed data.

15. A data storage system comprising: a host processor configured to generate a data write command and a data read command; and a data storage device comprising a device controller configured to communicate with the host processor, wherein the device controller is configured to receive user data before receiving the data write command from the host processor, wherein the device controller is configured to provide first processing data to the host processor based on the data read command, wherein the first processing data is data generated by the device controller and the host processor based on the user data, wherein the device controller is configured to generate second processed data based on the user data received from the host processor, and The host processor is configured to generate the first processed data based on the second processed data, and to generate the data write command based on the first processed data.

16. The data storage system according to claim 15, wherein: The device controller is configured to store the first processed data in the data storage device based on the device controller receiving the data write command, and wherein the device controller is configured to provide the first processed data to the host processor based on the device controller receiving the data read command.

17. The data storage system of claim 15, further comprising a host memory connected to the host processor, wherein: The host memory is configured to store metadata of the first processed data.

18. The data storage system according to claim 15, wherein: The host processor and the data storage device are connected via a peripheral component interconnect express bus.

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