Display panel

Abstract

A display panel is provided. The display panel includes: a substrate including a first region, a second region, a non-display region surrounding the first and second regions, and a display region surrounding the non-display region; a plurality of pixels located in the display region; a plurality of wirings configured to supply signals to the plurality of pixels; a load matching region connected to a first wiring among the wirings, the load matching region including a load cell in the non-display region; and a dummy region including a plurality of dummy cells spaced apart from the load cells in the non-display region, wherein each of the load cells includes a load semiconductor layer, a first load conductive layer, and a second load conductive layer at least partially overlapping each other, an insulating layer interposed between the load semiconductor layer, the first load conductive layer, and the second load conductive layer, and the load semiconductor layer is connected to the second load conductive layer via a first contact hole.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0027015, filed on March 8, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] One or more embodiments relate to a display panel. Background Art

[0003] The applications of display devices have recently diversified. In addition, due to their relatively small thickness and light weight, their application range has increased.

[0004] Considering that the display device is used for various reasons, various methods may be used to design the shape of the display device, and functions that may be applied to or linked to the display device may be increased.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the Invention

[0006] One or more example embodiments provide a method of adding functions that can be connected or linked to a display device, a display panel including an area in which a camera, a sensor, etc. can be arranged inside the display area, and a device including the display panel.

[0007] However, the one or more embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0009] According to some example embodiments, a display panel includes: a substrate including a first area, a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; a plurality of pixels arranged in the display area; wirings supplying signals to the plurality of pixels; a load matching area connected to a first wiring among the wirings, the load matching area including a load unit arranged in the non-display area; and a dummy area including a dummy unit spaced apart from the load unit in the non-display area, wherein each of the load units includes a load semiconductor layer, a first load conductive layer, and a second load conductive layer at least partially overlapping each other, an insulating layer is between the load semiconductor layer, the first load conductive layer, and the second load conductive layer, and the load semiconductor layer is connected to the second load conductive layer via a first contact hole.

[0010] According to some example embodiments, the first wiring may extend to the non-display area and be connected to the first load conductive layer.

[0011] According to some example embodiments, each of the dummy units may include a dummy semiconductor layer, a first dummy conductive layer, and a second dummy conductive layer that are at least partially overlapped with each other, an insulating layer is located between the dummy semiconductor layer, the first dummy conductive layer, and the second dummy conductive layer, and the dummy semiconductor layer and the first dummy conductive layer may be connected to the second dummy conductive layer via a second contact hole and a third contact hole, respectively.

[0012] According to some example embodiments, the first and second regions may be arranged from left to right in a first direction, wherein the load matching region may include a first load matching region disposed on a left side of the first region and a second load matching region disposed on a right side of the second region.

[0013] According to some example embodiments, the first load matching region may have a convex shape in a direction opposite to the first direction.

[0014] According to some example embodiments, the load matching region may further include a third load matching region disposed on the right side of the first region and a fourth load matching region disposed on the left side of the second region.

[0015] According to some example embodiments, the third load matching region may include an upper region and a lower region arranged in a second direction perpendicular to the first direction, and widths of the upper region and the lower region in the first direction may gradually increase and then decrease in the second direction.

[0016] According to some example embodiments, the load unit of the first load matching region may be connected to the load unit of the third load matching region through a wiring that bypasses the first region.

[0017] According to some example embodiments, the dummy region may be provided between the first region and the second region.

[0018] According to some example embodiments, the first and second regions may be arranged from left to right in a first direction, wherein the load matching region may include a third load matching region disposed on the right side of the first region and a fourth load matching region disposed on the left side of the second region.

[0019] According to some example embodiments, the first wiring connected to the third load matching region may bypass the first region.

[0020] According to some example embodiments, a display panel includes: a substrate including a first area, a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; a plurality of pixels arranged in the display area; scan lines connected to the plurality of pixels, the scan lines extending in a first direction; data lines connected to the plurality of pixels, the data lines extending in a second direction intersecting the first direction; and a load matching area connected to a first scan line among the scan lines, the load matching area including load units arranged in the non-display area, wherein each of the load units includes a load semiconductor layer, a first load conductive layer, and a second load conductive layer at least partially overlapping each other, an insulating layer between the load semiconductor layer, the first load conductive layer, and the second load conductive layer, and the load semiconductor layer is electrically connected to the second load conductive layer, wherein the load units overlap with some of the data lines.

[0021] According to some example embodiments, some of the some of the data lines are located on the same layer as the second load conductive layer and are spaced apart from the second load conductive layer.

[0022] According to some example embodiments, the first load conductive layer may overlap some of the data lines.

[0023] According to some example embodiments, the data lines may include first and second data lines arranged on different layers, wherein the second data lines may alternate with the first data lines in areas surrounding the first and second areas.

[0024] According to some example embodiments, the display panel may further include: a dummy area, arranged between the first area and the second area, the dummy area including a dummy unit, wherein the dummy unit may include a dummy semiconductor layer, a first dummy conductive layer, and a second dummy conductive layer that are at least partially overlapped with each other, an insulating layer is between the dummy semiconductor layer, the first dummy conductive layer, and the second dummy conductive layer, and the dummy semiconductor layer and the first dummy conductive layer may be connected to the second dummy conductive layer via a second contact hole and a third contact hole, respectively.

[0025] According to some example embodiments, the first and second regions may be arranged from left to right in a first direction, wherein the load matching region may include a first load matching region disposed on a left side of the first region and a second load matching region disposed on a right side of the second region.

[0026] According to some example embodiments, the load matching region may further include a third load matching region disposed on the right side of the first region and a fourth load matching region disposed on the left side of the second region.

[0027] According to some example embodiments, the first and second regions may be arranged from left to right in a first direction, wherein the load matching region may include a third load matching region disposed on the right side of the first region and a fourth load matching region disposed on the left side of the second region.

[0028] According to some example embodiments, the display panel may further include: a third area arranged between the first area and the second area, wherein the first area, the third area and the second area may be arranged from left to right in a first direction, wherein the load matching area may include a first load matching area arranged on the left side of the first area and a second load matching area arranged on the right side of the second area.

[0029] According to some example embodiments, the display panel may further include a driving voltage line applying a driving voltage to the plurality of pixels, wherein the second load conductive layer may be connected to the driving voltage line. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become more apparent and easier to understand through the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic perspective view of a display device according to some example embodiments;

[0032] Figure 2 is a cross-sectional view of a display device according to some example embodiments;

[0033] Figure 3 is a cross-sectional view of a display device according to some example embodiments;

[0034] Figure 4 is a schematic plan view of a display panel according to some example embodiments;

[0035] Figure 5A and Figure 5B is an equivalent circuit diagram of a pixel that may be used according to some example embodiments;

[0036] Figure 6 yes Figure 4 An enlarged plan view of region III;

[0037] Figure 7 yes Figure 6 An enlarged plan view of region IV;

[0038] Figure 8 It is along Figure 6 The line A-A' and Figure 7 a cross-sectional view of the display panel taken along line BB' and line CC';

[0039] Figure 9is a cross-sectional view of a portion of a display panel according to some example embodiments;

[0040] Figure 10 is a plan view of a portion of a display panel according to some example embodiments;

[0041] Figure 11 is a plan view of a portion of a display panel according to some example embodiments;

[0042] Figure 12 is a plan view of a portion of a display panel according to some example embodiments; and

[0043] Figure 13 is a plan view of a portion of a display panel according to some example embodiments. DETAILED DESCRIPTION

[0044] Since the present disclosure allows for various changes and many embodiments, aspects of some example embodiments will be illustrated in the accompanying drawings and described in more detail in the written description. Hereinafter, the effects and features of the present disclosure and methods for achieving them will be described more fully with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. However, the present disclosure can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein.

[0045] One or more exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Regardless of the figure number, the same or corresponding components may be given the same reference numerals, and redundant explanations may be omitted.

[0046] It will be understood that although the terms "first," "second," etc. may be used herein to describe various components, these components should not be limited to these terms. These components are only used to distinguish one component from another.

[0047] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] It will also be understood that the term “comprise” and / or variations thereof used herein specify the presence of stated features or components, but does not preclude the presence or addition of one or more other features or components.

[0049] It will be understood that when a layer, region, or component is referred to as being "formed on" another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

[0050] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0051] When a certain embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0052] It will also be understood that when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, the layer, region, or component may be directly connected or coupled to the other layer, region, or component, or intervening layers, regions, or components may be present. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, the layer, region, or component may be directly electrically connected or coupled to the other layer, region, or component, or intervening layers, regions, or components may be present.

[0053] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0054] Figure 1 is a schematic perspective view of a display device 1 according to some example embodiments.

[0055] Reference Figure 1 , the display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light.

[0056] The display device 1 may provide an image through the display area DA. The display device 1 may include a liquid crystal display (LCD), an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a quantum dot light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display, or a cathode ray display.

[0057] Although an organic light emitting display will now be illustrated and described as the display device 1 according to some example embodiments, the present disclosure is not limited thereto, and various types of display devices may be used.

[0058] The display device 1 includes a first region R1 and a second region R2. In the first region R1 and the second region R2, electronic components are arranged as will be described later. Figure 2The first region R1 and the second region R2 can be understood as an opening region or a transmission region capable of transmitting light or / and sound, which is output from the electronic component to the outside or travels from the outside toward the electronic component. Figure 1 In the embodiment, the opening region or the transmission region is the first region R1 and the second region R2, but the present disclosure is not limited thereto and may include three or more opening regions or transmission regions.

[0059] According to some example embodiments, when light passes through the first and second regions R1 and R2 , light transmittance may be about 50% or more, about 70% or more, about 80% or more, or about 85% or more.

[0060] The non-display area NDA may include a first non-display area NDA1 surrounding the first and second areas R1 and R2 and a second non-display area NDA2 surrounding the display area DA. The first non-display area NDA1 may completely surround the first and second areas R1 and R2, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0061] Although the first region R1 and the second region R2 Figure 1 The first region R1 and the second region R2 are disposed on the upper right side of the display area DA, but the present disclosure is not limited thereto. According to some example embodiments, positions of the first region R1 and the second region R2 may vary.

[0062] Figure 2 is a cross-sectional view of a display device 1 according to some example embodiments, and may be viewed along Figure 1 The cross section corresponds to the line II-II'.

[0063] Reference Figure 2 The display device 1 may include a display panel 10 and first and second electronic elements 20 and 30 respectively corresponding to the first and second regions R1 and R2 of the display panel 10. According to some example embodiments, components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder, or a color filter and a black matrix, and a transparent window may be arranged on the display panel 10.

[0064] The display panel 10 may include a substrate 100 , an encapsulation substrate 400A as an encapsulation member facing the substrate 100 , and a sealing member 450 between the substrate 100 and the encapsulation substrate 400A.

[0065] The substrate 100 may include glass or a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a layer comprising the aforementioned polymer resin and an inorganic layer (not shown). The encapsulation substrate 400A may include glass or the aforementioned polymer resin.

[0066] Thin film transistors TFT and organic light emitting diodes OLED as display elements connected thereto are arranged in the display area DA of the substrate 100. Signal lines SGL and dummy thin film transistors TFT' are arranged in the first non-display area NDA1 of the substrate 100.

[0067] According to some example embodiments, the signal line SGL may provide a certain signal (eg, a data signal and a scan signal) to display elements spaced apart from each other in the y-direction with respect to the first and second regions R1 and R2 .

[0068] The display panel 10 may include through holes corresponding to the first and second regions R1 and R2. For example, the substrate 100 and the encapsulation substrate 400A may include through holes 100H and 400AH, respectively, wherein the through hole 100H corresponds to the first and second regions R1 and R2, and the through hole 400AH corresponds to the first and second regions R1 and R2, and portions of the insulating layer IL or elements between the substrate 100 and the encapsulation substrate 400A (i.e., portions corresponding to the first and second regions R1 and R2) may be entirely removed.

[0069] Figure 2 The sealing member 450 is shown to be disposed on both sides of the first and second regions R1 and R2 , but the first and second regions R1 and R2 may be understood to be completely surrounded by the sealing member 450 when viewed from a direction perpendicular to the main surface of the substrate 100 .

[0070] The first electronic component 20 and the second electronic component 30 may be disposed in the first region R1 and the second region R2, respectively. The first electronic component 20 and the second electronic component 30 may be electronic components that utilize light or sound. For example, the electronic component may be a sensor that receives and utilizes light (such as an infrared sensor), a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or identify a fingerprint, a small light that outputs light, or a speaker that outputs sound. Electronic components that utilize light may utilize light of various wavelengths (such as visible light, infrared light, and ultraviolet light).

[0071] In which Figure 2 In the case where the display panel 10 includes the through holes corresponding to the first and second regions R1 and R2 , light or sound output or received by the first and second electronic components 20 and 30 may be more effectively utilized.

[0072] although Figure 2 The display panel 10 in the embodiment includes through holes corresponding to the first and second regions R1 and R2, but embodiments of the present disclosure are not limited thereto. For example, the encapsulation substrate 400A may include through holes 400AH corresponding to the first and second regions R1 and R2, while the substrate 100 may not include through holes. According to some example embodiments, both the encapsulation substrate 400A and the substrate 100 in the display panel 10 may not include through holes corresponding to the first and second regions R1 and R2. Even if the substrate 100 and the encapsulation substrate 400A do not include through holes, a portion of the insulating layer IL or element between the substrate 100 and the encapsulation substrate 400A (i.e., a portion corresponding to the first and second regions R1 and R2) may be removed, thereby ensuring the transmittance of the first electronic component 20 and the second electronic component 30.

[0073] Figure 3 is a cross-sectional view of a display device 1 according to some example embodiments, and may be viewed along Figure 1 The cross section corresponds to the line II-II'.

[0074] Refer to above Figure 2 The display device 1 described is similar, Figure 3 The display device 1 may include a display panel 10 including a display element, and first and second electronic components 20 and 30 respectively corresponding to the first and second regions R1 and R2 of the display panel 10. According to some example embodiments, the display device 1 may further include an input sensing member, an anti-reflection member, a transparent window, etc., disposed on the display panel 10 for sensing a touch input.

[0075] Refer to above Figure 2 Unlike the display panel 10 described above, which includes the encapsulation substrate 400A and the sealing member 450 as encapsulation members, the display panel 10 according to some example embodiments may include a thin film encapsulation layer 400B. In this case, the display panel 10 may have further improved flexibility. Hereinafter, for ease of description, the differences between them will be mainly described.

[0076] The thin film encapsulation layer 400B may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 3A first inorganic encapsulating layer 410 and a second inorganic encapsulating layer 430 and an organic encapsulating layer 420 between the first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 are shown.

[0077] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include at least one inorganic insulating material (such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride). The organic encapsulation layer 420 may include a polymer material. Examples of polymer materials may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0078] The display panel 10 may include through holes corresponding to the first and second regions R1 and R2. For example, the substrate 100 and the thin film encapsulation layer 400B may include through holes 100H corresponding to the first and second regions R1 and R2, respectively, and through holes 400BH corresponding to the first and second regions R1 and R2. As described above, the first and second electronic components 20 and 30 utilizing light or sound may be arranged in the first and second regions R1 and R2, respectively.

[0079] In the case where the display panel 10 includes through holes corresponding to the first and second regions R1 and R2 Figure 3 Differently, the display panel 10 may not include a through hole. For example, the thin film encapsulation layer 400B may include a through hole 400BH corresponding to the first region R1 and the second region R2, while the substrate 100 may not include a through hole. According to some example embodiments, both the thin film encapsulation layer 400B and the substrate 100 may not include a through hole corresponding to the first region R1 and the second region R2. Even if the substrate 100 does not include a through hole 100H, a portion of the insulating layer IL or element between the substrate 100 and the thin film encapsulation layer 400B (i.e., a portion corresponding to the first region R1 and the second region R2) may be removed, thereby ensuring the transmittance of the first electronic component 20 and the second electronic component 30.

[0080] Figure 4 is a schematic plan view of a display panel 10 according to some example embodiments.

[0081] Reference Figure 4 The display panel 10 includes a plurality of pixels P arranged in a display area DA. The plurality of pixels P may be connected to scan lines SLa and SLb extending in a first direction (x direction) and data lines DL and driving voltage lines PL both extending in a second direction (y direction) intersecting the first direction.

[0082] Each of the pixels P may include a display element (such as an organic light emitting diode). The pixel P may emit, for example, red light, green light, blue light, or white light via the organic light emitting diode. The pixel P used herein may be understood as a pixel that emits one of red light, green light, blue light, and white light as described above. The display area DA may be displayed by being referred to above. Figure 2 and Figure 3 The described packaging member is covered and protected from external air or moisture.

[0083] The first non-display area NDA1 surrounds the first and second areas R1 and R2. The first non-display area NDA1 is an area where no image is displayed. Signal lines that supply signals to pixels P around the first and second areas R1 and R2 may be arranged in the first non-display area NDA1.

[0084] The first scan driver 1100 and the second scan driver 1200 for providing scan signals to the pixels P may be disposed in the second non-display area NDA2. The first scan driver 1100 may be disposed corresponding to the left side of the display area DA, and the second scan driver 1200 may be disposed corresponding to the right side of the display area DA.

[0085] The scan signal generated by the first scan driver 1100 may be supplied to some pixels P and the scan signal generated by the second scan driver 1200 may be supplied to the remaining pixels P.

[0086] The first scan driver 1100 and the second scan driver 1200 may be arranged on both sides of the display area DA and may perform dual scanning. For example, the first scan driver 1100 may generate a scan signal and transmit the generated scan signal to some pixels P from among the pixels P included in the display area DA, and the second scan driver 1200 may generate a scan signal and transmit the generated scan signal to the remaining pixels P from among the pixels P included in the display area DA. The first scan driver 1100 and the second scan driver 1200 may be synchronized by a synchronization clock signal.

[0087] According to some example embodiments, the pixels P arranged on the left side of the first non-display area NDA1 may receive a scan signal generated by the first scan driver 1100 , and the pixels P arranged on the right side of the first non-display area NDA1 may receive a scan signal generated by the second scan driver 1200 .

[0088] A data driver 2000 for supplying data signals to the pixels P and the dummy pixels, a main power line for supplying a driving voltage and a common voltage, etc. may be disposed in the second non-display area NDA2.

[0089] Figure 5A and Figure 5B is an equivalent circuit diagram of a pixel P of the display panel 10 according to some example embodiments.

[0090] Reference Figure 5A , each pixel P includes a pixel circuit PC connected to a scan line SL and a data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

[0091] The pixel circuit PC may include a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst. The switching TFT T2 is connected to the scan line SL and the data line DL and transmits a data signal Dm received via the data line DL to the driving TFT T1 according to a scan signal Sn received via the scan line SL.

[0092] The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL and stores a voltage corresponding to a difference between a voltage received from the switching TFT T2 and a first power voltage (or driving voltage) ELVDD supplied to the driving voltage line PL.

[0093] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness according to the driving current.

[0094] Despite Figure 5A , a case where the pixel circuit PC includes two TFTs and one storage capacitor is shown, but the present disclosure is not limited thereto. Figure 5B As shown in , the pixel circuit PC may include seven TFTs and one storage capacitor.

[0095] Reference Figure 5B Each pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a plurality of TFTs and a storage capacitor Cst. The TFTs and storage capacitor Cst may be connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL.

[0096] Despite Figure 5B Each pixel P is connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL, but the present disclosure is not limited thereto. According to some example embodiments, at least one of the initialization voltage line VL, the driving voltage line PL, and the signal lines SL, SL-1, EL, and DL may be shared by adjacent pixels P.

[0097] The plurality of TFTs may include a driving TFT T1 , a switching TFT T2 , a compensation TFT T3 , a first initialization TFT T4 , an operation control TFT T5 , a light emission control TFT T6 , and a second initialization TFT T7 .

[0098] The signal lines SL, SL-1, EL, and DL may include a scan line SL that transmits a scan signal Sn, a previous scan line SL-1 that transmits a previous scan signal Sn-1 to a first initialization TFT T4 and a second initialization TFT T7, a light emission control line EL that transmits a light emission control signal En to an operation control TFT T5 and a light emission control TFT T6, and a data line DL that intersects the scan line SL and transmits a data signal Dm. A driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and an initialization voltage line VL transmits an initialization voltage Vint that initializes the driving TFT T1 and a pixel electrode of the organic light emitting diode OLED.

[0099] The driving TFT T1 includes: a driving gate electrode G1 connected to the first storage capacitor plate Cst1 (CE1) of the storage capacitor Cst; a driving source electrode S1 connected to the driving voltage line PL as the lower driving voltage line via the operation control TFT T5; and a driving drain electrode D1 electrically connected to the pixel electrode of the organic light emitting diode OLED via the light emission control TFT T6. The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2 and converts the driving current I OLED Supply to organic light-emitting diodes OLED.

[0100] The switching TFT T2 includes a switching gate electrode G2 connected to the scan line SL, a switching source electrode S2 connected to the data line DL, and a switching drain electrode D2 connected to the driving source electrode S1 of the driving TFT T1 and further connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on by a scan signal Sn received via the scan line SL and performs a switching operation to transmit a data signal Dm received from the data line DL to the driving source electrode S1 of the driving TFT T1.

[0101] The compensation TFT T3 includes a compensation gate electrode G3 connected to the scan line SL; a compensation source electrode S3 connected to the driving drain electrode D1 of the driving TFT T1 and also connected to the pixel electrode of the organic light emitting diode OLED via the light emission control TFT T6; and a compensation drain electrode D3 connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization TFT T4, and the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on in response to a scan signal Sn received via the scan line SL and electrically connects the driving gate electrode G1 and the driving drain electrode D1 of the driving TFT T1 to each other, so that the driving TFT T1 is diode-connected.

[0102] The first initialization TFT T4 includes a first initialization gate electrode G4 connected to the previous scan line SL-1; a first initialization source electrode S4 connected to the second initialization drain electrode D7 of the second initialization TFT T7 and the initialization voltage line VL; and a first initialization drain electrode D4 connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on in response to the previous scan signal Sn-1 received via the previous scan line SL-1 and transmits the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1, thereby initializing the voltage of the driving gate electrode G1 of the driving TFT T1.

[0103] The operation control TFT T5 includes: an operation control gate electrode G5 connected to the light emission control line EL; an operation control source electrode S5 connected to the driving voltage line PL; and an operation control drain electrode D5 connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0104] The light emission control TFT T6 includes: a light emission control gate electrode G6 connected to the light emission control line EL; a light emission control source electrode S6 connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3; and a light emission control drain electrode D6 electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0105] The operation control TFT T5 and the light emission control TFT T6 are simultaneously turned on according to the light emission control signal En received via the light emission control line EL, thereby transmitting the driving voltage ELVDD to the organic light emitting diode OLED so that the driving current I OLED Can flow in organic light-emitting diodes (OLEDs).

[0106] The second initialization TFT T7 includes a second initialization gate electrode G7 connected to the previous scan line SL-1; a second initialization source electrode S7 connected to the light emission control drain electrode D6 of the light emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED; and a second initialization drain electrode D7 connected to the first initialization source electrode S4 of the first initialization TFT T4 and the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 received via the previous scan line SL-1, and initializes the pixel electrode of the organic light emitting diode OLED.

[0107] Despite Figure 5B The first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SL-1, but the present disclosure is not limited thereto. According to some example embodiments, the first initialization TFT T4 may be connected to the previous scan line SL-1 and operate according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., a subsequent scan line) and operate according to a signal transmitted to the separate signal line.

[0108] The second storage capacitor plate Cst2 (CE2) of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving TFT T1. OLED and emits light, thereby displaying images.

[0109] Despite Figure 5B Each of the compensation TFT T3 and the first initialization TFT T4 has a double gate electrode, but each of the compensation TFT T3 and the first initialization TFT T4 may have a single gate electrode.

[0110] Figure 6 yes Figure 4 An enlarged plan view of region III, Figure 7 yes Figure 6 An enlarged plan view of region IV, Figure 8 It is along Figure 6 The line A-A' and Figure 7 1 is a cross-sectional view of the display panel 10 taken along line BB′ and line CC′.

[0111] Reference Figure 6 , the first and second regions R1 and R2 are arranged in the first direction, the first non-display area NDA1 surrounds the first and second regions R1 and R2, and the display area DA surrounds the first non-display area NDA1.

[0112] A plurality of pixels P may be arranged in the display area DA, and a first load matching area LMA1 , a second load matching area LMA2 , and a dummy area DMA may be arranged in the first non-display area NDA1 .

[0113] A plurality of signal lines may be arranged to electrically connect a plurality of pixels P. In this regard, Figure 6 It is shown that the first scan line SLa and the second scan line SLb each extending in the first direction (x direction) connect the pixels P in the display area DA, and the data line DLa and the data line DLb connect the pixels P along the second direction (y direction) intersecting the first direction.

[0114] According to some example embodiments, each of the first scan line SLa and the second scan line SLb may extend in the first direction (x direction), but may be disconnected in the first non-display area NDA1.

[0115] The second scan lines SLb arranged away from the first and second regions R1 and R2 in the first non-display area NDA1 or the second scan lines SLb that do not cross the first non-display area NDA1 may extend in the first direction to cross the display area DA without being disconnected. In this case, some of the second scan lines SLb crossing the first non-display area NDA1 may be arranged to bypass the first and second regions R1 and R2 without being disconnected.

[0116] If the first and second scan lines SLa and SLb crossing the first non-display area NDA1 are arranged to bypass the first and second regions R1 and R2 without being disconnected, more space may be required for the first non-display area NDA1 due to the bypassing of the scan lines SLa and SLb.

[0117] According to some example embodiments, the first scan line SLa of the first scan line SLa and the second scan line SLb crossing the first non-display area NDA1 is disconnected in the first non-display area NDA1, and thus, the space of the first non-display area NDA1 (e.g., the upper area or the lower area of the first non-display area NDA1) may be reduced.

[0118] The length of the first scan line SLa is shorter than that of the second scan line SLb, and the number of pixels P connected to the first scan line SLa is less than the number of pixels P connected to the second scan line SLb, so the load connected to the first scan line SLa can be different from the load connected to the second scan line SLb.

[0119] Therefore, according to some example embodiments, a load matching region in which a load unit is connected to the first scan line SLa to match a load connected to the first scan line SLa with a load connected to the second scan line SLb is provided.

[0120] In addition, according to some example embodiments, a dummy area DMA for matching pattern density may be located in the first non-display area NDA1 in which the load matching areas LMA1 and LMA2 are not arranged.

[0121] The load matching region may include a first load matching region LMA1 and a second load matching region LMA2. The first load matching region LMA1 may be disposed on the left side of the first region R1 and connected to the first scan line SLa disposed on the left side of the first region R1. The second load matching region LMA2 may be disposed on the right side of the second region R2 and connected to the first scan line SLa disposed on the right side of the second region R2.

[0122] The first load matching area LMA1 may have a convex shape in the first direction (-x direction). It is understood that the width of the first load matching area LMA1 in the first direction gradually increases and then decreases in the second direction. Alternatively, the first load matching area LMA1 may have a crescent shape.

[0123] The second load matching area LMA2 may have a convex shape in the first direction (+x direction). It is understood that the width of the second load matching area LMA2 in the first direction gradually increases and then decreases in the second direction. Alternatively, the second load matching area LMA2 may have a crescent shape.

[0124] However, according to some example embodiments of the present disclosure, the shapes of the first and second load matching areas LMA1 and LMA2 are not limited thereto. The first and second load matching areas LMA1 and LMA2 may have various shapes such as polygonal, circular, and elliptical shapes.

[0125] The dummy area DMA may be disposed between the first area R1 and the second area R2 .The dummy area DMA may be disposed between the first load matching area LMA1 and the second load matching area LMA2 and spaced apart from the first load matching area LMA1 and the second load matching area LMA2 .

[0126] The data lines DLa and DLb crossing the first non-display area NDA1 may extend in the second direction to cross the first and second load matching areas LMA1 and LMA2 and the dummy area DMA. That is, the data lines DLa and DLb may at least partially overlap the first and second load matching areas LMA1 and LMA2 and / or the dummy area DMA.

[0127] Reference Figure 7 and Figure 8The first load matching region LMA1 and the second load matching region LMA2 include a plurality of load units LU. Each of the load units LU may include a load semiconductor layer L10, a first load conductive layer L20, and a second load conductive layer L30. The load semiconductor layer L10, the first load conductive layer L20, and the second load conductive layer L30 are at least partially overlapped with each other, with insulating layers 112, 113, and 115 therebetween.

[0128] Since the load semiconductor layer L10 , the first load conductive layer L20 , and the second load conductive layer L30 in the load unit LU at least partially overlap each other, capacitance may be formed and functions as a load.

[0129] The first load conductive layer L20 may extend in the first direction. The first load conductive layer L20 may be provided on the same layer as the first scan line SLa and may be formed integrally with the first scan line SLa. However, the present disclosure is not limited thereto. The first load conductive layer L20 may be provided on a different layer from the first scan line SLa and may be connected to the first scan line SLa through a contact hole.

[0130] According to some example embodiments, a width W1 of the first load conductive layer L20 may be greater than a width W2 of the first scan line SLa. The width W1 of the first load conductive layer L20 may be variously changed according to the size of the load.

[0131] The second load conductive layer L30 may extend in the second direction. The second load conductive layer L30 may be integrally formed with the driving voltage line PL for transmitting the driving voltage ELVDD to the pixel P. In other words, the second load conductive layer L30 may receive the driving voltage ELVDD. The second load conductive layer L30 may be connected to the load semiconductor layer L10 through the first contact hole CNT1. Therefore, the load semiconductor layer L10 may have the same voltage level as the second load conductive layer L30. The load semiconductor layer L10 may have an island shape in the first non-display area NDA1.

[0132] The first load conductive layer L20 of the load unit LU may be electrically connected to the first scan line SLa, and the second load conductive layer L30 and the load semiconductor layer L10 may be electrically connected to the driving voltage line PL.

[0133] The dummy area DMA includes a plurality of dummy units DU. Each of the dummy units DU includes a dummy semiconductor layer D10, a first dummy conductive layer D20, and a second dummy conductive layer D30, which at least partially overlap each other with insulating layers 112, 113, and 115 therebetween.

[0134] The dummy unit DU may be disposed in an area of the first non-display area NDA1 where the load unit LU is not disposed. The dummy unit DU may be disposed to adjust pattern density and reduce process defects. Therefore, the dummy unit DU may be disposed separately from the load unit LU. That is, the first dummy conductive layer D20 may extend in the first direction, and an end portion of the first dummy conductive layer D20 may be spaced apart from an end portion of the first load conductive layer L20.

[0135] The second dummy conductive layer D30 may extend in the second direction. The second dummy conductive layer D30 may be integrally formed with the driving voltage line PL for transmitting the driving voltage ELVDD to the pixel P. That is, the second dummy conductive layer D30 may receive the driving voltage ELVDD. The second dummy conductive layer D30 may be connected to the dummy semiconductor layer D10 via the second contact hole CNT2. In addition, the second dummy conductive layer D30 may be connected to the first dummy conductive layer D20 via the third contact hole CNT3.

[0136] Therefore, the dummy semiconductor layer D10 and the first dummy conductive layer D20 may have the same voltage level as the second dummy conductive layer D30. The dummy semiconductor layer D10 and the first dummy conductive layer D20 may have an island shape in the first non-display area NDA1. Damage caused by electrostatic discharge can be reduced by receiving a voltage on the dummy semiconductor layer D10 and the first dummy conductive layer D20.

[0137] The first and second data lines DL1 and DL2 may be arranged in the first and second load matching areas LMA1 and LMA2 and the dummy area DMA. The first and second data lines DL1 and DL2 may overlap with the load unit LU and / or the dummy unit DU. For example, the first and second data lines DL1 and DL2 may overlap with the first load conductive layer L20 of the load unit LU. The first and second data lines DL1 and DL2 may not overlap with the load semiconductor layer L10 and the second load conductive layer L30 of the load unit LU. In some embodiments, the first data line DL1 may be arranged on the same layer as the second load conductive layer L30 and separated from the second load conductive layer L30. The second data line DL2 may be arranged on a different layer from the first data line DL1. The first and second data lines DL1 and DL2 arranged in different layers may be arranged alternately to reduce the spacing between the first and second data lines DL1 and DL2.

[0138] Now refer to Figure 8 The structures of the pixel P, the load unit LU, and the dummy unit DU are described in a stacking order.

[0139] The substrate 100 may include a glass material, a metal material, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin (such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate). The substrate 100 may have a single layer or multilayer structure of any of the aforementioned materials. The multilayer structure may also include an inorganic layer. In some embodiments, the substrate 100 may have a structure of an organic material / inorganic material / organic material.

[0140] The buffer layer 111 may be provided on the substrate 100 and may reduce or prevent infiltration of foreign matter, moisture, or ambient air from below the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic-inorganic composite, and may be formed as a single layer or multiple layers of an inorganic material and / or an organic material.

[0141] According to some example embodiments, a barrier layer may be further included between the substrate 100 and the buffer layer 111. The barrier layer may prevent or reduce the penetration of impurities from the substrate 100, etc. into the semiconductor layer (i.e., the semiconductor layer A of the thin film transistor TFT, the load semiconductor layer L10, and the dummy semiconductor layer D10). The barrier layer may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic-inorganic composite, and may be formed as a single layer or multiple layers of an inorganic material and / or an organic material.

[0142] The semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 of the thin film transistor TFT may be arranged on the buffer layer 111. The semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may include amorphous silicon or polycrystalline silicon. According to some example embodiments, the semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may include an oxide of at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). According to some example embodiments, the semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may include Zn oxide, In-Zn oxide, Ga-In-Zn oxide, or the like as a Zn oxide-based material. In other embodiments, the semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may be an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor containing a metal (such as In, Ga, and / or Sn) in ZnO. The semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may include a channel region and a source region and a drain region respectively arranged on both sides of the channel region. Each of the semiconductor layer A, the load semiconductor layer L10, and the dummy semiconductor layer D10 may be formed as a single layer or multiple layers.

[0143] The gate electrode G is disposed on the semiconductor layer A of the thin film transistor TFT, with the first gate insulating layer 112 between the gate electrode G and the semiconductor layer A of the thin film transistor TFT, so that the gate electrode G at least partially overlaps the semiconductor layer A. The gate electrode G may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may include a single layer or multiple layers. For example, the gate electrode G may include a single layer of Mo.

[0144] The first load conductive layer L20 may be formed on the first gate insulating layer 112 to at least partially overlap the load semiconductor layer L10. The first load conductive layer L20 may be formed on the same layer as the gate electrode G and include the same material as the gate electrode G.

[0145] The first dummy conductive layer D20 may be formed on the first gate insulating layer 112 to at least partially overlap the dummy semiconductor layer D10. The first dummy conductive layer D20 may be formed in the same layer as the gate electrode G and include the same material as the gate electrode G.

[0146] The first gate insulating layer 112 may include silicon oxide (SiO2), silicon nitride (SiN x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc.

[0147] A second gate insulating layer 113 may be included so that the second gate insulating layer 113 covers the gate electrode G, the first load conductive layer L20 and the first dummy conductive layer D20. The second gate insulating layer 113 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc.

[0148] The first storage capacitor plate CE1 of the storage capacitor Cst may overlap the thin film transistor TFT. For example, the gate electrode G of the thin film transistor TFT may serve as the first storage capacitor plate CE1 of the storage capacitor Cst.

[0149] The second storage capacitor plate CE2 of the storage capacitor Cst overlaps the first storage capacitor plate CE1, with the second gate insulating layer 113 between the second storage capacitor plate CE2 and the first storage capacitor plate CE1. In this case, the second gate insulating layer 113 can serve as a dielectric layer for the storage capacitor Cst. The second storage capacitor plate CE2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may be formed as a multilayer or single layer including the aforementioned materials. For example, the second storage capacitor plate CE2 may include a single layer of Mo or a multilayer of Mo / Al / Mo.

[0150] Although the storage capacitor Cst is overlapped with the thin film transistor TFT in the drawings, the present disclosure is not limited thereto. The storage capacitor Cst may not overlap with the thin film transistor TFT. In this manner, various modifications may be made.

[0151] An interlayer insulating layer 115 may be included to cover the second storage capacitor plate CE2 of the storage capacitor Cst. The interlayer insulating layer 115 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO2), etc.

[0152] The source electrode S and drain electrode D of the thin film transistor TFT may be disposed on the interlayer insulating layer 115. Each of the source electrode S and drain electrode D may include a conductive material including Mo, Al, Cu, or Ti, and may be a multilayer or single layer including the foregoing materials. For example, each of the source electrode S and drain electrode D may be a multilayer of Ti / Al / Ti.

[0153] The second load conductive layer L30, the second dummy conductive layer D30, and the first data line DL1 may be disposed on the interlayer insulating layer 115. The second load conductive layer L30 on the interlayer insulating layer 115 may at least partially overlap the load semiconductor layer L10 and the first load conductive layer L20. The second load conductive layer L30 may be electrically connected to the load semiconductor layer L10 via a first contact hole CNT1 penetrating the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112.

[0154] A second dummy conductive layer D30 on the interlayer insulating layer 115 may at least partially overlap the dummy semiconductor layer D10 and the first dummy conductive layer D20. The second dummy conductive layer D30 may be electrically connected to the dummy semiconductor layer D10 via a second contact hole CNT2 penetrating the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. Furthermore, the second dummy conductive layer D30 may be connected to the first dummy conductive layer D20 via a third contact hole CNT3 penetrating the interlayer insulating layer 115 and the second gate insulating layer 113.

[0155] The first data line DL1 is a wiring for transferring a data signal Dm to the pixel P, and may be disposed to be separated from the second load conductive layer L30 and the second dummy conductive layer D30 .

[0156] The via layer 117 and the additional via layer 118 may be disposed on the source electrode S, the drain electrode D, the second load conductive layer L30, the second dummy conductive layer D30, and the first data line DL1, and the organic light emitting diode OLED may be disposed in a region of the pixel P located on the additional via layer 118. According to some example embodiments, the additional via layer 118 may be omitted.

[0157] The via layer 117 and the additional via layer 118 may have a flat upper surface so that the pixel electrode 310 may be formed to be flat. The via layer 117 and the additional via layer 118 may each be formed as a single layer including an organic material or as a multilayer including an organic material. The via layer 117 and the additional via layer 118 may include commercial polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA) or polystyrene (PS)), polymer derivatives with phenolic groups, acryl polymers, imide polymers, acryl ether polymers, amide polymers, fluorine polymers, paraxylene polymers, vinyl alcohol polymers or blends thereof, etc. The via layer 117 and the additional via layer 118 may include an inorganic material. The via layer 117 and the additional via layer 118 may include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). When the via layer 117 and the additional via layer 118 include an inorganic material, chemical planarization polishing may be performed. The via layer 117 may include both organic and inorganic materials.

[0158] The second data line DL2 may be disposed between the via layer 117 and the additional via layer 118. The second data line DL2 is a wiring for transferring a data signal Dm to the pixel P and may alternate with the first data line DL1 in a region bypassing the first and second regions R1 and R2.

[0159] In the display area DA of the substrate 100 , the organic light emitting diode OLED is disposed on the additional via layer 118 . The organic light emitting diode OLED includes a pixel electrode 310 , an opposing electrode 330 , and an intermediate layer 320 including an organic emission layer 321 .

[0160] A via hole through which one of the source electrode S and the drain electrode D of the thin film transistor TFT is exposed is formed in the via layer 117 and the additional via layer 118 , and the pixel electrode 310 contacts the source electrode S or the drain electrode D through the via hole and is electrically connected to the thin film transistor TFT.

[0161] The pixel electrode 310 may be a (semi) light-transmitting electrode or a reflective electrode. According to some example embodiments, the pixel electrode 310 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a mixture thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 310 may have a stacked structure of ITO / Ag / ITO.

[0162] The pixel defining layer 119 may be provided on the additional via layer 118. The pixel defining layer 119 may define the light emission area of the pixel P by including openings corresponding to the pixel electrodes 310, respectively, in the display area DA (i.e., openings OP through which at least the central portion of the pixel electrode 310 is exposed). The pixel defining layer 119 may prevent or reduce arcing, etc., occurring at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 provided on the pixel electrode 310. The pixel defining layer 119 may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), or phenolic resin by spin coating or the like.

[0163] The pixel P (i.e., the light emission area of the pixel P) may be defined by the opening OP of the pixel defining layer 119. In other words, the edge of the pixel P may mean the edge of the opening OP of the pixel defining layer 119. The edge of the opening OP of the pixel defining layer 119 may mean the boundary of the pixel electrode 310 exposed through the opening OP.

[0164] The intermediate layer 320 of the organic light emitting diode OLED may include an organic emission layer 321 , and a first common layer 322 and a second common layer 323 that may be disposed on the bottom and top of the organic emission layer 321 , respectively.

[0165] The organic emission layer 321 may include an organic material including a fluorescent material or a phosphorescent material that emits red, green, blue, or white light. The organic emission layer 321 may include a low molecular weight organic material or a high molecular weight organic material.

[0166] The first common layer 322 may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second common layer 323 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0167] The intermediate layer 320 may be arranged to correspond to each of the plurality of pixel electrodes 310. However, the present disclosure is not limited thereto. The intermediate layer 320 may include a single layer (i.e., a first common layer 322 and / or a second common layer 323) extending above the plurality of pixel electrodes 310. In this manner, various modifications may be made. The first common layer 322 and / or the second common layer 323 may be omitted.

[0168] The counter electrode 330 may include a light-transmitting electrode or a reflective electrode. According to some example embodiments, the counter electrode 330 may include a transparent or translucent electrode and may include a metal film with a small work function containing lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), silver (Ag), magnesium (Mg), or a mixture thereof. A TCO layer including a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) may be further provided on the metal film. The counter electrode 330 may extend over both the display area DA and the non-display area NDA and may be arranged on the intermediate layer 320 and the pixel defining layer 119. The counter electrode 330 may be formed as a single body constituting a plurality of organic light emitting diodes OLED and may therefore correspond to a plurality of pixel electrodes 310.

[0169] When the pixel electrode 310 includes a reflective electrode and the counter electrode 330 includes a light-transmitting electrode, light emitted by the intermediate layer 320 is emitted toward the counter electrode 330, and thus the display device 1 may be a top-emission type. When the pixel electrode 310 includes a transparent or semi-transparent electrode and the counter electrode 330 includes a reflective electrode, light emitted by the intermediate layer 320 is emitted toward the substrate 100, and thus the display device 1 may be a bottom-emission type. However, embodiments are not limited thereto. The display device 1 according to some example embodiments may be a dual-emission type that emits light in two directions (i.e., toward the top and bottom surfaces of the display device 1).

[0170] The capping layer 340 may be disposed on the counter electrode 330. The capping layer 340 may have a refractive index different from that of the counter electrode 330 (a refractive index lower or higher than that of the counter electrode 330), and may improve luminous efficiency by increasing the percentage of light generated by the intermediate layer 320 including the organic emission layer 321 being totally reflected and emitted to the outside.

[0171] For example, the capping layer 340 may include an organic material such as poly(3,4-ethylenedioxythiophene) (or PEDOT), 4,4'-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (TPD), 4,4',4"-tris[(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), 1,3,5-tris[N,N-bis(2-methylphenyl)-amino]-benzene (o-MTDAB), 1,3,5-tris[N,N-bis(3-methylphenyl)-amino]-benzene (m-MTDAT ...m-MTDAT), 1,3,5-tris[N,N-bis(3-methylphenyl)-amino]-benzene (m-MTDAT), 1,3,5-tris[N,N-bis(2-methylphenyl)-amino]-benzene (m-MTDAT), 1,3,5-tris[N,N-bis(2-methylphenyl)-amino]-benzene (m-MTDATA), 1,3,5-tris[N,N-bis(2-methylphenyl)-amino]-benzene (m-MTDAT), 1,3,5-tris[N,N-bis(3-methylphenyl)-amino]-benzene (m- [N,N-bis(4-methylphenyl)-amino]-benzene (p-MTDAB), 4,4'-bis[N,N-bis(3-methylphenyl)-amino]-diphenylmethane (BPPM), 4,4'-dicarbazolyl-1,1'-biphenyl (CBP), 4,4',4"-tris(N-carbazolyl)triphenylamine (TCTA), 2,2',2"-(1,3,5-phenyltriyl)tris-[1-phenyl-1H-benzimidazole] (TPBI), and 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ).

[0172] Alternatively, the capping layer 340 may include an inorganic material such as zinc oxide, titanium oxide, zirconium oxide, silicon nitride, niobium oxide, tantalum oxide, tin oxide, nickel oxide, indium nitride, and gallium nitride. The material for forming the capping layer 340 is not limited thereto, and various other materials may be used.

[0173] According to some example embodiments, a capping layer may be disposed on the capping layer 340. The capping layer protects the organic light emitting diode OLED from damage that may occur during a subsequent process using plasma, etc. The capping layer may include LiF.

[0174] Figure 9 is a cross-sectional view of a portion of the display panel 10 according to some example embodiments. Figure 9 In, with Figure 8 The same reference numerals as in the figures denote the same components, and thus repeated description thereof will be omitted.

[0175] Reference Figure 9 The load unit LU includes a load semiconductor layer L10, a first load conductive layer L20, and a second load conductive layer L30. The load semiconductor layer L10, the first load conductive layer L20, the second load conductive layer L30 and the insulating layer (i.e., the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115) at least partially overlap each other, and the load semiconductor layer L10 is connected to the second load conductive layer L30 via the first contact hole CNT1.

[0176] The dummy unit DU includes a dummy semiconductor layer D10, a first dummy conductive layer D20 and a second dummy conductive layer D30, the dummy semiconductor layer D10, the first dummy conductive layer D20 and the second dummy conductive layer D30, the first gate insulating layer 112, the second gate insulating layer 113 and the interlayer insulating layer 115 at least partially overlap each other, and the dummy semiconductor layer D10 and the first dummy conductive layer D20 are electrically connected to the second dummy conductive layer D30 via the second contact hole CNT2 and the third contact hole CNT3, respectively.

[0177] According to some example embodiments, the first load conductive layer L20 and / or the first dummy conductive layer D20 may be disposed on the second gate insulating layer 113. That is, the first load conductive layer L20 and / or the first dummy conductive layer D20 may be formed in the same layer as the second storage capacitor plate CE2 and include the same material as the second storage capacitor plate CE2. Therefore, the first gate insulating layer 112 and the second gate insulating layer 113 are disposed between the first load conductive layer L20 and the load semiconductor layer L10. Therefore, the distance between the first load conductive layer L20 and the load semiconductor layer L10 can be increased, and thus damage caused by electrostatic discharge can be reduced.

[0178] Figure 10 is a plan view of a portion of the display panel 10 according to some example embodiments. Figure 10 In, with Figure 6 The same reference numerals as in the figures denote the same components, and thus repeated description thereof will be omitted.

[0179] Reference Figure 10 , the first and second regions R1 and R2 are arranged in the first direction, and the first non-display area NDA1 surrounds the first and second regions R1 and R2 and the display area DA surrounds the first non-display area NDA1.

[0180] A plurality of pixels P may be arranged in the display area DA, and a third load matching area LMA3 , a fourth load matching area LMA4 , and a dummy area DMA may be arranged in the first non-display area NDA1 .

[0181] According to some example embodiments, the third load matching area LMA3 and the fourth load matching area LMA4 may be arranged between the first region R1 and the second region R2. That is, the third load matching area LMA3 may be located on the right side of the first region R1, and the fourth load matching area LMA4 may be located on the left side of the second region R2.

[0182] The locations of the third and fourth load matching areas LMA3 and LMA4 can be set based on the size of the dead space. For example, if a large number of load units LU are required within the third and fourth load matching areas LMA3 and LMA4, the non-display area on the left side of the first region R1 may be insufficient. Therefore, the third and fourth load matching areas LMA3 and LMA4 can be positioned between the first and second regions R1 and R2 to effectively utilize the space within the first non-display area NDA1.

[0183] When the third and fourth load matching areas LMA3 and LMA4 are disposed between the first and second regions R1 and R2 , the first scan lines SLa of the load units LU connected to the third and fourth load matching areas LMA3 and LMA4 may bypass the first or second region R1 or R2 .

[0184] Some of the first scan lines SLa may bypass the upper portion of the first region R1, and the remaining first scan lines SLa may bypass the lower portion of the first region R1. Therefore, the third load matching area LMA3 may be divided into an upper load area LMA3-1 and a lower load area LMA3-2.

[0185] According to some example embodiments, the widths of the upper load area LMA3-1 and the lower load area LMA3-2 in the first direction may gradually increase and then decrease in the second direction. Likewise, the fourth load matching area LMA4 may be divided into the upper load area LMA4-1 and the lower load area LMA4-2.

[0186] The dummy area DMA may be between the third load matching area LMA3 and the fourth load matching area LMA4 and may be disposed to be separated from the third load matching area LMA3 and the fourth load matching area LMA4.

[0187] The data lines DLa and DLb extending in the second direction may be arranged to overlap the third load matching area LMA3 , the fourth load matching area LMA4 , and the dummy area DMA.

[0188] The load unit LU included in each of the third load matching area LMA3 and the fourth load matching area LMA4 may have a reference Figures 7 to 9 The dummy unit DU included in the dummy area DMA may have a structure similar to that of the load unit LU. Figures 7 to 9 The structure of the dummy unit DU is described.

[0189] Figures 11 to 13 is a plan view of a portion of the display panel 10 according to some example embodiments. Figures 11 to 13 In, with Figure 6 and Figure 10 The same reference numerals as in the figures denote the same components, and thus some repeated descriptions thereof will be omitted.

[0190] Reference Figure 11 , the first and second regions R1 and R2 are arranged in the first direction, the first non-display area NDA1 surrounds the first and second regions R1 and R2 , and the display area DA surrounds the first non-display area NDA1 .

[0191] A plurality of pixels P may be arranged in the display area DA, and first to fourth load matching areas LMA1 to LMA4 and a dummy area DMA may be arranged in the first non-display area NDA1 .

[0192] The first load matching area LMA1 may be disposed on the left side of the first region R1, and the second load matching area LMA2 may be disposed on the right side of the second region R2. The third load matching area LMA3 and the fourth load matching area LMA4 may be arranged between the first region R1 and the second region R2. That is, the third load matching area LMA3 may be disposed on the right side of the first region R1, and the fourth load matching area LMA4 may be disposed on the left side of the second region R2.

[0193] Since the first load matching area LMA1 to the fourth load matching area LMA4 are arranged on the left and right sides of the first area R1 and the second area R2, some of the first scan lines SLa connected to the first load matching area LMA1 to the fourth load matching area LMA4 may bypass the first area R1 or the second area R2, and the remaining first scan lines SLa may not bypass the first area R1 or the second area R2.

[0194] The positions of the first to fourth load matching areas LMA1 to LMA4 may be set in consideration of the size of the dead space. That is, some of the first scan lines SLa may be connected to the first load matching area LMA1 on the left side of the first region R1, and some of the first scan lines SLa may be connected to the third load matching area LMA3 on the right side of the first region R1. As a result, the first to fourth load matching areas LMA1 to LMA4 may be effectively distributed within the first non-display area NDA1.

[0195] According to some example embodiments, the case where two transmission areas are provided has been described as an example. However, the present disclosure is not limited thereto. The present disclosure can also be applied to the case where three or four or more transmission areas are provided.

[0196] like Figure 12As shown in FIG, the third region R3 as a transmission region may be provided between the first region R1 and the second region R2. That is, the first region R1, the third region R3 and the second region R2 may be arranged side by side in the first direction. Figure 13 As shown in FIG, the third region R3 and the fourth region R4 as the transmission regions may be arranged between the first region R1 and the second region R2. That is, the first region R1, the third region R3, the fourth region R4 and the second region R2 may be arranged side by side in the first direction.

[0197] The first scan line SLa of the first and second scan lines SLb extending in the first direction may be disconnected on the left side of the first region R1 and on the right side of the second region R2. The first scan line SLa may be connected to the load units LU of the first and second load matching regions LMA1 and LMA2.

[0198] The dummy area DMA may be provided in the first non-display area NDA1 in which the first and second load matching areas LMA1 and LMA2 are not arranged, and may be spaced apart from the first and second load matching areas LMA1 and LMA2 .

[0199] The data lines DLa and DLb extending in the second direction may be arranged to overlap the first and second load matching areas LMA1 and LMA2 or the dummy area DMA.

[0200] The positions of the first load matching area LMA1 and the second load matching area LMA2 may be modified in various ways. The first load matching area LMA1 and the second load matching area LMA2 may be arranged to correspond to the upper or lower portions of the first to fourth regions R1 to R4. For example, Figure 13 As shown in FIG, the fifth load matching area LMA5 and the sixth load matching area LMA6 may be arranged at upper and lower portions of the middle portion of the first non-display area NDA1.

[0201] According to some example embodiments, load matching regions are provided near regions corresponding to electronic components such as sensors and cameras, thereby providing a display panel in which luminance deviation due to load differences is reduced. Furthermore, dummy regions are provided between the load matching regions, thereby making pattern density uniform and providing a high-quality display panel.

[0202] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

[0203] Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display panel, comprising: A substrate comprising: a first area; a second area; a non-display area surrounding the first area and the second area; and a display area surrounding the non-display area; a plurality of pixels located in the display area; a plurality of wirings configured to supply signals to the plurality of pixels; a load matching region connected to a first wiring among the plurality of wirings, located in the non-display region, and including a load unit; and a dummy area located between the first area and the second area and including a plurality of dummy units spaced apart from the load unit in the non-display area, wherein each of the load units comprises a load semiconductor layer, a first load conductive layer, and a second load conductive layer at least partially overlapping each other, an insulating layer is located between the load semiconductor layer, the first load conductive layer, and the second load conductive layer, and the load semiconductor layer is connected to the second load conductive layer via a first contact hole, and The first area and the second area are opening areas.

2. The display panel according to claim 1, wherein: The first wiring extends to the non-display area and is connected to the first load conductive layer.

3. The display panel according to claim 1, wherein: Each of the dummy units comprises: a dummy semiconductor layer; a first dummy conductive layer; and A second dummy conductive layer, the dummy semiconductor layer, the first dummy conductive layer and the second dummy conductive layer are at least partially overlapped with each other, and an insulating layer is located between the dummy semiconductor layer, the first dummy conductive layer and the second dummy conductive layer, wherein the dummy semiconductor layer and the first dummy conductive layer are connected to the second dummy conductive layer via a second contact hole and a third contact hole, respectively.

4. The display panel according to claim 1, wherein: The first area and the second area are arranged from left to right in a first direction, The load matching region includes a first load matching region located on the left side of the first region and a second load matching region located on the right side of the second region.

5. The display panel according to claim 4, wherein: The first load matching region has a convex shape in a direction opposite to the first direction. The display panel according to claim 4 , wherein: The load matching region further includes a third load matching region located on the right side of the first region and a fourth load matching region located on the left side of the second region.

7. The display panel according to claim 6, wherein: The third load matching region includes an upper region and a lower region arranged in a second direction perpendicular to the first direction, and widths of the upper region and the lower region in the first direction gradually increase and then decrease in the second direction.

8. The display panel according to claim 6, wherein: The load cells in the first load matching region are connected to the load cells in the third load matching region through wiring that bypasses the first region.

9. The display panel according to claim 1, wherein: The first area and the second area are arranged from left to right in a first direction, The load matching region includes a third load matching region located on the right side of the first region and a fourth load matching region located on the left side of the second region.

10. The display panel according to claim 9, wherein: The first wiring connected to the third load matching region bypasses the first region.

11. A display panel, comprising: A substrate comprising: a first area; a second area; a non-display area surrounding the first area and the second area; and a display area surrounding the non-display area; a plurality of pixels located in the display area; a plurality of scan lines connected to the plurality of pixels, the plurality of scan lines extending in a first direction; a plurality of data lines connected to the plurality of pixels, the plurality of data lines extending in a second direction intersecting the first direction; and a load matching region connected to a first scan line among the plurality of scan lines, arranged in the non-display region, and comprising a load unit, Each of the load units includes: a load semiconductor layer; a first load conductive layer; and a second load conductive layer, wherein the load semiconductor layer, the first load conductive layer, and the second load conductive layer are at least partially overlapped with each other, an insulating layer is located between the load semiconductor layer, the first load conductive layer, and the second load conductive layer, and the load semiconductor layer is electrically connected to the second load conductive layer. wherein the load unit overlaps with some of the plurality of data lines, and The first area and the second area are opening areas.

12. The display panel according to claim 11, wherein: Some of the some of the plurality of data lines are located on the same layer as the second load conductive layer and are spaced apart from the second load conductive layer.

13. The display panel according to claim 11, wherein: The first load conductive layer overlaps some of the plurality of data lines.

14. The display panel according to claim 11, wherein: The plurality of data lines include a first data line and a second data line located on different layers, The second data lines alternate with the first data lines in the first area and an area surrounding the second area.

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