Method, apparatus and circuit for controlling timing of hysteretic current mode boost converter

Abstract

To control the timing of a current-mode boost converter, an example device (626) includes: a first input terminal (632) receiving an input voltage (630) of the current-mode boost converter (602); a second input terminal (634) receiving an output voltage (616) of the current-mode boost converter (602); a generator (636) generating a first timing signal (640) based on the input voltage (630) and the output voltage (616); a third input terminal (624) receiving a second timing signal (640) from the current-mode boost converter (602); and a third input terminal (624) receiving a second timing signal (640) from the current-mode boost converter (602). timing signal (622); a selector (638) that selects between the first on-off time signal (640) and the second on-off time signal (622) based on a comparison of a first off-time duration of the first on-off time signal (640) and a second off-time duration of the second on-off time signal (622) to generate a third on-off time signal (628); and an output terminal (629) that controls the off time of the current mode boost converter (602) based on the third on-off time signal (628).

Description

Technical Field

[0001] The present application relates generally to hysteretic current mode boost controllers, and more particularly to methods, apparatus, and circuits for controlling the timing of a hysteretic current mode boost converter. Background Art

[0002] Some conventional high efficiency boost converters use a hysteretic current control mode. Summary of the invention

[0003] In order to control the timing of a current-mode boost converter, an example device for controlling the timing includes: a first input terminal, which receives an input voltage of the current-mode boost converter; a second input terminal, which receives an output voltage of the current-mode boost converter; a generator, which generates a first timing signal based on the input voltage and the output voltage; a third input terminal, which receives a second timing signal from the current-mode boost converter; a selector, which selects between the first on-off time signal and the second on-off time signal based on a comparison of a first off-time duration of the first on-off time signal and a second off-time duration of the second on-off time signal to generate a third on-off time signal; and an output terminal, which controls the off time of the current-mode boost converter based on the third on-off time signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is an example conventional system including a hysteretic current-mode boost converter.

[0005] FIG. 2 is a graph of example waveforms for the system of FIG. 1 .

[0006] FIG. 3 is an example conventional system including a hysteretic current mode boost converter and an external diode.

[0007] FIG. 4 is an example graph of example waveforms for the example system of FIG. 3 .

[0008] Figure 5 An example converter according to aspects of the present description is shown.

[0009] Figure 6 It can be used for implementation Figure 5 An example circuit for a converter.

[0010] Figure 7 It can be used for implementation Figure 6 An example circuit for a timing generator.

[0011] Figure 8 It can be used for implementation Figure 6 Another example circuit of a timing generator.

[0012] Fig. 9 It can be used for implementation Figure 6 An example circuit for a selector.

[0013] Fig.10 is an example graph depicting example waveforms for an example converter described herein that is configured with an external Schottky diode.

[0014] Fig.11 is an example flow chart representing example logic, hardware logic, hardware-implemented state machines, etc., and / or any combination thereof, for implementing the example converters described herein.

[0015] Fig.12 An example processor platform is shown that is configured to execute example machine-readable instructions and / or Fig.11 to implement the example converters described herein. DETAILED DESCRIPTION

[0016] It is useful to use the same reference numerals in the drawings and this specification to refer to the same or similar parts. The drawings are not drawn to scale. The connecting lines and / or connectors shown in the various drawings represent example functional relationships and / or physical or logical couplings between the various elements. In the context of circuits and / or circuit interconnections, such couplings are associated with corresponding electrical conductors and / or optical conductors, wires, traces, terminals, inputs, outputs, printed circuit board (PCB) pads, etc. For example, a line between two components in a circuit shown in the drawings includes a first input and / or output of the first component, a second input and / or output of the second component, and one or more interconnected conductive members.

[0017] FIG1 illustrates an example system 100 including an example hysteretic current mode boost converter 102. The current mode boost converter 102 of FIG1 has an input terminal 104 for receiving an input current 106 and an output terminal 108 for delivering an output current 110 based on the input current 106. The current mode boost converter 102 implements a hysteretic current mode to sense the inductor current 106. In general, the current mode boost converter 102 uses the output current 110 to regulate the inductor current 106, thereby maintaining a stable inductor current ripple and a stable output voltage VOUT 112.

[0018] 2 depicts an example waveform 202 of an example input voltage VIN 114, an example waveform 204 of an output voltage VOUT 112, and an example waveform 206 of an example inductor current 106 associated with the input current 106. As shown in FIG2 , waveforms 202, 204, and 206 are stable (e.g., waveforms having substantially consistent amplitude, frequency, duty cycle, average value, etc.).

[0019] 3, another example system 300 is shown that includes the hysteretic current mode boost converter 102 of FIG 1. In certain current mode boost converter systems, such as shown in FIG 3, an optional external Schottky diode D1 302 is added in parallel with the rectifier field effect transistor (FET) 304 of the current mode boost converter 102 to increase the output current capability, for example, for high output current applications.

[0020] However, as shown in the example graph 400 of FIG4, the addition of the Schottky diode D1 302 may cause instability in the current-mode boost converter 102. The example graph 400 of FIG4 depicts an example waveform 402 of the input voltage VIN 114, an example waveform 404 of the output voltage VOUT 112, and an example waveform 406 of the inductor current 106. As shown in FIG4, the waveforms 402, 404, and 406 oscillate in an unstable and undesirable manner compared to the more stable configuration of FIG1. ​​For example, the input voltage VIN 114 has a variable frequency, the average value of the output voltage VOUT 112 varies, etc.

[0021] 1-4 , these types of hysteretic current mode converters 102 may not operate as intended when using an external Schottky diode 302 to boost the output current capability of the converter 102. When the external Schottky diode 302 is included, some or all of the inductor current 106 flows through the external Schottky diode 302 instead of through the current mode boost converter 102. As a result, the current mode boost converter 102 may not accurately sense the inductor current 106, which may cause the current mode boost converter 102 to become unstable or operate in an undesirable manner.

[0022] The present specification provides one or more solutions to at least solve the above problems. For example, the present specification introduces one or more hysteretic current mode converters that operate stably with or without an external Schottky diode. In an external Schottky diode application, the described example hysteretic current mode converter controls the timing of the converter (e.g., off time, on time, etc.). The off time is a low side driver (LSD) FET (e.g., such as Figure 6 The example LSDFET 612 shown) is turned off and the high-side driver (HSD) FET (e.g., Figure 6 The example HSD FET 613 shown is the period of time that the LSD FET is on. In contrast, the on-time is the period of time that the LSD FET is on and the HSD FET is off. The described hysteretic current mode converter controls the off-time to be substantially constant (e.g., within an expected variable range of each other, etc.).

[0023] Although reference is made herein to generating off-time signals TOFF, TOFF_HC, and TOFF_FIX in conjunction with controlling the timing of a current-mode boost converter to ensure stability of the current-mode boost converter, such off-time signals control both the off-time and the on-time. When the timing does not indicate an off-time, an on-time is indicated. Therefore, the examples described herein control both the on-time and the off-time of a current-mode boost converter and may be more generally represented as timing signals.

[0024] Figure 5 An example converter 500 is shown in accordance with aspects of the present specification. To boost or increase a first (e.g., input) current 502 at a first (e.g., input) terminal 504 to generate a second (e.g., output) current 506 at a second (e.g., output) terminal 508, the converter 500 includes an example current-mode boost converter 510. Figure 6 The example current-mode boost converter circuit 602 shown in FIG. 6A may implement the current-mode boost converter 510 .

[0025] To generate the off-time TOFF 512, the converter 500 includes an example timing controller 514 according to aspects of the present specification. For a given off-time TOFF_HC 518 at a fourth (e.g., input) terminal 520, a given input voltage VIN 522 at a fifth (e.g., input) terminal 524, and an output voltage VOUT 526 at a sixth (e.g., input) terminal 528, the timing controller 514 generates a constant (e.g., substantially constant, substantially constant, sufficiently constant, etc.) off-time TOFF 512 at a third (e.g., output) terminal 516.

[0026] Despite Figure 5 An example way of implementing the converter 500 is shown in FIG. Figure 5 One or more of the elements, processes and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated and / or implemented in any other manner. Figure 5 The converter 500 may include one or more elements, processes and / or devices, and / or the converter 500 may include more than one of the elements, processes and devices shown in , and / or the converter 500 may include any or all of the elements, processes and devices shown in . As used herein, the phrase "communication" (including variations thereof) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals and / or one-time events.

[0027] Figure 6 It can be used for implementation Figure 5An example converter 600 of the converter 500 of FIG. 500. To implement the current mode boost converter 510, the converter 600 includes an example current mode boost converter 602. The current mode boost converter 602 includes an example high side sensor 604 and an example low side sensor 606 to sense the inductor current flowing through an external diode (not shown) (if present). The amplifier EA 608 regulates the inductor current of the external diode (if present) to maintain the stability of the ripple of the inductor current 610 flowing through the inductor L1 614 at the seventh (e.g., input) terminal 612 of the current mode boost converter 602, and the stability of the output voltage VOUT 616 at the eighth (e.g., output) terminal 618 of the current mode boost converter 602. Typically, both the LSD transistor 620 and the HSD transistor 621 are sensed to replicate the inductor current flowing through the external diode (if present). The current mode boost converter 602 can be implemented using a current mode boost converter modified as follows, which is modified to provide its hysteresis current based off time TOFF_HC 622 to the ninth (e.g., input) terminal 624 of the timing controller 626, and receive its off time TOFF 628 from the on / off time controller 626 at the tenth (e.g., input) terminal 629 of the current mode boost converter 602. During the on time, the current 610 flowing through the inductor L1 614 will ramp up; during the off time, the inductor current 610 will ramp down. The inductor current 610 charges the output voltage VOUT 616 to maintain a stable output voltage VOUT 616 across the capacitor C1 632. In order to obtain a stable output voltage VOUT 616, a constant / stable off time is required.

[0028] To implement Figure 5 The converter 600 includes a timing controller 626. To generate a constant off-time TOFF 628 at a tenth terminal 629 for a given input voltage VIN 630 at an eleventh (e.g., input) terminal 632 and a given output voltage VOUT 616 at a twelfth (e.g., input) terminal 634, the timing controller 626 includes an example timing generator 636. The example selector 638 is an off-time selector. As shown below in conjunction with Fig. 9As discussed, the selector 638 may be implemented by the circuit 900, which selects the greater of the off-time TOFF_FIX 640 generated by the timing generator 636 and the off-time TOFF_HC 622 generated by the hysteresis current comparator 642 of the current-mode boost converter 602 as the off-time TOFF 628. The PWM controller 644 and the gate drivers 646 and 648 control the gate of the LSD driver 620 and the gate of the HSD driver 621, respectively, based on the off-time TOFF 628. For applications with an external Schottky diode, the TOFF_HC 624 generated by the current-mode boost converter circuit 602 is short, and the selector 638 selects the off-time TOFF_FIX 640 generated by the timing generator 636. Therefore, regardless of whether there is an external Schottky diode, the converter 600 operates seamlessly in peak current control with a reasonable and constant off-time. As will be described below in conjunction with Figures 7 to 9 As depicted, the selector 638 provides a gate control (GC) signal 650 to control charging in the off-time generator 636 .

[0029] although Figure 6 The implementation is shown in Figure 5 The example embodiment of the converter 500 is Figure 6 One or more of the circuits, elements, processes, and / or devices of (and / or more generally, converter 600) may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Figure 6 The converter 600 may include one or more circuits, elements, processes and / or devices as shown in FIG. 1 , and / or the converter 600 may include any or all of more than one of the elements, processes and devices shown.

[0030] Figure 7 is an example circuit 700 that can be used to implement the timing generator 636. Figure 7, the current 702 flowing through the resistor R 704 depends on the output voltage VOUT 616 at the twelfth terminal 634, and the transistor MN1 706 is controlled by the GC signal 650. When the GC signal 650 at the fourteenth (e.g., input) terminal 708 turns on the transistor MN1 706 (e.g., the GC signal 650 is a logic zero), the capacitor C 710 is charged by the voltage 712 generated by the current 712 flowing through the resistor R 704 to generate a voltage 714 across the capacitor C 710. The comparator 716 compares the voltage 714 across the capacitor C 710 with the input voltage VIN 630 at the eleventh terminal 632 to generate an off time TOFF_FIX 640 at the thirteenth (e.g., output) terminal 718. When the voltage 714 exceeds the input voltage VIN 630, the off time TOFF_FIX 640 is set high (e.g., to a logic 1). Variable current sources 720 and 722 allow the charging rate of voltage 714 across capacitor C 710 to be controlled, for example, as a design parameter. In circuit 700, TOFF_FIX = (R*C*VIN) / VOUT, and the switching frequency of timing controller 626 is substantially constant.

[0031] exist Figure 7 In the embodiment, the first terminal 632 is coupled to the input voltage VIN630 of the current mode boost converter 506; the second terminal 634 is coupled to the output voltage VOUT 616 of the current mode boost converter 506; the resistor R 704 has a third terminal 751 and a fourth terminal 752, and the third terminal 751 is coupled to the second terminal 634; the capacitor C 710 has a fifth terminal 753 and a sixth terminal 754, and the fifth terminal 753 is coupled to the second terminal 634, and the sixth terminal 754 is coupled to the ground; the seventh terminal 708 is coupled to the control signal 650; the transistor MN1 706 has an eighth terminal 755 and a ninth terminal 756, the eighth terminal 755 and the ninth terminal 756 are coupled to the fifth terminal 753 and the sixth terminal 754 respectively, and the gate 757 is coupled to the seventh terminal 708; and the comparator 716 has a tenth terminal 758, an eleventh terminal 759 and a twelfth terminal 760, the tenth terminal 758 is coupled to the fifth terminal 753, the eleventh terminal 759 is coupled to the first terminal 632, and the twelfth terminal 760 is coupled to the terminal 718.

[0032] Figure 86 is another example circuit 800 that can be used to implement the timing generator 636. Compared to the circuit 700, in the circuit 800, the current 702 flowing through the resistor R 704 is controlled by the input voltage VIN 630. Specifically, in the circuit 800, when the MOSFET MP1 transistor 802 (e.g., a P-channel MOSFET) is turned on by the input voltage VIN 630 at the eleventh terminal 632 and the GC signal 650 at the fourteenth terminal 708 closes the gate of the MN1 transistor 706 (e.g., the GC signal 650 is a logic zero), the capacitor C 710 is charged by the voltage 712 generated by the current 702 flowing through the resistor R 704 to generate a voltage 714 across the capacitor C 710. The comparator 804 compares the voltage 714 across the capacitor C 710 with the reference voltage VREF 806. When the voltage 714 exceeds the reference voltage VREF 806, TOFF_FIX 640 is set high. The final off time TOFF_FIX 640 at the fifteenth (e.g., output) terminal 808 is substantially constant at (R*C*VREF) / (VOUT-VIN). The reference voltage VREF 806 is a constant reference voltage and can be generated from the input voltage VIN 630 and / or the output voltage VOUT 616. In some examples, VREF 806 is a design parameter similar to the value of R 704 and / or C 710. The variable current sources 810, 812, 813, and 814 allow the charging rate of the voltage 714 across the capacitor C 710 to be controlled, for example, as a design parameter.

[0033] exist Figure 8In the embodiment, the first terminal 632 is coupled to the input voltage VIN630 of the current mode boost converter 506; the second terminal 634 is coupled to the output voltage VOUT 616 of the current mode boost converter 506; the resistor R 704 has a third terminal 851 and a fourth terminal 852, and the third terminal 851 is coupled to the second terminal 634; the transistor MP1 802 has a gate 853 and a fifth terminal 854 and a sixth terminal 855, the gate 853 is coupled to the first terminal 632, the fifth terminal 854 is coupled to the fourth terminal 852, and the sixth terminal 855 is coupled to the ground; the capacitor C 710 has a seventh terminal 856 and an eighth terminal 857, the seventh terminal 856 is coupled to the second terminal 634, and the eighth terminal 857 is coupled to the ground; the ninth terminal 708 is coupled to the control signal 650; the transistor MN1 706 has a tenth terminal 858 and an eleventh terminal 859, which are respectively coupled to the seventh terminal 856 and the eighth terminal 857, and the gate 860 is coupled to the ninth terminal 708; and the comparator 804 has a twelfth terminal 861, a thirteenth terminal 862 and a fourteenth terminal 863, the twelfth terminal 861 is coupled to the second terminal 634, the thirteenth terminal 862 is coupled to the reference voltage 806, and the fourteenth terminal 863 is coupled to the terminal 808.

[0034] exist Figure 7 and Figure 8 In the example of FIG. 6 , the current 610 flowing through the inductor L1 614 has a ripple IRIPPLE1002 ( Fig.10 ), IRIPPLE=(VOUT-VIN)*TOFF / L. If TOFF is set to (R*C*VREF) / (VOUT-VIN), then IRIPPLE=(R*C*VREF) / L. The ripple IRIPPLE 1002 is the peak-to-peak value of the inductor current 610. For a given input voltage VIN 630 and output voltage VOUT 616, the ripple current IRIPPLE 1002 is substantially constant. Under such conditions, the transition between the conventional hysteresis mode and the off-time control mode according to aspects of the present specification is smooth. The reference voltage VREF is the voltage 806, and L is the value of the inductor Ll 614.

[0035] although Figure 7 and Figure 8 The implementation of various aspects of this specification is shown in Figure 6 The example timing controller 626 is shown in FIG. Figure 7 and / or Figure 8One or more of the illustrated analog circuit(s), digital circuit(s), logic circuit(s), elements, processes, and / or devices may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Figure 7 and / or Figure 8 Those shown in Figure 7 The example circuit 700 and / or Figure 8 The example circuit 800 may include one or more analog circuits, one or more digital circuits, one or more logic circuits, elements, processes, and / or devices, and / or Figure 7 The example circuit 700 and / or Figure 8 The example circuit 800 may include any or all of the above-illustrated analog circuit(s), digital circuit(s), logic circuit(s), elements, processes, and devices.

[0036] Fig. 9 It can be used for implementation Figure 6 900. The circuit 900 selects the longer off time between the off time TOFF_FIX 640 generated by the off time generator 636 and the off time TOFF_HC 622 determined by the hysteresis current comparator 642. To select between the off time TOFF_FIX 640 and the off time TOFF_HC 622, the circuit 900 includes an exclusive OR (XOR) logic gate 902 that selects between the off time TOFF_FIX 640 and the off time TOFF_HC 622 based on the duration (one or more) of their respective off times. In the circuit 900, the off time TOFF_HC 622 is passed through an inverter 904 to generate a signal DFF1 906. The off time TOFF_FIX 640 is inverted by an inverter 908 and is Fig. 9 In the example of FIG. 9 , the GC signal 650 is passed through a multiplexer 910 and two additional inverters 912 and 914. By controlling the two inputs of the XOR 902 to be the same, the control signal 916 and the multiplexer 910 allow the output off time TOFF 628 to always be the off time TOFF_HC 622 or the off time TOFF_FIX 640. By inverting the inverted off time TOFF_FIX 640 using the inverter 918, a GC signal 650 is generated.

[0037] When an external Schottky diode is present, the off-time TOFF_HC 614 generated by the hysteresis current comparator 642 is short, so the output off-time TOFF 628 of the XOR 902 is the off-time TOFF_FIX 640 of the timing generator 636. Therefore, the off-time TOFF 628 is extended, thereby stabilizing the converter 500 in the presence of the external diode. When the external Schottky diode is not present, the off-time TOFF_HC 622 generated by the hysteresis current comparator 642 is long, and the selector 638 selects the off-time TOFF_HC 622. Therefore, the timing controller 626 can adapt between whether an external diode is present or not without being configured with such information.

[0038] exist Fig. 9 In the figure, the first inverter 908 has a first terminal 951 and a second terminal 952, the first terminal 951 is coupled to the third terminal 718, and the second terminal 952 is coupled to the fourth terminal 516; the second inverter 904 has a fifth terminal 953 and a sixth terminal 954, the fifth terminal 953 is coupled to the off time signal TOFF_HC 622 of the current mode boost converter 506, and the XOR logic element 902 has a seventh terminal 955, an eighth terminal 956 and a ninth terminal 957, the seventh terminal 955 is coupled to the sixth terminal 954, the eighth terminal 956 is coupled to the second terminal 952, and the ninth terminal 957 is coupled to the fourth terminal 516.

[0039] In operation, when the off time TOFF_HC 622 is low (e.g., logic zero), the selector 638, 900 and the timing generator 636, 700, 800 sets the signal DFF1 910 high (e.g., to logic 1) and sets the off time TOFF628 to low (e.g., logic zero). When the GC signal 650 is set high, the transistor MN1 704 is turned on. When the transistor MN1 706 is turned on, the capacitor C 710 is charged and the timer is started. The duration of the timer is controlled by the value of the resistor R 704 and the capacitor C 710. DFF1 910 remains high until the voltage 714 across the capacitor C 710 is higher than the input voltage VIN630 or the reference voltage VREF 806, and the off time TOFF_FIX 640 is set high. When the voltage 714 across the capacitor C710 is higher than the input voltage VIN 630 or the reference voltage VREF 806, DFF1 910 is set low. When DFF1 904 is set low, the off time TOFF 628 is set low for at least the minimum off time, and the GC signal 650 is reset, thereby turning off the transistor MN1 706. When the TOFF_HC signal 622 is set low again, the signal DFF1 904 rises. If the off time TOFF_FIX 640 is still low, the off time TOFF 628 remains low. Therefore, the longer of the off time TOFF_HC 622 and the off time TOFF_FIX 640 is selected.

[0040] Although circuit 900 may be used to implement selector 625, Fig. 9 One or more of the analog circuit(s), digital circuit(s), logic circuit(s), elements, processes, and / or devices shown in the drawings may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Furthermore, in addition to or in place of Fig. 9 , example 900 may include one or more analog circuits, one or more digital circuits, one or more logic circuits, elements, processes and / or devices, and / or example 900 may include any or all of more than one of the illustrated (one or more) analog circuits, (one or more) digital circuits, (one or more) logic circuits, elements, processes and devices.

[0041] Fig.10 1 is an example graph 1000 that depicts example waveforms for converter 600 where circuit 800 is configured with an external Schottky diode. Example graph 1000 includes input voltage VIN 630 ( Figure 6), an example waveform 1006 of the output voltage VOUT 616, and an example waveform 1004 of the inductor current 610. Fig.10 As shown in FIG. 1 , waveforms 1004, 1006, and 1008 are stable (e.g., waveforms having substantially consistent amplitude, frequency, duty cycle, average value, etc.). Example IRIPPLE 1002 is the ripple of current 610 flowing through inductor L1 614, which is the peak-to-peak value of example waveform 1004.

[0042] Fig.11 It is used for implementation Figures 5 to 9 Example flow chart 1100 of example logic, hardware logic, hardware-implemented state machine, etc., and / or any combination thereof, of all or part of an example. Figures 5 to 9 Many other methods of the examples of the present invention are described herein. For example, the order of execution of the blocks may be changed, and / or some of the blocks described may be changed, eliminated, or combined. Additionally and / or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuit systems, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) that are configured to perform corresponding operations without executing software or firmware.

[0043] In this specification, the term "and / or" (such as A, B and / or C) refers to any combination or subset of A, B, C, such as: (a) A only; (b) B only; (c) C only; (d) A and B; (e) A and C; (f) B and C; (g) A, B and C.

[0044] Fig.11 The example flowchart 1100 of begins at block 1102. A first off time is determined based on an input voltage and an output voltage (block 1102). For example, the example off time generator 636 uses, for example, the example circuit 700, the example circuit 800, etc., to determine a first off time TOFF_FIX 640 based on the output voltage VOUT 616 and the input voltage VIN 630. A high-side current (block 1104) flowing through a high-side transistor (e.g., HSD driver 621) is measured, and a low-side current (block 1106) flowing through a low-side transistor (e.g., LSD driver 620) is measured. For example, the example high-side sensor 652 measures the high-side current, and the example low-side sensor 654 measures the low-side current.

[0045] Low-side current is compared with high-side current to generate the second off-time (frame 1108). For example, hysteresis current comparator 642 compares low-side current with high-side current to generate the second off-time TOFF_HC 622. The first off-time TOFF_FIX 640 and the second off-time TOFF_HC 622 are used to generate the third off-time (frame 1110). For example, selector 638 compares the first time duration of the first off-time TOFF_FIX 640 and the second time duration of the second off-time TOFF_HC 622 to generate the third off-time TOFF 628. The third off-time TOFF 628 is used to control high-side driver 621 and low-side driver 620 (frame 1112). For example, PWM controller 644 and gate drivers 648 and 646 control low-side driver 620 and high-side driver 621 respectively based on the third off-time TOFF 628.

[0046] Fig.12 is constructed to execute Fig.11 instructions to implement Figures 5 to 9 The processor platform 1200 may be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, an iPad, etc.) TM tablet computer, etc.), personal digital assistant (PDA), Internet appliance, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headset or other wearable device, or any other type of computing device.

[0047] The processor platform 1200 of the illustrated example includes a processor 1210. The processor 1210 of the illustrated example is hardware. For example, the processor 1210 may be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor may be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements Figures 5 to 9 All or part of the timing controller, off-time generator and selector.

[0048] The processor 1210 of the illustrated example includes a local memory 1212 (e.g., a cache). The processor 1210 of the illustrated example communicates with a main memory including a volatile memory 1214 and a non-volatile memory 1216 via a bus 1218. The volatile memory 1214 may be comprised of synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), Dynamic Random Access Memory The non-volatile memory 1216 may be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 1214, 1216 is controlled by a memory controller.

[0049] The processor platform 1200 of the illustrated example also includes an interface circuit 1220. The interface circuit 1220 may be connected to the processor platform 1200 through an Ethernet interface, a universal serial bus (USB), interface, Near Field Communication (NFC) interface, and / or PCI Express interface.

[0050] In the example shown, one or more input devices 1222 are connected to the interface circuit 1220. In this example, the interface circuit 1220 enables the processor 1210 to communicate with, interface with, and / or control the current-mode boost converters 506, 602. In some examples, the current-mode boost converters 506, 602 are analog circuits implemented within the processor 1210 or external to the processor 1210.

[0051] Input device(s) 1222 allow a user to enter data and / or commands into the processor 1210. The input device(s) may be implemented, for example, by an audio sensor, microphone, camera (still or video), keyboard, buttons, mouse, touch screen, track pad, track ball, isometric point, and / or voice recognition system.

[0052] One or more output devices 1224 are also connected to the interface circuit 1220 of the illustrated example. The output device 1224 can be implemented, for example, by a display device (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-situ switching (IPS) display, a touch screen, etc.), a tactile output device, a printer, and / or a speaker. Therefore, the interface circuit 1220 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.

[0053] The interface circuitry 1220 of the illustrated example also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any kind of computing device) via network 1226. The communication may be via, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a line-of-site wireless system, a cellular telephone system, etc. In some examples of Wi-Fi systems, the interface circuitry 1220 includes a radio frequency (RF) module, antenna(s), amplifiers, filters, modulators, etc.

[0054] The processor platform 1200 of the illustrated example also includes one or more mass storage devices 1228 for storing software and / or data. Examples of such mass storage devices 1228 include floppy disk drives, hard disk drives, CD drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and DVD drives.

[0055] include Fig.11 The encoded instructions 1232 of the encoded instructions are stored in the mass storage device 1228, in the volatile memory 1214, in the non-volatile memory 1216, and / or on a removable non-transitory computer-readable storage medium (such as a CD-ROM or DVD).

[0056] According to the foregoing, example methods, devices, and circuits control the off time of a hysteretic current mode converter. According to the foregoing, the methods, devices, and circuits described herein enhance the operation of, for example, a hysteretic current mode converter in an application where a conventional converter cannot operate correctly or cannot operate satisfactorily. For example, when current sensing of a MOSFET is not available. When an external Schottky diode is used for a low-cost application, the output load is small, the output load is large (for example, when an external Schottky diode is used), etc. This example obtains the benefits of a hysteretic current mode and a constant off time mode by using a Schottky diode. The described example has improved performance compared to a conventional converter: no slope compensation, smaller die size, lower cost, smaller, smaller ripple, higher efficiency, stability when using an external Schottky diode, normal operation or light load and medium load, VIN and VOUT can be closed, when the converter operates in hysteresis mode, the inductor ripple current is set by internal parameters, and when the converter operates in constant off time mode, the inductor ripple current is determined by a constant off time generator.

[0057] Example methods, apparatus, and circuits for controlling timing of a hysteretic current mode converter are described herein. Other examples and combinations thereof include at least the following.

[0058] Example 1 is a device for controlling the timing of a current-mode boost converter, the device comprising: a device for controlling the timing of a current-mode boost converter, the device comprising:

[0059] a first input terminal receiving an input voltage of a current-mode boost converter;

[0060] a second input terminal receiving an output voltage of the current-mode boost converter;

[0061] A generator, which generates a first timing signal according to an input voltage and an output voltage;

[0062] a third input terminal receiving a second timing signal from a current mode boost converter;

[0063] a selector that selects between the first on-off time signal and the second on-off time signal based on a comparison of a first off-time duration of the first on-off time signal and a second off-time duration of the second on-off time signal to generate a third on-off time signal; and

[0064] The output terminal controls the off time of the current mode boost converter based on the third on-off time signal.

[0065] Example 2 is an example device for controlling the timing of a current-mode boost converter of Example 1, wherein the selector selects the first on-off time signal as the third on-off time signal when the first off-time duration is longer than the second off-time duration.

[0066] Example 3 is an example apparatus for controlling timing of a current mode boost converter of Example 1, wherein the generator includes:

[0067] Resistors;

[0068] a transistor coupled to the resistor, the transistor causing current to flow through the resistor when the transistor is turned on in response to the input voltage;

[0069] a capacitor that is charged by the current to generate a voltage across the capacitor; and

[0070] A comparator compares the voltage with a reference voltage to generate a first on-off time signal.

[0071] Example 4 is an example apparatus for controlling timing of a current mode boost converter of Example 1, wherein the generator includes:

[0072] a resistor that causes a current to flow through the resistor in response to a gate control signal generated by the selector, the amount of the current being based on the output voltage;

[0073] transistor;

[0074] a capacitor that is charged by current when the gate of the transistor is closed to generate a voltage across the capacitor; and

[0075] A comparator compares the voltage with an input voltage to generate a first on-off time signal.

[0076] Example 5 is an example device for controlling timing of a current mode boost converter of Example 1, wherein the selector comprises:

[0077] an inverter that inverts the second on-off time signal to generate a first control signal; and

[0078] The gate of the transistor sets the second control signal high to start charging of the capacitor of the generator when the first control signal is high.

[0079] Example 6 is a current mode boost converter apparatus comprising:

[0080] Current-mode boost converter;

[0081] a generator that generates a first off-time signal according to an input voltage of the current-mode boost converter and an output voltage of the current-mode boost converter; and

[0082] A selector selects between the first off-time signal and the second off-time signal of the current-mode boost converter to generate a third off-time signal, a driver of the current-mode boost converter operating in response to the third off-time signal.

[0083] Example 7 is the current mode boost converter apparatus of Example 6, wherein the selector is to select the first off-time signal when a first off-time duration of the first off-time signal is longer than a second off-time duration of the second off-time signal.

[0084] Example 8 is the current mode boost converter apparatus of Example 6, wherein the generator generates a voltage across the capacitor when the input voltage turns on the transistor, and the generator compares the voltage with a reference voltage to generate the first off-time signal.

[0085] Example 9 is the current mode boost converter apparatus of Example 6, wherein the generator generates a voltage across the capacitor in response to the control signal of the selector, and the generator compares the voltage with the input voltage to generate the first off-time signal.

[0086] Example 10 is a current-mode boost converter device of Example 6, wherein when the third off-time signal is low, the current-mode boost converter turns on the low-side drive FET and turns off the high-side drive FET; and when the first off-time signal is high, the current-mode boost converter turns off the low-side drive FET and turns on the high-side drive FET.

[0087] Example 11 is a method comprising:

[0088] determining a first off-time signal based on an input voltage of the current-mode boost converter and an output voltage of the current-mode boost converter;

[0089] selecting between the first off-time signal and a second off-time signal of the current-mode boost converter to generate a third off-time signal; and

[0090] Operation of the current mode boost converter is controlled based on the third off-time signal.

[0091] Example 12 is the method of Example 11, further comprising:

[0092] Measure the high-side current flowing through the high-side driver of a current-mode boost converter;

[0093] Measuring the low-side current flowing through the low-side driver of a current-mode boost converter; and

[0094] The low-side current and the high-side current are compared to generate a second off-time signal.

[0095] Example 13 is the method of Example 11, further comprising:

[0096] When the third off-time signal is low, turning on the low-side drive FET and turning off the high-side drive FET; and

[0097] When the first off-time signal is high, the low-side drive FET is turned off and the high-side drive FET is turned on.

[0098] Example 14 is the method of Example 11, further comprising:

[0099] determining a first off-time duration of a first off-time signal;

[0100] determining a second off-time duration of a second off-time signal; and

[0101] When the first off-time duration is longer than the second off-time duration, the first off-time signal is selected as the third off-time signal.

[0102] Example 15 is the method of Example 11, further comprising:

[0103] When the input voltage turns on the transistor, a voltage is generated across the capacitor; and

[0104] The voltage is compared with a reference voltage to generate a first off-time signal.

[0105] Example 16 is a device comprising:

[0106] a first terminal coupled to an input voltage of a current-mode boost converter;

[0107] a second terminal coupled to an output voltage of the current mode boost converter;

[0108] a resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal;

[0109] a transistor having a gate and a fifth terminal and a sixth terminal, the gate being coupled to the first terminal, the fifth terminal being coupled to the fourth terminal, and the sixth terminal being coupled to ground;

[0110] a capacitor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the second terminal and the eighth terminal coupled to ground;

[0111] a ninth terminal coupled to a control signal;

[0112] a transistor having tenth and eleventh terminals and a gate terminal, the tenth and eleventh terminals being coupled to the seventh and eighth terminals, respectively, and the gate being coupled to the ninth terminal; and

[0113] A comparator has a twelfth terminal, a thirteenth terminal and a fourteenth terminal, the twelfth terminal is coupled to the second terminal, and the thirteenth terminal is coupled to a reference voltage.

[0114] Example 17 is the apparatus of Example 16, further comprising:

[0115] a first inverter having a fifteenth terminal and a sixteenth terminal, the fifteenth terminal being coupled to the fourteenth terminal;

[0116] a second inverter having a seventeenth terminal and an eighteenth terminal, the seventeenth terminal coupled to an off-time signal of the current-mode boost converter; and

[0117] An exclusive-OR logic element has a nineteenth terminal, a twentieth terminal, and a twenty-first terminal, the nineteenth terminal coupled to the sixteenth terminal, the twentieth terminal coupled to the eighteenth terminal, and the twenty-first terminal coupled to an off-time input of the current-mode boost converter.

[0118] Example 18 is the device of Example 17, wherein the sixteenth terminal is coupled to the nineteenth terminal via one or more logic devices.

[0119] Example 19 is the apparatus of Example 17, further comprising a fourth inverter having a twenty-second terminal and a twenty-third terminal, the twenty-second terminal coupled to the sixteenth terminal, and the twenty-third terminal coupled to the ninth terminal.

[0120] Example 20 is the apparatus of Example 17, further comprising:

[0121] a PWM controller for a current mode boost converter having a twenty-second terminal and a twenty-third terminal, the twenty-second terminal coupled to the twenty-first terminal, the twenty-third terminal coupled to the gate driver; and

[0122] A hysteresis current comparator has a twenty-fourth terminal coupled to the seventeenth terminal.

[0123] Provisional patent application US62 / 621,148, filed on January 24, 2018, is incorporated herein by reference in its entirety.

[0124] Modifications in the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

Claims

1. A device for controlling the timing of a current mode boost converter, the device comprising: a first input terminal receiving an input voltage of the current-mode boost converter; a second input terminal receiving an output voltage of the current-mode boost converter; a generator that generates a first timing signal according to the input voltage and the output voltage, wherein the generator includes a transistor having a control terminal and a first current terminal and a second current terminal, and a capacitor connected between the first current terminal and the second current terminal; a third input terminal receiving a second timing signal from the current mode boost converter; a selector that selects between the first timing signal and the second timing signal based on a comparison of a first off-time duration of the first timing signal and a second off-time duration of the second timing signal to generate a third timing signal; an output terminal for controlling an off time of the current mode boost converter based on the third timing signal; and wherein the control terminal receives a first control signal, and the transistor is operable to charge the capacitor in response to the first control signal. 2 . The apparatus of claim 1 , wherein when the first off-time duration is longer than the second off-time duration, the selector selects the first timing signal as the third timing signal.

3. The apparatus of claim 1, wherein the generator comprises: a resistor coupled to the transistor; as well as A comparator compares the voltage across the resistor with a reference voltage to generate the first timing signal.

4. The apparatus of claim 1, wherein the selector comprises: an inverter that inverts the second timing signal to generate the first control signal; as well as The gate of the transistor sets the second control signal high to start charging of the capacitor of the generator when the first control signal is high.

5. A current mode boost converter device comprising: Current-mode boost converter; a generator that generates a first off-time signal based on an input voltage of the current-mode boost converter and an output voltage of the current-mode boost converter, wherein the generator includes a transistor having a control terminal and first and second current terminals, and a capacitor connected between the first and second current terminals; a selector that selects between the first off-time signal and a second off-time signal of the current-mode boost converter to generate a third off-time signal, a driver of the current-mode boost converter operating in response to the third off-time signal; and wherein the control terminal receives a first control signal, and the transistor is operable to charge the capacitor in response to the first control signal. 6 . The apparatus of claim 5 , wherein the selector selects the first off-time signal when a first off-time duration of the first off-time signal is longer than a second off-time duration of the second off-time signal. 7 . The apparatus of claim 5 , wherein the generator generates a voltage across the capacitor when the input voltage turns on the transistor, and the generator compares the voltage with a reference voltage to generate the first off-time signal.

8. The apparatus of claim 5 , wherein when the third off-time signal is low, the current-mode boost converter will turn on a low-side drive FET and turn off a high-side drive FET, and when the first off-time signal is high, the current-mode boost converter will turn off the low-side drive FET and turn on the high-side drive FET.

9. A device comprising: a first terminal coupled to an input voltage terminal of a current-mode boost converter; a second terminal coupled to an output voltage terminal of the current-mode boost converter; a resistor having a third terminal and a fourth terminal, the third terminal coupled to the second terminal; a transistor having a gate and a fifth terminal and a sixth terminal, the gate being coupled to the first terminal, the fifth terminal being coupled to the fourth terminal, and the sixth terminal being coupled to ground; a capacitor having a seventh terminal and an eighth terminal, the seventh terminal coupled to the second terminal and the eighth terminal coupled to the ground; a ninth terminal coupled to a control signal; a transistor having tenth and eleventh terminals and a gate, the tenth and eleventh terminals being coupled to the seventh and eighth terminals, respectively, and the gate being coupled to the ninth terminal; a comparator having a twelfth terminal, a thirteenth terminal and a fourteenth terminal, the twelfth terminal being coupled to the second terminal and the thirteenth terminal being coupled to a reference voltage terminal; a first inverter having a fifteenth terminal and a sixteenth terminal, the fifteenth terminal being coupled to the fourteenth terminal; a second inverter having a seventeenth terminal and an eighteenth terminal, wherein the seventeenth terminal is configured to receive an off-time signal from the current-mode boost converter; as well as An XOR logic element having a nineteenth terminal, a twentieth terminal and a twenty-first terminal, the nineteenth terminal being coupled to the sixteenth terminal, the twenty-th terminal being coupled to the eighteenth terminal, and the current-mode boost converter being configured to provide an off-time signal at the twenty-first terminal. 10 . The device of claim 9 , the sixteenth terminal being coupled to the nineteenth terminal via one or more logic devices.

11. The apparatus of claim 9, further comprising a fourth inverter having a twenty-second terminal and a twenty-third terminal, the twenty-second terminal coupled to the sixteenth terminal, and the twenty-third terminal coupled to the ninth terminal.

12. The apparatus according to claim 9, further comprising: a PWM controller of the current mode boost converter having a twenty-second terminal and a twenty-third terminal, the twenty-second terminal being coupled to the twenty-first terminal, the twenty-third terminal being coupled to the gate driver; as well as A hysteresis current comparator has a twenty-fourth terminal coupled to the seventeenth terminal.

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