Storage device and computing device including the storage device

Abstract

A storage device and a computing device including the storage device are disclosed. The storage device includes: a nonvolatile memory device including a plurality of memory blocks; and a controller using some of the plurality of memory blocks as a buffer area. Memory blocks storing invalid data among the some memory blocks are invalid memory blocks, and the controller identifies memory blocks among the invalid memory blocks whose elapsed time after erasure is greater than the reuse time as available buffer sizes, and provides the available buffer sizes to an external host device.

Description

Technical Field

[0001] Embodiments of the concepts described herein relate to a semiconductor device, and more particularly, to a memory device that provides improved reliability by identifying an available buffer size based on a reuse time and a computing device including the memory device. Background Art

[0002] The storage device refers to a device that stores data under the control of a host device such as a computer, a smart phone, a smart tablet, etc. The storage device includes a device that stores data on a magnetic disk such as a hard disk drive (HDD) or a device that stores data in a semiconductor memory (particularly, a nonvolatile memory) such as a solid state drive (SSD) or a memory card.

[0003] Non-volatile memory includes read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0004] With the advancement of semiconductor manufacturing technology, the integration and capacity of storage devices continue to increase. The high integration of storage devices can reduce the cost required to manufacture storage devices. However, the high integration of storage devices also leads to the reduction and structural change of storage devices. For example, damage to the data stored in the storage device may occur, thereby reducing the reliability of the storage device. Therefore, there is a continuous need to improve the reliability of storage devices. Summary of the invention

[0005] Embodiments of the present invention provide a storage device and a computing device capable of preventing errors from occurring in memory blocks of a buffer area due to frequent erase operations when some memory blocks are used as a buffer area.

[0006] According to an exemplary embodiment, a storage device includes: a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks, the plurality of memory blocks including a first memory block configured to store data received from a host device and a second memory block configured to write the data received from the host device into a buffer area of ​​the first memory block; and a controller that determines whether a time period between a time when data stored in the second memory block is erased from the second memory block in the buffer area and a current time exceeds a predetermined time, and based on determining that the time period exceeds the predetermined time, writes the data received from the host device into the second memory block in the buffer area.

[0007] According to an exemplary embodiment, a storage device includes: a nonvolatile memory device, the nonvolatile memory device including a plurality of memory blocks, the plurality of memory blocks being configured to include a user area of ​​a first memory block among the plurality of memory blocks and a buffer area including a second memory block among the plurality of memory blocks; and a controller, receiving a write command for writing data to the nonvolatile memory device, the write command including a turbo write command for a turbo write operation for writing data to the user area through the buffer area, based on identifying that a size of the data does not exceed an available buffer size of the buffer area, writing the data to the nonvolatile memory device through the buffer area according to the turbo write operation of the turbo write command, the available buffer size of the buffer area including a size of an available memory block among the second memory blocks, wherein a time period between a time when stored data stored in the available memory blocks is erased from the available memory blocks of the buffer area and a current time exceeds a predetermined time, and based on identifying that the size of the data exceeds the available size of the buffer area, writing the data to the nonvolatile memory device according to an ordinary write operation of an ordinary write command for directly writing the data to the user area.

[0008] According to an exemplary embodiment, a computing device includes: a storage device, the storage device including a user area including a first memory block among the memory blocks of the storage device and a buffer area including a second memory block among the memory blocks of the storage device, the storage device being configured to output an available size of the buffer area, the available buffer size of the buffer area including the size of the available memory block among the second memory block, wherein a time period between a time when storage data stored in the available memory block is erased from the available memory block of the buffer area and a current time exceeds a predetermined time; and a processor, sending a turbo write request for performing a turbo write operation to the storage device to store data with a size less than or equal to the available buffer size in the user area via the buffer area, and sending a normal write request for performing a normal write operation to the storage device to directly store data with a size greater than the available buffer size in the user area. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the concept will become apparent by describing in detail exemplary embodiments of the concept with reference to the attached drawings.

[0010] Figure 1 A storage device according to an embodiment is shown.

[0011] Figure 2 A method of operating a memory device according to an embodiment is illustrated.

[0012] Figure 3 A method of identifying available buffer size according to an embodiment is shown.

[0013] Figure 4 A state of a storage device before storing data in a buffer area according to an embodiment is shown.

[0014] Figure 5 A state of a storage device in which data is written to a portion of a buffer area according to an embodiment is shown.

[0015] Figure 6 A state of a storage device in which data is written to the remaining portion of the buffer area according to an embodiment is shown.

[0016] Figure 7 FIG. 1 shows a state of a storage device in which data in a write buffer area is migrated to a user area according to an embodiment.

[0017] Figure 8 Shown is the state of a storage device determining available buffer size according to an embodiment.

[0018] Fig. 9 A method in which a storage device according to an embodiment performs a write operation on a buffer area and a user area is illustrated.

[0019] Fig.10 A storage device according to an embodiment is shown.

[0020] Fig.11 A computing device according to an embodiment is shown.

[0021] Fig.12 A method of storing data performed between a processor and a storage device according to an embodiment is shown.

[0022] Fig.13 A diagram illustrating allocating a buffer area in a reduction mode when a storage device does not have an overprovision area according to an embodiment.

[0023] Fig.14 A diagram illustrating allocating a buffer area in a non-shrink mode when a storage device does not have an over-provisioning area according to an embodiment.

[0024] Fig.15 A diagram illustrating allocating a buffer area in a reduction mode when a storage device has an over-provisioned area according to an embodiment.

[0025] Fig.16 A diagram illustrating allocating a buffer area in a non-shrink mode when a storage device has an over-provisioned area according to an embodiment.

[0026] Fig.17 A method in which a processor writes data to a storage device according to an embodiment is shown.

[0027] Fig.18 A method for a computing device to change the size of a buffer area according to an embodiment is shown. DETAILED DESCRIPTION

[0028] Below, the embodiments may be described in detail and clearly to the extent that a person having ordinary skill in the art can easily implement the concept described herein.

[0029] Figure 1 1 shows a storage device 100 according to an embodiment. Figure 1 , the storage device 100 may include a nonvolatile memory device 110 and a controller 120 .

[0030] The nonvolatile memory device 110 is configured to perform a write operation, a read operation, and an erase operation under the control of the controller 120. The nonvolatile memory device 110 may include a plurality of memory blocks configured to store data. For example, the nonvolatile memory device 110 may include a first memory block BLK1 to a twentieth memory block BLK20. However, the number of memory blocks included in the nonvolatile memory device 110 is merely exemplary, and the nonvolatile memory device 110 may include any number of memory blocks.

[0031] The nonvolatile memory device 110 may perform an erase operation in units of memory blocks. For example, the nonvolatile memory device 110 may independently erase the first to twentieth memory blocks BLK1 to BLK20 under the control of the controller 120.

[0032] Each of the first to twentieth memory blocks BLK1 to BLK20 may include a plurality of memory cells. The nonvolatile memory device 110 may perform a write operation and a read operation in units smaller than a memory block. For example, under the control of the controller 120, the nonvolatile memory device 110 may select some of the memory cells of a specific memory block, and may perform a write operation or a read operation on the selected memory cells.

[0033] The controller 120 may control the nonvolatile memory device 110 under the control of an external host device. For example, the controller 120 may instruct the nonvolatile memory device 110 to perform a read operation, a write operation, or an erase operation. The controller 120 may set, divide, or otherwise configure a portion of the first to twentieth memory blocks BLK1 to BLK20 of the nonvolatile memory device 110 as a user area 111, and may use the remaining portion of the first to twentieth memory blocks BLK1 to BLK20 as a buffer area 112.

[0034] For example, the controller 120 may select the first to sixteenth memory blocks BLK1 to BLK16 as the user area 111, and may select the seventeenth to twentieth memory blocks BLK17 to BLK20 as the buffer area 112. The controller 120 may provide storage spaces of the first to sixteenth memory blocks BLK16 of the user area 111 to an external host device.

[0035] The controller 120 may provide the storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 as a buffer area of ​​the user area 111. For example, the controller 120 may not provide the storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 accessible for storage to an external host device.

[0036] The controller 120 may include a buffer size block 121, a migration block 122, a memory interface block 123, and a host interface block 124. The buffer size block 121, the migration block 122, the memory interface block 123, and the host interface block 124 may be modules of the controller 120 configured to perform operations of the controller 120.

[0037] The buffer size block 121 may identify the current available capacity of the storage space of the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112. For example, the controller 120 may identify the available storage space of unwritten data in the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 as the available buffer size in response to a request of an external host device or periodically.

[0038] The migration block 122 may migrate valid data of the seventeenth to twentieth memory blocks BLK17 to BLK20 written in the buffer area 112 to the user area 111 in response to a request of an external host device or at an idle time. The data migrated from the buffer area 112 to the user area 111 may be invalid in the buffer area 112 and may be identified as invalid data or dirty data.

[0039] In response to a request from an external host device or according to an internal schedule, the memory interface block 123 may provide a command, an address, or data to the nonvolatile memory device 110 so that the nonvolatile memory device 110 performs a write operation, a read operation, or an erase operation.

[0040] The host interface block 124 may receive various requests from an external host device. The host interface block 124 may parse the request received from the external host device. Based on the result of the parsing, the host interface block 124 may control the nonvolatile memory device 110 or may provide information to the external host device. For example, the host interface block 124 may provide the available buffer size identified by the buffer size block 121 to the external host device.

[0041] Figure 2 A method of operating the storage device 100 according to an embodiment is shown. Figure 1 and Figure 2 In operation S110, the host interface block 124 of the controller 120 may receive a command CMD, an address ADDR, and data DATA from an external host device. For example, the command CMD may be a write command, a read command, or an erase command.

[0042] The address ADDR may indicate a location where the data DATA is to be stored. For example, the location where the data DATA is to be stored may be a location on the user area 111 of the nonvolatile memory device 110. The data DATA may be write data that an external host device intends to write to the nonvolatile memory device 110.

[0043] In operation S120, the memory interface block 123 of the controller 120 may write the data DATA to the buffer area 112. For example, the location on the buffer area 112 where the data DATA is to be written may be independent of the address ADDR where the data DATA is to be ultimately written in the user area 111. The nonvolatile memory device 110 may increase the speed at which data is written to the nonvolatile memory device 110 by writing the data DATA using the memory cells of the buffer area 112 as single-layer cells SLC.

[0044] In operation S130, when a migration request is received from an external host device or in an idle time when there is no request from the external host device, the migration block 122 of the controller 120 may start data migration. Under the control of the migration block 122, the controller 120 may migrate (or move) the data written in the buffer area 112 to a location indicated by an address ADDR on the user area 111.

[0045] For example, the memory interface block 123 of the controller 120 may send a read command and an address of the buffer area 112 to the nonvolatile memory device 110, and may read the data DATA written to the buffer area 112. Thereafter, the memory interface block 123 of the controller 120 may send a write command and an address ADDR to the nonvolatile memory device 110, and may write the data DATA to the user area 111.

[0046] In operation S140 , the buffer size block 121 of the controller 120 may detect (or identify) an available buffer size of the buffer area 112 upon receiving a request from the external host device or periodically (or at a certain period) based on a reuse time.

[0047] For example, in operation S130, data DATA of the buffer area 112 may be invalidated by moving the data DATA from the buffer area 112 to the user area 111. A memory block of the buffer area 112 storing the data DATA may be an invalid memory block.

[0048] The buffer size block 121 may identify the capacity of the memory blocks to which the erase operation can currently be performed and data can be written among the invalid memory blocks of the buffer area 112 as the available buffer size. The available buffer size may not be consistent with the total capacity of the invalid memory blocks of the buffer area 112. The buffer size block 121 may determine which of the invalid memory blocks are included in the available buffer size and which of the invalid memory blocks are not included in the available buffer size by using the reuse time.

[0049] In operation S150, the host interface block 124 of the controller 120 may report the available buffer size to the external host device. Operations S140 and S150 may be sequentially performed in response to a request of the host device requesting the available buffer size.

[0050] Figure 3 A method for identifying available buffer size according to an embodiment is shown. Figures 1 to 3 In operation S141, the buffer size block 121 may determine whether a time (eg, an elapsed time) after a specific invalid memory block of the seventeenth to twentieth memory blocks BLK17 to BLK20 in the buffer area 112 is erased is greater than a reuse time.

[0051] When the elapsed time is greater than the reuse time, in operation S142, the specific invalid memory block may be identified as an available memory block in the buffer area 112 that can be used to store data. The capacity of the invalid memory block marked as available may be included in the calculation of the available buffer size. When the elapsed time is not greater than the reuse time, in operation S143, the specific invalid memory block may be identified as an unavailable memory block in the buffer area 112 that cannot be used to store data. The capacity of the invalid memory block marked as unavailable may not be included in the calculation of the available buffer size.

[0052] Typically, a memory cell (e.g., a flash memory cell) has a structure in which a main body, a tunnel insulating layer, an information storage layer, a blocking insulating layer, and a control gate are stacked. In a write operation, a high voltage is applied to the control gate, and a low voltage is applied to the main body. According to this write bias condition, the charge of the main body is injected into the information storage layer through the tunnel insulating layer. This injection of charge can make the threshold voltage of the memory cell high.

[0053] In the erase operation, a low voltage is applied to the control gate and a high voltage is applied to the main body. According to this erase bias condition, the charge of the information storage layer is pulled out through the tunnel insulating layer and transferred to the main body. This transfer of charge can reduce the threshold voltage of the memory cell.

[0054] When a write operation or an erase operation is performed, some charges may be trapped in the tunnel insulating layer or the blocking insulating layer. The charges trapped in the tunnel insulating layer or the blocking insulating layer are discharged over time. That is, immediately after the write operation or the erase operation is performed, the charges trapped in the tunnel insulating layer or the blocking insulating layer may have an effect on the threshold voltage of the memory cell.

[0055] When the charges trapped in the tunnel insulating layer or the blocking insulating layer are discharged over time, the threshold voltage of the memory cell may change due to the presence of the trapped charges. The process of discharging the charges trapped in the tunnel insulating layer or the blocking insulating layer may be considered as the memory cell being cured or stabilized.

[0056] When a write operation and an erase operation are performed on a specific memory block, curing or stabilization may cause a first change in the threshold voltage of memory cells in the specific memory block as much as the first level. In the case where an erase operation or a write operation is performed again before curing or stabilization of the specific memory block is completed, in addition to the first change in the threshold voltage caused in the previous erase operation and write operation, the current write operation and erase operation accompanying the curing or stabilization may cause a second change in the threshold voltage.

[0057] In this way, the first change and the second change are accumulated, thereby causing a larger change in the threshold voltage of the memory cell. As the change in the threshold voltage of the memory cell increases (or as the offset of the threshold voltage of the memory cell becomes larger), the probability of uncorrectable errors occurring in the data written to a particular memory block also increases.

[0058] Specifically, as an example considering the seventeenth memory block BLK17 to the twentieth memory block BLK20 of the buffer area 112, in the case where a limited number of memory blocks are used to store a single bit per memory cell, the probability of erase operations and write operations being triggered before curing or stabilization is completed may be related to the memory blocks BLK17 to BLK20 of the buffer area 112.

[0059] For example, before the solidification or stabilization of the buffer area 112 is completed, the external host device may intend to write data to the buffer area 112 , migrate the written data to the user area 111 , and further write any other data to the buffer area 112 .

[0060] The memory device 100 according to the embodiment may include memory blocks whose elapsed time after erasure is greater than the reuse time among the seventeenth memory blocks BLK17 to the twentieth memory blocks BLK20 of the buffer area 112 in the available buffer size. For example, the reuse time may be a time during which the charge captured in the tunnel insulating layer or the blocking insulating layer may be discharged over time. The reuse time may be a predetermined time for judging the availability or unavailability of the memory block. The memory device 100 may exclude memory blocks whose elapsed time after erasure is not greater than the reuse time from the available buffer size. Therefore, memory blocks whose charge captured in the tunnel insulating layer or the blocking insulating layer will not be discharged over time will not be included in the calculation of the available buffer size.

[0061] The reuse time can be determined based on the time when the seventeenth memory block BLK17 to the twentieth memory block BLK20 are solidified or stabilized. Such memory blocks can be indicated as available memory blocks. That is, the storage device 100 can support fast write operations by using the buffer area 112 for those memory blocks indicated as available, and can ensure the solidification or stabilization of the buffer area 112 for those memory blocks indicated as unavailable, so the reliability of the storage device 100 is improved.

[0062] Figures 4 to 8 It shows how the storage device 100 manages the buffer area 112 based on the reuse time. Figure 4 1 shows the state of the storage device before storing data in the buffer area 112. Figure 4 , the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 may be invalid memory blocks storing invalid data INV.

[0063] The buffer size block 121 may manage the timestamp TS of each of the seventeenth to twentieth memory blocks BLK17 to BLK20. The timestamp TS may indicate the time when each of the seventeenth to twentieth memory blocks BLK17 to BLK20 was previously erased. It is assumed that the curing or stabilization of the seventeenth to twentieth memory blocks BLK17 to BLK20 is completed. That is, the timestamp TS of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 and the elapsed time calculated from the current time may be greater than the reuse time. Therefore, the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 may be indicated as available memory blocks.

[0064] The buffer size block 121 can further manage the available buffer size. Because the solidification or stabilization of the seventeenth memory block BLK17 to the twentieth memory block BLK20 is completed, the available buffer size can be "4" (indicating the size of four memory blocks). However, the available buffer size is not limited to the number of memory blocks. The available buffer size can be represented by the capacity of the data to be actually written (such as B, KB, MB, GB or TB).

[0065] Figure 5 1 shows a state of a storage device in which data is written to a portion of the buffer area 112. The host interface block 124 of the controller 120 may receive a first command CMD1, a first address ADDR1, and first data DATA1 from an external host device. The first command CMD1 may be a write command. The first address ADDR1 may correspond to, for example, a thirteenth memory block BLK13 of the user area 111.

[0066] In operation S211, the memory interface block 123 of the controller 120 may transmit an erase command and addresses indicating seventeenth and eighteenth memory blocks BLK17 and BLK18 of the buffer area 112 to the nonvolatile memory device 110. The nonvolatile memory device 110 may erase the seventeenth and eighteenth memory blocks BLK17 and BLK18.

[0067] In operation S212, when the seventeenth memory block BLK17 and the eighteenth memory block BLK18 are erased, the buffer size block 121 may generate a first timestamp TS1 of the time when the seventeenth memory block BLK17 and the eighteenth memory block BLK18 are erased, and may record the first timestamp TS1 associated with the seventeenth memory block BLK17 and the eighteenth memory block BLK18. For example, the buffer size block 121 may store the timestamp TS associated with the corresponding memory block in a lookup table, a register, or any other storage mechanism.

[0068] In operation S213, the memory interface block 123 of the controller 120 may transmit a write command, addresses indicating the seventeenth and eighteenth memory blocks BLK17 and BLK18 of the buffer area 112, and the first data DATA1 to the nonvolatile memory device 110. The nonvolatile memory device 110 may write the first data DATA1 to the seventeenth and eighteenth memory blocks BLK17 and BLK18. The seventeenth and eighteenth memory blocks BLK17 and BLK18 may be indicated as valid memory blocks storing valid data VAL.

[0069] In operation S214, since the seventeenth memory block BLK17 and the eighteenth memory block BLK18 become valid memory blocks, the buffer size block 121 can reduce the available buffer size. For example, the available buffer size can be reduced to "2", "2" corresponds to that only the nineteenth memory block BLK19 and the twentieth memory block BLK20 are available invalid memory blocks.

[0070] Figure 6 The state of the storage device in which data is written to the remaining portion of the buffer area 112 is shown. The host interface block 124 of the controller 120 may receive a second command CMD2, a second address ADDR2, and second data DATA2 from an external host device. The second command CMD2 may be a write command. The second address ADDR2 may correspond to, for example, the fourteenth memory block BLK14 of the user area 111.

[0071] In operation S221, the memory interface block 123 of the controller 120 may transmit an erase command and addresses indicating the nineteenth and twentieth memory blocks BLK19 and BLK20 of the buffer area 112 to the nonvolatile memory device 110. The nonvolatile memory device 110 may erase the nineteenth and twentieth memory blocks BLK19 and BLK20.

[0072] In operation S222, when the nineteenth memory block BLK19 and the twentieth memory block BLK20 are erased, the buffer size block 121 may generate a second timestamp TS2 of the time when the nineteenth memory block BLK19 and the twentieth memory block BLK20 are erased, and may record the second timestamp TS2 associated with the nineteenth memory block BLK19 and the twentieth memory block BLK20.

[0073] In operation S223, the memory interface block 123 of the controller 120 may send a write command, addresses indicating the nineteenth memory block BLK19 and the twentieth memory block BLK20 of the buffer area 112, and the second data DATA2 to the nonvolatile memory device 110. The nonvolatile memory device 110 may write the second data DATA2 to the nineteenth memory block BLK19 and the twentieth memory block BLK20. The nineteenth memory block BLK19 and the twentieth memory block BLK20 may be valid memory blocks storing valid data VAL.

[0074] In operation S224, since the nineteenth and twentieth memory blocks BLK19 and BLK20 become valid memory blocks, the buffer size block 121 may reduce the available buffer size. For example, since all memory blocks of the buffer area 112 are valid memory blocks, the available buffer size may be reduced to "0".

[0075] Figure 7 The state of the storage device in which the data written in the buffer area 112 is migrated to the user area 111 is shown. Figure 7 , the migration block 122 of the controller 120 may start the migration operation in response to a request of the external host device or at an idle time when there is no command from the external host device.

[0076] In operation S231, the memory interface block 123 may transmit a read command and addresses indicating the seventeenth to twentieth memory blocks BLK17 to BLK20 of the buffer area 112 to the nonvolatile memory device 110. The nonvolatile memory device 110 may read the first data DATA1 from the seventeenth and eighteenth memory blocks BLK17 and BLK18, and may read the second data DATA2 from the nineteenth and twentieth memory blocks BLK19 and BLK20. The nonvolatile memory device 110 may transmit the first and second data DATA1 to the controller 120.

[0077] In operation S232, the memory interface block 123 may transmit a write command, a first address ADDR1 indicating a thirteenth memory block BLK13, and first data DATA1 to the nonvolatile memory device 110. In addition, the memory interface block 123 may transmit a write command, a second address ADDR2 indicating a fourteenth memory block BLK14, and second data DATA2 to the nonvolatile memory device 110.

[0078] The nonvolatile memory device 110 may write first data DATA1 into the thirteenth memory block BLK13 and second data DATA2 into the fourteenth memory block BLK14. For example, the memory interface block 123 may use memory cells of the thirteenth and fourteenth memory blocks BLK13 and BLK14 of the user area 111 as multi-level cells MLC.

[0079] However, the memory cells of the user area 111 are not limited to the multi-level cell MLC. The memory cells of the user area 111 may be used as triple-level cell TLC or quad-level cell QLC.

[0080] When the first data DATA1 and the second data DATA2 are migrated, the first data DATA1 and the second data DATA2 written in the buffer area 112 are invalidated. The seventeenth memory block BLK17 to the twentieth memory block BLK20 of the buffer area 112 may be invalid memory blocks storing invalid data INV. The thirteenth memory block BLK13 and the fourteenth memory block BLK14 of the user area 111 may be valid memory blocks storing valid data VAL.

[0081] In operation S233 and operation S234, in response to a request from an external host device or according to an internal schedule (for example, periodically or when a specific condition is met), the buffer size block 121 may compare the timestamp of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 with the current time, and may determine the available buffer size based on the result of the comparison.

[0082] For example, in operation S233, the seventeenth memory block BLK17 and the eighteenth memory block BLK18 have the first time stamp TS1. The difference between the first time stamp TS1 and the current time (i.e., the elapsed time ET1 of the seventeenth memory block BLK17 and the eighteenth memory block BLK18) may be greater than the reuse time. Therefore, the memory blocks BLK17 and BLK18 may be indicated as available.

[0083] In contrast, in operation S234, the nineteenth memory block BLK19 and the twentieth memory block BLK20 have the second time stamp TS2. The difference between the second time stamp TS2 and the current time (i.e., the elapsed time ET2 of the nineteenth memory block BLK19 and the twentieth memory block BLK20) may not be greater than the reuse time. Therefore, the memory blocks BLK19 and BLK20 may be indicated as unavailable.

[0084] The buffer size block 121 may identify the seventeenth memory block BLK17 and the eighteenth memory block BLK18 as available memory blocks of the buffer area 112, and may identify the nineteenth memory block BLK19 and the twentieth memory block BLK20 as unavailable memory blocks of the buffer area 112. Therefore, the number of invalid memory blocks of the buffer area 112 may be "4", however, in operation S235, the available buffer size identified by the buffer size block 121 may be "2".

[0085] In operation S236, the host interface block 124 may report the available buffer size to the external host device. For example, the identification and reporting of the available buffer size may be performed in response to one same command or different separate commands provided from the external host device.

[0086] Figure 8 Shows the status of the storage device that determines the available buffer size. Figure 8 In response to a request from an external host device or according to an internal schedule (e.g., periodically or when a specific condition is met), the buffer size block 121 may compare the timestamp of each of the seventeenth to twentieth memory blocks BLK17 to BLK20 with the current time, and may determine the available buffer size based on the result of the comparison.

[0087] For example, in operation S241, the nineteenth memory block BLK19 and the twentieth memory block BLK20 have the second time stamp TS2. The difference between the second time stamp TS2 and the current time (ie, the elapsed time ET2 of the nineteenth memory block BLK19 and the twentieth memory block BLK20) may be greater than the reuse time.

[0088] The nineteenth memory block BLK19 and the twentieth memory block BLK20 may be identified as available memory blocks of the buffer area 112. Therefore, in operation S242, the available buffer size identified by the buffer size block 121 may be "4".

[0089] In operation S243, the host interface block 124 may report the available buffer size to the external host device. For example, the identification and reporting of the available buffer size may be performed in response to one same command or different separate commands provided from the external host device.

[0090] Fig. 9 FIG. 1 shows a method in which the storage device 100 performs a write operation on the user area 111 and the buffer area 112. Figure 1 and Fig. 9 In operation S310 , the host interface block 124 of the controller 120 may receive a command CMD, an address ADDR, and data DATA from an external host device. The command CMD may be a write command. The address ADDR may indicate a specific storage location of the user area 111 .

[0091] In operation S320, the host interface block 124 may determine whether the received command CMD is a turbo write command. When the received command CMD is a turbo write command, in operations S330 and S340, the controller 120 may relatively quickly perform a turbo write operation of writing the data DATA.

[0092] For example, in operation S330, the memory interface block 123 may write the received data DATA into the buffer area 112. Since the memory cells of the buffer area 112 are used as single-layer cells SLC, the speed at which the data DATA is written is relatively fast. Thereafter, in operation S340, in response to a request from an external host device or at an idle time, the memory interface block 123 may migrate the data DATA written into the buffer area 112 to the user area 111 based on the address ADDR.

[0093] When it is determined in operation S320 that the received write command is not a turbo write command (i.e., when the received write command is a typical / normal write command), operation S350 is performed. In operation S350, the controller 120 may perform a normal write operation of writing the data DATA to the memory, which may be slower than the turbo write operation. The memory interface block 123 may write the data DATA directly to the user area 111 based on the address ADDR without using the buffer area 112.

[0094] That is, the storage device 100 may allow the host device to select a turbo write operation using the buffer area 112 and a normal write operation not using the buffer area 112. When a large amount of write data is generated (for example, in the case of storing image data), the external host device may select a turbo write operation to perform fast data processing. When a small amount of write data is generated (for example, in the case of storing document data), the external host device may select a normal write operation to allow for a margin of resources in the buffer area 112. Optionally, the storage device 100 may control the selection of a turbo write operation or a normal write operation based on the available size of the buffer area 112 and the size of the data DATA. If the size of the data DATA is smaller than the available size of the buffer area, the storage device 100 may perform a turbo write operation. If the size of the data DATA is larger than the available size of the buffer area, the storage device may perform a normal write operation. Optionally, as will be described for Fig.17 As described above, if the size of the data DATA is larger than the available size of the buffer, the storage device may split the data DATA and perform a turbo write operation on a portion of the data DATA and a normal write operation on the remaining portion of the data DATA.

[0095] Fig.10 2 shows a storage device 200 according to an embodiment. Fig.10 , the storage device 200 includes a nonvolatile memory device 210 , a controller 220 , and a random access memory 230 .

[0096] As reference Figure 1 As described above, the nonvolatile memory device 210 may include a user area 211 and a buffer area 212. Figure 1 As described above, the controller 220 may include a buffer size block 221 , a migration block 222 , a memory interface block 223 , and a host interface block 224 . In addition, the controller 220 may further include a memory controller 225 .

[0097] The memory controller 225 may be configured to control the random access memory 230. The memory device 200 may use the random access memory 230 as a buffer between the nonvolatile memory device 210 and the external host device. The controller 220 may store data received from the external host device in the random access memory 230.

[0098] The controller 220 may write the data stored in the random access memory 230 into the nonvolatile memory device 210. In this case, as shown in FIG. Fig. 9 As described above, the controller 220 may select one of the turbo write operation and the normal write operation. Figures 1 to 8 As described above, the buffer size block 221 may identify the available buffer size of the buffer area 212 .

[0099] The controller 220 may not provide the available buffer size to the external host device and may use the available buffer size internally. The controller 220 may refer to the available buffer size when writing write data stored in the random access memory 230 to the buffer area 212 through a turbo write operation. For example, the controller 220 may write data whose size is less than or equal to the available buffer size to the buffer area 212 through a turbo write operation.

[0100] The controller 220 may store data read from the nonvolatile memory device 210 in the random access memory 230. The controller 220 may transmit the data stored in the random access memory 230 to an external host device.

[0101] Fig.11 FIG. 3 shows a computing device 300 according to an embodiment. Fig.11 , the computing device 300 may be implemented as a mobile device (such as a smart phone, a smart tablet, or a notebook computer) or a fixed device (such as a computer, a workstation, or a server).

[0102] The computing device 300 includes a processor 310, a random access memory 320, a modem 330, a user interface 340, and a storage device 350. The processor 310 may run an operating system required to drive the computing device 300 and various applications executable on the operating system. The processor 310 may be a host device of the storage device 350.

[0103] For example, the processor 310 may read program codes of an operating system and an application from the storage device 350, and may store the read codes in the random access memory 320. The processor 310 may execute the operating system and the application by executing the codes stored in the random access memory 320. The processor 310 may include a central processing unit (CPU) or an application processor (AP).

[0104] The random access memory 320 may be used as a system memory or a working memory of the computing device 300. The random access memory 320 may store various codes to be executed by the processor 310. The random access memory 320 may store user data generated by an operating system or an application of the processor 310.

[0105] The random access memory 320 may store data received from an external device through the modem 330 or data to be transmitted to an external device through the modem 330. The random access memory 320 may store data input from an external user through the user interface 340 or data to be output to an external user through the user interface 340.

[0106] The random access memory 320 may include dynamic random access memory (DRAM), static random access memory (SRAM), phase change RAM (PRAM), magnetic RAM (MRAM), ferroelectric RAM (FRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc.

[0107] The modem 330 is a communication interface configured to perform wired or wireless communication with an external device. The modem 330 may communicate with the external device based on at least one of various standards such as Ethernet, Long Term Evolution (LTE), 5th Generation (5G) mobile communication, wireless fidelity Bluetooth, and near field communication (NFC).

[0108] The user interface 340 is configured to exchange information with a user. The user interface 340 may include a user input device capable of receiving information from a user, such as a keyboard, a mouse, a touch pad, a touch panel, a microphone. The user interface 340 may include a user output device capable of providing information to a user, such as a monitor, a beam projector, a speaker, and a motor.

[0109] The storage device 350 may be used to store the code of the operating system and applications and user data. The storage device 350 may be a disk and may include a reference Figures 1 to 10 The storage device 100 described above. The storage device 350 may identify a memory block whose elapsed time after erasure is greater than the reuse time among the invalid memory blocks of the buffer area 112 or 212 as an available buffer area.

[0110] As reference Figures 1 to 9 As described above, the storage device 350 may identify the available buffer size and may report the available buffer size to the processor 310. The processor 310 may select one of the turbo write operation and the normal write operation based on the available buffer size. The processor 310 may write data to the storage device 350 through the selected write operation.

[0111] As reference Fig.10 As described above, the storage device 350 may not separately report the available buffer size to the processor 310. The processor 310 may request a write operation from the storage device 350 without distinguishing between a turbo write operation and a normal write operation.

[0112] The storage device 350 may store the write data in the random access memory 320. When writing the data stored in the random access memory 320 to the storage device 350, the storage device 350 may select one of a turbo write operation and a normal write operation based on an available buffer size.

[0113] Fig.12 FIG. 3 shows a method of storing data executed between the processor 310 and the storage device 350. Fig.12 In the storage device 350, the reference Figures 1 to 9 The storage device 100 described herein. Figure 1 , Fig.11 and Fig.12 , in operation S410 and operation S412, the processor 310 and the storage device 350 may perform a supply operation.

[0114] For example, in operation S410, the processor 310 may request the storage device 350 to supply the buffer area 212. The request of operation S410 may be performed by using a universal flash memory (UFS) based query request UFS protocol information unit (UPIU). The processor 310 may send a write descriptor query request UPIU to the storage device 350.

[0115] The write descriptor query request UPIU may include mode information, size information, and logical unit (LU) information. The mode information may indicate a way of generating the buffer area 212, and may include a reduction mode and a non-reduction mode.

[0116] The size information may include information about the size of the buffer area 212. The LU information may indicate whether all LUs share the buffer area 212 in a state where the buffer area 212 is implemented with one LU of the storage device 350, or whether the buffer area 212 is implemented with each LU of the storage device 350. In operation S412, the storage device 350 may send a response UPIU to the processor 310. For example, the response UPIU may include an available buffer size of the buffer area.

[0117] Figures 13 to 16 A diagram showing the execution of a provisioning operation. For example, Fig.13 A diagram showing allocation of a buffer area in a reduction mode when the storage device 350 does not have an over-provisioning (OP) area.

[0118] Reference Fig.11 and Fig.13 , the storage space of the storage device 350 may be divided into a meta area and a user area. The meta area may be used by the storage device 350 to store metadata (e.g., a mapping table of logical addresses and physical addresses) required for managing the storage device 350. The meta area is not accessible to an external host device (e.g., the processor 310).

[0119] The user area may be an area of ​​the storage device 350 accessible to the processor 310 and may be accessed by the processor 310 to write data. When the computing device 300 is initialized (or booted), the storage device 350 may provide the processor 310 with capacity information of the user area.

[0120] In the provisioning operation S410, the processor 310 may provide the size information of the buffer area to the storage device 350. The storage device 350 may allocate an area of ​​the user area corresponding to the size information for the buffer area. That is, in the reduction mode, when the provisioning operation is performed, the size of the user area may be reduced to be smaller than the original size. The buffer area may be allocated to be equal in size to the reduction of the user area.

[0121] The size of the buffer area may be fixed. The memory block selected as the buffer area may be physically fixed. That is, when restarting and resupplying are performed, the previously selected memory block may be consistently selected as the buffer area. Fig.13 For example, while a buffer area supporting a turbo write operation can be stably ensured, a user area of ​​the storage device 350 allocated to write data can be reduced.

[0122] Fig.14 A diagram showing allocation of a buffer area in a non-reduction mode when the storage device 350 does not have an over-provisioning (OP) area. Fig.11 and Fig.14 In the supply operation, the size information may include a maximum size of the buffer area. The size of the buffer area may vary with the size information.

[0123] The storage device 350 may provide the original size of the user area to the processor 310. The storage device 350 may adaptively or dynamically allocate the buffer area in the user area. For example, the storage device 350 may allocate a memory block of the user area where data is not written as the buffer area.

[0124] In one example, the storage device 350 may change the number of memory blocks included in the buffer area in proportion to the ratio of the capacity of the data written to the user area to the capacity of the user area. In another example, when there is no data written to the user area, the storage device 350 may allocate the buffer area to have a maximum size. When data is written to the user area, the storage device 350 may reduce the size of the buffer area. For example, as the fill rate of the user area increases, the storage device 350 may reduce the size of the buffer area.

[0125] The buffer area may be reduced to a minimum size of the size information. For example, the minimum size may be automatically determined by the storage device 350. As the fill rate of the user area decreases, the storage device 350 may increase the size of the buffer area. The storage device 350 may adaptively or dynamically select the memory blocks to be included in the buffer area.

[0126] For example, the memory device 350 may adaptively select memory blocks to be included in the buffer area with reference to the age or usage degree of the memory device 350 and the number of program / erase cycles of each memory block. Memory blocks with a low (or high) usage degree or a small (or large) number of program / erase cycles may be included in the buffer area.

[0127] The storage device 350 may manage a specific memory block differently based on whether the specific memory block is included in the buffer area. For example, the storage device 350 may manage parameters such as a read count and the number of program / erase cycles of the memory block, and may manage data by using the parameters.

[0128] The storage device 350 may differently set the weight to be applied to the read count and the weight to be applied to the number of program / erase cycles based on whether a specific memory block is included in the buffer area. For example, a smaller (or larger) weight may be applied to the read count of the memory block belonging to the buffer area, and a smaller (or larger) weight may be applied to the number of program / erase cycles of the memory block belonging to the buffer area.

[0129] As reference Fig.14 As described above, the processor 310 may select the non-reduction mode to perform the provisioning operation, thereby effectively utilizing the original size of the user area of ​​the storage device 350 .

[0130] Fig.15 A diagram showing allocation of a buffer area in a reduction mode when the storage device 350 has an over-provisioned (OP) area. Fig.11 and Fig.15 , in addition to the meta area and the user area, the storage device 350 may also have an over-provisioning area.

[0131] The over-provisioning area may be a storage space set to improve the performance of the storage device 350. For example, in the case where there are free memory blocks where no data is written, when a garbage collection operation or a read reclaim operation is performed on data written to the user area, the garbage collection operation and the read reclaim operation may be performed faster.

[0132] The storage device 350 may provide a user area to an external host device, and may write and manage user data using the user area and the over-provisioning area as a whole.

[0133] In the provisioning operation S410, the storage device 350 may fixedly allocate a portion of the over-provisioning area or the user area for the buffer area. A portion of the buffer area may be included in the over-provisioning area, and the remaining portion of the buffer area may be included in the user area. Therefore, the user area or the over-provisioning area may have an original size or a reduced size.

[0134] Fig.16 A diagram showing allocation of a buffer area in a non-reduction mode when the storage device 350 has an over-provisioning (OP) area. Fig.11 and Fig.16 , in addition to the meta area and the user area, the storage device 350 may also have an over-provisioning area.

[0135] In the provisioning operation S410, the storage device 350 may maintain the original size of the user area or the over-provisioning area. The storage device 350 may dynamically allocate the user area or the over-provisioning area for the buffer area. A portion of the buffer area may be included in the over-provisioning area, and the remaining portion of the buffer area may be included in the user area.

[0136] return Fig.12 In operation S420 and operation S422, the processor 310 and the storage device 350 may perform a turbo write operation. For example, in operation S420, the processor 310 may request the storage device 350 for a turbo write operation.

[0137] For example, a request for a turbo write operation may use a UFS-based write command UPIU. By setting the group number of the write command UPIU to a specific value (e.g., "0x11"), the write command UPIU may be identified as a request for a turbo write operation. The storage device 350 may write data to the buffer area 112 in response to the write command UPIU having the group number "0x11". In one embodiment, the turbo write command and the normal write command have UFS-based write command UPIUs with different group numbers. In operation S422, the storage device 350 may send the response UPIU to the processor 310.

[0138] In operation S430 and operation S432, the processor 310 and the storage device 350 may perform a normal write operation. For example, in operation S430, the processor 310 may request the storage device 350 for a normal write operation.

[0139] For example, the request for a normal write operation may use a UFS-based write command UPIU. The storage device 350 may write data to the user area 111 in response to the write command UPIU. In operation S432, the storage device 350 may send a response UPIU to the processor 310.

[0140] In operation S440, the processor 310 and the storage device 350 may perform a migration operation or may set a migration operation. For example, in operation S440, the processor 310 may request a migration operation from the storage device 350. The request for the migration operation may be performed by using a UFS-based query request UPIU.

[0141] For example, the processor 310 may send a set flag query request UPIU to the storage device 350. The set flag query request UPIU may include refresh information or sleep information. In one embodiment, the set flag query request UPIU may activate the migration operation. When the set flag query request UPIU includes refresh information, the storage device 350 may perform a reference operation in response to the set flag query request UPIU. Figure 7 Describes the migration operation.

[0142] When the set flag query request UPIU includes the sleep information, the storage device 350 may change the migration setting. For example, in response to the set flag query request UPIU, the storage device 350 may change the migration setting so that the migration operation is autonomously performed in the sleep mode or so that the autonomous migration operation is not performed.

[0143] In operation S442, the storage device 350 may send a response UPIU to the processor 310. For example, the response UPIU may include an available buffer size. That is, when the migration operation is completed, the storage device 350 may identify the available buffer size and may report the available buffer size to the processor 310.

[0144] In operation S450 and operation S452, the processor 310 and the storage device 350 may perform a buffer size query operation. For example, in operation S450, the processor 310 may query the storage device 350 to obtain the buffer size. The query about the buffer size may be performed by using a query request based on UFS.

[0145] For example, the processor 310 may send a read attribute query request UPIU to the storage device 350. In operation S452, the storage device 350 may send a response UPIU to the processor 310. The response UPIU may include an available buffer size. For example, in response to the read attribute query request UPIU, the storage device 350 may identify the available buffer size and may provide an indication of the available buffer size to the processor 310.

[0146] In one embodiment, as shown in FIG. Fig.10 When the storage device 350 includes a random access memory 320, refer to Fig.12 The turbo write operation, normal write operation, and migration operation described above may be autonomously performed by the controller 220. Fig.12 As described above, the storage device 350 may perform the supply operation in response to the request of the processor 310. The buffer size query operation may be omitted.

[0147] Fig.17 FIG. 3 shows a method in which the processor 310 writes data into the storage device 350. Figure 1 , Fig.11 and Fig.17 In operation S510, the processor 310 may determine whether the data to be written requires a turbo write operation. For example, when the data to be written requires a write operation for a large amount of data (such as video data), the processor 310 may determine that the data to be written requires a turbo write operation.

[0148] When the data to be written requires a turbo write operation, the processor 310 may determine whether the size of the data to be written is greater than the available buffer size in operation S520. When the size of the data to be written is not greater than the available buffer size, the processor 310 may perform a turbo write operation to write the data to the buffer area 112 in operation S530.

[0149] When the size of the data to be written is larger than the available buffer size, the processor 310 may divide the data into a turbo part and a normal part in operation S540. In operation S550, the processor 310 may perform a turbo write operation of writing the turbo part of the data to the buffer area 112.

[0150] In operation S560, the processor 310 may perform a normal write operation to write a normal portion of data to the user area 111. That is, the processor 310 may split the data to be written and may write the split portions to the storage device 350 through a turbo write operation and a normal write operation.

[0151] When it is determined in operation S510 that the data to be written does not require a turbo write operation, the processor 310 may perform a normal write operation of writing the data to the user area 111 of the storage device 350 in operation S570 .

[0152] As reference Fig.10 When the storage device 350 includes a random access memory 320, refer to Fig.17 The described method may be performed autonomously by the controller 220 .

[0153] Fig.18 The method of changing the size of the buffer area in the computing device 300 is shown. Figure 1 , Fig.11 and Fig.18 In operation S610, as described above, the computing device 300 may perform booting and provisioning when powered. For example, the processor 310 may perform provisioning operations on the storage device 350 based on the size of the buffer area of ​​the existing provisioning setting. Thereafter, the computing device 300 may run an operating system and applications under the control of a user.

[0154] In operation S620, the computing device 300 may receive a buffer area change input. For example, the computing device 300 may receive the buffer area change input from the user through the user interface 340. In operation S630, in response to the buffer area change input, the processor 310 may update the size of the buffer area of ​​the supply setting.

[0155] Thereafter, in operation S640, the computing device 300 may perform booting and provisioning again. For example, the processor 310 may perform a provisioning operation on the storage device 350 based on the size of the buffer area of ​​the updated provisioning setting.

[0156] As described above, computing device 300 may change the size of the buffer area based on user input. Changing the size of the buffer area may be accompanied by restarting and re-provisioning. When changes in the size of the buffer area are allowed, computing device 300 may provide greater flexibility for the user.

[0157] When the size of the buffer area increases, the existing memory block that has been used as the user area can be used as the buffer area. When the size of the buffer area decreases, the existing memory block that has been used as the buffer area can be used as the user area.

[0158] The storage device 350 may manage a specific memory block differently based on whether the specific memory block is included in the buffer area. For example, the storage device 350 may manage parameters such as a read count and the number of program / erase cycles of the memory block, and may manage data by using the parameters.

[0159] The storage device 350 may differently set the weight to be applied to the read count and the weight to be applied to the number of program / erase cycles based on whether a specific memory block is included in the buffer area. For example, a smaller (or larger) weight may be applied to the read count of the memory block belonging to the buffer area, and a smaller (or larger) weight may be applied to the number of program / erase cycles of the memory block belonging to the buffer area.

[0160] As described above, the components of the storage device 100 or 200 and the computing device 300 are described by using the terms "first", "second", "third", etc. However, the terms "first", "second", "third", etc. may be used to distinguish the components from each other and do not limit the description of the components. For example, the terms "first", "second", "third", etc. do not refer to any form of order or numerical meaning.

[0161] In the above embodiments, the components according to the embodiments are described by using blocks. The blocks can be implemented using various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), and complex programmable logic devices (CPLDs)), firmware driven in hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, the blocks may include semiconductor elements in circuits or integrated circuits registered as circuits.

[0162] According to an embodiment, the available buffer size of the buffer area is identified based on whether the reuse time has passed after the memory block of the buffer area is erased. Therefore, a storage device and a computing device are provided that can prevent errors from occurring in the buffer area due to frequent erase operations and provide improved reliability.

[0163] While the above concepts have been described with reference to exemplary embodiments, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the concepts as set forth in the following claims.

Claims

1. A storage device, include: a non-volatile memory device comprising a plurality of memory blocks; as well as a controller configured to use some of the plurality of memory blocks as a buffer area, wherein the memory blocks storing invalid data among the some memory blocks are invalid memory blocks, The controller is further configured as follows: identifying the capacity of a memory block whose elapsed time after erasure is greater than the reuse time among the invalid memory blocks as an available buffer size; and Provides the available buffer size to the external host device, The controller is further configured to: receive a supply command from an external host device, The controller is further configured to: when the mode information of the supply command indicates a reduction mode, fixedly select some of the memory blocks included in the buffer area, The controller is further configured to adaptively select the some memory blocks included in the buffer area when the mode information of the supply command indicates a non-reduction mode.

2. The storage device according to claim 1, in, The controller checks the invalid memory block in response to a request of an external host device or periodically, and updates the available buffer size based on a result of the check.

3. The storage device according to claim 1, in, The controller provides the available buffer size to the external host device in response to a universal flash protocol information unit based on a read attribute query request of the universal flash memory received from the external host device.

4. The storage device according to claim 1, in, The controller is configured as: receiving a write command, address, and data from an external host device; When the write command is a turbo write command, the data is written into the buffer area; When the write command is a normal write command, data is written at a location indicated by an address in other memory blocks except for the buffer area.

5. The storage device according to claim 4, in, The turbo write command and the normal write command have a universal flash memory-based write command universal flash memory protocol information unit with different group numbers.

6. The storage device according to claim 4, in, The turbo write commands include: A universal flash based set flag query request universal flash protocol information unit for activating a migration operation; and Write command based on universal flash memory universal flash protocol information unit.

7. The storage device according to claim 4, in, The controller is further configured to: respond to a request from an external host device or in a sleep mode, Migrating valid data written into the buffer area to a location indicated by an address in another memory block except the buffer area; and Invalidate valid data.

8. The storage device according to claim 7, in, The request of the external host device includes a universal flash protocol information unit based on a set flag query request of the universal flash.

9. The storage device according to claim 7, in, Activate or deactivate moving valid data in sleep mode by requesting a universal flash protocol information unit based on a set flag query of the universal flash.

10. The storage device according to claim 1, in, The controller is also configured to: In a boot operation, providing the capacity of the plurality of memory blocks to an external host device; receiving a provision command including capacity information of a buffer area from an external host device; and The some of the plurality of memory blocks are selected based on the capacity information to be allocated to the buffer area.

11. The storage device according to claim 10, in, The controller is further configured to provide storage capacity of remaining memory blocks of the plurality of memory blocks except for the some memory blocks in the buffer area as a user area to the external host device when the mode information indicates a reduction mode.

12. The storage device according to claim 11, in, The controller uses the memory cells of the some memory blocks as single-level cells and uses the memory cells of the remaining memory blocks as at least multi-level cells.

13. The storage device according to claim 10, in, The controller is further configured to provide storage capacity of the plurality of memory blocks as a user area to an external host device when the mode information indicates a non-shrink mode.

14. The storage device according to claim 13, in, The controller uses the memory cells of the some memory blocks as single-level cells and uses the memory cells of the remaining memory blocks as at least multi-level cells.

15. The storage device according to claim 14, in, The capacity information indicates the maximum capacity of the buffer area, and The controller is further configured to change the number of the some memory blocks included in the buffer area within a range less than or equal to the maximum capacity.

16. The storage device according to claim 15, in, The controller changes the number of the some memory blocks included in the buffer area in proportion to the ratio of the capacity of the data written to the user area to the capacity of the user area.

17. A storage device, include: a nonvolatile memory device including a plurality of memory blocks, the plurality of memory blocks being configured as a user area including a first memory block among the plurality of memory blocks and a buffer area including a second memory block among the plurality of memory blocks; as well as The controller is configured as: receiving a write command for writing data into a nonvolatile memory device, the write command comprising a turbo write command for a turbo write operation for writing data into a user area through a buffer area, writing the data to the nonvolatile memory device through the buffer area according to a turbo write operation of a turbo write command based on recognizing that the size of the data does not exceed the available buffer size of the buffer area, the available buffer size of the buffer area including the size of an available memory block selected from the memory blocks storing invalid data among the second memory blocks, wherein a time period between a time when the storage data stored in the available memory blocks is erased from the available memory blocks of the buffer area and a current time exceeds a predetermined time, and writing the data to the nonvolatile memory device according to a normal write operation of a normal write command for directly writing the data to the user area based on recognizing that the size of the data exceeds the available size of the buffer area, The controller is further configured to: receive a supply command from an external host device, The controller is further configured to: when the mode information of the supply command indicates the reduction mode, fixedly select the second memory block included in the buffer area, The controller is further configured to adaptively select a second memory block included in the buffer area when the mode information of the supply command indicates a non-reduction mode.

18. The storage device according to claim 17, further comprising: include: Random Access Memory, The controller reads data from the random access memory and writes the data into the non-volatile memory device.

19. A computing device, include: a storage device including a buffer area and a user area, and configured to output, as an available buffer size, a size of a storage space in the buffer area storing invalid data for which an elapsed time after erasure is greater than a reuse time; as well as A processor, wherein the processor is configured to: Receive available buffer size; sending data requiring a turbo write operation and having a size no greater than the available buffer size to the storage device together with the turbo write command; and Send data that does not require a turbo write operation to the storage device along with a normal write command. The storage device is further configured to: receive a supply command from the processor, The storage device is further configured to: when the mode information of the supply command indicates the reduction mode, allocate an area of ​​the user area corresponding to the size information of the supply command as a buffer area, The storage device is further configured to adaptively allocate the buffer area in the user area when the mode information of the supply command indicates a non-reduction mode.

20. The computing device according to claim 19, in, The processor is also configured to: Splitting data requiring a turbo write operation and having a size larger than an available buffer size into a turbo portion and a normal portion having an available buffer size; sending the turbo portion along with a turbo write command to the storage device; and The normal portion is sent to the storage device along with a normal write command.

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