Semiconductor device having a die pad with a bank-like structure

Abstract

A semiconductor device is disclosed, comprising: a semiconductor substrate; a power transistor formed in the semiconductor substrate, the power transistor including an active region in which one or more power transistor cells are formed; a first metal pad formed above the semiconductor substrate and substantially covering all active regions of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active region of the power transistor, the first metal pad including an inner region, the inner region being laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; and a first interconnect board or semiconductor die attached to the inner region of the first metal pad by a die attach material. A corresponding manufacturing method is also described.

Description

Background Art

[0001] Many semiconductor device technologies use metal clips for source / emitter pad interconnection. Cross contamination between adjacent bonding pads is associated with the use of clip bonding with solder paste material. Undesirable distribution or spreading of solder paste material is commonly referred to as "overflow" and can cause severe die pad corrosion. Cu-based logic die pads are particularly sensitive to solder paste material overflow. For example, a typical Cu-to-Cu nail head bonding process does not allow any organic foreign matter or corrosive byproducts on the Cu die pad surface.

[0002] Therefore, there is a need for improved semiconductor device interconnection techniques. Summary of the invention

[0003] According to an embodiment of a semiconductor device, the semiconductor device includes: a semiconductor substrate; a power transistor formed in the semiconductor substrate, the power transistor including an active area, one or more power transistor units formed in the active area; a first metal pad formed above the semiconductor substrate and substantially covering all active areas of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of ​​the power transistor, the first metal pad including an inner area laterally surrounded by a peripheral area, the peripheral area being thicker than the inner area; and a first interconnect board or a semiconductor die attached to the inner area of ​​the first metal pad by a die attach material.

[0004] In one embodiment, the inner region of the first metal pad has a thickness in a range of 5 μm to 10 μm, and the outer region of the first metal pad has a thickness of about 20 μm or more.

[0005] Alone or in combination, the semiconductor substrate may have a thickness of 250 μm or less, for example, 60 μm or less.

[0006] Either alone or in combination, a peripheral region of the first metal pad may be thicker than the die attach material.

[0007] Either alone or in combination, the die attach material can be thicker than the peripheral region of the first metal pad such that a bottom surface of the first interconnect board or the semiconductor die is disposed above a top surface of the peripheral region of the first metal pad.

[0008] Either alone or in combination, the bottom surface of the first interconnect board may have one or more structures disposed laterally inward from a peripheral region of the first metal pad and extending vertically toward an interior region of the first metal pad.

[0009] Either alone or in combination, the peripheral region of the first metal pad may be divided into a plurality of segments, and adjacent ones of the segments may be laterally separated by a gap.

[0010] Either alone or in combination, the power transistor may include a plurality of output channels, each configured to deliver current to a load, the power transistor may include an individual active region for each output channel, and the first metal pad may substantially cover a first one of the active regions of the power transistor.

[0011] Either alone or in combination, the semiconductor device may further include: a plurality of additional metal pads formed above the semiconductor substrate, each additional metal pad substantially covering a corresponding one of the active regions of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active region substantially covered by the metal pad, each metal pad comprising an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; and a plurality of additional interconnect boards, each additional interconnect board being attached to the inner region of a corresponding one of the additional metal pads by a die connection material.

[0012] Alone or in combination, the semiconductor device may also include one or more logic devices integrated as power transistors in different regions of the semiconductor substrate.

[0013] Either alone or in combination, the first metal pad may be a Cu pad and the first interconnect plate may be a Cu clip.

[0014] According to an embodiment of a method for manufacturing a semiconductor device, the method includes: forming a power transistor in a semiconductor substrate, the power transistor including an active area, forming one or more power transistor units in the active area; forming a first metal pad above the semiconductor substrate, and the first metal pad substantially covers all active areas of the power transistor, the first metal pad is electrically connected to a source or emitter region in the active area of ​​the power transistor, the first metal pad includes an inner area laterally surrounded by a peripheral area, the peripheral area is thicker than the inner area; and attaching a first interconnect board or a semiconductor die to the inner area of ​​the first metal pad by a die attach material.

[0015] In one embodiment, forming a first metal pad includes: depositing a first Cu layer over a semiconductor substrate, and the first Cu layer substantially covers all active areas of a power transistor; forming a mask on a portion of the first Cu layer corresponding to an inner region of the first metal pad, the mask being configured to prevent Cu deposition; and depositing a second Cu layer on a portion of the first Cu layer not protected by the mask to form a peripheral region of the first metal pad, the inner region of the first metal pad being formed by a portion of the first Cu layer protected by the mask during deposition of the second Cu layer. The first Cu layer may have a thickness in a range of 5 μm to 10 μm, and the second Cu layer may have a thickness in a range of 10 μm to 20 μm.

[0016] In another embodiment, forming the first metal pad may include: depositing a Cu layer over the semiconductor substrate, and the Cu layer substantially covers all active areas of the power transistor; forming a mask on a portion of the Cu layer corresponding to a peripheral region of the first metal pad, the mask being configured to prevent Cu etching; and etching a portion of the Cu layer not protected by the mask to form an inner region of the first metal pad, the peripheral region of the first metal pad being formed by a portion of the Cu layer protected by the mask during etching of the Cu layer. The thickness of the deposited Cu layer may be about 20 μm or greater, and the thickness of the etched portion of the Cu layer may be in the range of 5 μm to 10 μm.

[0017] Either alone or in combination, the peripheral region of the first metal pad may be thicker than the die attach material, and wherein attaching the first interconnect board or the semiconductor die to the inner region of the first metal pad may include: depositing the die attach material on the inner region of the first metal pad; and placing the first interconnect board in contact with the die attach material while aligning the first interconnect board with the first metal pad using the peripheral region of the first metal pad.

[0018] Either alone or in combination, the die attach material may be thicker than a peripheral region of the first metal pad, and wherein attaching the first interconnect board or the semiconductor die to an inner region of the first metal pad may include: depositing the die attach material on the inner region of the first metal pad; and placing the first interconnect board in contact with the die attach material while aligning the first interconnect board with the first metal pad using surface tension of the die attach material.

[0019] Either individually or in combination, the bottom surface of the first interconnect board may have one or more structures disposed laterally inward from a peripheral region of the first metal pad, and attaching the first interconnect board or the semiconductor die to the inner region of the first metal pad may include: depositing a die attach material on the inner region of the first metal pad; and placing the first interconnect board in contact with the die attach material such that one or more features at the bottom surface of the first interconnect board extend vertically toward the inner region of the first metal pad and are disposed laterally inward from the peripheral region of the first metal pad to align the first interconnect board with the first metal pad.

[0020] Either individually or in combination, the power transistor may include a plurality of output channels, each output channel being configured to deliver current to a load, the power transistor may include an individual active region for each output channel, the first metal pad may substantially cover a first one of the active regions of the power transistor, and the method may further include: forming a plurality of additional metal pads above the semiconductor substrate, each additional metal pad substantially covering a corresponding one of the active regions of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active region substantially covered by the metal pad, each metal pad including an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; and attaching each of the plurality of additional interconnect boards to the inner region of a corresponding one of the additional metal pads by a die attach material.

[0021] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The elements of the drawings are not necessarily to scale with respect to each other. The same reference numerals represent corresponding similar parts. The features of the various illustrated embodiments may be combined unless they are mutually exclusive. The embodiments are depicted in the drawings and described in detail in the following description.

[0023] Figure 1 A side perspective view of an embodiment of a semiconductor device having a metal pad with a bank-like configuration is shown.

[0024] Figure 2A A top view of another embodiment of a semiconductor device having a metal pad with a bank-like configuration is shown.

[0025] Figure 2B Shown along Figure 2A A cross-sectional view of a semiconductor device taken along line AA′ in FIG.

[0026] Figure 2C Shown with Figure 2A-2B The device shown is a similar semiconductor device, but the semiconductor die is attached to the inner region of the metal pad having a bank-like configuration.

[0027] FIG. 3A to FIG. 3C It shows the formation of FIG. 2A to FIG. 2B A corresponding top view of an embodiment of a metal pad 102 having a bank-like configuration is shown.

[0028] Figure 4 Shown attached to FIG. 3A to FIG. 3C A side perspective view of an embodiment of an interconnect board showing a thinner inner region of a first metal pad.

[0029] Figures 5 to 7Corresponding cross-sectional views of other embodiments of semiconductor devices having metal pads with bank-like configurations, each device having a different chip pad-to-interconnect interface, are shown.

[0030] Figure 8 A top view of an embodiment of a semiconductor device is shown having four separate active areas, four output channels, and a separate metal pad having a bank-like configuration for each active area / output channel.

[0031] 9A to 9E Respective cross-sectional views are shown during different stages of fabricating a semiconductor device having one or more metal pads with a bank-like configuration.

[0032] FIG. 10A to FIG. 10C Respective cross-sectional views are shown during different stages of fabricating a semiconductor device having one or more metal pads with a bank-like configuration according to another embodiment. DETAILED DESCRIPTION

[0033] Embodiments described herein provide a metal pad structure for a semiconductor die and a corresponding manufacturing method. The metal pad has an inner region laterally surrounded by a peripheral region. The peripheral region is thicker than the inner region. The inner region of the metal pad is configured for attachment to an interconnection board such as a metal clip or a metal block, or for attachment to another semiconductor die. The thicker peripheral region of the metal pad forms a dam-like structure for retaining material for attaching an interconnection board or another semiconductor die to the metal pad. It is also beneficial that, since the inner region of the metal pad is made thinner, the metal pad exerts less mechanical stress on the semiconductor substrate during heating and cooling of the device.

[0034] Figure 1 A side perspective view of an embodiment of a semiconductor device 100 having a metal pad 102 with a bank-like structure is shown. According to the embodiment, the semiconductor device 100 includes a semiconductor substrate 104 and a power transistor formed in the semiconductor substrate 104, such as a power MOSFET (metal oxide semiconductor field effect transistor), an IGBT (insulated gate bipolar transistor), a HEMT (high electron mobility transistor), etc. One or more logic devices can be integrated in a region of the semiconductor substrate 104 different from the power transistor, for example, to control the power transistor. For example, a driver circuit and / or a controller can be integrated in the semiconductor substrate 104 to control the power transistor.

[0035] The semiconductor substrate 104 may be relatively thick, for example, greater than 250 μm thick, or relatively thin, for example, less than 250 μm thick. The semiconductor substrate 104 may be made of any semiconductor material suitable for manufacturing power transistors. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN) or indium gallium arsenic phosphide (InGaAsP), etc.

[0036] The power transistor formed in the semiconductor substrate 104 includes an active region in which one or more power transistor cells are formed. The active region is covered by the metal pad 102 having a bank-like structure, and thus Figure 1 1. A metal pad 102 having a bank-like structure is formed over a semiconductor substrate 104 and substantially covers all of the active area of ​​the power transistor. The metal pad 102 is electrically connected to a source or emitter region in the active area of ​​the power transistor. The metal pad 102 has an inner region 106 laterally surrounded by a peripheral region 108. The peripheral region 108 is thicker than the inner region 106. The thicker peripheral region 108 of the metal pad 102 forms a bank-like structure for holding material for attaching an interconnect board or another semiconductor die to the metal pad 102. Figure 1 An interconnect board or another semiconductor die attached to metal pad 102 having a bank-like configuration is not shown in order to provide an unobstructed view of the entire metal pad 102 .

[0037] In one embodiment, the inner region 106 of the metal pad 102 having the bank-like configuration has a thickness t1 in the range of about 5 μm to about 20 μm, and the peripheral region 108 of the metal pad 102 has a thickness t2 of about 20 μm or more. Other thickness ranges of the inner and peripheral regions 106, 108 of the metal pad 102 are contemplated. In general, the inner and peripheral regions 106, 108 of the metal pad 102 having the bank-like configuration may have any desired thickness, as long as the peripheral region 108 is thicker than the inner region 106. Such a metal pad 102 having a thinner inner region 106 and a thicker peripheral region 108 is particularly advantageous for thinner semiconductor dies, for example, in the case where the semiconductor substrate 104 has a thickness of 60 μm or less, because the metal pad 102 exerts less mechanical stress on the semiconductor substrate 104 during heating and cooling of the device 100.

[0038] The side of the semiconductor device 100 having the metal pad 102 with the bank-like structure may include additional metal structures, such as other metal pads 110 and / or metal traces 112 formed in the same metal layer as the metal pad 102 with the bank-like structure. For example, the side of the semiconductor device having the metal pad 102 with the bank-like structure may also include a gate pad 110, which is electrically connected to the gate electrode in the active area of ​​the power transistor. The gate pad 110 may or may not have the same thickness as the peripheral area 108 of the metal pad 102 with the bank-like structure. One or more metal traces 112 may be formed on the side of the semiconductor device 100 having the metal pad 102 with the bank-like structure. The metal traces 112 provide signal routing for the power transistor and may or may not have the same thickness as the inner area 106 of the metal pad 102 with the bank-like structure.

[0039] Figure 2A A top view of another embodiment of a semiconductor device 200 having a metal pad 102 with a bank-like structure is shown, and Figure 2B Shown along Figure 2A FIG. 2 is a cross-sectional view of the semiconductor device 200 along the line marked AA′ in FIG. Figure 2A and Figure 2B The embodiment shown is similar to Figure 1 However, differently, the semiconductor device 200 includes additional pads 202, 204 on the side of the semiconductor device 200 having the metal pad 102 with the thinner inner region 106 and the thicker peripheral region 108. The additional pads 202, 204 may be used to electrically contact different or additional regions of the power transistor formed in the semiconductor substrate 104, and / or may be used to make electrical contact from the back side to the front side of the semiconductor device 200.

[0040] Figure 2B Also shown is the semiconductor device 200 after attaching an interconnect board 206, such as a metal clip or a metal block, to the inner region 106 of the metal pad 102 having the bank-like configuration. The interconnect board 206 is attached to the inner region 106 of the metal pad 102 by a die attach material 208, such as solder, conductive glue, conductive tape, etc. Both the interconnect board 206 and the inner region 106 of the metal pad 102 to which the interconnect board 206 is attached may have one or more additional layers 210, 212, such as adhesion promoting layers.

[0041] Figure 2BAlso shown is an active region 214 of a power transistor formed in the semiconductor substrate 104. The active region 214 includes one or more power transistor cells. Each power transistor cell includes a gate electrode 216 insulated from the semiconductor substrate 216 by a dielectric 218, a source or emitter region 220 of a first conductivity type, and a body region 222 of a second conductivity type, which provides a channel controlled by a voltage applied to the gate electrode 216. To simplify the illustration, the active region 214 includes one or more power transistor cells. Figure 2B A power transistor cell is shown in FIG. Each gate electrode 216 may be disposed in a gate trench 224 formed in the semiconductor substrate 104 and may or may not include a field electrode 226 under and insulated from the gate electrode 216. Figure 2B In the illustrated embodiment, the power transistor is a vertical device having a drift region 228 between a body region 222 and the back side of the semiconductor substrate 104, which forms the drain or collector region of the power transistor. A metal body 230, such as a die pad of a lead frame, a metal block, a metalized surface of a substrate, is attached to the back side of the semiconductor substrate 104 by a die attach material 232 to form a drain / collector terminal of the semiconductor device 200. The source / emitter terminal is on the opposite side of the device 200 and is formed in part by a metal pad 102 having a thinner inner region 106 and a thicker peripheral region 108, and an interconnect plate 206 attached to the thinner region 106 of the metal pad 102. In one embodiment, the metal pad 102 having a bank-like configuration is a Cu pad, and the interconnect plate 207 is a Cu clip. The power transistor may alternatively have a planar gate electrode insulated from the front side of the semiconductor substrate 104 and / or may be a lateral device rather than a vertical device.

[0042] Figure 2C Shows something like Figure 2A-2B 3. The semiconductor device 300 of the device 200 shown in FIG. 2 is a semiconductor device 300 of the device 200 shown in FIG. 2, but the semiconductor die 302 is attached to the inner region 106 of the metal pad 102 having the bank configuration instead of an interconnect board. The semiconductor die 302 may have a metallized surface 304 attached to the inner region 106 of the metal pad 102 by the die attach material 208, and one or more die pads 306 on opposite sides of the semiconductor die 302. A passivation layer 308 may be applied to the side of the semiconductor die 302, and electrical conductors 310 may be attached to the die pads 306 to provide electrical connections to different terminals of the die 302. In one embodiment, the lower die 104 and the upper die 302 are power transistor dies electrically connected in a half-bridge configuration via the metal pad 102 having the bank configuration.

[0043] FIG. 3A to FIG. 3C It shows the formation of FIG. 2A to FIG. 2B The illustrated embodiment of metal pad 102 has a bank-like configuration.

[0044] Figure 3A A first patterned metal layer 400 is shown formed over semiconductor substrate 104. In one embodiment, first patterned metal layer 400 is a Cu layer formed by electrochemical deposition (ECD). First patterned metal layer 400 forms metal traces 402 and metal pad pedestals 404, 406, 408, 410.

[0045] Figure 3B A second patterned metal layer 412 is shown formed on the first patterned metal layer 400. In one embodiment, the second patterned metal layer 412 is a Cu layer formed by ECD. The second patterned metal layer 412 is formed where thicker metal is needed. This includes a first metal pad 414 / 102, where the second patterned metal layer 412 stacked on the first patterned metal layer 400 forms a thicker peripheral region 416 of the first metal pad 414 / 102. The first metal pad 414 / 102 also has a thinner inner region 418 formed only by the first patterned metal layer 400. The second patterned metal layer 412 can also be used to form other thick metal pads 420, 422, 424. The second patterned metal layers 400, 412 can be Cu layers as described above, or can be other types of metal layers such as Al, AlCu, Au, etc. The first and second patterned metal layers 400, 412 can include additional metal layers such as anti-oxidation layers, adhesion promotion layers, etc. In one embodiment, outer lateral edge 426 of second patterned metal layer 412 is spaced inwardly from outer lateral edge 428 of first patterned metal layer 400 by a distance d1, for example, about 5 μm, along one or more sides of first metal pad 414 / 102. Outer lateral edge 426 of second patterned metal layer 412 may alternatively be vertically aligned with outer lateral edge 428 of first patterned metal layer 400 along one or more sides of first metal pad 414 / 102.

[0046] Figure 3C An interconnect board 430 is shown attached to the thinner inner region 418 of the first metal pad 414 / 102. The interconnect board 430 may be attached to the inner region 418 of the first metal pad 414 / 102 by a die attach material (out of sight) such as solder, conductive glue, conductive tape, etc. An inner lateral edge 432 of the second patterned metal layer 412 may be spaced apart from a lateral edge 434 of the interconnect board 430 along one or more sides of the first metal pad 414 / 102 by a distance d2, e.g., about 100 μm.

[0047] As previously described herein, the peripheral region 416 of the first metal pad 414 / 102 has a bank-like shape. Figure 3BAs shown, the bank-like shape can be continuous and uninterrupted over the entire periphery of the first metal pad 414 / 102. Alternatively, the second patterned metal layer 412 can be constructed so that the peripheral area 416 of the first metal pad 414 / 102 is divided into a plurality of segments, wherein adjacent segments of the segments are laterally separated by a certain gap. Such gaps are formed by Figure 3B Thus, the bank-like shape of peripheral region 416 of first metal pad 414 / 102 may be continuous and uninterrupted along all sides of first metal pad 414 / 102, along some but not all sides of first metal pad 414 / 102, may have breaks between wall segments, or have any other type of desired shape or configuration.

[0048] Figure 4 Shown attached to FIG. 3A to FIG. 3C 4. A side perspective view of an embodiment of an interconnect plate 430 with a thinner inner region 416 of a first metal pad 414 / 102 is shown in FIG. According to this embodiment, the interconnect plate 430 is a metal clip, such as a Cu clip. The metal clip has a first region 436 extending along a first level L1, a second region 438 extending along a second level L2 above the first level L1, and an intermediate region 440 connecting the first and second regions 436, 438 and providing a transition between the first and second levels L1, L2. The first region 436 of the metal clip 430 is attached to the thinner inner region 418 of the first metal pad 414 / 102, and the intermediate region 440 of the metal clip 430 provides a height transition so that the metal clip 430 does not contact the peripheral region 416 of the first metal pad 414 / 102.

[0049] Figures 5 to 7 Corresponding cross-sectional views of other embodiments of semiconductor devices are shown, each having a different chip pad-to-interconnect interface.

[0050] exist Figure 5 , the peripheral region 108 of the metal pad 102 having the bank-like configuration is thicker than the die attach material 208 used to attach the interconnect board 206 (or another semiconductor die) to the thinner inner region 106 of the metal pad 102. According to an embodiment, when placing the first interconnect board 206 (or another semiconductor die), the peripheral region 108 of the metal pad 102 may be used as a guide to ensure that the interconnect board 206 (or another semiconductor die) properly lands on the thinner inner region 106 of the metal pad 102. For example, after depositing the die attach material 208 on the inner region 106 of the metal pad 102, the interconnect board 206 (or another semiconductor die) may be placed in contact with the die attach material 208 while aligning the interconnect board 206 (or another semiconductor die) with the metal pad 102 using the peripheral region 108 of the metal pad 102.

[0051] exist Figure 6 In the embodiment, the die attach material 208 is thicker than the peripheral region 108 of the metal pad 102 having the bank-like configuration, so that the bottom surface 500 of the first interconnect board 206 (or alternatively, the bottom surface of another semiconductor die) is disposed above the top surface 502 of the peripheral region 108 of the metal pad 102. According to this embodiment, the properties of the die attach material 208 allow the interconnect board 206 (or another semiconductor die) to be automatically centered on the thinner inner region 106 of the metal pad 102 having the bank-like configuration. For example, after the die attach material 208 is deposited on the inner region 206 of the metal pad 102, the interconnect board 206 (or another semiconductor die) can be placed in contact with the die attach material 208 while aligning the interconnect board 206 (or another semiconductor die) with the metal pad 102 using the surface tension of the die attach material 208. The interconnect board 206 (or another semiconductor die) is soft landed on the thinner inner region 106 of the metal pad 102, which means that the interconnect board 206 (or another semiconductor die) is not pressed into the die attach material 208, but is gently placed on the die attach material 208. In the case of glue as the die attach material 208, the surface tension of the glue centers the interconnect board 206 (or another semiconductor die). This method produces a rough alignment of the interconnect board 206 (or another semiconductor die) relative to the metal pad 102 with a bank-like configuration.

[0052] exist Figure 7 , the bottom surface 500 of the interconnect board 206 has one or more structures 504 disposed laterally inwardly from the peripheral region 108 of the metal pad 102 having the bank-like configuration and extending vertically toward the inner region 106 of the metal pad 102. The one or more structures 504 may be formed, for example, by embossing and assist in the alignment of the interconnect board 206 with the inner region 106 of the metal pad 102 during the landing process. For example, after depositing the die attach material 208 on the inner region 106 of the metal pad 102, the interconnect board 206 may be placed in contact with the die attach material 208 such that the one or more features 504 at the bottom surface 500 of the interconnect board 206 extend vertically toward the inner region 106 of the metal pad 102 and are disposed laterally inwardly from the peripheral region 108 of the metal pad 102 to align the interconnect board 206 with the metal pad 102.

[0053] Figure 1 , Figure 2A-2B , Figures 3A-3C and Figure 5-7The semiconductor device embodiment shown shows a metal pad having a thinner inner region and a thicker peripheral region, and an interconnect plate (or another semiconductor die) attached to the thinner inner region of the metal pad. This is done for ease of illustration only. In general, the power transistor included in the semiconductor device described herein may have one or more output channels or phases for delivering current to a load. In the case of a single output channel, the semiconductor device is a single-phase device. In the case of multiple (more than one) output channels, the semiconductor device is a multi-phase device such as a multi-phase voltage regulator.

[0054] The power transistor included in each semiconductor device described herein has an individual active area for each output channel and a separate dike-shaped metal pad of the type described herein for each output channel. Typically, for a power transistor with N output channels (where N is an integer greater than or equal to 1), the corresponding semiconductor device has N separate active areas and N dike-shaped metal pads of the type described herein-one for each output channel / active area of ​​the device. One or more interconnection plates may be attached to each of the N dike-shaped metal pads. In other words, the active area of ​​each channel depends on the Ron (on-resistance) requirement of the channel. In this way, depending on the size of the active area of ​​each channel, interconnection plates of different sizes may be used. For example, a power transistor may have 1 larger active area and 3 smaller active areas. A smaller interconnection plate may be used for 3 smaller active areas, and 1 larger interconnection plate or a plurality of smaller interconnection plates may be used for a larger active area.

[0055] Figure 8 A top view of an embodiment of a semiconductor device 600 having four separate active regions and therefore four output channels is shown. Each active region is substantially covered by a separate bank-shaped metal pad 102 of the type described herein. Each bank-shaped metal pad 102 is electrically connected to a source or emitter region in the underlying active region and has a thinner inner region 106 laterally surrounded by a thicker peripheral region 108. One or more interconnect boards or another semiconductor die are attached to the inner region 106 of each bank-shaped metal pad 102 by a die attach material. The interconnect boards / additional semiconductor dies are not provided in the embodiment of the present invention. Figure 8 1 is shown so that the details of the bank-shaped metal pad 102 are clear.

[0056] 9A to 9E Respective cross-sectional views are shown during different stages of fabricating a semiconductor device having one or more bank-shaped metal pads of the kind described herein.

[0057] Fig. 9AA barrier layer 700, such as TiW, formed on a semiconductor substrate 702, and a Cu seed layer 704 formed on the barrier layer 700 are shown. The barrier layer 700 and the Cu seed layer 704 may be deposited, for example, by physical vapor deposition (PVD). The barrier layer 700 and the Cu seed layer 704 may be relatively thin, for example, each about 300 nm thick.

[0058] Fig. 9B A first Cu layer 706 is shown formed on the Cu seed layer 704. The first Cu layer 706 may be formed by ECD using a photoresist mask 708 to pattern the deposited Cu into a base 708 for a metal pad and a metal trace 710 for signal routing. In one embodiment, the first Cu layer 706 has a thickness in a range of about 5 μm to about 20 μm, for example, a thickness in a range of about 5 μm to about 10 μm.

[0059] Fig. 9C The inner region / base 708 of the first Cu layer 706 corresponding to the bank-shaped metal pad patterned into the first Cu layer 706 protected by a mask 712 (e.g., resist), and a portion of the metal trace 710 are shown. The mask 712 prevents Cu from being subsequently deposited on the first Cu layer 706 in the masked area. The second Cu layer 714 is then deposited on the portion of the first Cu layer 706 not protected by the mask 712 to form the peripheral region 108 of the bank-shaped metal pad 102, and to thicken other pads (if necessary). The inner region 106 of the bank-shaped metal pad 102 is formed by the portion of the first Cu layer 706 protected by the mask 712 during the deposition of the second Cu layer 714. The same mask can be used to form two Cu layers 706, 714, wherein portions of the mask are removed after the first Cu layer 706 is deposited to form the second Cu layer 714 in the desired area. In one embodiment, the second Cu layer 714 has a thickness in a range of about 10 μm to about 20 μm, for example, in a range of about 10 μm to about 15 μm.

[0060] Fig.9D The structure is shown after removing the mask 708 / 712 used for Cu deposition, after forming a new mask 716 (e.g., an imide mask) covering a portion of the periphery of the metal trace 710 and the metal pad 708 / 106, and after a protective layer 718 such as a passivation is formed on the exposed portion of the second Cu layer 714. In the case of Ag etching, the exposed portion of the second Cu layer 714 is protected by the protective layer 718.

[0061] Fig.9EThe structure is shown after an interconnect plate 206 such as a metal clip or metal block or another semiconductor die is attached to the thinner inner region 708 / 106 of the bank-shaped metal pad 102, after a conductor 720 such as a wire bump, a pillar, a vertical (cut) bond wire is attached to the other of the bond pads 708 that do not have a bank-shaped configuration, and after a metal body 230 such as a die pad of a lead frame, a metal block, a metalized surface of a substrate is attached to the back side of the semiconductor substrate 104. A die attach material 208, 232 such as solder, conductive glue, conductive tape, etc. may be used to facilitate some or all of the attachment operations. Additional layers 212, 304, 722 such as adhesion promoting layers may be used in conjunction with the die attach material 208, 232.

[0062] FIG. 10A to FIG. 10C Respective cross-sectional views are shown during different stages of fabricating a semiconductor device having one or more bank-shaped metal pads of the kind described herein according to another embodiment.

[0063] Fig. 10A A barrier layer 800 such as TiW is shown formed on a semiconductor substrate 802, a Cu layer 804 formed on the barrier layer 800, and an optional silver or aluminum layer 806 formed on the Cu layer 804. In one embodiment, the barrier layer 800 is relatively thin, such as about 300 nm thick, and the Cu layer 804 is relatively thick, such as at least 10 μm or at least 20 μm thick. In the case where the silver or aluminum layer 806 is deposited on the Cu layer 804, the optional layer 806 is thinner than the Cu layer 804, such as about 200 nm in the case of Ag, or about 50 nm in the case of Al.

[0064] Fig. 10BA Cu layer 804 is shown, which is patterned, for example, by photolithography and etching to form metal pads and metal trace structures 808, 810, 812 in the Cu layer 804. The patterning process may include, for example, Ag or Al etching using dilute hydrofluoric acid, followed by Cu etching, for example, using H3PO4 or H2O2, and then TiW etching, for example, using H2O2. After the Cu layer patterning process, a mask 814, such as an imide mask, is formed, which covers the metal trace structure 812, the metal pad structure 810, which will have a uniform thickness, and the periphery of the bank-like metal pad structure 808. Then, for example, the exposed portion of the Cu layer 804 that is not protected by the mask 814 is etched using H3PO4 or H2O2 to form a metal pad 102 with a bank-like configuration, which has a thinner inner region 106 and a thicker peripheral region 108. The thickness t_ec of the etched portion of the Cu layer 804 may be in the range of 5 μm to 10 μm. The peripheral region 108 of the banked metal pad 102 is formed by the portion of the Cu layer 804 that is protected by the mask 814 during the etching of the Cu layer 804. An interconnect board such as a metal clip or metal block, or another semiconductor die may then be attached to the thinner inner region 106 of the banked metal pad 102 as previously described herein.

[0065] Terms such as "first", "second", etc. are used to describe various elements, regions, parts, etc., and are not intended to be limiting. Throughout the specification, similar terms refer to similar elements.

[0066] As used herein, the terms "having", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0067] It should be understood that the features of the various embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0068] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: Semiconductor substrate; a power transistor formed in the semiconductor substrate, the power transistor comprising an active region in which one or more power transistor cells are formed; a first metal pad formed over the semiconductor substrate and substantially covering all of the active area of ​​the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of ​​the power transistor, the first metal pad comprising an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; as well as A first interconnect board or semiconductor die is attached to the inner region of the first metal pad by a die attach material on a side of the inner region facing away from the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein The inner region of the first metal pad has a thickness in a range of 5 μm to 10 μm, wherein the outer region of the first metal pad has a thickness of 20 μm or more.

3. The semiconductor device according to claim 2, wherein: The semiconductor substrate has a thickness of 60 μm or less.

4. The semiconductor device according to claim 1, wherein: The peripheral region of the first metal pad is thicker than the die attach material.

5. The semiconductor device according to claim 1, wherein The die attach material is thicker than the peripheral region of the first metal pad such that a bottom surface of the first interconnect board or the semiconductor die is disposed above a top surface of the peripheral region of the first metal pad.

6. The semiconductor device according to claim 1, wherein The bottom surface of the first interconnect board has one or more structures disposed laterally inward from the peripheral region of the first metal pad and extending vertically toward the interior region of the first metal pad.

7. The semiconductor device according to claim 1, wherein The peripheral region of the first metal pad is divided into a plurality of segments, and wherein adjacent ones of the segments are laterally separated by gaps.

8. The semiconductor device according to claim 1, wherein The power transistor comprises a plurality of output channels, each output channel being configured to deliver current to a load, wherein the power transistor comprises an individual active region for each output channel, and wherein the first metal pad substantially covers a first one of the active regions of the power transistor.

9. The semiconductor device according to claim 8, further comprising: a plurality of additional metal pads formed over the semiconductor substrate, each additional metal pad substantially covering a corresponding one of the active regions of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active region substantially covered by the metal pad, each metal pad comprising an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; as well as A plurality of additional interconnect boards, each additional interconnect board being attached to the inner region of a corresponding one of the additional metal pads by a die attach material at a side of the inner region facing away from the semiconductor substrate. 10 . The semiconductor device of claim 1 , further comprising one or more logic devices integrated in a region of the semiconductor substrate different from the power transistor.

11. The semiconductor device according to claim 1, wherein The first metal pad is a Cu pad, and wherein the first interconnect plate is a Cu clip.

12. A method for manufacturing a semiconductor device, the method comprising: forming a power transistor in a semiconductor substrate, the power transistor comprising an active region in which one or more power transistor cells are formed; forming a first metal pad over the semiconductor substrate, and the first metal pad substantially covers the entire active area of ​​the power transistor, the first metal pad is electrically connected to a source or emitter region in the active area of ​​the power transistor, the first metal pad comprises an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; as well as A first interconnect board or a semiconductor die is attached to the inner region of the first metal pad by a die attach material at a side of the inner region facing away from the semiconductor substrate.

13. The method according to claim 12, wherein: Forming the first metal pad includes: Depositing a first Cu layer over the semiconductor substrate, wherein the first Cu layer substantially covers all of the active areas of the power transistor; forming a mask on a portion of the first Cu layer corresponding to the inner region of the first metal pad, the mask being configured to prevent Cu deposition; and A second Cu layer is deposited on portions of the first Cu layer not protected by the mask to form the peripheral region of the first metal pad, the inner region of the first metal pad being formed by the portions of the first Cu layer protected by the mask during deposition of the second Cu layer.

14. The method according to claim 13, wherein: The first Cu layer has a thickness in the range of 5 μm to 10 μm, and wherein the second Cu layer has a thickness in the range of 10 μm to 20 μm.

15. The method according to claim 12, wherein: Forming the first metal pad includes: Depositing a Cu layer over the semiconductor substrate, the Cu layer substantially covering all of the active area of ​​the power transistor; forming a mask on a portion of the Cu layer corresponding to the peripheral region of the first metal pad, the mask being configured to prevent Cu etching; and Portions of the Cu layer not protected by the mask are etched to form the inner region of the first metal pad, the peripheral region of the first metal pad being formed by the portions of the Cu layer protected by the mask during etching of the Cu layer.

16. The method according to claim 15, wherein: The deposited Cu layer has a thickness of 20 μm or more, and wherein the thickness of the etched portion of the Cu layer is in a range of 5 μm to 10 μm.

17. The method according to claim 12, wherein: The peripheral region of the first metal pad is thicker than the die attach material, and wherein attaching the first interconnect board or the semiconductor die to the inner region of the first metal pad comprises: depositing the die attach material on the interior region of the first metal pad; and The first interconnect board is placed in contact with the die attach material while aligning the first interconnect board with the first metal pad using the peripheral region of the first metal pad.

18. The method according to claim 12, wherein: The die attach material is thicker than the peripheral region of the first metal pad, and wherein attaching the first interconnect board or the semiconductor die to the inner region of the first metal pad comprises: depositing the die attach material on the interior region of the first metal pad; and The first interconnect board is placed in contact with the die attach material while aligning the first interconnect board with the first metal pad using surface tension of the die attach material.

19. The method according to claim 12, wherein: The bottom surface of the first interconnect board has one or more structures disposed laterally inward from the peripheral region of the first metal pad, and wherein attaching the first interconnect board or the semiconductor die to the inner region of the first metal pad comprises: depositing the die attach material on the interior region of the first metal pad; and The first interconnect board is placed in contact with the die attach material such that the one or more features at the bottom surface of the first interconnect board extend vertically toward the interior region of the first metal pad and are laterally disposed inward from the peripheral region of the first metal pad to align the first interconnect board with the first metal pad.

20. The method according to claim 12, wherein: The power transistor comprises a plurality of output channels, each output channel being configured to deliver current to a load, wherein the power transistor comprises an individual active area for each output channel, and wherein the first metal pad substantially covers a first one of the active areas of the power transistor, the method further comprising: forming a plurality of additional metal pads over the semiconductor substrate, each additional metal pad substantially covering a corresponding one of the active regions of the power transistor, each additional metal pad being electrically connected to a source or emitter region in the active region substantially covered by the metal pad, each metal pad comprising an inner region laterally surrounded by a peripheral region, the peripheral region being thicker than the inner region; and Each of a plurality of additional interconnect boards is attached to the inner region of a corresponding one of the additional metal pads by a die attach material at a side of the inner region facing away from the semiconductor substrate.

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