Vfet standard cell architecture

Abstract

A cell architecture for a vertical field effect transistor (VFET) is provided. The cell architecture includes a top source / drain (S / D) contact structure having a square shape in a top view, a horizontal metal pattern formed on the top S / D contact structure and extending in a first direction, and a vertical metal pattern sending out an output signal of a logic circuit formed by the VFET. The cell architecture also includes a gate contact structure formed on a gate connection pattern connecting gates of the VFET, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.

Description

Technical Field

[0001] The apparatus, consistent with exemplary embodiments of the inventive concept, relates to a semiconductor cell architecture for a vertical field-effect transistor (VFET). Background Technology

[0002] Figures 1A-1D A portion of a related technology semiconductor cell architecture (hereinafter referred to as "cell architecture") is shown as viewed from different orientations. This cell architecture is provided to allow multiple VFETs on a semiconductor substrate SUB for use as... Figure 1A The two fin structures F1 and F2 extending in the Y direction are shown to form a two-fin inverter. Figure 1E It shows the result of Figures 1A-1D The diagram shows a schematic of an inverter implemented using a modular architecture. Specifically, Figure 1A A top view of the unit architecture is shown. Figures 1B-1D They are shown respectively Figure 1A The diagram shows sectional views taken along lines A-A', B-B', and C-C' of the unit architecture. Note that, for the sake of brevity, [the text is incomplete]. Figures 1A-1D In some cases, some elements shown in one figure may not be shown in another figure.

[0003] Figures 1A-1D The inverter in the cell architecture is formed by two p-channel metal-oxide-semiconductor (PMOS) VFETs P1 and P2 arranged in the X direction, and two n-channel MOS (NMOS) VFETs N1 and N2 also arranged in the X direction (i.e., the cell width direction) and respectively disposed below the two PMOS VFETs in the Y direction (i.e., the cell height direction). These four VFETs are formed on or around corresponding fins F11, F12, F21, and F22, which are formed on two fin structures F1 and F2 extending in the Y direction and arranged side-by-side in the X direction. In the following text, for the sake of brevity, PMOS VFETs and NMOS VFETs are referred to as PMOS and NMOS, respectively.

[0004] Specifically, regarding Figure 1B The PMOS P1 shown has a bottom source / drain (S / D) region RX1 located at the lower part of fin F11, and a top S / D region T1 formed on or around the upper part of fin F11. Furthermore, a gate G1 is formed between the top S / D region T1 and the bottom S / D region RX1, surrounding the middle portion of fin F11. Regarding... Figure 1BThe shown NMOS N1, a bottom S / D region RX2 is provided at a lower portion of the fin F12, a top S / D region T2 is formed on or around an upper portion of the fin F12. Further, a gate G2 is formed between the top S / D region T2 and the bottom S / D region RX2 in a form of surrounding a middle portion of the fin F12. Regarding Figure 1C The shown PMOS P2, a bottom S / D region RX1 is provided at a lower portion of the fin F21, a top S / D region T3 is formed on or around an upper portion of the fin F21. Further, a gate G3 is formed between the top S / D region T3 and the bottom S / D region RX1 in a form of surrounding a middle portion of the fin F21. Regarding Figure 1C The shown NMOS N2, a bottom S / D region RX2 is provided at a lower portion of the fin F22, a top S / D region T4 is formed on or around an upper portion of the fin F22. Further, a gate G4 is formed between the top S / D region T4 and the bottom S / D region RX2 in a form of surrounding a middle portion of the fin F22.

[0005] Referring to Figure 1A and Figure 1B a gate connection pattern PB is formed between the four VFETs to connect the gates G1 to G4 of the four VFETs. On the gate connection pattern PB, a gate contact structure CB is formed, on the gate contact structure CB, a metal pattern M13 is formed. The metal pattern M13 can be connected to the gate contact structure CB through a via V05 formed between the metal pattern M13 and the gate contact structure CB. An input signal V in is input to this cell architecture through the metal pattern M13.

[0006] Referring to Figure 1B the top S / D region T1 of the PMOS P1 and the top S / D region T2 of the NMOS N1 are connected to a top S / D contact structure CA1 and a top S / D contact structure CA2 formed thereon, respectively. Referring to Figures 1B-1D, the top S / D region T3 of PMOS P2 is connected to the top S / D contact structure CA1 to which the top S / D region T1 of PMOS P1 is connected. Thus, the top S / D region T1 of PMOS P1 and the top S / D region T3 of PMOS P2 are connected to the same top S / D contact structure CA1, which extends in a bar shape in the X direction in the top view of the cell architecture. Similarly, the top S / D region T4 of NMOS N2 is connected to the top S / D contact structure CA2 to which the top S / D region T2 of NMOS N1 is connected. Thus, the top S / D region T2 of NMOS N1 and the top S / D region T4 of NMOS N2 are connected to the same top S / D contact structure CA2, which extends in a bar shape in the X direction in the top view of the cell architecture. The two respective common top S / D contact structures CA1 and CA2 are connected to another metal pattern M14 through vias V06 and V07, respectively. The output signal V out is sent out through the metal pattern M14.

[0007] Further, with reference to Figures 1A-1C , the bottom S / D regions RX1 and RX2 of the VFETs are connected to the power rail Vdd and the ground rail Vss through the power contact structures CR1 to CR4 and the respective vias V01 to V04, respectively.

[0008] In Figures 1B to 1D , the top S / D regions, the bottom S / D regions, the top S / D contact structures, the power contact structures, the vias and the metal patterns can be insulated from each other by an interlayer structure IL such as a dielectric layer, the bottom S / D regions RX1 and RX2 are surrounded by or isolated from each other by a shallow trench isolation region STI on the semiconductor substrate SUB. In the following, for brevity, the description of the interlayer structure IL and the shallow trench isolation region STI will be omitted when describing the respective cell architectures.

[0009] The above cell architecture can also be used to constitute more complex logic circuits such as a two-finned AND OR INVERT (AOI) 22 circuit by including more VFETs and forming corresponding gate connection patterns, gate contact structures, top S / D contact structures and metal patterns for internal wiring and power connections.

[0010] Figures 2A-2C Parts of a related art cell architecture provided for an AOI 22 circuit are shown. In Figure 2D , a schematic diagram equivalent to the AOI 22 circuit is shown.

[0011] With reference to Figure 2A , the cell architecture provides a plurality of equally spaced fin structures F1 to F8, eight PMOS and eight NMOS Figure 2DThe number of VFETs in the schematic diagram is doubled) can be formed along the plurality of equally-spaced fin structures F1-F8. Figure 2A Bottom S / D regions RX1, RX2, and RX3, gate connection pattern PB, gate contact structures CB1, CB2 through CB4, top S / D contact structures CA1 and CA2, power contact structures CR1 through CR3, vias V01 through V06, metal patterns M13, …, M15 through M17 for input signals V in and output signals V out of AOI22 circuit, and metal patterns M11 and M12 for connection to power rail Vdd and ground rail Vss are also shown. Gate contact structures CB1 through CB4 connect corresponding gates to corresponding vertical metal patterns M13 through M16 through corresponding vias V01 through V04. As shown in a cross-sectional view taken along line D-D' of the unit architecture as Figure 2A Figure 2B At least one of vertical metal patterns M13 through M16 is further connected to at least one uppermost metal pattern M21 through via V11. One of gate input signals V in of AOI22 circuit is input to metal pattern M21.

[0012] Figure 2A A pair of top S / D contact structures CA1 and CA2 connected to metal pattern M17 for internal routing are also shown. Specifically, as shown in a cross-sectional view taken along line E-E' of the unit architecture as Figure 2A Figure 2A Figure 2C V06 is further connected to metal pattern M22 through via V12.

[0013] ​​​As described above, a related art cell architecture for a logic circuit composed of VFETs uses a top S / D contact structure having a bar shape extending in an X direction for internal wiring, and thus, it is difficult to reduce a cell height and / or a cell width of the cell architecture. In addition, the related art cell architecture has limitations in reducing an overall size thereof in consideration of widths of a gate contact structure CB, a top S / D contact structure, and a power contact structure required in a standard cell architecture, and spaces between the contact structures. For example, if the top S / D contact structure is to be reduced, it is required to secure sufficient spaces by surrounding the top S / D contact structure, which makes the cell architecture more complicated. In addition, it is difficult to reduce an area of the top S / D contact structure on which a via is to be overlapped to connect the top S / D contact structure to a metal pattern due to a sufficient area required to form the via on the top S / D contact structure. Thus, in order to reduce the cell height and the cell width of the cell architecture for the VFET logic circuit without sacrificing an overall space of the cell architecture, a different structural improvement is required.

[0014] The information disclosed in this Background section is for the purpose of generally presenting the context of the disclosure. The information described herein is not prior art to the claimed disclosure and was not publicly known at the time of filing this disclosure. SUMMARY

[0015] Various embodiments of the inventive concept are directed to a standard cell architecture for a logic circuit formed of vertical field effect transistors (VFETs).

[0016] The embodiments provide an improved cell architecture including a square top source / drain (S / D) contact structure for internal wiring between VFETs and a super via for a gate connection, thereby providing a cell architecture having a reduced size.

[0017] According to an embodiment, a cell architecture can include a plurality of VFETs formed on a substrate to constitute a logic circuit, a first top S / D contact structure formed on a first top S / D region of a first VFET and connected to a first horizontal metal pattern formed thereon and extending in an X direction of the cell architecture to connect an output signal output from the first top S / D region of the logic circuit to a first vertical metal pattern, a second top S / D contact structure formed on a second top S / D region of a second VFET and connected to a second horizontal metal pattern formed thereon and extending in the X direction to connect an output signal output from the second top S / D region of the logic circuit to the first vertical metal pattern, and a gate contact structure formed on a gate connection pattern connected to respective gates of the first VFET and the second VFET, the gate contact structure being connected to an input signal of the logic circuit through a super via (SPV).

[0018] In the above embodiments, the first VFET and the second VFET can be formed along a first fin structure extending in a Y direction of the cell architecture, both the first top S / D contact structure and the second top S / D contact structure can have a substantially square shape in a top view of the cell architecture.

[0019] According to an embodiment, there is also provided a cell architecture, which can include: a first type of top S / D contact structure formed on top S / D regions of at least two of VFETs constituting a logic circuit, respectively; at least one gate contact structure connected to at least one gate connection pattern connecting gates of the at least two of the VFETs to each other; a first metal pattern extending in a Y direction and configured to receive one or more input signals of the logic circuit and send out an output signal of the logic circuit; and a second metal pattern extending in an X direction and provided for internal wiring of the logic circuit by connecting at least two of the first type of top S / D contact structure to one of the first metal pattern to send out the output signal.

[0020] In the above embodiments, the at least two of the first type of top S / D contact structure can have a substantially square shape in a top view of the cell architecture, the first metal pattern can be formed at a higher level than the second metal pattern, the second metal pattern being formed at a higher level than the first type of top S / D contact structure.

[0021] According to an embodiment, there is also provided a cell architecture, which can include: a top source / drain (S / D) contact structure formed on top S / D regions of at least two of vertical field effect transistors (VFETs) constituting a logic circuit, respectively; at least one gate contact structure connected to at least one gate connection pattern connecting gates of the at least two of the VFETs to each other; a first metal pattern extending in a Y direction and configured to receive one or more input signals of the logic circuit and send out an output signal of the logic circuit; a second metal pattern extending in an X direction and provided for internal wiring of the logic circuit by connecting at least two of the top S / D contact structure to one of the first metal pattern to send out the output signal; and at least one super-passage formed on the gate contact structure and connected to another of the first metal pattern to receive one of the input signals.

[0022] In the above embodiments, the first metal pattern can be formed at a higher level than the second metal pattern, the second metal pattern being formed at a higher level than the top S / D contact structure. BRIEF DESCRIPTION OF DRAWINGS

[0023] The above and further aspects of the present inventive concept will become more apparent when detailed description of example embodiments of the present inventive concept, with reference to the annexed drawings, is made. In the drawings:

[0024] Figures 1A-1D Portions of a related art cell architecture provided for a two-fin inverter are shown;

[0025] Figure 1E A schematic diagram of an inverter implemented by Figures 1A-1D the cell architecture shown;

[0026] Figures 2A-2C Portions of a related art cell architecture provided for an AOI22 circuit are shown;

[0027] Figure 2D A schematic diagram equivalent to the AOI22 circuit is shown;

[0028] Figures 3A-3D Portions of a cell architecture provided for a two-fin inverter according to an embodiment are shown;

[0029] Figures 4A-4C Portions of a cell architecture provided for a two-fin inverter according to another embodiment are shown;

[0030] Figures 5A-5C Portions of a cell architecture provided for a NAND3 circuit according to an embodiment are shown;

[0031] Figure 5D A schematic diagram of a NAND3 circuit implemented by Figures 5A-5C the cell architecture;

[0032] Figures 6A-6C Portions of a cell architecture provided for a two-fin AOI22 circuit according to an embodiment are shown;

[0033] Figures 7A-7C Portions of a cell architecture provided for a one-fin AOI22 circuit according to an embodiment are shown;

[0034] Figures 8A-8E Portions of a cell architecture provided for a one-fin AOI22 circuit according to another embodiment are shown;

[0035] Figure 8F An alternative structure of Figure 8B is shown; and

[0036] Figure 9 A mobile device applying the cell architecture of the above embodiments is shown. DETAILED DESCRIPTION

[0037] Various embodiments of the inventive concept will be described more fully below with reference to the accompanying drawings. These embodiments are merely exemplary and can be embodied in many different forms and should not be interpreted as limiting the inventive concept. Rather, these embodiments are provided as illustrative examples so that a thorough and complete disclosure of the inventive concept will be achieved and fully conveyed to those skilled in the art. In the drawings, the sizes and relative sizes of the various layers and regions shown in the figures can be exaggerated for clarity and clarity, and thus the drawings are not necessarily drawn to scale, and some features can be exaggerated to show details of particular components or elements. Therefore, the specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as representative of the various ways in which the embodiments can be used to teach those skilled in the art various ways of using the embodiments.

[0038] It is not excluded that an embodiment provided herein is associated with one or more features of another example or another embodiment provided herein or not provided herein but consistent with the inventive concept. For example, even if the content described in a particular embodiment is not described in a different embodiment, it can be understood to be related to or combined with the different embodiment unless otherwise mentioned in its description.

[0039] For the purpose of description hereinafter, the terms "upper", "lower", "top", "bottom", "left" and "right" and their derivatives can be related to the disclosed structure as they are oriented in the drawings based on the context. The same reference numerals in different drawings can refer to the same structural components or elements thereof.

[0040] It will be understood that when an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, directly connected or coupled to the other element or layer, or there can be an intervening element or layer. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0041] The term "and / or", as used herein when used in a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and each of the items in the list. Expressions such as "at least one of A, B or C" when following a list of items, modify the entire list of items and does not modify the individual items of the list. Thus, for example, "at least one of A, B or C" and "A, B and / or C" both mean A, B, C or any combination thereof.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0043] Figures 3A-3D Portions of a cell architecture are shown as seen in different directions according to an embodiment. Like the cell architecture shown Figures 1A-1D , a cell architecture according to the present embodiment can be provided to use Figure 3A The two fin structures F1 and F2 shown constitute a logic circuit such as a two-fin inverter formed by a plurality of VFETs. By Figures 3A-3D The two-fin inverter implemented by the cell architecture of Figure 1E is represented by the same schematic diagram as the two-fin inverter shown. Figure 3A A top view of the cell architecture is shown, Figures 3B-3D Cross-sectional views of the cell architecture of Figure 3A taken along lines F-F', G-G', and H-H' are shown, respectively. Note, however, that some elements shown in any one of Figures 3A-3D may not be visible in at least another one of Figures 3A-3D for the sake of brevity.

[0044] Because the VFETs forming the two-fin inverter in the cell architecture of the present embodiment have the same or substantially the same structure as compared to the VFETs included in the related art cell architecture of Figures 1A-1D , redundant descriptions are omitted here. However, the cell architecture according to the present embodiment differs from the related art cell architecture in at least the following aspects which will be described in detail below: the structural shape of the top S / D contact structures, the metal pattern formed on the top S / D contact structures through which the input signal of the inverter is received and the output signal of the inverter is sent out, and the via structure formed on the gate contact structure.

[0045] Unlike the cell architecture shown in Figures 1A-1D , the cell architecture according to the present embodiment provides top S / D contact structures CA1 to CA4 on the top S / D regions T1 to T4 of PMOS P1, NMOS N1, PMOS P2, and NMOS N2, respectively, as shown in Figures 3A-3D . Moreover, these top S / D contact structures CA1 to CA4 have a square shape in a top view of the cell architecture, as shown in Figures 3A-3D .

[0046] Furthermore, for connecting the square-top S / D contact structure CA1 of PMOS P1 and the square-top S / D contact structure CA3 of PMOS P2, a horizontal metal pattern M13 is formed and connected to the two square-top S / D contact structures CA1 and CA3 through respective vias V03 and V07, as shown. Figures 3A-3D Meanwhile, for connecting the square-top S / D contact structure CA2 of NMOS N1 and the square-top S / D contact structure CA4 of NMOS N2, another horizontal metal pattern M14 is formed and connected to the two square-top S / D contact structures CA2 and CA4 through respective vias V04 and V08, as shown. Figures 3A-3D These two horizontal metal patterns M13 and M14 extend in parallel in the X direction.

[0047] Referring to Figures 3A-3C , the bottom S / D regions RX1 and RX2 of the VFET are connected to the power rail Vdd and the ground rail Vss through the power contact structures CR1, CR2, CR3 and CR4 and respective vias V01, V02, V05 and V06, respectively.

[0048] Although the corresponding top S / D region T1 of PMOS P1 and the corresponding top S / D region T3 of PMOS P2 shown in the related art cell architecture of Figures 1A-1D are connected to each other through a bar-top S / D contact structure CA1, in Figure 3A and 3D , the top S / D region T1 of PMOS P1 and the top S / D region T3 of PMOS P2 are connected to each other through respective square-top S / D contact structures CA1 and CA3 and a horizontal metal pattern M13 connected to the respective square-top S / D contact structures CA1 and CA3 via respective vias V03 and V07. In a similar manner, the top S / D region T2 of NMOS N1 and the top S / D region T4 of NMOS N2 are connected to each other through respective square-top S / D contact structures CA2 and CA4 and a horizontal metal pattern M14 connected to the respective square-top S / D contact structures CA2 and CA4 via respective vias V04 and V08.

[0049] The metal pattern M13 connects the top S / D region T1 of PMOS P1 to the top S / D region T3 of PMOS P2 for sending out the output signal V out of the inverter, and the metal pattern M14 connects the top S / D region T2 of NMOS N1 to the top S / D region T4 of NMOS N2 for sending out the same output signal V outTherefore, these two metal patterns M13 and M14 can be referred to as internal wiring metal patterns. These two horizontal metal patterns M13 and M14 are connected to each other via vertical metal pattern M22 through paths V11 and V12 formed thereon, respectively. The vertical metal pattern M22, extending in the Y direction, can be connected to external circuitry, where the inverter's output signal V... out It is sent to the external circuit.

[0050] and Figures 1A-1D Compared to the strip-shaped top S / D contact structures CA1 and CA2 in the related technology unit architecture shown, the square top S / D contact structures CA1 to CA4 can have a smaller width in the Y direction in the top view of the unit architecture. Therefore, the unit architecture according to this embodiment can achieve a unit architecture with a smaller unit height in the Y direction. Furthermore, because horizontal metal patterns M13 and M14 for internal wiring of logic circuits are used, the unit architecture according to this embodiment can provide additional wiring resources to construct more complex logic circuits.

[0051] The top view shape of the top S / D contact structures CA1 to CA4 used in the cell architecture according to this embodiment is not limited to a precise square. As long as the shape of these top S / D contact structures is small enough to help reduce the cell height of the cell architecture, a generally square shape is sufficient to form the top S / D contact structures CA1 to CA4 for the VFET cell under the inventive concept.

[0052] Now, referring to Figure 3A and Figure 3B A gate connection pattern PB is formed between PMOS P1, NMOS N1, PMOS P2, and NMOS N2 to connect their respective gates, and a gate contact structure CB is formed on the gate connection pattern PB. This structure of the gate connection pattern PB and the gate contact structure CB is similar to... Figures 1A-1D The cell architecture for the inverter shown is the same as those related to the technology shown. However, due to the square top S / D contact structures CA1 to CA4 formed on the top S / D regions T1 to T4 of the four VFETs, and the two horizontal metal patterns M13 and M14 formed on the square top S / D contact structures CA1 to CA4 through corresponding paths V03, V04, V07 and V08, the cell architecture for the inverter according to this embodiment provides a super-path SPV, and the vertical metal pattern M21 formed on the super-path SPV makes the input signal V of the inverter V in Input is given to the vertical metal pattern M21. This super-path SPV is configured to be higher than other paths such as V01 to V08 used in the cell architecture according to this embodiment. Furthermore, the super-path SPV is configured to be higher than those formed in the related art cell architecture. Figure 1BThe path V05 between the metal pattern M13 and the gate contact structure CB is higher.

[0053] Because a superpath SPV with a greater height in the Z direction than other paths is used, the cell architecture according to this embodiment can eliminate the need for metal patterns formed on or below other paths for connection to the power rail Vdd, ground rail Vss, or another circuit, thereby eliminating the need to ensure a minimum area or space for such metal patterns in the cell architecture.

[0054] exist Figures 3A-3D In the unit architecture, paths V03, V04, V07, and V08 are formed on top S / D contact structures CA1 to CA4, respectively, to connect these top S / D contact structures CA1 to CA4 to horizontal metal patterns M13 and M14. However, according to one embodiment, the top S / D contact structure CA1 and path V03 can be replaced by a higher top S / D contact structure that omits path V03. This embodiment using a higher top S / D contact structure can also be applied to top S / D contact structures CA2 and path V04, top S / D contact structures CA3 and path V07, top S / D contact structures CA4 and path V08, power contact structure CR1 and path V01, power contact structure CR2 and path V02, power contact structure CR3 and path V05, and power contact structure CR4 and path V06. Therefore, the cell architecture according to this embodiment does not require paths V03, V04, V07, V08, V01, V02, V05, and V06 to form a two-fin inverter composed of multiple VFETs, such as Figures 4A-4C As shown.

[0055] Figures 4A to 4C Corresponding to Figures 3B to 3D . Reference Figures 4A to 4C According to the structure of the unit architecture in this embodiment and Figures 3A-3D The structural difference in the cell architecture shown is that the top S / D contact structures CM1 to CM4 of PMOS P1, NMOS N1, PMOS P2, and NMOS N2 do not have features such as... Figures 3A-3D The corresponding paths V03, V04, V07, and V08 used in the unit architecture are connected to the horizontal metal patterns M13 and M14. Furthermore, the unit architecture according to this embodiment provides a way to connect without using, for example,... Figures 3A-3D In the case of the corresponding paths V01, V02, V05 and V06 used in the unit architecture, they are connected to the power contact structures CR1 to CR4 of the metal patterns M11 and M12, which connect the power contact structures CR1 to CR4 to the power rail Vdd and the ground rail Vss.

[0056] Because the top S / D contact structures CM1 to CM4 according to the present embodiment can replace the top S / D contact structures CA1 to CA4 and the corresponding vias V03, V04, V07, and V08 in Figures 3A-3D , each of the top S / D contact structures CM1 to CM4 becomes higher than the top S / D contact structures CA1 to CA4. For example, the height of the top S / D contact structure CM1 in the Z-direction is equal to the sum of the height of the top S / D contact structure CA1 and the via V03 formed on the top S / D contact structure CA1 in Figures 3A-3D . Similarly, the power contact structures CR1 and CR2 in the cell architecture of the present embodiment have a greater height than the power contact structures CR1 and CR2 in Figures 3A-3D . For example, the height of the power contact structure CR1 according to the present embodiment is equal to the sum of the height of the power contact structure CR1 and the corresponding via V01 formed on the power contact structure CR1 as shown in Figure 3B . By using these heightened top S / D contact structures CM1 to CM4 and power contact structures CR1 and CR2, the manufacturing process of the cell architecture can be simplified because no vias are formed during the manufacturing process.

[0057] However, like the cell architecture of Figures 3A-3D , the cell architecture of the present embodiment is also characterized in that the top S / D contact structures CM1 to CM4 have a square shape in a top view of the cell architecture and that horizontal metal patterns M13 and M14 extending in the X-direction are used to connect the top S / D contact structures CM1 to CM4 to the vertical metal pattern M22 through the vias V11 and V12 formed thereon, respectively. The vertical metal pattern M22 extending in the Y-direction can be connected to an external circuit to which the output signal V out of the inverter is sent. Furthermore, the cell architecture of the present embodiment also uses a super via SPV that connects the gate contact structure CB with the vertical metal pattern M21 so that the input signal V in of the inverter is input to the vertical metal pattern M21.

[0058] By using the square top S / D contact structures CM1 to CM4 and the super via SPV, the cell architecture according to the present embodiment is also capable of achieving a reduced cell architecture size.

[0059] Figures 5A-5C A portion of a cell architecture according to an embodiment is shown that provides for constructing a logic circuit, such as a NAND3 circuit formed from a plurality of VFETs. Figure 5D A schematic diagram of a NAND3 circuit implemented by the cell architecture of Figures 5A-5C is shown. Figure 5A A top view of the cell architecture of the NAND3 circuit is shown,Figure 5B and 5C partially illustrate Figure 5A cross-sectional views taken along lines I-I' and J-J' of the unit architecture of Figures 5A-5C However, note that some elements illustrated in any one of Figures 5A-5C may not be visible in at least another one of

[0060] Referring to Figure 5A , the unit architecture according to the present embodiment provides a plurality of equi-pitch fin structures F1-F6, Figure 5D three PMOS and three NMOS illustrated in the schematic diagram of the NAND3 circuit can be formed along the plurality of equi-pitch fin structures F1-F6.

[0061] Figure 5A Also illustrated are bottom S / D regions RX1, RX2 and RX3, gate connection pattern PB, gate contact structure CB1-CB3, top S / D contact structures CA1, CA2 and CA3, super-paths SPV1-SPV3 and paths V01, V02, V11 and V12, metal patterns M21-M24 for receiving input signals V in and sending out output signals V out of the NAND3 circuit, metal patterns M13 and M14 for internal wiring, and metal patterns M11 and M12 for connecting to power rail Vdd and ground rail Vss.

[0062] Referring to Figure 5B , the unit architecture according to the present embodiment provides a super-path structure 510 including a super-path SPV3 that receives one of the input signals V in of the NAND3 circuit, that is, a gate signal.

[0063] Figure 5C illustrates metal / path / contact structures 520 for internal wiring of the top S / D contact structure CA2 and sending out output signals V out of the NAND3 circuit in the unit architecture according to the present embodiment. Figure 5C The metal pattern M14 illustrated is also used for internal wiring between VFETs of the NAND3 circuit in the unit architecture according to the present embodiment.

[0064] Similar to the super-paths SPV for inverters as illustrated in Figure 3A and 3B , Figures 5A-5B the super-path SPV3 of the NAND3 circuit is formed between the gate contact structure CB3 (which is formed on the gate connection pattern PB) and the vertical metal pattern M23 (one of the input signals V inOne of them is input into the vertical metal pattern M23). Therefore, the height of the super-path SPV3 in the Z direction is as follows: Figure 5C In the metal / path / contact structure 520 shown, the sum of the heights of the passage V02, the metal pattern M14, and the passage V12 sequentially formed on the top S / D contact structure CA2 are the same or substantially the same.

[0065] picture Figure 3A and 3B The superpath SPV shown is the same as that used for inverters. Figure 5B The super-channel structure 510 can help reduce the cell height of the cell architecture by eliminating the minimum size required for the metal pattern, such as the metal pattern M14 included in the metal / channel / contact structure 520. Here, the minimum size of the metal pattern in the top view of the cell architecture includes the length of the upper surface of the metal pattern M14 in the Y direction.

[0066] Figures 6A-6C A portion of a cell architecture for constructing a logic circuit, such as a two-fin AOI22 circuit formed by a plurality of VFETs, is shown according to one embodiment. Except for the different cell architecture, this AOI22 circuit is equivalent to the one described above. Figures 2A-2D The AOI22 circuit is described. Figure 6A A top view of the cell architecture used in the AOI22 circuit is shown. Figure 6B and 6C They are shown respectively Figure 6A The section view taken along lines K-K' and L-L' of the unit architecture. However, note that for simplicity, in Figures 6A-6C Some of the elements shown in any of them may be Figures 6A-6C At least one of them cannot be seen in the other.

[0067] Reference Figure 6A The unit architecture according to this embodiment provides multiple equally pitched fin structures F1 to F8, and the eight PMOS and eight NMOS can be similar to Figure 2A Fins are formed along multiple equally spaced fin structures F1 to F8.

[0068] Figure 6A It also shows the bottom S / D regions RX1, RX2, and RX3; the gate connection pattern PB; the gate contact structures CB1 to CB4; the top S / D contact structures CA1 to CA10 and CA11; the super channels SPV1 to SPV4 and channels V01 to V08, V11, and V12; the metal patterns M13 and M14 for internal wiring; and the input signal V for receiving the AOI22 circuit. in And send out the output signal V of the AOI22 circuit. outmetal patterns M21-M25, metal patterns M11 and M12 for connecting to power rail Vdd and ground rail Vss.

[0069] Referring to Figure 6B , the cell architecture according to the present embodiment provides a super via structure 610 including a super via SPV4 that receives one of the input signals V in of the AOI 22 circuit.

[0070] Figure 6C The internal routing for the top S / D contact structures CA8 and sending out the output signals V out of the AOI 22 circuit in the cell architecture according to the present embodiment is shown in the metal / via / contact structure 620. Figure 6C The metal pattern M14 shown is also used for internal routing between the VFETs of the AOI 22 circuit in the cell architecture according to the present embodiment.

[0071] Similar to Figure 3A and 3B the super via for the inverter, Figures 6A-6B the super via SPV4 is formed between the gate contact structure CB4 (which is formed on the gate connection pattern PB) and the metal pattern M24 (to which one of the input signals V in of the AOI 22 circuit is input). Thus, the height of the super via SPV4 in the Z direction is the same as or substantially the same as the sum of the heights of the via V08, the metal pattern M14 and the via V12 that are sequentially formed on the top S / D contact structure CA8 in the metal / contact / via structure 620 as shown in Figure 6C . Like in the previous embodiments, the super via structure 610 should also help to reduce the cell height of the cell architecture.

[0072] In addition, Figures 6A-6C the cell architecture shown is characterized by two types of top S / D contact structures. The first type of top S / D contact structures includes the top S / D contact structures CA9 to CA11, and the second type of top S / D contact structures includes the top S / D contact structures CA1 to CA8. The first type of top S / D contact structures have a bar shape in a top view of the cell architecture and extend in the X and Y directions such that they can connect the corresponding VFETs to the power rail Vdd and the ground rail Vss through the metal patterns M11 and M12. However, the second type of top S / D contact structures for internal routing have a square shape in a top view of the cell architecture, which enables them to be connected to the VFETs through the metal patterns M21 to M25 as described above with reference to Figures 3A-3DThis explains the reduction in cell height within the cell architecture. Furthermore, due to the reduced area size, the square top S / D contact structure allows the cell architecture to ensure sufficient space between the gate contact structure CB and adjacent pathways, as well as between the first type of top S / D contact structure and the second type of top S / D contact structure.

[0073] Figures 7A-7C Part of a cell architecture for constituting a logic circuit, such as a one-fin AOI22 circuit formed by a plurality of VFETs, is shown according to one embodiment. The one-fin AOI22 circuit consists of… Figure 2D The diagram shown illustrates this. Figure 7A A top view of the cell architecture used in the AOI22 circuit is shown. Figure 7B and 7C They are shown respectively Figure 7A The section view taken along lines M-M' and N-N' of the unit architecture. However, note that for simplicity, in Figures 7A-7C Some of the elements shown in any of them may be Figures 7A-7C At least one of them cannot be seen in the other.

[0074] Reference Figure 7A According to the unit architecture of this embodiment, multiple equally pitched fin structures F1 to F5 are provided. Along fin structures F1, F2, F4, and F5, as... Figure 2D The four PMOS and four NMOS shown can be formed to constitute a fin AOI22 circuit.

[0075] Figure 7A It also shows the bottom S / D regions RX1, RX2, and RX3; the gate connection pattern PB; the gate contact structures CB1 to CB4; the top S / D contact structures CA1 to CA9; the superpaths SPV1 to SPV4 and the paths V11 and V12; the metal patterns M13 and M14 for internal wiring; and the input signal V for receiving the AOI22 circuit. in And send out the output signal V of the AOI22 circuit. out Metal patterns M21-M25, and metal patterns M11 and M12 for connecting to the power rail Vdd and the ground rail Vss.

[0076] Reference Figure 7B According to the unit architecture of this embodiment, a superpath structure 710 including a superpath SPV4 is provided, wherein the superpath SPV4 receives the input signal V from the AOI22 circuit. in One of them is the gate signal.

[0077] Figure 7C The internal wiring for the top S / D contact structure CA1 and the output signal V of the AOI22 circuit are shown in the unit architecture according to this embodiment.out 720 metal / channel / contact structure. Figure 7C The metal pattern M13 shown is used for internal wiring between VFETs of the AOI22 circuit in the cell architecture according to this embodiment.

[0078] Similar to Figure 3A and 3B Superpath SPV for inverters, Figures 7A-7B The super-path SPV4 is formed on the gate contact structure CB4 (which is formed on the gate connection pattern PB) and the metal pattern M24 (the input signal V of the AOI22 circuit). in One of them is input into the metal pattern M24). Here, the height of the super-path SPV4 in the Z direction is as follows: Figure 7C In the illustrated metal / path / contact structure 720, the sum of the heights of the metal patterns M13 and the pathways V11 sequentially formed on the top S / D contact structure CA1 is the same or substantially the same. As in the previous embodiments, the super-path structure 710 should also contribute to reducing the cell height of the cell architecture.

[0079] picture Figures 6A-6C The unit architecture shown is the same. Figure 7A The cell architecture shown is further characterized by two types of top S / D contact structures. The first type of top S / D contact structure includes top S / D contact structures CA7 to CA9, and the second type includes top S / D contact structures CA1 to CA6. The first type of top S / D contact structures have a strip shape in the top view of the cell architecture and extend in the X and Y directions, allowing them to connect the corresponding VFETs to the power rail Vdd and ground rail Vss via metal patterns M11 and M12. However, the second type of top S / D contact structures used for internal wiring have a square shape in the top view of the cell architecture, which allows for the connection of the corresponding VFETs to the power rail Vdd and ground rail Vss as described above. Figures 3A-3D This explains the reduction in cell height within the cell architecture. Furthermore, due to the reduced area size, the square top S / D contact structure allows the cell architecture to ensure sufficient space between the gate contact structure CB and adjacent pathways, as well as between the first type of top S / D contact structure and the second type of top S / D contact structure.

[0080] However, Figures 7A-7CThe shown cell architecture for the AOI 22 circuit is configured to provide a metal pattern M25 formed on the fin structure F3 where no gate for the VFET of the AOI 22 circuit is formed. Thus, in this cell architecture, the ratio of the grid cell gate pitch (CPP) to the metal pattern pitch (MP) is 1:1, which is also referred to as the gear ratio. That is, this cell architecture requires five grid cell gate pitches, which can not meet the minimum grid cell gate pitch requirement of the AOI 22, which is four. To address this issue, the AOI 22 circuit can be implemented by a cell architecture with a gear ratio of 3:2 or 2:1, in which case the minimum grid cell gate pitch requirement can be met.

[0081] Figures 8A-8E Portions of a cell architecture that provide for constructing a logic circuit such as a one-fin AOI 22 circuit formed of a plurality of VFETs are shown in accordance with an embodiment. The one-fin AOI 22 circuit is also shown in the same schematic representation. Figure 2D Figure 8A A top view of the cell architecture for the AOI 22 circuit is shown, Figures 8B-8E Portions of cross-sectional views taken along lines O-O', P-P', Q-Q' and R-R' marked in Figure 8A However, note that some elements shown in any one of Figures 8A-8E may not be visible in at least another one of Figures 8A-8E

[0082] Referring to Figures 8A-8E , the cell architecture in accordance with the present embodiment provides a plurality of equi-pitched fin structures F1-F4, as shown in Figure 2D Four PMOS and four NMOS can be formed along the plurality of equi-pitched fin structures F1-F4 to construct a one-fin AOI 22 circuit, as shown in

[0083] Figures 8A-8E Bottom S / D regions RX1, RX2 and RX3, gate connection pattern PB, gate contact structures CB1-CB4, top S / D contact structures CA1-CA7, super vias SPV1-SPV4 and vias V01-V08, V11 and V12, metal patterns M13 and M14 for internal wiring, metal patterns M21-M24 for receiving input signals V in of the AOI 22 circuit, metal pattern M25 for sending out output signals V out of the AOI 22 circuit, metal patterns M11 and M12 for connecting to power rail Vdd and ground rail Vss are also shown.

[0084] Referring to Figure 8A ​​, super-paths SPV1 to SPV4 are formed on gate contact structures CB1 to CB4 formed on the gate connection pattern PB to receive four input signals V in (that is, four gate signals). Specifically, Figures 8B-8E It is shown that the super-paths SPV2 and SPV3 are higher than the vias V01 to V08, V11 and V12, such that the height of the super-path SPV3 in the Z-direction is the same as or substantially the same as the sum of the heights of the via V01, the metal pattern M13 and the via V11, and the sum of the heights of the via V02, the metal pattern M14 and the via V12. Here, the via V01 is formed on the top S / D contact structure CA1 to connect the PMOS P1 to the metal pattern M13 connected with the metal pattern M25 to send out an output signal V out of the AOI22 circuit. Similarly, the via V02 is formed on the top S / D contact structure CA2 to connect the NMOS N1 to the metal pattern M14 connected with the metal pattern M25 to send out the same output signal V out of the AOI22 circuit. The super-paths SPV1 to SPV4 are the same in height.

[0085] Figures 8A-8E The cell architecture according to the present embodiment shown is further characterized by two types of top S / D contact structures. The first type of top S / D contact structures includes the top S / D contact structures CA5 to CA7, and the second type of top S / D contact structures includes the top S / D contact structures CA1 to CA4. The first type of top S / D contact structures have a bar shape in a top view of the cell architecture and extend in the X and Y directions such that they can connect the corresponding VFETs to the power rail Vdd and the ground rail Vss through the power contact structures CR1 to CR4 and the metal patterns M11 and M12. However, the second type of top S / D contact structures for internal wiring have a square shape in a top view of the cell architecture, which can reduce the cell height of the cell architecture as explained above with reference to Figures 3A-3D In addition, due to the reduced area dimension, the square top S / D contact structures can enable the cell architecture to secure spaces between the gate contact structures CB and the adjacent vias and between the first type of top S / D contact structures and the second type of top S / D contact structures.

[0086] Also, the cell architecture according to the present embodiment is configured such that the vias V01 to V08 are formed on the respective top S / D contact structures CA1 to CA4 and the power contact structures CR1 to CR4, thereby preventing undesired connections between the top S / D contact structures CA5 to CA7 for power connection and the metal patterns M13 and M14 for internal wiring of the AOI22 circuit.

[0087] Alternatively, according to an embodiment similar to that of Figures 4A-4C , the top S / D contact structures CA1 to CA4 can be replaced by elevated top S / D contact structures CM1 to CM4 that omit the corresponding vias V01 to V04. In the same manner, the power contact structures CR1 to CR4 can also be replaced by elevated power contact structures CR1 to CR4 without using the corresponding vias V01, V02, V05 and V06. In this embodiment, the height of the replacement top S / D contact structure CM1 in the Z direction should be the same as the sum of the heights of the top S / D contact structure CA1 and the via V01. The heights of the other replacement top S / D contact structures CM2 to CM3 are the same as that of the replacement top S / D contact structure CM1.

[0088] According to another embodiment, the cell architecture can omit the super vias SPV1 to SPV4 by providing elevated gate contact structures CB1 to CB4. For example, Figure 8F An alternative structure of Figure 8B is shown, in which Figure 8B the super via SPV3 and the gate contact structure CB3 of are replaced by an elevated gate contact structure CB3. By using these elevated gate contact structures CB1 to CB4, the manufacturing process of the logic circuit can be simplified.

[0089] Figures 7A-7C Compared with the cell architecture of the one-fin AOI22 circuit described above with reference to , the cell architecture for the same one-fin AOI22 circuit according to the present embodiment is characterized in that the same metal pattern M25 for transmitting the output signal V out of the logic circuit is disposed between two adjacent fin structures F2 and F3, thereby achieving a 2:1 transmission ratio. That is, in the cell architecture of the present embodiment, the ratio of the grid cell gate pitch (CPP) to the metal pattern pitch (MP) is 2:1. With this structure, the cell architecture of the present embodiment can meet the minimum grid cell gate pitch CPP requirement of the AOI22 and can achieve a more reduced size of the cell architecture.

[0090] Figure 9 Referring to , the mobile device 1000 can include at least one application processor 100, a communication module 200, a display / touch module 300, a storage device 400 and a buffer storage 500, to which the above-described cell architecture can be applied.

[0091] The application processor 100 can control operations of the mobile device 1000. The communication module 200 is implemented to perform wireless or wired communication with external devices. The display / touch module 300 is implemented to display data processed by the application processor 100 and / or receive data through a touch panel. The storage device 400 is implemented to store various data including user data. The storage device 400 can be an embedded Multi-Media Card (eMMC), a Solid State Drive (SSD), a Universal Flash Storage (UFS) device, or the like. The storage device 400 can perform mapping data and caching of user data as described above.

[0092] The buffer memory 500 can temporarily store data for processing operations of the mobile device 1000. For example, the buffer memory 500 can be a volatile memory such as a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM), a Low Power Double Data Rate (LPDDR) SDRAM, a Graphics Double Data Rate (GDDR) SDRAM, a Rambus Dynamic Random Access Memory (RDRAM), or the like.

[0093] At least one component in the mobile device 1000 can include at least one standard cell having one of the cell architectures provided according to the above embodiments. The above embodiments can be applied to any electronic device and system. For example, the embodiments can be applied to systems such as a memory card, a Solid State Drive (SSD), an Embedded Multi-Media Card (eMMC), a mobile phone, a smart phone, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a digital camera, a camcorder, a Personal Computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book, a Virtual Reality (VR) device, an Augmented Reality (AR) device, or the like.

[0094] According to the above embodiments, a cell height of 150 nm or less of the VFET cell architecture can be achieved compared to a cell height of 180 nm-210 nm of a related art VFET cell architecture. In addition, a cell width reduction of about 5% to 10% can be achieved due to an increase in a ratio of a mesh cell gate pitch (CPP) to a metal pattern pitch (MP).

[0095] The foregoing is merely illustrative of the example embodiments and should not be construed as limiting the example embodiments. Although some embodiments have been described, those skilled in the art will readily devise many modifications to the described embodiments without substantial departure from the concept of the present inventive concept.

[0096] This application claims priority to U.S. Provisional Patent Application No. 62 / 819,056, filed March 15, 2019, in the U.S. Patent and Trademark Office, and U.S. Non-Provisional Patent Application No. 16 / 711,582, filed December 12, 2019, in the U.S. Patent and Trademark Office, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A cell architecture comprising: a plurality of vertical field effect transistors (VFETs) formed on a substrate to constitute a logic circuit; a first top source / drain (S / D) contact structure formed on a first top S / D region of a first VFET and connected to a first horizontal metal pattern formed thereon and extending in a first direction of the cell architecture to connect an output signal of the logic circuit output from the first top S / D region to a first vertical metal pattern; a second top S / D contact structure formed on a second top S / D region of a second VFET and connected to a second horizontal metal pattern formed thereon and extending in the first direction to connect the output signal of the logic circuit output from the second top S / D region to the first vertical metal pattern; and a gate contact structure formed on a gate connection pattern connected to respective gates of the first VFET and the second VFET, the gate contact structure connected to a gate input signal of the logic circuit through a super via, wherein the first VFET and the second VFET are formed along a first fin structure extending in a second direction of the cell architecture, wherein both the first top S / D contact structure and the second top S / D contact structure have a square shape in a top view of the cell architecture, and wherein the first vertical metal pattern is formed at a higher level than the first horizontal metal pattern and the second horizontal metal pattern, which are formed at a higher level than the first top S / D contact structure and the second top S / D contact structure.

2. The cell architecture of claim 1, wherein the super via is connected to a second vertical metal pattern to which the gate input signal of the logic circuit is input, the second vertical metal pattern being formed at a higher level than the first horizontal metal pattern and the second horizontal metal pattern, and wherein the first horizontal metal pattern and the second horizontal metal pattern are connected to the first vertical metal pattern through a first via and a second via, respectively.

3. The cell architecture of claim 2, wherein the first vertical metal pattern and the second vertical metal pattern are parallel to each other without overlapping each other in the top view of the cell architecture and are disposed at a same level from an upper surface of the substrate.

4. The cell architecture of claim 3, wherein an upper surface of the first top S / D contact structure, an upper surface of the second top S / D contact structure, and an upper surface of the gate contact structure are disposed at the same level from the upper surface of the substrate.

5. The cell architecture of claim 4, wherein a height of the super via is the same as a sum of heights of the first via and the first horizontal metal pattern. ​ 6. The cell architecture of claim 4, wherein the first top S / D contact structure is connected to the first horizontal metal pattern through a third via formed thereon, the second top S / D contact structure is connected to the second horizontal metal pattern through a fourth via formed thereon.

7. The cell architecture of claim 6, wherein a height of the super via is the same as a sum of heights of the first via, the first horizontal metal pattern, and the third via.

8. The cell architecture of claim 1, further comprising a third top S / D contact structure formed on a third top S / D region of a third VFET and extending to an edge of the cell architecture to connect to a power rail, wherein an upper surface of the third top S / D contact structure is spaced apart from a lower surface of the first horizontal metal pattern.

9. The cell architecture of claim 8, further comprising a fourth top S / D contact structure formed on a fourth top S / D region of a fourth VFET and connected to the second horizontal metal pattern formed thereon and extending in the first direction to connect the output signal of the logic circuit to the first vertical metal pattern through a second via.

10. The cell architecture of claim 9, wherein the third VFET and the fourth VFET are formed on a second fin structure extending in parallel with the first fin structure, wherein the first vertical metal pattern is formed between the first fin structure and the second fin structure through which the output signal of the logic circuit is sent out.

11. A cell architecture, comprising: a first type of top source / drain (S / D) contact structure formed on a top S / D region of at least two of vertical field effect transistors (VFETs) that constitute a logic circuit, respectively; a first metal pattern extending in a second direction and configured to receive one or more gate input signals of the logic circuit or send out an output signal of the logic circuit; a second metal pattern extending in a first direction and provided for internal wiring of the logic circuit to send out the output signal by connecting at least two of the first type of top S / D contact structure to one of the first metal pattern; and at least one gate contact structure formed on at least one gate connection pattern that connects gates of the at least two of the VFETs to each other, connected to another one of the first metal pattern to receive one of the gate input signals, wherein the at least two of the first type of top S / D contact structure have a square shape in a top view of the cell architecture, and wherein the first metal pattern is formed at a higher level than the second metal pattern, the second metal pattern is formed at a higher level than the first type of top S / D contact structure.

12. The cell architecture of claim 11, further comprising at least two first vias respectively formed on the second metal pattern to connect the at least two of the first type of top S / D contact structures to the one of the first metal pattern.

13. The cell architecture of claim 12, further comprising at least one super via formed on the gate contact structure and connecting the gate contact structure to the other of the first metal pattern.

14. The cell architecture of claim 13, further comprising at least two second vias respectively formed on the at least two of the first type of top S / D contact structures and connected to the second metal pattern.

15. The cell architecture of claim 13, wherein the at least two of the first type of top S / D contact structures are connected to the second metal pattern without passing through a respective via.

16. The cell architecture of claim 12, wherein the gate contact structure is connected to the other of the first metal pattern to receive one of the gate input signals without passing through a via.

17. The cell architecture of claim 11, further comprising a second type of top S / D contact structure having a strip shape in the top view of the cell architecture, formed on top S / D regions of at least two other of the VFETs, and extending to an edge of the cell architecture to connect to a power rail and a ground rail, wherein an upper surface of the second type of top S / D contact structure is spaced apart from a lower surface of the second metal pattern.

18. A cell architecture, comprising: top source / drain (S / D) contact structures respectively formed on top S / D regions of at least two of vertical field effect transistors (VFETs) that constitute a logic circuit; at least one gate contact structure connected to at least one gate connection pattern that connects gates of the at least two of the VFETs to each other; a first metal pattern extending in a second direction and configured to receive one or more gate input signals of the logic circuit and send out an output signal of the logic circuit; a second metal pattern extending in a first direction and provided for internal wiring of the logic circuit to send out the output signal by connecting at least two of the top S / D contact structures to one of the first metal pattern; and at least one super via formed on the gate contact structure and connected to another of the first metal pattern to receive one of the gate input signals, wherein the first metal pattern is formed at a higher level than the second metal pattern, which is formed at a higher level than the top S / D contact structures.

19. The cell architecture of claim 18, wherein the top S / D contact structures have a square shape in a top view of the cell architecture.

20. The cell architecture of claim 19, further comprising additional top S / D contact structures formed on top S / D regions of at least two additional ones of the VFETs, extending to an edge of the cell architecture to connect to a power rail or ground rail, and having upper surfaces spaced apart from lower surfaces of the second metal pattern.

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