Integrated circuit device including transistors with variable channel pitch

Abstract

An integrated circuit device may include active regions spaced apart from each other in one direction. The active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions. The first pair of active regions may be spaced apart from each other by a first distance in the said direction, the second pair of active regions may be spaced apart from each other by a first distance in the said direction, and the third pair of active regions may be spaced apart from each other by a first distance in the said direction. The second pair of active regions may be spaced apart from the first pair of active regions and the third pair of active regions by a second distance in the said direction, and the first distance may be shorter than the second distance.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 819,152, entitled "Standard VFET Cell with Variable Fin Pitch," filed March 15, 2019, with the United States Patent and Trademark Office (USPTO), and U.S. Application No. 16 / 520,717, entitled "Integrated Circuit Device Including Transistors with Variable Channel Pitch," filed July 24, 2019, with the United States PTO, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of electronics, and more specifically to integrated circuit devices. Background Technology

[0004] Transistors with different structures and layouts have been studied to increase the integration density of integrated circuit devices. For example, vertical field-effect transistors (VFETs) have been studied due to their high scalability. Summary of the Invention

[0005] According to some embodiments of the present invention, an integrated circuit device may include a plurality of active regions spaced apart from each other in a first direction. Each of the plurality of active regions may protrude from the upper surface of a substrate. The plurality of active regions may include a first pair of active regions, a second pair of active regions, and a third pair of active regions, which may be spaced apart from each other in the first direction and arranged sequentially along the first direction. The first pair of active regions may be spaced apart from each other by a first distance in the first direction, the second pair of active regions may be spaced apart from each other by a first distance in the first direction, and the third pair of active regions may be spaced apart from each other by a first distance in the first direction. The first pair of active regions may be spaced apart from the second pair of active regions by a second distance in the first direction, and the second pair of active regions may be spaced apart from the third pair of active regions by a second distance in the first direction, and the first distance may be shorter than the second distance.

[0006] According to some embodiments of the present invention, an integrated circuit device may include a bottom source / drain region on a substrate, a first active region and a second active region spaced apart from each other in a first direction, and a gate structure on the side of the first active region. Both the first and second active regions may protrude from the upper surface of the substrate. In a plan view, the first and second active regions may be located within the bottom source / drain region, and the second active region may be a dummy active region.

[0007] According to some embodiments of the present invention, an integrated circuit device may include a plurality of active regions, including a first pair of active regions and a second pair of active regions. The first pair of active regions may be spaced apart from each other in a first direction, and the second pair of active regions may also be spaced apart from each other in the first direction. The first pair of active regions and the second pair of active regions may be spaced apart from each other in a second direction different from the first direction, and each active region in the first pair of active regions may have a linear shape extending longitudinally in the second direction. Each active region in the second pair of active regions may have: a body portion having a linear shape extending longitudinally in the second direction and a protruding portion protruding from the body portion. Attached Figure Description

[0008] Figure 1 This is a circuit diagram of an inverter according to some embodiments.

[0009] Figure 2A and Figure 2B Illustrations are shown according to some embodiments Figure 1 The layout of the inverter.

[0010] Figure 3A , Figure 3B and Figure 3C According to some embodiments, respectively along Figure 2B A cross-sectional view taken by the Y1-Y1' line, Y2-Y2' line and X-X' line.

[0011] Figure 4A and Figure 4B According to some embodiments Figure 3A A magnified view of area A.

[0012] Figure 5 This is a circuit diagram of an inverter according to some embodiments.

[0013] Figure 6A and Figure 6B According to some embodiments Figure 5 The layout of the inverter.

[0014] Figure 7A , Figure 7B and Figure 7C They are respectively along Figure 6B A cross-sectional view taken by the Y1-Y1' line, Y2-Y2' line and X-X' line.

[0015] Figure 8 This is a circuit diagram of a two-input NAND gate according to some embodiments.

[0016] Figure 9A and Figure 9B According to some embodiments Figure 8 The layout of a two-input NAND gate.

[0017] Figure 10A and Figure 10B They are respectively along Figure 9B A cross-sectional view taken by the Y1-Y1' and Y2-Y2' lines. Figure 10C and Figure 10D They are respectively along Figure 9A A cross-sectional view taken by the X1-X1' and X2-X2' lines.

[0018] Figure 11 According to some embodiments Figure 8 The layout of a two-input NAND gate.

[0019] Figure 12A , Figure 12B and Figure 12C The layout of a portion of an integrated circuit device according to some embodiments is shown.

[0020] Figure 13 and Figure 15 According to some embodiments Figure 8 The layout of a two-input NAND gate.

[0021] Figure 14A and Figure 14B They are respectively along Figure 13 A cross-sectional view taken from the Z1-Z1' and Z2-Z2' lines.

[0022] Figure 16A and Figure 16B They are respectively along Figure 15 A cross-sectional view taken from the Z1-Z1' and Z2-Z2' lines.

[0023] Figure 17 According to some embodiments Figure 8 The layout of a two-input NAND gate.

[0024] Figure 18A and Figure 18B They are respectively along Figure 17 A cross-sectional view taken from the Z1-Z1' and Z2-Z2' lines.

[0025] Figures 19A to 19D A planar view shows various active regions with non-linear shapes.

[0026] Figure 20 According to some embodiments Figure 5 The layout of the inverter.

[0027] Figure 21 and Figure 22 According to some embodiments Figure 8 The layout of a two-input NAND gate.

[0028] Figures 23 to 28 A method for forming a plurality of standard cells comprising active regions having different shapes, according to some embodiments, is illustrated.

[0029] Figures 29 to 32 A method for forming a plurality of standard cells comprising active regions having different shapes, according to some embodiments, is illustrated.

[0030] Figure 33 An integrated circuit device comprising a standard cell with a double-height structure is shown. Detailed Implementation

[0031] According to some embodiments of the present invention, a single integrated circuit device (e.g., a single chip) may include multiple standard cells. Standard cells may be, for example, inverters, two-input NAND gates, three-input NAND gates, two-input NOR gates, three-input NOR gates, AND-OR inverters (AOI), OR-AND inverters (OAI), XNOR gates, XOR gates, multiplexers (MUX), latches, or D flip-flops. In some embodiments, a single integrated circuit device may include multiple sections (e.g., units) with different functions (e.g., a central processing unit (CPU) section, an application processor (AP) section, and a microprocessor unit (MPU) section). Each of these multiple sections may include multiple standard cells.

[0032] According to some embodiments of the present invention, the active regions (e.g., channel regions) of transistors have variable spacing to increase the integration density of integrated circuit devices. In some embodiments, the transistors included in the integrated circuit device may be vertical field-effect transistors (VFETs), which include active regions projecting vertically from the substrate. In some embodiments, each active region may have a non-linear shape in a plan view. For example, each active region may include a body portion having a linear shape and a protruding portion projecting from the body portion. It should be understood that "active region" refers to the region in which a channel is formed when the transistor is turned on. Therefore, it should also be understood that "active region" and "channel region" are interchangeable.

[0033] According to some embodiments of the present invention, the standard unit may be an inverter. Figure 1 This is a circuit diagram of an inverter according to some embodiments. (Refer to...) Figure 1 The drain voltage V can be DD Applied to a P-type VFET, and the source voltage V can be... SS Apply to an N-type VFET.

[0034] Figure 2A and Figure 2B Illustrations are shown according to some embodiments Figure 1 The layout of the inverter. Figure 2A and Figure 2B The layout of the same area of ​​the inverter is shown, and Figure 2A and Figure 2B Each of the figures shows a set of elements rather than all of them to simplify the illustrations.

[0035] Figure 3A , Figure 3B and Figure 3C Based on some embodiments respectively Figure 2B A cross-sectional view taken by the Y1-Y1' line, Y2-Y2' line and X-X' line. Figure 4A and Figure 4B According to some embodiments Figure 3A A magnified view of area A.

[0036] Reference Figures 2A to 3C The inverter may include a P-type VFET and an N-type VFET. The P-type VFET may include a first bottom source / drain region 12_P, a first channel region 14_P, and a first top source / drain region 16_P. The N-type VFET may include a second bottom source / drain region 12_N, a second channel region 14_N, and a second top source / drain region 16_N. In some embodiments, both the first bottom source / drain region 12_P and the second bottom source / drain region 12_N may extend longitudinally in the first horizontal direction X, such as... Figure 2A As shown in the figure. The first horizontal direction X can be parallel to the upper surface 100S of the substrate 100.

[0037] The first channel region 14_P and the first top source / drain region 16_P can be sequentially stacked on the substrate 100 in the vertical direction Z, and the second channel region 14_N and the second top source / drain region 16_N can also be sequentially stacked on the substrate 100 in the vertical direction Z. The vertical direction Z can be perpendicular to the upper surface 100S of the substrate 100. In some embodiments, the P-type VFET and the N-type VFET can be spaced apart from each other in a second horizontal direction Y that is perpendicular to the vertical direction Z and different from the first horizontal direction X. In some embodiments, the second horizontal direction Y can also be perpendicular to the first horizontal direction X.

[0038] The inverter may include a common gate layer 18. A first portion of the common gate layer 18 may be the gate electrode of a P-type VFET, and a second portion of the common gate layer 18 may be the gate electrode of an N-type VFET. Since the P-type VFET and the N-type VFET share the common gate layer 18, the same input can be applied to both the P-type VFET and the N-type VFET as the gate input. Spacers 20 may be provided to electrically isolate the common gate layer 18 from the first bottom source / drain region 12_P and the second bottom source / drain region 12_N, and from the first top source / drain region 16_P and the second top source / drain region 16_N. The first bottom source / drain region 12_P and the second bottom source / drain region 12_N may be electrically isolated from each other by an isolation layer 10 (e.g., a shallow trench isolation layer).

[0039] Since the common gate layer 18 is the gate electrode of both the P-type VFET and the N-type VFET, it should be understood that the common gate layer 18 is operatively connected to the first channel region 14_P of the P-type VFET and the second channel region 14_N of the N-type VFET. It should be understood that the reference herein to "element A is operatively connected to element B" (or similar language) means that element A is connected (e.g., directly or indirectly) to element B to produce the appropriate effect. For example, when the common gate layer 18 is connected to the first channel region 14_P of the P-type VFET and the second channel region 14_N of the N-type VFET to induce channel formation in the first channel region 14_P of the P-type VFET and the second channel region 14_N of the N-type VFET, the common gate layer 18 is operatively connected to the first channel region 14_P of the P-type VFET and the second channel region 14_N of the N-type VFET.

[0040] The top contact layer 32 can be on both the P-type VFET and the N-type VFET, and can contact both the first top source / drain region 16_P and the second top source / drain region 16_N. The top contact layer 32 can include a metal, such as cobalt (Co), tungsten (W), and / or copper (Cu). The first top source / drain region 16_P and the second top source / drain region 16_N can be electrically connected to each other through the top contact layer 32.

[0041] The first via contact 42_1 and the first wire 44_1 can be sequentially stacked on the top contact layer 32. In some embodiments, the first via contact 42_1 can contact the top contact layer 32, and the first wire 44_1 can contact the first via contact 42_1, such as... Figure 3BAs shown in the diagram. In some embodiments, the top contact layer 32 can be connected to the output node of the inverter via a first via contact 42_1 and a first wire 44_1. Both the first via contact 42_1 and the first wire 44_1 can comprise metals, such as Cu and / or Co. In some embodiments, the first wire 44_1 can be the metal line closest to the substrate 100 in the vertical direction Z, and can be referred to as the first metal line for wiring.

[0042] Reference Figure 2B In some embodiments, the first wire 44_1 and the second wire 44_2 can both extend longitudinally in the second horizontal direction Y, and the first wire 44_1 and the second wire 44_2 can be spaced apart from each other in the first horizontal direction X.

[0043] The gate contact 34 can contact the common gate layer 18. In some embodiments, a portion of the common gate layer 18 may be exposed by the spacer 20 and may contact the gate contact 34, such as... Figure 3A As shown in the diagram. The gate contact 34 may include a metal, such as Co, W, and / or Cu. In some embodiments, the gate contact 34 may be spaced apart from both the first top source / drain region 16_P and the second top source / drain region 16_N in the second horizontal direction Y, as shown in the diagram. Figure 2B As shown in the image.

[0044] The second via contact 42_2 and the second wire 44_2 can be sequentially stacked on the gate contact 34, such as Figure 3A As shown in the figure. In some embodiments, the second via contact 42_2 can contact the gate contact 34, and the second wire 44_2 can contact the second via contact 42_2, as shown in the figure. Figure 3A As shown in the figure. In some embodiments, the input of the inverter can be applied to the common gate layer 18 through the second wire 44_2, the second via contact 42_2 and the gate contact 34.

[0045] In some embodiments, the inverter may include a first bottom contact portion 36 and a second bottom contact portion 36, such as Figure 2A As shown in the diagram. The first bottom contact portion 36 can contact the first bottom source / drain region 12_P, and the second bottom contact portion 36 can contact the second bottom source / drain region 12_N, as shown in the diagram. Figure 3A and Figure 3B As shown in the figure. In some embodiments, a first voltage (e.g., drain voltage V) is provided. DD The first power can be applied to the first bottom source / drain region 12_P through the first bottom contact 36, having a second voltage (e.g., source voltage V). SSThe second power can be applied to the second bottom source / drain region 12_N through the second bottom contact 36. For example, the first bottom contact 36 and the second bottom contact 36 may include metals such as Co, W and / or Cu.

[0046] Reference Figure 2A and Figure 3B The inverter may further include a first dummy channel region 14_D1 and a second dummy channel region 14_D2. The first dummy channel region 14_D1 and the first channel region 14_P may be spaced apart from each other in a first horizontal direction X and may be arranged along the first horizontal direction X. The second dummy channel region 14_D2 and the second channel region 14_N may be spaced apart from each other in the first horizontal direction X and may be arranged along the first horizontal direction X. A common gate layer 18 may be spaced apart from the first dummy channel region 14_D1 and the second dummy channel region 14_D2, and thus the common gate layer 18 may not be operatively connected to the first dummy channel region 14_D1 and the second dummy channel region 14_D2. It should be understood that the reference herein to "element A and element B arranged along direction C" (or similar language) may mean that element A and element B are aligned with each other along direction C.

[0047] In some embodiments, the first dummy channel region 14_D1 may be located within the first bottom source / drain region 12_P in a plan view, and the second dummy channel region 14_D2 may be located within the second bottom source / drain region 12_N in a plan view, such as... Figure 2A As shown in the diagram. In some embodiments, in a plan view, the first bottom source / drain region 12_P may (e.g., partially or completely) surround the first dummy channel region 14_D1, and the second bottom source / drain region 12_N may (e.g., partially or completely) surround the second dummy channel region 14_D2.

[0048] Reference Figure 3A , Figure 3B and Figure 3C The inverter may further include an interlayer insulating layer 11, and the first dummy channel region 14_D1 and the second dummy channel region 14_D2 may be located within the interlayer insulating layer 11. In some embodiments, the interlayer insulating layer 11 may contact the side and top surfaces of the first dummy channel region 14_D1 and the second dummy channel region 14_D2, such as... Figure 3B As shown in the image.

[0049] Here, "dummy trench area" refers to a region that may have a similar shape to a trench area (e.g., the first trench area 14_P and the second trench area 14_N) and / or may have a similar material to the trench area, but is not used as a trench area. In some embodiments, the first dummy trench area 14_D1 and the second dummy trench area 14_D2 may be formed of an insulating material.

[0050] Reference Figure 4A and Figure 4B A gate insulator 15 can be provided between the first channel region 14_P and the common gate layer 18 to electrically isolate the first channel region 14_P and the common gate layer 18. Although Figure 4A and Figure 4B The gate insulator 15 is shown between the spacer 20 and the first channel region 14_P, but it should be understood that the gate insulator 15 between the spacer 20 and the first channel region 14_P can be omitted, and the spacer 20 can contact the first channel region 14_P.

[0051] In some embodiments, the lower surface of the first channel region 14_P may overlap with the first bottom source / drain region 12_P, such as Figure 4A As shown in the figure. In some embodiments, the lower surface of the first channel region 14_P can be connected to the substrate 100 via a protrusion 100P of the substrate 100, and the first bottom source / drain region 12_P can be located on the side of the protrusion 100P of the substrate 100, as shown in the figure. Figure 4B As shown. Although Figure 4A and Figure 4B Only P-type VFETs are shown, but it should be understood that... Figures 3A to 3C All VFETs, including N-type VFETs, can have the same or similar structure as P-type VFETs.

[0052] Since the gate insulator 15 and the common gate layer 18 jointly serve as the gates of the P-type VFET and the N-type VFET, the gate insulator 15 and the common gate layer 18 can be collectively referred to as the gate structure. In some embodiments, the gate structure may contact the sides of the first channel region 14_P and the second channel region 14_N, such as... Figure 3A As shown in the image.

[0053] Refer again Figure 2A and Figure 2B In some embodiments, the first through-hole contact portion 42_1 that contacts the top contact layer 32 and the second through-hole contact portion 42_2 that contacts the contact gate contact portion 34 may be spaced apart from each other in the first horizontal direction X and may be arranged along the first horizontal direction X.

[0054] According to some embodiments, the standard unit may be Figure 5 The inverter shown is shown in the figure. Figure 5 This is a circuit diagram of an inverter according to some embodiments. (Refer to...) Figure 5 In some embodiments, this is compared with an inverter comprising a single P-type VFET and a single N-type VFET (e.g., Figure 1 Compared to the inverter shown, an inverter can include two P-type VFETs connected in parallel and two N-type VFETs connected in parallel to achieve better performance (e.g., higher current).

[0055] Figure 6A and Figure 6B According to some embodiments Figure 5 The layout of the inverter. Figure 6A and 6B Each of the figures shows a set of elements rather than all of them to simplify the illustrations. Figure 6A and Figure 6B Not shown Figure 2A and Figure 2B Some of the components shown (e.g., Figure 2A The first bottom source / drain region 12_P and the second bottom source / drain region 12_N in the figure are shown to simplify these figures.

[0056] Figure 7A , Figure 7B and Figure 7C They are respectively along Figure 6B A cross-sectional view taken by the Y1-Y1', Y2-Y2', and X-X' lines. It should be understood that... Figure 7A and Figure 3A Same or similar.

[0057] Reference Figure 6A In some embodiments, a first portion of the common gate layer 18 may be the gate electrode of the first of two P-type VFETs (i.e., the first P-type VFET), a second portion of the common gate layer 18 may be the gate electrode of the second of two P-type VFETs (i.e., the second P-type VFET), a third portion of the common gate layer 18 may be the gate electrode of the first of two N-type VFETs (i.e., the first N-type VFET), and a fourth portion of the common gate layer 18 may be the gate electrode of the second of two N-type VFETs (i.e., the second N-type VFET). Since the two P-type VFETs and the two N-type VFETs share the common gate layer 18, the same input can be applied to both P-type VFETs and the two N-type VFETs as the gate input.

[0058] In some embodiments, such as Figure 6B and Figure 7B As shown, the first via contact portion 42_1 that contacts the top contact layer 32 can be spaced apart from both the first top source / drain region 16_P and the second top source / drain region 16_N in the second horizontal direction Y.

[0059] Reference Figure 6A and Figures 7A to 7C The top contact layer 32 can contact the two first top source / drain regions 16_P and the two second top source / drain regions 16_N, so the two first top source / drain regions 16_P and the two second top source / drain regions 16_N can be fully electrically connected through the top contact layer 32.

[0060] Figure 8This is a circuit diagram of a two-input NAND gate according to some embodiments. According to some embodiments, the standard cell may be... Figure 8 The two-input NAND gate shown. Figure 8 A two-input NAND gate may include a first P-type VFET P1 and a first N-type VFET N1 connected to each other, and Figure 1 The circuit shown is the same. Specifically, the first P-type VFET P1 and the first N-type VFET N1 may share a first input (e.g., Input A) and an output (e.g., Output). The two-input NAND gate may also include a second P-type VFET P2 and a second N-type VFET N2 that share a second input (e.g., Input B).

[0061] Figure 9A and Figure 9B According to some embodiments Figure 8 The layout of a two-input NAND gate. Figure 9A and Figure 9B The layout of the same region of a two-input NAND gate is shown. Figure 9A and Figure 9B Each of the figures shows a set of elements rather than all of them to simplify the illustrations.

[0062] Figure 10A and Figure 10B They are respectively along Figure 9B A cross-sectional view taken by the Y1-Y1' and Y2-Y2' lines. Figure 10C and Figure 10D They are respectively along Figure 9A A cross-sectional view taken by the X1-X1' and X2-X2' lines.

[0063] although Figures 9A to 10D The diagram shows that each transistor (i.e., the first P-type VFET P1, the first N-type VFET N1, the second P-type VFET P2, and the second N-type VFET N2) comprises two transistors for better performance; however, it should be understood that each transistor may comprise a single transistor. For simplicity, the diagram is shown in [the original text]. Figures 10A to 10D The substrate 100 is not shown in the figure.

[0064] Reference Figures 9A to 10DThe first P-type VFET P1 may include two first P-type VFETs. Each of these two first P-type VFETs may include a first bottom source / drain region 12_P, a first channel region 14_P1, and a first top source / drain region 16_P1. The first N-type VFET N1 may include two first N-type VFETs. Each of these two first N-type VFETs may include a second bottom source / drain region 12_N, a second channel region 14_N1, and a second top source / drain region 16_N1. The second P-type VFET P2 may include two second P-type VFETs. Each of these two second P-type VFETs may include a first bottom source / drain region 12_P, a third channel region 14_P2, and a third top source / drain region 16_P2. The first bottom source / drain region 12_P may be shared by the two first P-type VFETs and the two second P-type VFETs. The second N-type VFET N2 may include two second N-type VFETs. Each of the two second N-type VFETs may include a second bottom source / drain region 12_N, a fourth channel region 14_N2, and a fourth top source / drain region 16_N2. The second bottom source / drain region 12_N may be shared by the two first N-type VFETs and the two second N-type VFETs.

[0065] A two-input NAND gate may include a first common gate layer 18A. A first portion of the first common gate layer 18A may be the gate electrode of each of two first P-type VFETs P1, and a second portion of the first common gate layer 18A may be the gate electrode of two first N-type VFETs N1. Since the two first P-type VFETs P1 and the two first N-type VFETs N1 share the first common gate layer 18A, the same input (e.g., ...) can be used. Figure 8 Input A is applied to two first P-type VFETs P1 and two first N-type VFETs N1 as gate inputs. Spacers 20 can be provided to electrically isolate the first common gate layer 18A from the first bottom source / drain region 12_P and the second bottom source / drain region 12_N, and from the first top source / drain region 16_P1 and the second top source / drain region 16_N1. The first bottom source / drain region 12_P and the second bottom source / drain region 12_N can be electrically isolated from each other via an isolation layer 10 (e.g., a shallow trench isolation layer).

[0066] A two-input NAND gate may also include a second common gate layer 18B. A first portion of the second common gate layer 18B may be the gate electrode of each of the two second P-type VFETs P2, and a second portion of the second common gate layer 18B may be the gate electrode of each of the two second N-type VFETs N2. Since the two second P-type VFETs P2 and the two second N-type VFETs N2 share the second common gate layer 18B, the same input (e.g., ...) can be used. Figure 8Input B) is applied to two second P-type VFETs P2 and two second N-type VFETs N2 as gate inputs. Spacers 20 can be provided to electrically isolate the second common gate layer 18B from the first bottom source / drain region 12_P and the second bottom source / drain region 12_N, as well as from the third top source / drain region 16_P2 and the fourth top source / drain region 16_N2.

[0067] The first top contact layer 32_1 may extend over two first P-type VFETs P1, two first N-type VFETs N1, and two second P-type VFETs P2. The first top contact layer 32_1 may contact and electrically connect the two first top source / drain regions 16_P1, the two second top source / drain regions 16_N1, and the two third top source / drain regions 16_P2. The first top contact layer 32_1 may include a metal, such as Co, W, and / or Cu. The first top contact layer 32_1 may not overlap with the two fourth top source / drain regions 16_N2 and may be spaced apart from the two fourth top source / drain regions 16_N2, such as... Figure 9A and Figure 10D As shown in the image.

[0068] The second top contact layer 32_2 may extend over the two second N-type VFETs N2 and may contact the two fourth top source / drain regions 16_N2. In some embodiments, such as Figure 9A and Figure 10A As shown, the second top contact layer 32_2 can extend toward and contact the bottom contact portion 36 adjacent to the two second N-type VFETs N2, thereby transmitting the source voltage V through the bottom contact portion 36 and the second top contact layer 32_2. SS It is applied to the two fourth top source / drain regions 16_N2. The second top contact layer 32_2 may include a metal, such as Co, W and / or Cu.

[0069] A two-input NAND gate may further include a first gate contact 34A and a second gate contact 34B. The first gate contact 34A may contact a first common gate layer 18A, and the second gate contact 34B may contact a second common gate layer 18B. In some embodiments, the first gate contact 34A and the second gate contact 34B may be spaced apart from each other in a first horizontal direction X and may be arranged along the first horizontal direction X, such as... Figure 9A and Figure 9B As shown in the figure. In some embodiments, the first gate contact portion 34A and the second gate contact portion 34B can be aligned along the first horizontal direction X.

[0070] A two-input NAND gate may include multiple via contacts 42. A first via contact 42 may contact a first gate contact 34A, a second via contact 42 may contact a second gate contact 34B, and a third via contact 42 may contact a first top contact layer 32_1. The first, second, and third via contacts 42 may be spaced apart from each other in a first horizontal direction X and may be arranged along the first horizontal direction X, such as... Figure 9B As shown in the diagram, the first, second, and third via contacts 42 can be aligned along a first horizontal direction X. A two-input NAND gate can include multiple wires 44, and each wire 44 can contact a corresponding first, second, and third via contact 42.

[0071] Figure 11 According to some embodiments Figure 8 The layout of the two-input NAND gates. Figure 11 A two-input NAND gate may include: a first P-type VFET P1 including three first channel regions 14_P1, a first N-type VFET N1 including three second channel regions 14_N1, a second P-type VFET P2 including three third channel regions 14_P2, and a second N-type VFET N2 including three fourth channel regions 14_N2.

[0072] It should be understood that, if referred to Figure 5 , Figure 9A , Figure 9B and Figure 11 Using multiple channel regions for a single transistor can increase the channel current of the single transistor, but it can also increase the area occupied by the single transistor. Therefore, the integration density of an integrated circuit device comprising a single transistor may be reduced. Thus, in some embodiments, only a portion of the integrated circuit device may include transistors each comprising multiple channel regions. For example, a standard cell may include an inverter connected to an output node, and only the inverter may include transistors each comprising multiple channel regions, and each other transistor may include a single channel region. The standard cell may be, for example, a 2-OR to 2-AND gate (AO22), a multiplexer, or a 2-NAND gate.

[0073] Figure 12A , Figure 12B and Figure 12C The layout of a portion of an integrated circuit device according to some embodiments is shown. Figure 12A , Figure 12B and Figure 12C The layout of the same part of the integrated circuit device is shown, and Figure 12A , Figure 12B and Figure 12C Each of the figures shows a set of elements rather than all of them to simplify the illustrations.

[0074] Reference Figure 12A This portion of the integrated circuit device may include a first pair of active regions AP1 to a fourteenth pair of active regions AP14. The first pair of active regions AP1 to the seventh pair of active regions AP7 may be spaced apart in a first horizontal direction X and may be arranged along the first horizontal direction X. The eighth pair of active regions AP8 to the fourteenth pair of active regions AP14 may be spaced apart in the first horizontal direction X and may be arranged along the first horizontal direction X. The first pair of active regions AP1 to the seventh pair of active regions AP7 and the eighth pair of active regions AP8 to the fourteenth pair of active regions AP14 may be spaced apart in a second horizontal direction Y.

[0075] The first pair of active regions AP1 to the fourteenth pair of active regions AP14 can each include two active regions 14 spaced apart from each other by a first distance d1 in the first horizontal direction X. The first pair of active regions AP1 to the fourteenth pair of active regions AP14 can include one or more dummy active regions 14_D. The dummy active region 14_D can have the same characteristics as the reference active region. Figures 2A to 3C The first dummy source region 14_D1 and the second dummy source region 14_D2 are described as having similar structures. In some embodiments, the dummy source region 14_D can be derived from a substrate (e.g., ...). Figure 3B The substrate 100 in the middle is prominent.

[0076] In some embodiments, two pairs of active regions AP1 to AP7 that are directly adjacent in the first horizontal direction X (e.g., the second pair of active regions AP2 and the third pair of active regions AP3) may be spaced apart from each other by a second distance d2 in the first horizontal direction X. In some embodiments, two pairs of active regions AP8 to AP14 that are directly adjacent in the first horizontal direction X (e.g., the tenth pair of active regions AP10 and the eleventh pair of active regions AP11) may be spaced apart from each other by a second distance d2 in the first horizontal direction X. In some embodiments, the first distance d1 may be different from the second distance d2. For example, the first distance d1 may be shorter than the second distance d2, such as... Figure 12A As shown in the image.

[0077] It should be understood that the term “directly adjacent” as used herein includes a configuration in which two elements described as being directly adjacent to each other (e.g., the second pair of active regions AP2 and the third pair of active regions AP3) are positioned such that no other similar elements are located between the two elements.

[0078] Two active regions in one pair of active regions AP1 to AP14 can be separated from each other by a first spacing pt1 in the first horizontal direction X, and two directly adjacent pairs of active regions AP1 to AP7 and AP8 to AP14 can be separated from each other by a second spacing pt2 in the first horizontal direction X, as shown below. Figure 12A As shown in the image.

[0079] In some embodiments, the metal wires disposed on the first pair of active regions AP1 to the fourteenth pair of active regions AP14 (e.g., Figure 2B The first conductor 44_1 and the second conductor 44_2 are configured to have a third spacing between the first spacing pt1 and the second spacing pt2. In some embodiments, the third spacing is the average of the first spacing pt1 and the second spacing pt2.

[0080] Reference Figure 12B This portion of the integrated circuit device may include multiple source / drain regions, including a first bottom source / drain region 12_1 to a tenth bottom source / drain region 12_10. The first bottom source / drain regions 12_1 to the fourth bottom source / drain regions 12_4 may be spaced apart in a first horizontal direction X and may be arranged along the first horizontal direction X. The fifth bottom source / drain regions 12_5 to the tenth bottom source / drain regions 12_10 may be spaced apart in the first horizontal direction X and may be arranged along the first horizontal direction X. The first bottom source / drain regions 12_1 to the fourth bottom source / drain regions 12_4 and the fifth bottom source / drain regions 12_5 to the tenth bottom source / drain regions 12_10 may be spaced apart in a second horizontal direction Y.

[0081] In some embodiments, two bottom source / drain regions directly adjacent to each other in the first horizontal direction X (e.g., the second bottom source / drain region 12_2 and the third bottom source / drain region 12_3) from the first bottom source / drain region 12_1 to the fourth bottom source / drain region 12_4 may be spaced apart from each other by a third distance d3 in the first horizontal direction X. In some embodiments, two bottom source / drain regions directly adjacent to each other in the first horizontal direction X from the fifth bottom source / drain region 12_5 to the tenth bottom source / drain region 12_10 (e.g., the sixth bottom source / drain region 12_6 and the seventh bottom source / drain region 12_7) may be spaced apart from each other by a third distance d3 in the first horizontal direction X. In some embodiments, the third distance d3 may be shorter than the second distance d2.

[0082] The space between two directly adjacent bottom source / drain regions in the first horizontal direction X can be called a "bottom source / drain region gap" because no bottom source / drain region is set therein. In some embodiments, each bottom source / drain region gap may be set between two directly adjacent pairs of active regions in a plan view, and the bottom source / drain region gap may not be set between the active regions in a single pair of active regions in a plan view, such as... Figure 12B As shown in the image.

[0083] In some embodiments, some of the first bottom source / drain regions 12_1 to the tenth bottom source / drain region 12_10 (e.g., the sixth bottom source / drain region 12_6) may have a first width w1 in the first horizontal direction X, and others of the first bottom source / drain regions 12_1 to the tenth bottom source / drain region 12_10 (e.g., the ninth bottom source / drain region 12_9) may have a second width w2 in the first horizontal direction X. The second width w2 may be wider than the first width w1. In some embodiments, the first width w1 may be greater than the first distance d1.

[0084] Still refer to Figure 12B In a plan view, each of the first pair of active regions AP1 to the fourteenth pair of active regions AP14 can be located within a corresponding one of the first bottom source / drain regions 12_1 to the tenth bottom source / drain region 12_10. In a plan view, the second pair of active regions AP2 and the third pair of active regions AP3 can be located within a single bottom source / drain region (i.e., the second bottom source / drain region 12_2), thus the second bottom source / drain region 12_2 can be referred to as the common bottom source / drain region of the second pair of active regions AP2 and the third pair of active regions AP3. In some embodiments, the first bottom source / drain regions 12_1 to the tenth bottom source / drain regions 12_10 can each overlap with an even number (e.g., 2, 4, or 6) of active regions, such as... Figure 12B As shown in the image.

[0085] Reference Figure 12C This portion of the integrated circuit device may also include multiple common gate layers (e.g., first common gate layer 18_1 to eighth common gate layer 18_8). Each common gate layer may extend longitudinally in a second horizontal direction Y. The first common gate layer 18_1 to the eighth common gate layer 18_8 may be spaced apart in a first horizontal direction X.

[0086] In some embodiments, this portion of the integrated circuit device may include a plurality of standard units (e.g., first standard unit STC1 to fourth standard unit STC4) that may be spaced apart in a first horizontal direction X and may be arranged along the first horizontal direction X.

[0087] The first standard cell STC1 may include a first pair of active regions AP1, an eighth pair of active regions AP8, a first bottom source / drain region 12_1 and a fifth bottom source / drain region 12_5, and a first common gate layer 18_1. The first standard cell STC1 may include: a first field-effect transistor (e.g., VFET), including the first active region in the first pair of active regions AP1, the first bottom source / drain region 12_1, and the first common gate layer 18_1; and a second field-effect transistor (e.g., VFET), including the first active region in the eighth pair of active regions AP8, the fifth bottom source / drain region 12_5, and the first common gate layer 18_1. The first standard cell STC1 may also include two dummy active regions 14_D, such as... Figure 12C As shown in the figure. In some embodiments, the first common gate layer 18_1 may be spaced apart from the dummy active region 14_D, and the first common gate layer 18_1 may not be operatively connected to the dummy active region 14_D. For example, the first standard cell STC1 may be an inverter.

[0088] In some embodiments, the second standard unit STC2 may be a two-input NAND gate, and the third standard unit STC3 may be an inverter.

[0089] Figure 13 and Figure 15 According to some embodiments Figure 8 The layout of a two-input NAND gate. Figure 14A and Figure 14B They are respectively along Figure 13 A cross-sectional view taken from lines Z1-Z1' and Z2-Z2'. Figure 16A and Figure 16B They are respectively along Figure 15 A cross-sectional view taken along lines Z1-Z1' and Z2-Z2'. It should be understood that... Figures 13 to 16B All components of a two-input NAND gate are not shown in the figure to simplify the illustration.

[0090] Reference Figure 13 and Figure 15A two-input NAND gate may include a non-VFET (e.g., a planar transistor and a FinFET), wherein current flows along the surface of the substrate. The two-input NAND gate may include a first active region 114_1 and a second active region 114_2 spaced apart from each other in a second horizontal direction Y. Both the first active region 114_1 and the second active region 114_2 may extend longitudinally in the first horizontal direction X. The first active region 114_1 may be the active region of a first P-type VFET P1 and a second P-type VFET P2, and the second active region 114_2 may be the active region of a first N-type VFET N1 and a second N-type VFET N2. In some embodiments, the first P-type VFET P1, the second P-type VFET P2, the first N-type VFET N1, and the second N-type VFET N2 may all be FinFETs or planar transistors.

[0091] A two-input NAND gate may further include a first common gate layer 118_1 to a fourth common gate layer 118_4. The first common gate layer 118_1 to the fourth common gate layer 118_4 may all extend longitudinally in the second horizontal direction Y. The first common gate layer 118_1 to the fourth common gate layer 118_4 may be spaced apart in the first horizontal direction X and arranged along the first horizontal direction X.

[0092] In some embodiments, the first common gate layers 118_1 to the fourth common gate layers 118_4 can be arranged with variable spacing. For example, the second common gate layer 118_2 and the third common gate layer 118_3 can have a third spacing pt3. The first common gate layer 118_1 and the second common gate layer 118_2 can have a fourth spacing pt4, and the third common gate layer 118_3 and the fourth common gate layer 118_4 can also have a fourth spacing pt4. The third spacing pt3 can be shorter than the fourth spacing pt4.

[0093] In some embodiments, a first power contact 132p1, a second power contact 132p2, and an output contact 132o may be provided between two adjacent common gate layers. For example, the drain voltage V can be... DD The power is applied to the first electrical contact 132p1, and the source voltage V can be applied to the first electrical contact 132p1. SS The power is applied to the second power contact 132p2. The two-input NAND gate can output its output through the output contact 132o.

[0094] Reference Figure 14A , Figure 14B , Figure 16A and Figure 16BIn some embodiments, the first power contact 132p1, the second power contact 132p2, and the output contact 132o can all be disposed on one of the first active region 114_1 and the second active region 114_2 and between two adjacent common gate layers.

[0095] Figure 17 According to some embodiments Figure 8 The layout of two-input NAND gates, Figure 18A and Figure 18B They are respectively along Figure 17 A cross-sectional view taken from the Z1-Z1' and Z2-Z2' lines.

[0096] In addition to the first embedded power rail 132bp1 and the second embedded power rail 132bp2, Figure 17 , Figure 18A and Figure 18B The two-input NAND gate shown is similar to the reference gate. Figures 13 to 16B The described two-input NAND gate. (Refer to...) Figure 18A and Figure 18B The two-input NAND gate may include a first embedded power rail 132bp1 and a second embedded power rail 132bp2 respectively disposed in the first active region 114_1 and the second active region 114_2. Because the first embedded power rail 132bp1 and the second embedded power rail 132bp2 are not disposed between the sides of two adjacent common gate layers in the first active region 114_1 and the second active region 114_2, the possibility of an electrical short circuit between the two adjacent common gate layers and one of the first embedded power rail 132bp1 and the second embedded power rail 132bp2 can be reduced.

[0097] Figures 19A to 19D Various active regions with non-linear shapes are shown in a plan view. Specifically, Figures 19A to 19D Each shows four adjacent active regions (e.g., Figure 12A The first pair of active regions AP1 and the eighth pair of active regions AP8 in the middle.

[0098] Reference Figure 19A Each active region 14 may include a body portion 14m having a linear shape (e.g., a line) extending longitudinally in a second horizontal direction Y and a protruding portion 14p projecting from the body portion 14m in a first horizontal direction X. In some embodiments, each active region 14 may include two protruding portions 14p projecting from a respective end of the body portion 14m, such as... Figure 19A As shown in the image.

[0099] Reference Figures 19B to 19DTwo active regions directly adjacent to each other in the first horizontal direction X (e.g., two active regions in the first pair of active regions AP1) can be connected to each other and can form a single active region. Each of the two active regions directly adjacent to each other in the first horizontal direction X may include: a main body portion 14m having a linear shape (e.g., linear) extending longitudinally in the second horizontal direction Y, and a portion protruding from the main body portion 14m. The portions protruding from the main body portion 14m can be connected to each other to form a connecting portion 14c. It should be understood that the protruding portion 14p and the connecting portion 14c can increase the channel width, and thus can contribute to an increase in channel current.

[0100] In some embodiments, the main body portions 14m of two active regions that are directly adjacent to each other in the first horizontal direction X may be spaced apart by a first distance d1 in the first horizontal direction X, as shown in reference. Figure 12A As stated above.

[0101] It should be understood that Figures 19A to 19D The active region shown can be used to include a reference. Figures 1 to 12C In various standard units, including inverters and two-input NAND gates.

[0102] Figure 20 According to some embodiments Figure 5 The layout of the inverters. For simplicity of illustration, Figure 20 Not shown Figure 5 All components of the inverter. Except for the shape of the channel region, Figure 20 The inverter shown is similar to Figure 6A The inverter shown is illustrated. (Refer to...) Figure 20 , Figure 6A The two first channel regions 14_P can be connected to form a single first channel region 14_P. Figure 6A The two second channel regions 14_N can be connected to form a single second channel region 14_N.

[0103] Figure 21 and Figure 22 According to some embodiments Figure 8 The layout of the two-input NAND gates. Besides the shape of the channel region... Figure 21 and Figure 22 The two-input NAND gate shown is similar to Figure 11 The two-input NAND gate shown.

[0104] Reference Figure 21 , Figure 11 The two first channel regions 14_P1 can be connected to form a single first channel region 14_P1. Figure 11 The two third channel regions 14_P2 can be connected to form a single third channel region 14_P2. Figure 11 The two second channel regions 14_N1 can be connected to form a single second channel region 14_N1. Figure 11 The two fourth channel regions 14_N2 can be connected to form a single fourth channel region 14_N2.

[0105] Reference Figure 22 , Figure 11 The three first channel regions 14_P1 can be connected to form a single first channel region 14_P1. Figure 11 The three third channel regions 14_P2 in the image can be connected to form a single third channel region 14_P2. Figure 11 The three second channel regions 14_N1 can be connected to form a single second channel region 14_N1. Figure 11 The three fourth channel regions 14_N2 can be connected to form a single fourth channel region 14_N2.

[0106] Figures 23 to 28 A method for forming a plurality of standard cells comprising active regions of different shapes, according to some embodiments, is illustrated. Specifically, some standard cells may include active regions having linear shapes, and some standard cells may include active regions having nonlinear shapes. Figures 23 to 28 The intermediate structure is shown in a plan view.

[0107] Reference Figure 23 Support layers 210 can be formed on multiple standard cells arranged along a first horizontal direction X and a second horizontal direction Y. The standard cells can be separated from each other by cell boundaries CB. Each support layer 210 can extend longitudinally in the second horizontal direction Y and can extend across multiple standard cells (e.g., three standard cells) spaced apart in the second horizontal direction Y.

[0108] Reference Figure 24 The patterned support layer 211 can be formed by removing a portion of the support layer 210. The patterned support layer 211 can have various lengths in the second horizontal direction Y, such as... Figure 24 As shown in the figure. In some embodiments, a number of patterned support layers 211 spaced apart in the second horizontal direction Y may have the same width in the first horizontal direction X.

[0109] Reference Figure 25 Channel layers 213 can be formed on the side surfaces of the support layer 210 and the patterned support layer 211, respectively. In some embodiments, each channel layer 213 may have a uniform thickness along the corresponding side surface of the support layer 210 and the patterned support layer 211.

[0110] Reference Figure 26The support layer 210 and the patterned support layer 211 can be removed. The support layer 210 and the patterned support layer 211 may include materials different from the material of the channel layer 213, thereby allowing for selective removal of the support layer 210 and the patterned support layer 211.

[0111] Reference Figure 27 A mask layer 216 can be formed on the first portion of the channel layer 213 to protect the first portion from removal by subsequent processes. The second portion of the channel layer 213 exposed by the mask layer 216 can be removed by, for example, an etching process (e.g., a wet etching process and / or a dry etching process).

[0112] Reference Figure 28 The mask layer 216 can be removed after the second portion of the channel layer 213 exposed by the mask layer 216 is removed, and active regions 214 with various shapes can be formed.

[0113] According to reference Figures 23 to 28 The described method can simultaneously form active regions with linear shapes and active regions with various nonlinear shapes.

[0114] Figures 29 to 32 A method for forming multiple standard cells comprising active regions of different shapes, according to some embodiments, is illustrated. According to this method, two standard cells that are adjacent to each other in a second horizontal direction Y and have different shapes can be formed simultaneously.

[0115] Reference Figure 29 A support layer 210 and a patterned support layer 211 can be formed, and then a channel layer 213 can be formed on the sides of the support layer 210 and the patterned support layer 211.

[0116] Reference Figure 30 The support layer 210 and the patterned support layer 211 can be selectively removed.

[0117] Reference Figure 31 A mask layer 216 can be formed on the first portion of the channel layer 213 to protect the first portion from removal by subsequent processes. The second portion of the channel layer 213 exposed by the mask layer 216 can be removed by, for example, an etching process.

[0118] Reference Figure 32 The mask layer 216 can be removed after the second portion of the channel layer 213 exposed by the mask layer 216 is removed, and active regions 214 with various shapes can be formed. Two standard cells that are directly adjacent to each other in the second horizontal direction Y can include active regions 214 with different shapes.

[0119] Figure 33An integrated circuit device including standard cells with a double-height structure is shown. The integrated circuit device may include a fifth standard cell STC5 and a sixth standard cell STC6, and both the fifth standard cell STC5 and the sixth standard cell STC6 may have a double-height structure. Both the fifth standard cell STC5 and the sixth standard cell STC6 may include three unit cells separated by cell boundaries CB.

[0120] In some embodiments, each unit cell in the fifth standard cell STC5 may include two active regions 214 having a non-linear shape. In some embodiments, the sixth standard cell STC6 may include a long active region 214L. Each long active region 214L may have a portion that extends longitudinally in the second horizontal direction Y and can cross the cell boundary CB. It should be understood that the long active region 214L can provide a wide channel, and thus can contribute to an increase in channel current.

[0121] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the spirit and teachings of this disclosure, and therefore this disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided to make this disclosure thorough and complete, and to convey the scope of this disclosure to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be enlarged for clarity. Throughout the drawings, the same reference numerals denote the same elements.

[0122] Example embodiments of the inventive concept are described herein with reference to cross-sectional or plan views of intermediate structures illustrating idealized and exemplary embodiments. Therefore, deviations from the illustrated shapes are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the example embodiments of the inventive concept should not be construed as limited to the specific shapes shown herein, but rather include, for example, shape deviations caused by manufacturing processes.

[0123] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having the same meaning as they have in the relevant technical context, and should not be interpreted in an idealized or overly formal sense, unless otherwise explicitly defined.

[0124] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. The singular forms “a,” “an,” and “the” as used herein are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0125] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish elements from one another. Thus, without departing from the teachings of the inventive concept, a first element may be referred to as a second element.

[0126] The subject matter disclosed above should be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, alterations, and other embodiments falling within the true spirit and scope of the inventive concept. Therefore, to the maximum extent permitted by law, the scope of this disclosure shall be determined by the broadest possible interpretation of the appended claims and their equivalents, and should not be construed as limited by the foregoing detailed description.

Claims

1. An integrated circuit device, comprising: a plurality of active regions spaced apart from each other in a first direction, each of the plurality of active regions protruding from an upper surface of a substrate; and a first bottom source / drain region on the substrate, wherein the plurality of active regions includes a first pair of active regions, a second pair of active regions, and a third pair of active regions, and the first pair of active regions, the second pair of active regions, and the third pair of active regions are spaced apart from each other in the first direction and sequentially arranged along the first direction, wherein the first pair of active regions are spaced apart from each other in the first direction by a first distance, the second pair of active regions are spaced apart from each other in the first direction by the first distance, and the third pair of active regions are spaced apart from each other in the first direction by the first distance, wherein the first pair of active regions are spaced apart from the second pair of active regions in the first direction by a second distance, and the second pair of active regions are spaced apart from the third pair of active regions in the first direction by the second distance, wherein the first distance is shorter than the second distance, wherein the first pair of active regions includes a first active region and a second active region spaced apart from the first active region in the first direction by the first distance, and wherein the integrated circuit device includes a first vertical field effect transistor (VFET) including the first active region of the first pair of active regions and the first bottom source / drain region, and the second active region of the first pair of active regions is a dummy active region.

2. The integrated circuit device of claim 1, wherein, The first bottom source / drain region has a first width in the first direction, and the first width is greater than the first distance.

3. The integrated circuit device of claim 2, wherein, The integrated circuit device further includes a second VFET including the second pair of active regions and a second bottom source / drain region, and wherein the first bottom source / drain region and the second bottom source / drain region are spaced apart from each other in the first direction by a third distance, and the third distance is shorter than the second distance.

4. The integrated circuit device of claim 1, wherein, In a plan view, the first pair of active regions are within the first bottom source / drain region.

5. The integrated circuit device of claim 4, wherein, The first vertical field effect transistor further includes a first gate structure connected to the first active region of the first pair of active regions, and the first gate structure is not connected to the second active region of the first pair of active regions.

6. The integrated circuit device of claim 1, wherein, The integrated circuit device further includes: a second VFET including the second pair of active regions and a second bottom source / drain region; and a third VFET including the third pair of active regions and a third bottom source / drain region, wherein the second bottom source / drain region is spaced apart from the first bottom source / drain region and the third bottom source / drain region in the first direction by a third distance.

7. The integrated circuit device of claim 6, wherein, Each of the first bottom source / drain region, the second bottom source / drain region, and the third bottom source / drain region has a first width in the first direction.

8. The integrated circuit device of claim 1, wherein, The integrated circuit device further includes: a second VFET including the second pair of active regions and a second bottom source / drain region; and a third VFET including the third pair of active regions and a third bottom source / drain region, wherein the second bottom source / drain region and the third bottom source / drain region are first and second portions, respectively, of a common bottom source / drain region, and wherein the first bottom source / drain region and the common bottom source / drain region are spaced apart from each other in the first direction by a third distance, the third distance being shorter than the second distance.

9. An integrated circuit device, comprising: a bottom source / drain region on a substrate; first and second active regions spaced apart from each other in a first direction, wherein the first and second active regions each protrude from an upper surface of the substrate, in plan view the first and second active regions are within the bottom source / drain region, and the second active region is a dummy active region; and a gate structure on a side of the first active region, wherein the gate structure is connected to the first active region, the gate structure is not connected to the second active region.

10. The integrated circuit device of claim 9, wherein, the gate structure is spaced apart from the second active region.

11. The integrated circuit device of claim 9, further comprising an insulating layer on the substrate, wherein, the gate structure is in the insulating layer, and wherein the insulating layer contacts the second active region.

12. The integrated circuit device of claim 9, further comprising: third and fourth active regions spaced apart from each other in the first direction, wherein the third active region is directly adjacent to the second active region in the first direction, wherein the first and second active regions are spaced apart from each other in the first direction by a first distance, and the third and fourth active regions are spaced apart from each other in the first direction by the first distance, and wherein the second and third active regions are spaced apart from each other in the first direction by a second distance, the second distance being longer than the first distance.

13. The integrated circuit device of claim 12, wherein, the integrated circuit device comprises: a first standard cell comprising the first and second active regions; and a second standard cell comprising the third and fourth active regions.

14. The integrated circuit device of claim 9, wherein, the bottom source / drain region is a first bottom source / drain region of a plurality of bottom source / drain regions, and directly adjacent bottom source / drain regions of the plurality of bottom source / drain regions are spaced apart from each other in the first direction by a third distance, wherein the first active region is a first active region of a plurality of active regions, the second active region is a second active region of the plurality of active regions, and the plurality of active regions are spaced apart from each other in the first direction, wherein the plurality of active regions comprises a plurality of groups, and each group of the plurality of groups comprises an even number of active regions of the plurality of active regions, and wherein each bottom source / drain region of the plurality of bottom source / drain regions overlaps with a respective group of active regions of the plurality of groups of the plurality of active regions.

15. The integrated circuit device of claim 9, wherein, the first active region is a first active region of a plurality of active regions, the second active region is a second active region of the plurality of active regions, and the plurality of active regions are spaced apart from each other in the first direction, wherein the plurality of active regions further comprises third and fourth active regions, and The third active region and the fourth active region each include a first portion and a second portion of a single active region, and the single active region further includes a connecting portion between the third active region and the fourth active region and contacting both the third active region and the fourth active region.

16. The integrated circuit device of claim 9, wherein, The first active region is a first active region of a plurality of active regions, the second active region is a second active region of the plurality of active regions, and the plurality of active regions are spaced apart from each other in the first direction, and The plurality of active regions further includes a third active region and a fourth active region, The third active region includes a first main portion extending longitudinally in a second direction different from the first direction and a first protruding portion protruding from the first main portion toward the fourth active region, and The fourth active region includes a second main portion extending longitudinally in the second direction and a second protruding portion protruding from the second main portion toward the third active region.

17. An integrated circuit device, comprising: a plurality of active regions including a first pair of active regions and a second pair of active regions, The first pair of active regions are spaced apart from each other in a first direction, and the second pair of active regions are spaced apart from each other in the first direction, The first pair of active regions and the second pair of active regions are spaced apart from each other in a second direction different from the first direction, and Each active region of the first pair of active regions has a linear shape extending longitudinally in the second direction, and Each active region of the second pair of active regions includes a main portion having a linear shape extending longitudinally in the second direction and a protruding portion protruding from the main portion in the first direction.

Images