Display panel

Abstract

A display panel, comprising: a substrate including an opening region, a display region surrounding the opening region, and an intermediate region between the opening region and the display region; a plurality of display elements in the display region and electrically connected to thin film transistors; a plurality of wirings disposed along an edge of the opening region in the intermediate region; and at least one metal pattern spaced apart from the plurality of wirings in the intermediate region, the at least one metal pattern surrounding the opening region and having an annular shape with an opening on one side.

Description

Technical Field

[0001] Aspects of one or more example embodiments relate to a display panel and a method of manufacturing the display panel. Background Art

[0002] Recently, the applications of display devices have been quite diversified. In addition, since display devices have become thinner and lighter in weight, their usage ranges have gradually expanded.

[0003] When the area occupied by the display region of a display device increases, functions combined with or associated with the display device can be added. As a way of adding various functions while increasing the area, display devices in which various elements can be provided are being studied.

[0004] The above information disclosed in the background section is only for enhancing the understanding of the background, and thus it may include information that does not constitute the prior art. Summary of the Invention

[0005] In the case where a display device has an opening, foreign substances such as moisture can penetrate into the side surface of the opening, and in this case, display elements near the opening may be damaged. One or more example embodiments include a display panel having a structure capable of preventing or reducing the penetration of moisture through the opening, and a method of manufacturing the display panel to reduce various problems including the above problems. However, it should be understood that the example embodiments described herein should be considered only in a descriptive sense and not for limiting the present disclosure.

[0006] Additional aspects will be partially set forth in the following description, and will be partially obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to one or more example embodiments, a display panel includes: a substrate including an opening region, a display region surrounding the opening region, and an intermediate region between the opening region and the display region; a plurality of display elements disposed in the display region and electrically connected to thin film transistors; a plurality of wirings disposed in the intermediate region along an edge of the opening region; and at least one metal pattern disposed in the intermediate region and spaced apart from the plurality of wirings, the at least one metal pattern surrounding the opening region and having an annular shape with an opening on one side.

[0008] According to some example embodiments, the at least one metal pattern may include: a first portion surrounding the opening region; a second portion extending from the first portion and bending toward the opening region; and a third portion extending from the second portion, the third portion having a length corresponding to the width of the second portion, the length being greater than the width of the second portion.

[0009] According to some example embodiments, at least one metal pattern may include: a first portion surrounding an opening region; and a second portion extending from the first portion and curved toward the opening region, wherein the second portion may extend to an edge of a hole corresponding to the opening region.

[0010] According to some example embodiments, at least one metal pattern may be disposed on the same layer as source and drain electrodes of a thin film transistor.

[0011] According to some example embodiments, at least one metal pattern may be disposed on the same layer as a gate electrode of a thin film transistor.

[0012] According to some example embodiments, a display panel may further include a capacitor having a lower electrode disposed on the same layer as a gate electrode of a thin film transistor and an upper electrode at least partially overlapping the lower electrode, with an insulating layer between the lower electrode and the upper electrode, wherein at least one metal pattern may be disposed on the same layer as the upper electrode of the capacitor.

[0013] According to some example embodiments, each of a plurality of display elements may include: a pixel electrode electrically connected to at least one of a source electrode and a drain electrode of a thin film transistor; a counter electrode on the pixel electrode; and an emission layer disposed between the pixel electrode and the counter electrode.

[0014] According to some example embodiments, a display panel may further include: a functional layer between the pixel electrode and the emission layer, between the emission layer and the counter electrode, or between the pixel electrode and the emission layer and between the emission layer and the counter electrode, wherein each of the functional layer and the counter electrode may be cut away at least around at least a portion of a surface of at least one metal pattern.

[0015] According to some example embodiments, a display panel may further include: a package layer covering the plurality of display elements, the package layer including a first inorganic package layer, a second inorganic package layer, and an organic package layer between the first inorganic package layer and the second inorganic package layer.

[0016] According to some example embodiments, at least one metal pattern may include: a first metal pattern disposed closer to a display region than the opening region; and a second metal pattern disposed between the first metal pattern and the opening region, wherein the first inorganic package layer and the organic package layer may be in contact with each other on the first metal pattern, and the first inorganic package layer and the second inorganic package layer may be in contact with each other on the second metal pattern.

[0017] According to one or more exemplary embodiments, a method of manufacturing a display panel includes: forming at least one metal pattern in an intermediate region of a substrate, the substrate including an opening region, a display region surrounding the opening region, and an intermediate region between the opening region and the display region, the at least one metal pattern surrounding the opening region and having an annular shape with an opening on one side; forming pixel electrodes in the display region; forming a peeling pattern on the at least one metal pattern, the peeling pattern being in contact with the at least one metal pattern and having a negative thermal expansion coefficient; sequentially forming an emission layer and a counter electrode to cover the pixel electrodes and the peeling pattern; and separating a portion of the emission layer and the counter electrode together with the peeling pattern from the substrate by applying a current to both ends of the at least one metal pattern and heating the at least one metal pattern.

[0018] According to some exemplary embodiments, the method may further include: forming a thin film transistor in the display region that is electrically connected to the pixel electrode.

[0019] According to some exemplary embodiments, the at least one metal pattern may be disposed on the same layer as the source electrode and the drain electrode of the thin film transistor.

[0020] According to some exemplary embodiments, the at least one metal pattern may be disposed on the same layer as the gate electrode of the thin film transistor.

[0021] According to some exemplary embodiments, the method may further include: forming a capacitor having a lower electrode disposed on the same layer as the gate electrode of the thin film transistor and an upper electrode at least partially overlapping the lower electrode, with an insulating layer between the lower electrode and the upper electrode, wherein the at least one metal pattern may be disposed on the same layer as the upper electrode of the capacitor.

[0022] According to some exemplary embodiments, the peeling pattern may include at least one of polyolefin, propylene-based polymer, and polyester.

[0023] According to some exemplary embodiments, the separation of the portion of the emission layer and the counter electrode may include heating the at least one metal pattern at a temperature of about 100°C to about 150°C.

[0024] According to some exemplary embodiments, the method may further include: forming a encapsulation layer on the counter electrode, the encapsulation layer including a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0025] According to some example embodiments, forming at least one metal pattern may include: forming a first metal pattern closer to the display area than the opening area; and forming a second metal pattern, at least a part of which is located between the first metal pattern and the opening area, wherein the first inorganic encapsulation layer and the organic encapsulation layer may be in contact with each other on the first metal pattern, and the first inorganic encapsulation layer and the second inorganic encapsulation layer may be in contact with each other on the second metal pattern.

[0026] According to some example embodiments, the method may further include: forming a hole corresponding to the opening area, wherein an end portion of the second metal pattern is cut along an edge of the hole. Description of the Drawings

[0027] In conjunction with the drawings, from the following description of the embodiments, these and / or other aspects will become more apparent and easier to understand, wherein:

[0028] Figure 1 is a perspective view of a display device according to some example embodiments;

[0029] Figure 2 is along Figure 1 a cross-sectional view of the display device taken along line II-II';

[0030] Figure 3 is a cross-sectional view of a display panel according to some example embodiments;

[0031] Figure 4 is a plan view of a display panel according to some example embodiments;

[0032] Figure 5 is an equivalent circuit diagram of a pixel of a display panel according to some example embodiments;

[0033] Figure 6 is a plan view of a part of a display panel according to some example embodiments;

[0034] Figures 7A to 7C is along Figure 6 an example of a cross-sectional view of the display panel taken along line VII-VII';

[0035] Figures 8A to 8G is a cross-sectional view sequentially illustrating a manufacturing process of a display panel according to some example embodiments; and

[0036] Figure 9 is along Figure 8B a graph showing physical properties of a material for forming a peeling pattern LO. Detailed Description

[0037] Reference will now be made in more detail to example embodiments illustrated in the accompanying drawings, in which, throughout the specification, like reference numerals refer to like elements. In this regard, the present example embodiments may have different forms and should not be construed as limited to the description set forth herein. Accordingly, the example embodiments are described only by referring to the accompanying drawings to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. When the expression "at least one of" is used after a list of elements, it modifies the entire list of elements and not individual elements of the list.

[0038] Since the present disclosure allows for various changes and many embodiments, example embodiments will be illustrated in the accompanying drawings and described in more detail in the written description. However, it is not intended to limit the present disclosure to a particular practice mode, and it is to be understood that all changes, equivalents, and alternatives included in the present disclosure that do not depart from the spirit and technical scope of the present disclosure. In the description of the present disclosure, when it is considered that certain detailed explanations in the relevant art may unnecessarily obscure the essence of the present disclosure, they are omitted.

[0039] Although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another.

[0040] It will be understood that when a layer, film, region, plate, or component is referred to as being "on" another layer, film, region, plate, or component, it may be formed directly or indirectly on the other layer, film, region, plate, or component. That is, for example, there may be intermediate layers, films, regions, plates, or components.

[0041] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0042] Hereinafter, aspects of some example embodiments will be described with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same reference numerals are used for substantially the same or corresponding elements, and their repeated description is omitted. In the drawings, the thickness is enlarged to clearly illustrate multiple layers and regions. Additionally, in the drawings, for ease of explanation, the thickness of some layers and regions may be exaggerated.

[0043] Figure 1 is a perspective view of a display device 1 according to some example embodiments, and Figure 2 is a cross-sectional view of the display device 1 taken along the line II-II'. Figure 1

[0044] Refer to Figure 1, the display device 1 includes an opening area OA as a first area and a display area DA as a second area that at least partially surrounds the opening area OA. The display device 1 can provide an image by using light emitted from a plurality of pixels provided in the display area DA. Figure 1 shows that an opening area OA is provided within the display area DA, and the opening area OA can be completely surrounded by the display area DA. The opening area OA can be an area where components to be described below with reference to Figure 2 are provided.

[0045] An intermediate area MA as a third area can be provided between the opening area OA and the display area DA, and the display area DA can be surrounded by an outer area PA as a fourth area. The intermediate area MA and the outer area PA can be a non-display area where no pixels are provided. The intermediate area MA can be completely surrounded by the display area DA, and the display area DA can be completely surrounded by the outer area PA.

[0046] Although an organic light-emitting display device is described as an example of the display device 1 according to some of the following exemplary embodiments, the display device 1 is not limited thereto. According to some exemplary embodiments, various types of display devices such as inorganic light-emitting displays and quantum dot light-emitting displays can be used.

[0047] Although Figure 1 shows that an opening area OA is provided and is approximately circular, the embodiments according to the present disclosure are not limited thereto. The number of the opening areas OA can be two or more, and the shape of each of the opening areas OA can be circular, elliptical, polygonal, star-shaped, rhombic, etc., and can be modified differently.

[0048] Referring to Figure 2 , the display device 1 can include a display panel 10, an input detection layer 40, and an optical function layer 50 provided on the display panel 10. These layers can be covered by a window 60. The display device 1 can include various electronic devices such as mobile phones, laptop computers, and smart watches.

[0049] The display panel 10 can display an image. The display panel 10 includes pixels provided in the display area DA. Each of the pixels can include a display element and a pixel circuit connected to the display element. The display element can include an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, etc.

[0050] The input detection layer 40 obtains coordinate information corresponding to an external input (e.g., a touch event). The input detection layer 40 may include detection electrodes (or touch electrodes) and traces connected to the detection electrodes. The input detection layer 40 may be disposed on the display panel 10. The input detection layer 40 may detect an external input using the mutual capacitance method and / or the self-capacitance method.

[0051] The input detection layer 40 may be directly formed on the display panel 10, or may be separately formed and then coupled by using an adhesive layer such as an optically clear adhesive (OCA). For example, the input detection layer 40 may be formed after the process of forming the display panel 10. In this case, the adhesive layer may not be disposed between the input detection layer 40 and the display panel 10. Although Figure 2 it is shown that the input detection layer 40 is disposed between the display panel 10 and the optical function layer 50, according to some example embodiments, the input detection layer 40 may be disposed on the optical function layer 50.

[0052] The optical function layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce the reflectance of light (external light) incident from the outside through the window 60 toward the display panel 10. The anti-reflection layer may include a retarder and a polarizer. The retarder may include a film-type retarder or a liquid crystal coating-type retarder. The retarder may include a λ / 2 retarder and a λ / 4 retarder. The polarizer may include a film-type polarizer or a liquid crystal coating-type polarizer. The film-type polarizer may include a stretchable synthetic resin film, and the liquid crystal coating-type polarizer may include liquid crystals arranged in a predetermined arrangement. Each of the retarder and the polarizer may further include a protective film. The retarder and the polarizer themselves or their protective films may be defined as the base layer of the anti-reflection layer.

[0053] According to some example embodiments, the anti-reflection layer may include a black matrix and a color filter. The color filter may be set by considering the colors of light emitted from the pixels of the display panel 10, respectively. According to some example embodiments, the anti-reflection layer may include a destructive interference structure. The destructive interference structure may include a first reflection layer and a second reflection layer disposed in different layers, respectively. The first reflected light and the second reflected light reflected by the first reflection layer and the second reflection layer, respectively, may generate destructive interference, and thus the reflectance of external light may be reduced.

[0054] The optical function layer 50 may include a lens layer. The lens layer may improve the light emission efficiency of the light emitted from the display panel 10, or reduce the color deviation of light. The lens layer may include a layer having a concave lens or convex lens shape, and / or include a plurality of layers having different refractive indexes, respectively. The optical function layer 50 may include both an anti-reflection layer and a lens layer, or include one of the anti-reflection layer and the lens layer.

[0055] The display panel 10, the input detection layer 40, and / or the optical function layer 50 may include openings. In this regard, Figure 2 It is shown that the display panel 10, the input detection layer 40, and the optical function layer 50 respectively include first to third openings 10H, 40H, and 50H, and the first to third openings 10H, 40H, and 50H of the display panel 10, the input detection layer 40, and the optical function layer 50 overlap each other. The first to third openings 10H, 40H, and 50H are positioned to correspond to the opening region OA. According to some example embodiments, at least one of the display panel 10, the input detection layer 40, and the optical function layer 50 may not include an opening. For example, one or two of the display panel 10, the input detection layer 40, and the optical function layer 50 may not include an opening. Alternatively, the display panel 10, the input detection layer 40, and the optical function layer 50 may not include an opening.

[0056] As described above, the opening region OA may be a kind of component region (such as a sensor region, a camera region, a speaker region, etc.) where the component 20 for adding various functions to the display device 1 is located. As Figure 2 shown, the component 20 may be located in the first to third openings 10H, 40H, and 50H. However, the embodiments according to the present disclosure are not limited thereto, and the component 20 may be disposed under the display panel 10.

[0057] The component 20 may include electronic components. For example, the component 20 may include electronic components using light or sound. For example, the electronic component may be a sensor (such as an infrared sensor) that emits and / or receives light, a camera that receives light and captures an image, a sensor that outputs and detects light or sound to measure distance or identify a fingerprint, a small lamp that outputs light, or a speaker that outputs sound. The electronic component using light may use light in various bands such as visible light, infrared light, and ultraviolet light. According to some example embodiments, the opening region OA may be understood as a transmission region through which light and / or sound transmitted from the component 20 to the outside or propagating from the outside toward the electronic component can pass.

[0058] According to some example embodiments, when the display device 1 is used as a smart watch or a car dashboard, the component 20 may be a member including clock hands or hands indicating predetermined information (such as vehicle speed, etc.). When the display device 1 includes clock hands or a car dashboard, the component 20 may be exposed to the outside through a window 60 including an opening corresponding to the opening region OA.

[0059] As described above, the component 20 may include elements related to the function of the display panel 10, or elements such as accessories that increase the aesthetic sense of the display panel 10. According to some example embodiments, a layer including OCA or the like may be located between the window 60 and the optical function layer 50.

[0060] Figure 3 is a cross-sectional view of a display panel 10 according to some exemplary embodiments.

[0061] Referring to Figure 3 , the display panel 10 includes a display layer 200 disposed on a substrate 100. The substrate 100 may include a glass material or a polymer resin. The substrate 100 may include multiple layers. For example, as shown in the enlarged view of Figure 3 , the substrate 100 may include a first base layer 101, a first barrier layer 102, a second base layer 103, and a second barrier layer 104.

[0062] Each of the first base layer 101 and the second base layer 103 may include a polymer resin. For example, the first base layer 101 and the second base layer 103 may include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), triacetyl cellulose (TAC), or cellulose acetate propionate (CAP). The polymer resin may be transparent.

[0063] Each of the first barrier layer 102 and the second barrier layer 104 may include a barrier layer configured to prevent the penetration of external foreign substances, and includes: a single layer or multiple layers including inorganic materials such as SiN x and / or SiO x .

[0064] The display layer 200 includes a plurality of pixels. The display layer 200 may include a display element layer 200A and a pixel circuit layer 200B. The display element layer 200A includes display elements disposed in each pixel, and the pixel circuit layer 200B includes pixel circuits and insulating layers disposed in each pixel. Each pixel circuit may include a thin film transistor and a storage capacitor. Each display element may include an organic light emitting diode OLED (as shown in Figure 5 ).

[0065] The display elements of the display layer 200 may be covered by a packaging member such as a packaging layer 300, and an inorganic layer 520 is disposed on the packaging layer 300. The inorganic layer 520 may cover the end of the packaging layer 300 in the middle region MA. The inorganic layer 520 may extend further toward the opening region OA than the end of the packaging layer 300 in the middle region MA and contact the layer disposed under the end of the packaging layer 300. The inorganic layer 520 may include an inorganic insulating material, and the inorganic insulating material may include, for example, silicon nitride, silicon oxide, and silicon oxynitride.

[0066] When the display panel 10 includes a substrate 100 and a encapsulation layer 300 that are each multi-layered, the flexibility of the display panel 10 can be improved. The display panel 10 may include a first opening 10H passing through the display panel 10. The first opening 10H may be located in the opening area OA, and in this case, the opening area OA may be a kind of opening area.

[0067] Figure 3 It is shown therein that the substrate 100, the encapsulation layer 300, and the inorganic layer 520 each include through-holes 100H, 300H, and 520H, respectively, and the through-holes 100H, 300H, and 520H each correspond to the first opening 10H. The display layer 200 may include a through-hole 200H corresponding to the opening area OA.

[0068] According to some example embodiments, the substrate 100 may not include a through-hole corresponding to the opening area OA. In this case, the encapsulation layer 300 may include a through-hole 300H corresponding to the opening area OA. The inorganic layer 520 may include a through-hole 520H corresponding to the opening area OA, or may cover the opening area OA while not including a through-hole.

[0069] Although Figure 3 it is shown therein that the display element layer is not provided in the opening area OA, the present disclosure is not limited thereto. According to some example embodiments, an auxiliary display element layer may be located in the opening area OA, and in this case, the auxiliary display element layer may have the same structure and / or operation mode as the display elements of the display element layer 200A, or may have a structure and / or operation mode different from that of the display elements of the display element layer 200A.

[0070] Figure 4 is a plan view of the display panel 10 according to some example embodiments, and Figure 5 is an equivalent circuit diagram of one pixel of the display panel 10 according to some example embodiments.

[0071] Referring to Figure 4 , the display panel 10 may include a display area DA, an opening area OA, an intermediate area MA, and an outer area PA. Figure 4 It can be understood as a diagram of the substrate 100 of the display panel 10. For example, the substrate 100 can be understood to include a display area DA, an opening area OA, an intermediate area MA, and an outer area PA.

[0072] The display panel 10 includes a plurality of pixels P provided in the display area DA. As Figure 5As shown, each pixel P includes a pixel circuit PC and an organic light-emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a first thin-film transistor T1, a second thin-film transistor T2, and a storage capacitor Cst. Each pixel P can emit, for example, red light, green light, or blue light, or red light, green light, blue light, or white light through the organic light-emitting diode OLED.

[0073] The second thin-film transistor T2 is a switching thin-film transistor and is connected to a scan line SL and a data line DL, and can transfer a data voltage input from the data line DL to the first thin-film transistor T1 in response to a switching voltage input from the scan line SL. The storage capacitor Cst can be connected to the second thin-film transistor T2 and a driving voltage line PL, and can store a voltage corresponding to the difference between the voltage transferred from the second thin-film transistor T2 and a first power supply voltage ELVDD supplied to the driving voltage line PL.

[0074] The first thin-film transistor T1 is a driving thin-film transistor and can be connected to the driving voltage line PL and the storage capacitor Cst, and can control a driving current flowing through the organic light-emitting diode OLED from the driving voltage line PL in response to the voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED can emit light with a predetermined brightness by using the driving current. The counter electrode (e.g., cathode) of the organic light-emitting diode OLED can receive a second power supply voltage ELVSS.

[0075] Although Figure 5 it is shown in that the pixel circuit PC includes two thin-film transistors and one storage capacitor, the present disclosure is not limited thereto. The number of thin-film transistors and the number of storage capacitors can be differently modified depending on the design of the pixel circuit PC.

[0076] Referring again to Figure 4 , an intermediate region MA can surround an opening region OA. The intermediate region MA is a region where a display element such as the organic light-emitting diode OLED is not provided, and signal lines configured to supply signals to the pixels P disposed around the opening region OA can pass through the intermediate region MA. A scan driver 1100 configured to supply a scan signal to each pixel P, a data driver 1200 configured to supply a data signal to each pixel P, a main power supply wiring configured to supply a first power supply voltage and a second power supply voltage, etc. can be disposed in an outer region PA. Although Figure 4 it is shown in that the data driver 1200 is adjacent to one side of the substrate 100, the data driver 1200 can be disposed on a flexible printed circuit board (FPCB) electrically connected to pads disposed on one side of the display panel 10.

[0077] Figure 6It is a plan view of a part of a display panel according to some example embodiments.

[0078] Referring to Figure 6 , pixel P is disposed around the opening area OA in the display area DA. Pixels P may be spaced apart from each other around the opening area OA. In the plan view, pixels P may be disposed on the upper side, lower side, left side, and right side with respect to the opening area OA.

[0079] Among the signal lines for supplying signals to pixel P, the signal lines adjacent to the opening area OA may detour around the opening area OA. In Figure 6 's plan view, some data lines DL passing through the display area DA in the data lines DL may extend in the y direction to supply data signals to the pixels P disposed above and below the opening area OA, and may detour along the edge of the opening area OA in the intermediate area MA. In the plan view, some scan lines SL passing through the display area DA in the scan lines SL may extend in the x direction to supply scan signals to the pixels P disposed on the left side and right side of the opening area OA respectively, and may detour along the edge of the opening area OA in the intermediate area MA. In Figure 6 , the areas bent along the edge of the opening area OA respectively correspond to the detour portions of the scan line SL and the detour portions of the data line DL. The detour portion of the scan line SL and / or the detour portion of the data line DL may be integrally formed on the same layer as the extending portion across the display area DA. According to some example embodiments, the detour portion of the scan line SL and / or the detour portion of the data line DL may be formed on a layer different from the extending portion across the display area DA, and are electrically connected to the extending portion via contact holes.

[0080] At least one metal pattern HM1 and HM2 are disposed in the intermediate area MA to be spaced apart from the above-mentioned scan line SL and data line DL. At least one metal pattern HM1 and HM2 surround the opening area OA and have a substantially annular shape. In this case, the annulus may correspond to the edge shape of the opening area OA, but may be different from the edge shape of the opening area OA. The annulus is not limited to a circle and may be differently changed into an ellipse, a polygon, etc.

[0081] The annulus is a shape with one side open, and thus, the two side ends of at least one metal pattern HM1 and HM2 may be spaced apart from each other to form an opening OP.

[0082] According to some example embodiments, at least one of the metal patterns HM1 and HM2 may include a first metal pattern HM1 and a second metal pattern HM2. The first metal pattern HM1 is positioned adjacent to the display area DA closer to the display area DA than the opening area OA. The second metal pattern HM2 is a pattern disposed between the first metal pattern HM1 and the opening area OA, and is positioned closer to the opening area OA than the display area DA.

[0083] For example, as Figure 6 shown, the first metal pattern HM1 may be disposed between the bypass portions of the scan line SL and the data line DL and the display area DA described above.

[0084] According to some example embodiments, the first metal pattern HM1 may include a first portion HM1-1, a second portion HM1-2, and a third portion HM1-3. The first portion HM1-1 is a portion surrounding the opening area OA, and represents a curved portion having an annular shape. In this case, the first portion HM1-1 may have a shape corresponding to the bypass portions of at least some of the scan line SL and the data line DL described above.

[0085] The second portion HM1-2 may be a portion extending from the first portion HM1-1 and curved toward the opening area OA. In this case, the second portion HM1-2 may be straight, different from the first portion HM1-1, and according to some example embodiments, the second portion HM1-2 may extend in the y direction which is the extending direction of the data line DL in the display area DA. The opening OP of the first metal pattern HM1 described above may be a space between the second portion HM1-2 which is a side end portion of the first metal pattern HM1 and the second portion HM1-2 which is an opposing side end portion of the first metal pattern HM1.

[0086] The third portion HM1-3 may be an end portion of the first metal pattern HM1 extending from the second portion HM1-2. In this case, the length of the third portion HM1-3 defined in the x direction may be greater than the width of the second portion HM1-2 defined in the x direction. Specifically, the third portion HM1-3 may be a portion extending from the second portion HM1-2 and curved toward the outside of the opening OP. The third portion HM1-3 may be greater in size or area than the second portion HM1-2. This is so that the first metal pattern HM1 is electrically connected to an external power supply through the third portion HM1-3, and by increasing the width, size, or area of the third portion HM1-3, the current applied from the external power supply can flow through the first portion HM1-1 and the second portion HM1-2 of the first metal pattern HM1. Accordingly, the third portion HM1-3 may be provided with a contact portion CNT for contacting a probe or the like for supplying an external power supply.

[0087] AsFigure 6 As shown in Figure 6 , the second metal pattern HM2 may be disposed between the bypass portions of the scan line SL and the data line DL and the opening region OA.

[0088] According to some example embodiments, the second metal pattern HM2 may include a first portion HM2-1 and a second portion HM2-2C. The first portion HM2-1 of the second metal pattern HM2 may be a curved portion having an annular shape surrounding the opening region OA, similar to the first portion HM1-1 of the first metal pattern HM1. Thus, the first portion HM2-1 may also have a shape corresponding to the bypass portions of at least some of the scan line SL and the data line DL described above.

[0089] The second portion HM2-2C of the second metal pattern HM2 may be a portion extending from the first portion HM2-1 of the second metal pattern HM2 and bending toward the opening region OA, similar to the second portion HM1-2 of the first metal pattern HM1. In this case, the second portion HM2-2C may be straight, different from the first portion HM2-1, and according to some example embodiments, the second portion HM2-2C may extend in the y direction, which is the extending direction of the data line DL in the display region DA. Similar to the first metal pattern HM1, the second metal pattern HM2 may have an opening defined as a space between the second portions HM2-2C located at two side ends of the second metal pattern HM2.

[0090] However, different from the first metal pattern HM1, the second metal pattern HM2 may not have a portion corresponding to the third portion HM1-3 of the first metal pattern HM1 and may extend to the edge of the opening region OA. Thus, the second portion HM2-2C of the second metal pattern HM2 may be an end portion of the second metal pattern HM2.

[0091] Hereinafter, with reference to Figures 7A to 7C , the positions of at least one of the metal patterns HM1 and HM2 will be described in detail.

[0092] Figures 7A to 7C is an example of a cross-sectional view taken along line VII-VII' of the display panel along Figure 6 .

[0093] With reference to Figure 7A of the display region DA, the substrate 100 may include a polymer resin. According to some example embodiments, the substrate 100 may include the multi-layer described above with reference to Figure 3 .

[0094] A buffer layer 201 configured to prevent impurities from penetrating into the semiconductor layer Act of the thin film transistor TFT may be provided on the substrate 100. The buffer layer 201 may include, for example, silicon nitride (SiNx )、Silicon oxynitride (SiON) and silicon oxide (SiO x ) inorganic insulating materials, and may include: a single layer or multiple layers including the above inorganic insulating materials.

[0095] The pixel circuit PC may be disposed on the buffer layer 201. The pixel circuit PC includes a thin film transistor TFT and a storage capacitor Cst. The thin film transistor TFT may include a semiconductor layer Act, a gate electrode GE, a source electrode SE, and a drain electrode DE. Figure 7A The thin film transistor TFT shown in Figure 5 corresponds to the driving thin film transistor described with reference to. Although the present embodiment shows a top-gate type thin film transistor in which the gate electrode GE is disposed above the semiconductor layer Act and the gate insulating layer 203 is between the gate electrode GE and the semiconductor layer Act, according to some exemplary embodiments, the thin film transistor TFT may be a bottom-gate type thin film transistor.

[0096] The semiconductor layer Act may include polysilicon. Alternatively, the semiconductor layer Act may include amorphous silicon, an oxide semiconductor, or an organic semiconductor. The gate electrode GE may include a low-resistance metal material. The gate electrode GE may include: a conductive material including at least one of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may include: a single layer or multiple layers including the above materials.

[0097] The gate insulating layer 203 between the semiconductor layer Act and the gate electrode GE may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The gate insulating layer 203 may include: a single layer or multiple layers including the above materials.

[0098] The source electrode SE and the drain electrode DE may include materials with good conductivity. The source electrode SE and the drain electrode DE may include: a conductive material including at least one of Mo, Al, Cu, and Ti, and may include: a single layer or multiple layers including the above materials. According to some exemplary embodiments, the source electrode SE and the drain electrode DE may include a multilayer of Ti / Al / Ti.

[0099] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2 that overlap each other, and a first interlayer insulating layer 205 is between the lower electrode CE1 and the upper electrode CE2. The storage capacitor Cst may overlap with the thin film transistor TFT. Regarding this point, Figure 7AThe gate electrode GE of the thin film transistor TFT is shown as the lower electrode CE1 of the storage capacitor Cst. According to some example embodiments, the storage capacitor Cst may not overlap with the thin film transistor TFT. The storage capacitor Cst may be covered by the second interlayer insulating layer 207. The upper electrode CE2 may include: a conductive material including at least one of Mo, Al, Cu, and Ti, and may include: a single layer or multiple layers including the above materials.

[0100] The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, and hafnium oxide. The first interlayer insulating layer 205 and the second interlayer insulating layer 207 may include: a single layer or multiple layers including the above materials.

[0101] The pixel circuit PC including the thin film transistor TFT and the storage capacitor Cst may be covered by the planarization insulating layer 209. The planarization insulating layer 209 may include an approximately flat top surface. The planarization insulating layer 209 may include an organic insulating material, and the organic insulating material includes general polymers such as polymethyl methacrylate (PMMA) and polystyrene (PS), polymer derivatives having a phenolic group, allyl polymers, imide-based polymers, aryl ether-based polymers, amide-based polymers, fluorine-based polymers, parylene polymers, vinyl alcohol-based polymers, or mixtures thereof. According to some example embodiments, the planarization insulating layer 209 may include polyimide. Alternatively, the planarization insulating layer 209 may include an inorganic insulating material, or an inorganic insulating material and an organic insulating material.

[0102] The pixel electrode 221 may be formed on the planarization insulating layer 209. The pixel electrode 221 may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). According to some example embodiments, the pixel electrode 221 may include: a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof. According to some example embodiments, the pixel electrode 221 may further include a layer including ITO, IZO, ZnO, or In 2 O 3 on / under the reflective layer.

[0103] The pixel defining layer 211 may be formed on the pixel electrode 221. The pixel defining layer 211 may include an opening that exposes the top surface of the pixel electrode 221 and covers the edge of the pixel electrode 221. The pixel defining layer 211 may include an organic insulating material. Alternatively, the pixel defining layer 211 may include silicon nitride (SiNx ) an inorganic insulating material of silicon oxynitride (SiON) and silicon oxide (SiO x ). Alternatively, the pixel defining layer 211 may include an organic insulating material and an inorganic insulating material.

[0104] The intermediate layer 222 includes an emission layer 222b. The intermediate layer 222 may include a first functional layer 222a disposed under the emission layer 222b and / or a second functional layer 222c disposed on the emission layer 222b. The emission layer 222b may include a polymer or a low molecular weight organic material that emits light of a predetermined color.

[0105] The first functional layer 222a may include a single layer or multiple layers. For example, when the first functional layer 222a includes a polymer material, the first functional layer 222a includes a hole transport layer (HTL), the hole transport layer (HTL) has a single layer structure, and may include poly-(3,4)-ethylenedioxythiophene (PEDOT) or polyaniline (PANI). When the first functional layer 222a includes a low molecular weight material, the first functional layer 222a may include a hole injection layer (HIL) and an HTL.

[0106] The second functional layer 222c may be omitted. For example, when the first functional layer 222a and the emission layer 222b include polymer materials, the second functional layer 222c may be provided. The second functional layer 222c may include a single layer or multiple layers. The second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0107] The emission layer 222b of the intermediate layer 222 may be provided for each pixel in the display area DA. The emission layer 222b may contact the top surface of the pixel electrode 221 exposed through the opening of the pixel defining layer 211. Different from the emission layer 222b, the first functional layer 222a and the second functional layer 222c of the intermediate layer 222 may be provided not only in the display area DA but also in the intermediate area MA.

[0108] The counter electrode 223 may include a conductive material having a low work function. For example, the counter electrode 223 may include: a (semi)transparent layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, or an alloy thereof. Alternatively, the counter electrode 223 may further include a layer including ITO, IZO, ZnO, or In 2 O 3 on the (semi)transparent layer including the above materials. The counter electrode 223 may be provided not only in the display area DA but also in the intermediate area MA. The intermediate layer 222 and the counter electrode 223 may be formed by a thermal deposition method.

[0109] The capping layer 230 may be disposed on the counter electrode 223. For example, the capping layer 230 may include LiF and may be formed by a thermal deposition method. The capping layer 230 may be omitted.

[0110] The spacer 213 may be provided on the pixel defining layer 211. The spacer 213 may include an organic insulating material such as polyimide. Alternatively, the spacer 213 may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include an organic insulating material and an inorganic insulating material.

[0111] The spacer 213 may include a material different from that of the pixel defining layer 211. Alternatively, the spacer 213 may include the same material as that of the pixel defining layer 211. In this case, the pixel defining layer 211 and the spacer 213 may be formed simultaneously during a mask process using a halftone mask or the like. According to some example embodiments, the pixel defining layer 211 and the spacer 213 may include polyimide.

[0112] The organic light emitting diode OLED is covered by the encapsulation layer 300. The encapsulation layer 300 may include at least one organic encapsulation layer and at least one inorganic encapsulation layer 300IL, and Figure 7A shows that the encapsulation layer 300 includes a first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330. According to some example embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be modified.

[0113] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulating materials such as alumina, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, or silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include: a single layer or multiple layers including the above materials. The organic encapsulation layer 320 may include a polymer-based material. The polymer-based material may include an acrylic-based resin, an epoxy-based resin, polyimide, and polyethylene. The thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. For example, the thickness of the first inorganic encapsulation layer 310 may be about 1 μm, and the thickness of the second inorganic encapsulation layer 330 may be about 0.7 μm. Alternatively, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thicknesses of the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be equal to each other.

[0114] Referring to Figure 7A the middle region MA, as referred to above Figure 6At least one of the described metal patterns HM1 and HM2 is disposed in the intermediate region MA. In this case, if the region where the bypass portions of the scan line SL and the data line DL shown in Figure 6 is the second intermediate region MA2, the region at the side of the display region DA can be defined as the first intermediate region MA1, and the region at the side of the opening region OA can be defined as the third intermediate region MA3, with the second intermediate region MA2 between the first intermediate region MA1 and the third intermediate region MA3. Accordingly, the first metal pattern HM1 can be disposed in the first intermediate region MA1, and the second metal pattern HM2 can be disposed in the third intermediate region MA3.

[0115] Since the cross-section of the display panel is taken along the line VII-VII’ of Figure 6 , with reference to Figure 6 the scan line SL described is shown in Figure 7A to be disposed in the second intermediate region MA2. That is, when the display panel of Figure 6 is cut along a line different from the line VII-VII’, the data line (i.e., the data line DL in Figure 6 ) and the scan line SL can be illustrated as being together in the second intermediate region MA2, or only the data line (i.e., the data line DL in Figure 6 ) can be illustrated in the second intermediate region MA2.

[0116] Although the scan line SL is shown in Figure 7A to be formed on the same layer as the gate electrode GE of the thin film transistor TFT or the lower electrode CE1 of the storage capacitor Cst, the scan line can be formed on the same layer as the upper electrode CE2 of the storage capacitor Cst. According to some example embodiments, the data line (i.e., the data line DL in Figure 6 ) can be formed on the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT. In this case, the data line (i.e., the data line DL in Figure 6 ) and the scan line SL can be arranged to be in different layers.

[0117] According to the embodiment shown in Figure 7A , the first metal pattern HM1 and the second metal pattern HM2 can be disposed on the same layer as the source electrode SE and the drain electrode DE of the thin film transistor TFT. In this case, the first metal pattern HM1 and the second metal pattern HM2 can include the same material as the source electrode SE and the drain electrode DE, for example, a conductive material including at least one of Mo, Al, Cu, Ti, etc. According to some example embodiments, the first metal pattern HM1 and the second metal pattern HM2 can have a multi-layer structure of Ti / Al / Ti.

[0118] In this embodiment, the pixel defining layer 211 and the planarization insulating layer 209 on the first metal pattern HM1 may be removed or omitted, and thus, a common layer CL such as a part of the intermediate layer 222, the counter electrode 223, and the capping layer 230 may be sequentially formed on the metal pattern HM1. For example, a part of the intermediate layer 222 may include a first functional layer 222a and a second functional layer 222c.

[0119] The common layer CL may be integrally formed to cover the display area DA and the intermediate area MA, and each of the common layers CL may be formed by thermal evaporation. In this case, an organic material, which is a material of the first functional layer 222a and the second functional layer 222c of the common layer CL, may provide a path through which moisture permeates. However, according to an embodiment, as Figure 7A shown, since the first functional layer 222a and the second functional layer 222c are cut away at least around each of the first metal pattern HM1 and the second metal pattern HM2, moisture permeation to the organic light emitting diode OLED may be prevented through the first functional layer 222a and / or the second functional layer 222c.

[0120] Specifically, the second metal pattern HM2 is a pattern closer to the opening area OA than the display area DA, and moisture permeation may be mainly blocked at the position of the second metal pattern HM2. For example, when the common layer CL is cut away around the second metal pattern HM2, moisture permeation that may permeate through the first opening 10H when the first opening 10H is formed at the edge of the opening area OA as the cutting line L is prevented from permeating into the intermediate area MA.

[0121] The first metal pattern HM1 is a pattern closer to the display area DA than the opening area OA, and moisture permeation may be additionally blocked at the first metal pattern HM1. For example, when the common layer CL is cut away around the first metal pattern HM1, moisture that permeates despite the presence of the second metal pattern HM2 or moisture that permeates through a path other than the first opening 10H is prevented from permeating into the display area DA.

[0122] After the first functional layer 222a and the second functional layer 222c, the counter electrode 223, and the capping layer 230 are formed, a first inorganic encapsulation layer 310 is formed. The first inorganic encapsulation layer 310 covers the disconnected part of the common layer CL and extends to the opening area OA. That is, the first inorganic encapsulation layer 310 may be formed to substantially span the entire surface of the substrate 100.

[0123] The barrier wall 410 is disposed between the first metal pattern HM1 and the second metal pattern HM2. The barrier wall 410 serves as a dam to prevent monomers, which are materials for forming the organic encapsulation layer 320, from overflowing toward the opening region OA. Accordingly, an end portion of the organic encapsulation layer 320 is positioned adjacent to a wall surface of the barrier wall 410 at a side edge of the display region DA. That is, the organic encapsulation layer 320 may not be disposed in a region between the barrier wall 410 and the opening region OA.

[0124] The second inorganic encapsulation layer 330 is formed on the organic encapsulation layer 320. The second inorganic encapsulation layer 330 covers a disconnected portion of the common layer CL and extends to the opening region OA, similar to the first inorganic encapsulation layer 310. The second inorganic encapsulation layer 330 is also formed together with the first inorganic encapsulation layer 310 to substantially span the entire surface of the substrate 100, thereby preventing moisture and foreign substances from penetrating into the organic light-emitting diode OLED.

[0125] When the encapsulation layer 300 is formed as described above, an encapsulation structure in which the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 are sequentially stacked may be directly formed on the first metal pattern HM1. Accordingly, a space between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 above the first metal pattern HM1 is filled with the organic encapsulation layer 320, and the organic encapsulation layer 320 contacts the first inorganic encapsulation layer 310.

[0126] On the other hand, since the second metal pattern HM2 is not covered by the organic encapsulation layer 320, an encapsulation structure in which the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 are sequentially stacked may be directly formed on the second metal pattern HM2. Accordingly, the second inorganic encapsulation layer 330 contacts the first inorganic encapsulation layer 310 on the second metal pattern HM2.

[0127] Figure 7B and Figure 7C The embodiment shown in Figure 7A is substantially the same as the embodiment described above with reference to Figure 7A except for the positions of the first metal pattern HM1 and the second metal pattern HM2. Accordingly, the following description focuses on the differences from the embodiment shown in Figure 7A and simplifies or omits the description overlapping with the embodiment shown in

[0128] In addition, in Figure 7BIn the display panel 10' shown in [FIG.], common layers CL such as a first functional layer 222a, a second functional layer 222c, a counter electrode 223, and a capping layer 230 are cut away around each of a first metal pattern HM1' and a second metal pattern HM2', and thus moisture can be prevented from penetrating into an intermediate region MA and a display region DA through a first opening 10H.

[0129] In the present embodiment, each of the first metal pattern HM1' and the second metal pattern HM2' may be disposed on the same layer as a gate electrode GE of a thin film transistor TFT or a lower electrode CE1 of a storage capacitor Cst. In this case, the first metal pattern HM1' and the second metal pattern HM2' may be disposed on the same layer as a scan line SL.

[0130] In this case, the first metal pattern HM1' and the second metal pattern HM2' may include a low-resistance material of the same material as the gate electrode GE. For example, the first metal pattern HM1' and the second metal pattern HM2' may include: a conductive material including at least one of Mo, Al, Cu, and Ti, and may include: a single layer or multiple layers including the above materials.

[0131] In addition, in Figure 7C the display panel 10” shown in [FIG.], common layers CL such as a first functional layer 222a, a second functional layer 222c, a counter electrode 223, and a capping layer 230 are cut away around each of a first metal pattern HM1” and a second metal pattern HM2”, and thus moisture can be prevented from penetrating into the display region DA.

[0132] In the present embodiment, each of the first metal pattern HM1” and the second metal pattern HM2” may be disposed on the same layer as an upper electrode CE2 of a storage capacitor Cst. In this case, the first metal pattern HM1” and the second metal pattern HM2” may be disposed on the same layer as Figure 6 a data line DL or a scan line SL in [FIG.].

[0133] In this case, the first metal pattern HM1” and the second metal pattern HM2” may include the same material as the upper electrode CE2 of the capacitor Cst (for example, a conductive material including at least one of Mo, Al, Cu, and Ti), and may include: a single layer or multiple layers including the above materials.

[0134] Hereinafter, a manufacturing process of a display panel according to some exemplary embodiments will be described in detail with reference to Figures 8A to 8G FIGS.

[0135] Figures 8A to 8G are cross-sectional views sequentially illustrating a manufacturing process of a display panel according to some exemplary embodiments.

[0136] Specifically, Figures 8A to 8G the sequential diagram illustrates a process of forming an upper layer of the second metal pattern HM2 on the second metal pattern HM2 shown in Figure 6 , and for convenience of description, a part of a display panel including an opening area OA and a third intermediate area MA3 (e.g., the third intermediate area MA3 in Figures 8A to 8G ) surrounding the opening area OA is shown in Figure 7A . Figures 8A to 8G The cross-sectional view CSV of each of those in Figure 7A refers to the view defined in the xz plane shown in Figures 8A to 8G , and the plan view PV of each of those in Figure 6 refers to the view defined in the xy plane shown in

[0137] First, as shown in the cross-sectional view CSV of Figure 8A , a base substrate 100B is prepared and the second metal pattern HM2 is formed on the base substrate 100B. The base substrate 100B refers to the substrate 100 in the state where the buffer layer 201, the gate insulating layer 203, the first interlayer insulating layer 205, and the second interlayer insulating layer 207 described in Figure 7A are stacked.

[0138] According to some exemplary embodiments, the second metal pattern HM2 may be formed on the same layer as the Figure 7A source electrode SE etc. of the thin film transistor TFT in Figure 7A or the Figure 7A drain electrode DE etc. in Figure 7A , and may include the same material as the Figure 7A source electrode SE etc. or the

[0139] drain electrode DE etc. in Figure 6 . At this stage, the second metal pattern HM2 may have the same shape as the first metal pattern HM1 shown in Figure 8A . Referring to the plan view PV of

[0140] The first part HM2-1 has a curved part in a ring shape around the opening area OA and can be retained without being cut off in subsequent processes. The second part HM2-2 is a part extending from the first part HM2-1 and bent toward the opening area OA, and the third part HM2-3 is a part extending from the second part HM2-2 and corresponding to the end of the second metal pattern HM2 at this stage. In this case, the length w2 corresponding to the width w1 of the second part HM2-2 of the third part HM2-3 can be greater than the width w1 of the second part HM2-2. The third part HM2-3 can have a larger size or a larger area than the second part HM2-2.

[0141] Next, as shown in the cross-sectional view CSV of Figure 8B , a peeling pattern LO is formed on the second metal pattern HM2. The peeling pattern LO is separated from the second metal pattern HM2 in subsequent processes, and although the peeling pattern LO is shown in the cross-sectional view CSV of Figure 8B to be formed narrower than the upper surface of the second metal pattern HM2, the present disclosure is not limited thereto. That is, the peeling pattern LO can be formed to cover at least the entire upper surface of the second metal pattern HM2.

[0142] Referring to the plan view PV of Figure 8B , the peeling pattern LO can be formed in a shape corresponding to the first part HM2-1 of the second metal pattern HM2 and can have an annular shape with a closed curve form without one side being open, different from the second metal pattern HM2.

[0143] According to some example embodiments, the peeling pattern LO can include a material having a negative thermal expansion coefficient, for example, polyolefin, acrylic polymer, polyester, or a combination of at least one of them.

[0144] According to some example embodiments, a separable layer can be further provided between the peeling pattern LO and the second metal pattern HM2. The separable layer can be used to facilitate separation, and the material, size, etc. of the separable layer can be differently changed according to the physical properties of each of the peeling pattern LO and the second metal pattern HM2 and other process conditions.

[0145] This operation is performed before forming the intermediate layer 222 (for example, the first functional layer 222a and the second functional layer 222c in Figure 7A ) of the organic light-emitting diode OLED, and according to some example embodiments, this operation can be immediately performed after forming the pixel defining layer 211 in Figure 7A . Figure 7A

[0146] Next, as shown in Figure 8CAs shown in the cross-sectional view CSV, a common layer CL is formed on the peeling pattern LO. The common layer CL may include Figure 7A a part of the intermediate layer 222 in Figure 7A such as the first functional layer 222a and the second functional layer 222c in Figure 7A the counter electrode 223 in Figure 7A the capping layer 230 in

[0147] The common layer CL may be formed to substantially span the entire surface of the base substrate 100B. Thus, Figure 8C the second metal pattern HM2 and the peeling pattern LO in the plan view PV of

[0148] Next, as shown in the cross-sectional view CSV and the plan view PV of Figure 8D an external power supply E is supplied to the second metal pattern HM2 which is the lower layer of the peeling pattern LO.

[0149] At this stage, the external power supply E may be supplied to the second metal pattern HM2 in various ways. According to some exemplary embodiments, a method of forming holes in a part TH of the common layer CL directly above the peeling pattern LO and bringing a probe with a sharp shape into contact with the second metal pattern HM2 may be used. In this case, the probe may contact the third part HM2-3 of the second metal pattern HM2. To this end, the width, size or area of the third part HM2-3 of the second metal pattern HM2 may be greater than the width, size or area of the second part HM2-2 so that current can flow quickly to the second part HM2-2 and the first part HM2-1.

[0150] However, the method of supplying the external power supply E is not limited thereto. According to some exemplary embodiments, a method of forming contact holes in at least a part of the base substrate 100B and bringing the second metal pattern HM2 into contact with the external power supply through the contact holes may be used.

[0151] As a result, as shown in the cross-sectional view CSV of Figure 8D current is applied to the second metal pattern HM2, and thus heat HEAT is generated at the interface between the second metal pattern HM2 and the peeling pattern LO. The heat HEAT may be Joule heat generated by the current in the conductor.

[0152] As described with reference to Figure 8B the peeling pattern LO may have a negative coefficient of thermal expansion. As a result, when heat is generated in the second metal pattern HM2 and the temperature of the peeling pattern LO increases, a contraction stress is generated in the peeling pattern LO substantially in the direction of the arrow shown in the peeling pattern LO.

[0153] Next, as shown in Figure 8EAs shown in the cross-sectional view CSV and the plan view PV, due to the shrinkage stress caused by thermal shrinkage, the peeling pattern LO can be separated from the second metal pattern HM2. In this case, a part of the common layer CL located above the peeling pattern LO can be broken and separated from the second metal pattern HM2 together with the peeling pattern LO. As a result, the remaining part of the common layer CL can be retained on the surface of the second metal pattern HM2, and at least a part of the common layer CL around the surface (e.g., the upper surface of the second metal pattern HM2) of the second metal pattern HM2 is cut off.

[0154] At this stage, the two cut ends of the common layer CL can have a fracture surface FS with irregular roughness.

[0155] Subsequently, as Figure 8F shown in the cross-sectional view CSV and the plan view PV, an encapsulation layer is formed to substantially cover the entire surface of the base substrate 100B. The encapsulation layer can include the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 described above with reference to Figure 7A . However, since only the opening area OA and the third intermediate area MA3 adjacent to the opening area OA are shown in Figure 8F , the encapsulation layer formed on the base substrate 100B can include: a stacked structure 300IL including the first inorganic encapsulation layer 310 in Figure 7A and the second inorganic encapsulation layer 330 in Figure 7A .

[0156] Subsequently, as Figure 8G shown in the cross-sectional view CSV and the plan view PV, the base substrate 100B and the layers on the base substrate 100B are cut along a cutting line L corresponding to the edge of the opening area OA. As a result, a first opening 10H is formed in the opening area OA, and since the common layer CL is cut off around at least a part of the surface of the second metal pattern HM2, moisture is difficult to penetrate through the first opening 10H.

[0157] As described above, when the opening area OA is cut, the third part HM2-3 of the second metal pattern HM2 (see Figure 8F ) and a part of the second part HM2-2 (see Figure 8F ) can also be removed. As a result, as Figure 8G shown, the second metal pattern HM2 has a first part HM2-1 and a cut second part HM2-2C.

[0158] Referring to Figure 6 the first metal pattern HM1 described above can also be formed by a process similar to the process shown in Figures 8A to 8G . However, in the case of the first metal pattern HM1 in Figure 6 , even if asFigure 8G The opening area OA shown therein is cut, Figure 6 the first part HM1-1 in Figure 6 the second part HM1-2 in Figure 6 and the third part HM1-3 in

[0159] Figure 9 is a graph showing the physical properties of the material for forming the Figure 8B peeling pattern LO in

[0160] Referring to Figure 9 , the x-axis of the graph represents the temperature change of the material for forming the peeling pattern LO, and the y-axis of the graph represents the linear shrinkage rate of the material for forming the peeling pattern LO.

[0161] The first line G1 shows the change in the physical properties of polyolefin as one of the materials for forming the peeling pattern LO, and the second line G2 shows the change in the physical properties of a polypropylene polymer as one of the materials for forming the peeling pattern LO.

[0162] Due to the first line G1 and the second line G2, when the temperature range of the material for forming the peeling pattern LO is from about 100 °C to about 150 °C, the change in the linear shrinkage rate is relatively large, and thus, the temperature range of about 100 °C to about 150 °C can be regarded as the effective temperature Te at which the peeling pattern LO can be mainly affected by shrinkage stress.

[0163] When this physical property data is applied to the Figure 8D process shown in Figure 6 , the peeling pattern LO can be easily separated when the second metal pattern HM2 is heated at a temperature of about 100 °C to about 150 °C. Therefore, by adjusting the amount of current applied to the Figure 8D first metal pattern HM1 and the second metal pattern HM2 shown in

[0164] so that the first metal pattern HM1 and the second metal pattern HM2 are heated at a temperature of about 100 °C to about 150 °C, the cutting operation of the common layer CL in

[0165] As described above, the display panel according to some example embodiments can prevent or reduce the penetration of foreign substances such as moisture into the side surfaces of the openings formed in the display device and damage to the display elements surrounding the openings.

[0166] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. The description of a feature or aspect within each embodiment is generally to be considered as applicable to other similar features or aspects in other embodiments.

[0167] Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the appended claims and their equivalents.

Claims

1. A display panel, comprising: a substrate including an opening region, a display region surrounding the opening region, and an intermediate region between the opening region and the display region; a plurality of display elements in the display region, each of the plurality of display elements being electrically connected to a thin film transistor; a plurality of wirings disposed along an edge of the opening region in the intermediate region; and at least one metal pattern spaced apart from the plurality of wirings in the intermediate region, in a plan view, the at least one metal pattern surrounding the opening region and having an annular shape with an opening on one side.

2. The display panel according to claim 1, wherein the at least one metal pattern includes: a first portion surrounding the opening region; a second portion extending from the first portion and bending toward the opening region; and a third portion extending from the second portion, the third portion having a length corresponding to the width of the second portion, the length being greater than the width of the second portion.

3. The display panel according to claim 1, wherein the at least one metal pattern includes: a first portion surrounding the opening region; and a second portion extending from the first portion and bending toward the opening region, wherein the second portion extends to an edge of a hole corresponding to the opening region.

4. The display panel according to claim 1, wherein the at least one metal pattern and source and drain electrodes of the thin film transistor are disposed on the same layer.

5. The display panel according to claim 1, wherein the at least one metal pattern and a gate electrode of the thin film transistor are disposed on the same layer.

6. The display panel according to claim 1, further comprising: a capacitor having a lower electrode disposed on the same layer as the gate electrode of the thin film transistor and an upper electrode at least partially overlapping the lower electrode, wherein the at least one metal pattern and the upper electrode of the capacitor are disposed on the same layer.

7. The display panel according to claim 1, wherein each of the plurality of display elements includes: a pixel electrode electrically connected to at least one of the source and drain electrodes of the thin film transistor; a counter electrode on the pixel electrode; and an emission layer between the pixel electrode and the counter electrode.

8. The display panel according to claim 7, further comprising: a functional layer between the pixel electrode and the emission layer, between the emission layer and the counter electrode, or between the pixel electrode and the emission layer and between the emission layer and the counter electrode, wherein each of the functional layer and the counter electrode is cut away at least partially around a surface of the at least one metal pattern.

9. The display panel according to claim 1, further comprising: a packaging layer covering the plurality of display elements, the packaging layer including a first inorganic packaging layer, a second inorganic packaging layer, and an organic packaging layer between the first inorganic packaging layer and the second inorganic packaging layer.

10. The display panel according to claim 9, wherein, the at least one metal pattern includes: a first metal pattern disposed closer to the display area than the opening area; and a second metal pattern between the first metal pattern and the opening area, wherein the first inorganic encapsulation layer and the organic encapsulation layer are in contact with each other on the first metal pattern, and the first inorganic encapsulation layer and the second inorganic encapsulation layer are in contact with each other on the second metal pattern.

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