Method for operating a power converter

Abstract

A method for operating a power converter is provided. The method includes operating the power converter (10) in a reduced switching mode. The power converter includes: three input nodes (A, B, C), each input node being configured to receive a respective one of three input voltages (V1, V2, V3); two DC link nodes (X, Z), configured to provide a DC link voltage (V4); a midpoint (Y), coupled to each of the two DC link nodes (X, Z); three inductors (L1, L2, L3), each inductor being connected to a respective one of the three input nodes (A, B, C); and a rectifier bridge (1), including three bridge arms (11, 12, 13), each bridge arm being coupled to a respective one of the three input nodes (A, B, C) through a respective one of the three inductors (L1, L2, L3) and being connected to a respective one of the three inductors (L1, L2, L3) at a respective switching node (A', B', C'), wherein each of the three bridge arms (11, 12, 13) is further connected to the two DC link nodes (X, Z) and the midpoint (Y) and includes at least one electronic switch (Q1, Q2, Q3). Operating the power converter in a reduced switching mode includes deactivating at least one of the three bridge arms (11, 12, 13) during a predefined time period.

Description

Technical Field

[0001] The present disclosure generally relates to methods for operating a power converter. Background Art

[0002] Efficient power conversion using an electronic power converter is an important issue in many electronic applications. For example, charging the battery of an electric vehicle requires efficient power conversion, and this is becoming increasingly important as the number of various electric vehicles (cars, bicycles, scooters, etc.) is expected to increase in the coming years. In this type of application, as well as in any other type of power conversion application, it is desirable to keep the losses associated with power conversion as low as possible, that is, to keep the losses occurring in the power converter and associated with operating the power converter as low as possible. Summary of the Invention

[0003] One example relates to a method. The method includes operating a power converter in a reduced switching mode. The power converter includes three input nodes, each configured to receive a respective one of three input voltages; two DC link nodes configured to provide a DC link voltage; and a midpoint coupled to each of the two DC link nodes. In addition, the power converter includes three inductors, each inductor connected to a respective one of the three input nodes; and a rectifier bridge including three bridge arms. Each bridge arm is coupled to a respective one of the three input nodes through a respective one of the three inductors and is connected to a respective one of the three inductors at a respective switching node. Each of the three bridge arms is also connected to the two DC link nodes and the midpoint and includes at least one electronic switch. Operating the power converter in a reduced switching mode includes deactivating at least one of the three bridge arms during a predefined time period. Brief Description of the Drawings

[0004] Examples are explained below with reference to the drawings. These drawings are used to illustrate certain principles and thus only show aspects necessary for understanding these principles. These drawings are not drawn to scale. In the drawings, the same reference numerals denote similar features.

[0005] Figure 1 A circuit diagram of a power converter having a Vienna rectifier topology is shown;

[0006] Figure 2 A signal diagram of the input voltage of a power converter according to an example is shown;

[0007] Figure 3 Shown in more detail Figure 1 An example of a power converter of the type shown;

[0008] Figure 4A signal diagram is shown, which shows operating a power converter in a conventional manner;

[0009] Figure 5 A diagram is shown of Figure 3 an example of a bidirectional blocking switch that can be used in the power converter shown;

[0010] Figure 6 A diagram is shown of Figure 4 an example of a control circuit configured to operate a power converter according to the method shown;

[0011] Figures 7A-7F A diagram is shown of Figure 1 different examples of the bridge arms of a bridge rectifier in a power converter of the type shown;

[0012] Figure 8 A signal diagram is shown, which shows operating a power converter in a reduced switching mode (1 / 3 mode) according to an example;

[0013] Figure 9 A diagram is shown of a power converter device having a first power converter and a second power converter, wherein the second power converter is operated according to the method shown in Figure 8 and Figure 9 ;

[0014] Figure 10 A diagram is shown of an example of a control circuit configured to operate a power converter device such that the first power converter is operated according to the method shown in Figure 8 and Figure 9 ;

[0015] Figure 11 A diagram is shown of an example of a second power converter including two converter stages;

[0016] Figure 12 A diagram is shown of an example of a control circuit configured to operate a second power converter according to Figure 11 ;

[0017] Figure 13 A signal diagram is shown, which shows in more detail operating a power converter in the reduced switching mode shown in Figure 9 ;

[0018] Figure 14 A diagram is shown of Figure 13 a modification of the control circuit shown;

[0019] Figure 15 A signal diagram is shown, which shows operating the power converter device shown in Figure 10 in a full 1 / 3 mode, a partial boost mode, and a full 3 / 3 mode;

[0020] Figure 16 shows Figure 15 the different operating modes shown in, which depend on the DC link voltage required during one of six operating phases;

[0021] Figure 17 shows a further example of a control circuit configured to operate a second power converter according to Figure 11 ;

[0022] Figure 18 shows an example of a power converter device including a balancing circuit;

[0023] Figure 19 shows an example of a balancing circuit;

[0024] Figure 20 shows a signal diagram which shows operating a power converter in 2 / 3 mode or 3 / 3 mode;

[0025] Figure 21 shows Figure 20 the different operating modes shown in, which depend on the DC link voltage during one of six operating phases;

[0026] Figure 22 shows a signal diagram of a power converter operating in 2 / 3 mode or 3 / 3 mode at different DC link voltages;

[0027] Figure 23 shows an example of a control circuit configured to operate a power converter in 2 / 3 mode or 3 / 3 mode;

[0028] Figure 24 shows operating a power converter in one of 1 / 3 mode, 2 / 3 mode or 3 / 3 mode depending on the DC link voltage during one of six operating phases; and

[0029] Figure 25 shows a signal diagram of a power converter operating in 1 / 3 mode, 2 / 3 mode or 3 / 3 mode at different DC link voltages. Detailed Description

[0030] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings form a part of the specification and, for purposes of illustration, show examples of how to use and implement the invention. It should be understood that the features of the various embodiments described herein may be combined with each other unless otherwise specifically stated.

[0031] Figure 1The circuit diagram of a power converter 10 known as a Vienna rectifier is shown. The power converter is a switched-mode three-phase (3Ф) AC-DC power converter. The power converter includes: an input having three input nodes A, B, C, each input node being configured to receive a respective one of three input voltages V1, V2, V3; two DC link nodes X, Z configured to provide a DC link voltage V4 therebetween; and a midpoint Y coupled to each of the two DC link nodes X, Z. Each of the three input voltages V1, V2, V3 is a voltage between a respective one of the input nodes A, B, C and a common ground node N. The power converter further includes three inductors L1, L2, L3, each inductor being coupled to a respective one of the three input nodes A, B, C. In Figure 1 the example shown, the inductors L1, L2, L3 are directly coupled to the inputs A, B, C. However, this is only an example. According to another example (not shown), an input filter is connected between the inputs A, B, C and the inductors L1, L2, L3.

[0032] Referring Figure 1 to, the power converter further includes a rectifier bridge 1 having three bridge arms 1 1 、1 2 、1 3 . Only in Figure 1 are the three bridge arms 1 1 、1 2 、1 3 shown schematically. Each of the three bridge arms 1 1 、1 2 、1 3 includes at least one electronic switch Q1, Q2, Q3 and is connected to a respective one of the three inductors L1, L2, L3 such that each of the bridge arms 1 1 、1 2 、1 3 is coupled to a respective one of the three input nodes A, B, C through a respective one of the three inductors L1, L2, L3. Additionally, each of the three bridge arms 1 1 、1 2 、1 3 is connected to the two DC link nodes X, Z and the midpoint Y.

[0033] As shown, the midpoint Y can be coupled to the first DC link node X of the two DC link nodes X, Z via a first capacitor C1 and to the second DC link node Z of the two DC link nodes X, Z via a second capacitor C2. Hereinafter, the voltage VC1 across the first capacitor C1 is referred to as the first capacitor voltage, and the voltage VC2 across the second capacitor C2 is referred to as the second capacitor voltage.

[0034] According to one example, the input voltages V1, V2, V3 received by the power converter are AC input voltages such as sinusoidal input voltages. The phase shift between each pair of these input voltages V1, V2, V3 can be 120°. Figure 2 A signal diagram of the sinusoidal input voltages V1, V2, V3 during one period of each of these input voltages V1, V2, V3 is shown. In this example, the phase shift between each pair of these input voltages V1 - V3 is 120° (2π / 3). Each of the three sinusoidal input voltages V1 - V3 periodically varies between a minimum voltage level and a maximum voltage level, where in this example the maximum voltage level is a positive voltage level and the minimum voltage level is a negative voltage level. According to one example, the magnitude of the minimum level is substantially equal to the magnitude of the maximum level, and the three input voltages V1 - V3 have substantially the same minimum voltage level and the same maximum voltage level. In addition, the three input voltages V1 - V3 can have substantially the same frequency, where the frequency is, for example, between 50 Hz and 60 Hz.

[0035] Figure 2 The input voltages V1, V2, V3 depending on the phase angle are shown. Hereinafter, the plurality of input voltages V1, V2, V3 are also referred to as an input voltage system. In addition, for the purpose of illustration, it is assumed that a specific phase angle α of the input voltage system corresponds to the phase angle α of the first input voltage V1, where α = 0 is the phase angle at the start of the positive half - wave of the first input voltage V1.

[0036] The magnitudes A1, A2, A3 of the maximum voltage level and the minimum voltage level of each input voltage V1, V2, V3 can also be referred to as the amplitudes of the respective input voltages V1, V2, V3. The root - mean - square (RMS) value of the input voltage A1 RMS , A2 RMS , A3 RMS is obtained by dividing the amplitude by the square root of 2, that is where A represents the amplitude of any one of the three input voltages V1, V2, V3, and where A RMS represents the respective RMS value. According to one example, each of the three input voltages V1, V2, V3 is a 230V RMS grid voltage, that is A RMS = A1 RMS = A2 RMS = A3 RMS = 230V RMS . In this example, the amplitude is given by A = A1 = A2 = A3 = 325V.

[0037] In each stage of a cycle of the three input voltages V1, V2, and V3, one of the three input voltages has the highest (positive) voltage level among the three input voltages V1, V2, and V3, and one of the three input voltages has the lowest (negative) voltage level among the three input voltages V1, V2, and V3. Among them, in each cycle, during a specific time period, each of the three input voltages V1, V2, and V3 has the highest level, and each of the three input voltages V1, V2, and V3 has the lowest level. The difference between the highest voltage level and the lowest voltage level is called the line-to-line voltage V LL . Associated with Figure 2 the input voltages V1, V2, and V3 shown in LL the line-to-line voltage V LL is also shown in Figure 2 . It can be seen that the line-to-line voltage is periodic, where the duration of one cycle of the line-to-line voltage V LL is 1 / 6 of the duration of one cycle of the input voltages V1, V2, and V3. In other words, one cycle of the input voltages V1, V2, and V3 includes a phase angle from 0° to 360° (0 to 2π), while one cycle of the line-to-line voltage V LL ranges within 60° of one cycle of the input voltages V1, V2, and V3. The maximum value of the line-to-line voltage V LL_MAX , also referred to as the maximum line-to-line voltage hereinafter, is given by the square root of 3 multiplied by the amplitude A of the three input voltages, that is For example, in an input voltage system with three 230V RMS input voltages V1, V2, and V3, the maximum line-to-line voltage V LL_MAX is 563V.

[0038] Operation Figure 1 A power converter of the type shown may include (a) regulating the DC link voltage V4 to have a predefined voltage level, and (b) regulating each of the three input currents I1, I2, and I3 to have a current waveform that is substantially the same as the waveform of the respective input voltages V1, V2, and V3. Therefore, when the input voltages V1, V2, and V3 are sinusoidal voltages, these input currents I1, I2, and I3 are substantially sinusoidal waveforms. Regulating each input current I1, I2, and I3 may include regulating the inductor voltages VL1, VL2, and VL3 across the corresponding inductors L1, L2, and L3, where regulating the inductor voltages VL1, VL2, and VL3 may include regulating the voltages VA', VB', and VC' at the circuit nodes A', B', and C' arranged between the inductors L1, L2, and L3 and the bridge arms 1 1 , 1 2 , 1 3 . Hereinafter, these circuit nodes A', B', and C' are referred to as the bridge arms 1 1 , 12 and 1 3 of the switching nodes, and the voltages VA', VB', VC' at these switching nodes A', B', C' are referred to as switching node voltages, where these voltages VA', VB', VC are referenced to a common ground node N. In the following, reference is made to Figure 3 and Figure 4 to explain an example of a method for regulating the inductor voltages VL1, VL2, VL3 in order to regulate the input currents I1, I2, I3.

[0039] Figure 3 shows Figure 1 a power converter of the type shown, where leg 1 is implemented according to a specific example 1 and 1 2 and 1 3 . (Further examples for implementing the inductor voltages VL1, VL2, VL3 are explained below in this document). Figure 4 shows a signal diagram of the signals that occur in the power converter during one period of the input voltages V1, V2, V3. In Figure 3 the example shown, each leg 1 1 and 1 2 and 1 3 includes electronic switches Q1, Q2, Q3 connected between the respective switching nodes A', B', C' and the midpoint Y, first rectifier elements D11, D21, D31 connected between the respective switching nodes A', B', C' and the first DC link node X, and second rectifier elements D12, D22, D32. The electronic switches Q1, Q2, Q3 can be implemented as bidirectional blocking switches. A "bidirectional blocking switch" is a switch that can block current regardless of the polarity of the voltage applied to the electronic switch.

[0040] Figure 5 shows an example of a bidirectional blocking switch. In this example, the electronic switch Q (where Q represents any one of the switches Q1, Q2, Q3) includes two MOSFETs (metal-oxide-semiconductor field-effect transistors) connected in series such that the integrated body diodes are connected in a back-to-back configuration. That is, these MOSFETs are connected in series such that the body diodes integrated in these MOSFETs either connect their anodes or connect their cathodes. The two MOSFETs can be driven by the same drive signal S (where S represents any one of the drive signals S1, S2, S3 received by the switches Q1, Q2, Q3). However, implementing the bidirectional switches Q1, Q2, Q3 in the manner shown in Figure 5 is only an example. Any other type of bidirectional electronic switch, such as a HEMT (high electron mobility transistor), can also be used.

[0041] Reference Figure 3 The first and second rectifier elements D11 - D32 can be implemented as passive rectifier elements such as diodes. However, this is only an example. Active rectifier elements, such as MOSFETs operating as synchronous rectifiers, can also be used.

[0042] In Figure 3 the example shown, the first rectifier elements D11, D21, D31 are configured to effect (positive) current flow from the respective switching nodes A', B', C' to the first DC - link node X, and the second rectifier elements D12, D22, D32 are configured to effect (positive) current flow from the second DC - link node Z to the respective switching nodes A', B', C'. That is, in Figure 3 the example shown, the cathodes of the diodes forming the first rectifier elements D11, D21, D31 are connected to the first DC - link node X and their anodes are connected to the respective switching nodes A', B', C', and the anodes of the diodes forming the second rectifier elements D12, D22, D32 are connected to the second DC - link node Z and their cathodes are connected to the respective switching nodes A', B', C'.

[0043] Referring to the above, controlling the currents I1, I2, I3 through each inductor L1, L2, L3 includes controlling the voltages VL1, VL2, VL3 across the respective inductors L1, L2, L3. Each inductor voltage VL1, VL2, VL3 is given by subtracting the respective switching - node voltages VA', VB', VC' from the respective input voltages V1, V2, V3. The input voltages V1, V2, V3 are predefined by a voltage source (such as the power grid) and can be measured, so that the inductor voltages VL1, VL2, VL3 and thus the inductor currents I1, I2, I3 can be regulated by adjusting the switching - node voltages VA', VB', VC'. This will be explained below with reference to Figure 4 this.

[0044] Figure 4 Shown are the drive signals S1, S2, S3 of the electronic switches Q1, Q2, Q3, the sinusoidal input voltages V1, V2, V3, and the corresponding input currents I1, I2, I3, which are substantially sinusoidal. Figure 4 Further shown are the currents ID11, ID12 through the first rectifier element D11 and the second rectifier element D12 in the first leg 1 1 、1 2 、1 3 in leg 1 1 in the first leg 1 1 in the first leg 1, the current IQ1 through the electronic switch Q1 in the first leg 1 1The voltage VQ1 across the electronic switch Q1 in

[0045] For purposes of explanation, assume that the power converter is in a steady state, in which the DC link voltage V4 has reached the desired voltage level, and the power consumption of the load Z (as shown by the dashed line in Figure 3 ) connected to the DC link nodes X, Z is constant. The load can be any load, including a load that includes another power converter. Referring to Figure 4 , the power converter can operate in continuous conduction mode (CCM), i.e., during each of the positive and negative half-cycles of the respective input voltages V1, V2, V3, the inductor currents I1, I2, I3 do not decrease to zero. (When the respective input voltages V1, V2, V3 cross zero, the input currents I1, I2, I3 become zero only for a short period of time).

[0046] The current flow directions of the inductor currents I1, I2, I3 depend on the instantaneous voltage levels of the input voltages V1, V2, V3 and the midpoint voltage VY. The "midpoint voltage" VY is the voltage at the midpoint Y, which is not directly connected to the ground node N, and the "midpoint voltage" VY is referenced to the ground node N. The midpoint voltage VY or the negative value -VY of the midpoint voltage may also be referred to as the common-mode voltage VCM hereinafter. For purposes of illustration only, hereinafter, the negative value of the midpoint voltage VY will be referred to as the common-mode voltage VCM = -VY. The common-mode voltage VCM can be adjusted to be zero so that the potential of the midpoint is equal to the potential of the ground node. Alternatively, the common-mode voltage VCM can be adjusted to be different from zero and vary over one cycle of the input voltages V1, V2, V3. In each of these cases, the inductor currents can be adjusted so that each inductor current I1, I2, I3 is positive during the positive half-cycle of the respective input voltages V1, V2, V3 and negative during the negative half-cycle of the respective input voltages V1, V2, V3. Examples for adjusting the common-mode voltage VCM will be explained in further detail below.

[0047] The control of the input currents I1, I2, I3 will be explained below with reference to controlling the current I1 through the first inductor L1 of the inductors L1, L2, L3 (which is the inductor connected to the first bridge arm 1 1 ). The adjustment of the other two input currents I2, I3 among the input currents I1, I2, I3 is implemented in the same way. Hereinafter, the input A coupled to the first bridge arm 1 1 will be referred to as the first input, the voltage V1 received at this input will be referred to as the first input voltage, the switch node A' of the first bridge arm 1 1 will be referred to as the first switch node, the inductor L1 connected to the first switch node A' will be referred to as the first inductor, and the voltage VL1 across the first inductor L1 will be referred to as the first inductor voltage VL1.

[0048] During the positive half - wave of the first input voltage V1, the first inductor current I1 is positive, i.e., the inductor current flows in the direction as indicated by the arrow in Figure 3 . In this case, the inductor current I1 flows through the first rectifier element D11 during the off - time period of the first switch Q1 (i.e., after the first switch Q1 has been turned off). During the off - time period of the electronic switch Q1, the voltage VA' at the first switch node A' is given by the voltage VX at the first DC - link node X minus the voltage drop across the first rectifier element D11. However, this voltage drop across the first rectifier element is negligible, such that during the off - time period of the first electronic switch Q1, the potential at the first switch node A' is essentially clamped at the voltage VX at the first DC - link node X. This voltage VX is referenced to the ground node and is hereinafter referred to as the first DC - link node voltage.

[0049] During the negative half - wave of the first input voltage V1, the first inductor current I1 is negative, i.e., the inductor current flows in the direction opposite to that indicated by the arrow in Figure 3 . In this case, the inductor current I1 flows through the second rectifier element D12 during the off - time period of the first switch Q1. During the off - time period of the electronic switch Q1, the potential at the first switch node A' is given by the voltage VZ at the second DC - link node Z minus the voltage drop across the second rectifier element D12. However, this voltage drop across the second rectifier element is negligible, such that during the off - time period of the first electronic switch Q1, the potential at the first switch input node A' is essentially clamped at the voltage VZ at the second DC - link node Z. This voltage VZ is referenced to the ground node and is hereinafter referred to as the second DC - link node voltage.

[0050] In the Figure 3 shown power converter, depending on the polarity of the first input voltage V1 and the switching state of the first electronic switch Q1, the voltage VA' at the first switch node A' (and the other two switch nodes B', C') can have three different levels: (1) VA' = VY during the on - time period of the electronic switch Q1; (2) VA' = VX during the off - time period of the electronic switch Q1 and when the first input voltage V1 is positive, i.e., during the positive half - wave of the first input voltage V1; and (3) VA' = VZ during the off - time period of the electronic switch Q1 and when the first input voltage V1 is negative, i.e., during the negative half - wave of the first input voltage V1.

[0051] The first DC - link node voltage VX is given by the first capacitor voltage VC1 minus the common - mode voltage VCM,

[0052] VX = VC1 - VCM (1a),

[0053] and the second DC link node voltage VZ is given by the common-mode voltage VCM multiplied by negative one minus the second capacitor voltage VC2,

[0054] VZ = -VC2 - VCM = -(VC2 + VCM) (1b),

[0055] where, for illustrative purposes only, it is assumed that the common-mode voltage VCM is VN - VY, where VN is the potential at the ground node N and VY is the potential at the midpoint.

[0056] The common-mode voltage VCM can be positive or negative. In each case, the magnitude of the common-mode voltage VCM is lower than the magnitude of each of the first and second capacitor voltages, such that the first DC link node voltage VX is positive and the second DC link node voltage VZ is negative.

[0057] The voltage VL1 across the first inductor L1 is given by where L1 represents the inductance of the first inductor L1. Thus, when the inductor voltage VL1 is positive, the inductor current I1 increases; when the inductor voltage VL1 is negative, the inductor current I1 decreases; and when the inductor voltage VL1 is zero, the inductor current I1 remains constant. By appropriately switching the voltage VA' at the first switch node A' between two of the three voltage levels VX, VY, VZ, a first input current I1 can be generated such that it follows a sinusoidal waveform. During the positive half-cycle of the first input voltage V1, (a) the inductor current I1 increases during the conduction period of the first switch Q1, and (b) the inductor current I1 decreases during the off period of the first switch Q1. During the negative half-cycle of the first input voltage V1, (c) the inductor current I1 increases during the conduction period of the first switch Q1, and (d) the inductor current I1 decreases during the off period of the first switch Q1. In each case, when the average value of the inductor voltage VL1 over one conduction period and one off period of the first switch Q1 is positive, the inductor current I1 increases; and when the average value of the inductor voltage VL1 over one conduction period and one off period of the first switch Q1 is negative, the inductor current I1 decreases.

[0058] The electronic switch Q1 (and the other switches Q2, Q3) can be operated in a pulse-width modulation (PWM) manner at a fixed switching frequency f SW which is significantly higher than the frequency of the first input voltage V1. For example, the switching frequency f SW is significantly higher than the frequency of the first input voltage V1. For example, the switching frequency f SWBetween a few kHz and several tens of kHz, and its range can reach several hundreds of kHz. To adjust the first switching node voltage VA', the duty cycle d1 of the first switch Q1 is varied, where, in each drive cycle, the duty cycle d1 is given by the relationship between the duration T of the conduction period of the electronic switch Q1 ON or the duration T of the off period of the electronic switch Q1 OFF and the duration T of one drive cycle, where the duration T of the drive cycle is given by the reciprocal of the switching frequency (T = 1 / f SW ). The duration T of the off period of the electronic switch Q1 OFF is given by subtracting the duration T of the conduction period from the duration T of the drive cycle ON , i.e., T OFF = T - T ON . For illustrative purposes only, it is assumed that the magnitude |d1| of the duty cycle d1 is given by the ratio of the duration T of the off period OFF to the duration T of the drive cycle, i.e.,

[0059] Furthermore, it is assumed that the duty cycle d1 can be positive or negative, where the duty cycle d1 is positive during the positive half-cycle of the first input voltage V1 and negative during the negative half-cycle of the first input voltage V1. For example, a duty cycle d1 = 0 means that the first switch Q1 is conducting during the corresponding drive cycle; a duty cycle d1 = 1 means that the first switch Q1 is off during the corresponding drive cycle in the positive half-cycle of the first input voltage V1; and a duty cycle d1 = -1 means that the first switch Q1 is off during the corresponding drive cycle in the negative half-cycle of the first input voltage V1. A positive duty cycle d1 different from one (1) or zero (0) represents the ratio of the duration of the conduction period to the duration of the off period in the drive cycle in the positive half-cycle of the first input voltage V1. Similarly, a negative duty cycle d1 different from 1 or 0 represents the ratio of the duration of the conduction period to the duration of the off period in the drive cycle in the negative half-cycle of the first input voltage V1.

[0060] Referring to the above, the first switching node voltage VA' is obtained by switching between the first DC link node voltage VX and the midpoint voltage VY or between the second DC link node voltage VZ and the midpoint voltage VY. Thus, the first switching node voltage VA' is given by the average voltage at the first switching node A' in one drive cycle. For example, during the positive half-cycle of the input voltage V1, the first switching node voltage VA' is given by

[0061]

[0062] and for example, during the negative half-cycle of the input voltage V1, the first switching node voltage VA' is given by

[0063]

[0064] Therefore, by appropriately adjusting the duty ratio d1 of the first electronic switch Q1, the first switching node voltage VA' can be adjusted, and thereby the first inductor voltage VL1 can be adjusted. On the other hand, based on the desired first switching node voltage VA' and the common-mode voltage VCM, the duty ratio d1 can be calculated. Referring to the above, the duty ratio d1 is given by the duration T OFF of the off-time period divided by the duration T of one driving cycle, and the duty ratio d1 is positive in the positive half-cycle of the first input voltage V1 and negative in the negative half-cycle of the first input voltage V1. Therefore, in Equation (2a) and in Equation (2b) Therefore, during the positive half-cycle, based on Equation (2a), the duty ratio d1 is given by

[0065]

[0066] And, during the negative half-cycle, based on Equation (2b), the duty ratio d1 is given by

[0067]

[0068] The capacitor voltages VC1, VC2 can be adjusted such that each of these voltages is 50% of the DC link voltage V4, such that VC1 = VC2 = V4 / 2. In this case, the duty ratio d1 can be calculated according to Equations (3a) and (3b) as follows

[0069]

[0070] Referring Figure 1 and Figure 3 , the power converter includes a control circuit 2, which is configured to operate the bridge arms 1 1 、1 2 、1 3 such that at least one of the electronic switches Q1, Q2, Q3 in each of the bridge arms. More specifically, the control circuit 2 can be configured to generate drive signals S1, S2, S3 received by the electronic switches Q1, Q2, Q3 such that the DC link voltage V4 has a predefined voltage level and such that the inductor currents (input currents) I1, I2, I3 substantially have the same waveform as the input voltages V1, V2, V3. To this end, the control circuit 2 receives a DC link voltage signal S V4 , where the DC link voltage signal S V4 represents the DC link voltage V4. The DC link voltage V4 can be measured in a conventional manner by any kind of voltage measurement circuit (not shown) to obtain the DC link voltage signal S V4In addition, the control circuit 2 receives input voltage signals S V1 、S V2 、S V3 , each representing a corresponding one of the input voltages V1, V2, V3, and receives input current signals S I1 、S I2 、S I3 , each representing a corresponding one of the input currents I1, I2, I3. The input voltages V1, V2, V3 can be measured in a conventional manner to obtain the input voltage signals S V1 、S V2 、S V3 . In addition, the input currents I1, I2, I3 can be measured in a conventional manner to obtain the input current signals S I1 、S I2 、S I3 . Figure 6 Shows an example of a control circuit 2 configured to generate drive signals S1 - S3.

[0071] Figure 6 The control circuit 2 shown in includes a first filter 21 that receives a DC link voltage signal S V4 and a DC link voltage reference signal S V4_REF , where the DC link voltage reference signal S V4_REF represents the desired voltage level of the DC link voltage V4. The filter 21 subtracts the DC link voltage reference signal S V4 from the DC link voltage signal S V4_REF , and filters the difference to generate a DC link voltage error signal S V4_ERR . The filter (or controller) can have one of a proportional (P) characteristic, a proportional - integral (PI) characteristic, a proportional - integral - derivative (PID) characteristic, etc. The multiplier 22 receives the DC link voltage error signal S V4_ERR and the DC link voltage reference signal S V4_REF , where the output signal S22 of the multiplier 22 represents the desired output power of the power converter. The divider 23 divides the multiplier output signal S22 by a signal representing 1.5 times the square of the amplitudes of the input voltages V1, V2, V3 The output signal S23 of the divider 23 represents the total desired input current of the power converter, where the total desired input current is the input current required for the power converter to achieve the desired voltage level of the DC link voltage V4 defined by the DC link voltage reference signal S V4_REF .

[0072] Reference Figure 6, the control circuit 2 further includes three branches, each of which receives the divider output signal S23 and generates a corresponding one of the three drive signals S1, S2, S3. Each of these branches includes a multiplier 24 1 , 24 2 , 24 3 , which multiplies the divider output signal S23 by the corresponding input voltage signal S V1 , S V2 , S V3 . Among them, the output signal of each of these multipliers 24 1 , 24 2 , 24 3 is the input current reference signal S I1_REF , S I2_REF , S I3_REF , that is, each of these signals S I1_REF , S I2_REF , S I3_REF represents the desired current level of a corresponding one of the input currents I1, I2, I3. Using a corresponding subtractor 25 1 , 24 2 , 24 3 downstream of the corresponding multiplier 24 1 , 25 2 , 25 3 subtracts the corresponding input current signal S I1_REF , S I2_REF , S I3_REF from each of these reference signals S I1 , S I2 , S I3 . The output signal of each of these subtractors 25 1 , 25 2 , 25 3 is filtered by a corresponding filter 26 1 , 25 2 , 25 3 downstream of the corresponding subtractor 25 1 , 26 2 , 26 3 . Among them, the output signal S 1 , 26 2 , 26 3 of the corresponding filter 26 VL1_REF , S VL2_REF , S VL3_REF represents the desired voltage level of a corresponding one of the three inductor voltages VL1, VL2, VL3. Another subtractor 27 1 , 27 2 , 27 3 subtracts from the corresponding inductor voltage reference signal SVL1_REF , S VL2_REF , S VL3_REF subtract the input voltage signal S from V1 , S V2 , S V3 to obtain a switching node voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF , where these switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF each represents the desired voltage level of a corresponding one of the three leg input voltages VA', VB', VC'.

[0073] Reference Figure 6 , each of the three branches for generating the drive signals S1, S2, S3 includes a PWM modulator 28 1 , 28 2 , 28 3 , which receives a corresponding one of the leg input voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF , where these modulators 28 1 , 28 2 , 28 3 each is configured to generate a corresponding one of the drive signals S1, S2, S3 based on the corresponding reference signal S VA'_REF , S VB'_REF , S VC'_REF such that in each drive cycle of at least one of the electronic switches Q1, Q2, Q3, the average value of the corresponding leg input voltages VA', VB', VC' is equal to the voltage level defined by the corresponding leg input voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF . The specific implementation of the PWM modulator 28 1 , 28 2 , 28 3 depends on the type of leg 1 1 , 1 2 , 1 3 used in the power converter.

[0074] In a three-level power converter, i.e., a power converter implemented with the legs shown in Figure 3 and Figures 7A-7C , for example, each PWM modulator 28 1 , 28 2 , 28 3It can be configured to calculate the duty cycles d1, d2, d3 of the drive signals S1, S2, S3 based on one of the equations (3a), (3b), or (3c), and generate the drive signals S1, S2, S3 according to the calculated duty cycles.

[0075] Referring to these equations, by appropriately adjusting the duty cycles d1, d2, d3, not only can the switch node voltages VA', VB', VC' be adjusted, but also the common-mode voltage VCM can be adjusted. Basically, in order to obtain a sinusoidal current waveform, the first DC-link node voltage VX must be equal to or higher than the highest voltage level of the three input voltages V1, V2, V3, and the second DC-link node voltage VZ must be equal to or lower than the lowest voltage level of the three input voltages V1, V2, V3. For example, if it is desired that the common-mode voltage VCM be zero, then each capacitor voltage VC1, VC2 must be higher than the amplitude of the three input voltages. Therefore, when the input voltages V1, V2, V3 are 230V RMS voltages, each capacitor voltage must be higher than 325V, such that the DC-link voltage must be higher than 650V (= 2 × 325V). For example, if the DC-link voltage is twice the amplitude of the input voltage and the common-mode voltage VCM is zero, then in the steady state, the duty cycles d1, d2, d3 defined by the equations (3a), (3b), and (3c) basically follow the corresponding input voltages V1, V2, V3.

[0076] However, in some cases, it may be desired to regulate the DC-link voltage V4 to a voltage level lower than twice the amplitude of the input voltages V1, V2, V3. This can be achieved by appropriately adjusting the common-mode voltage VCM. In Figure 4 the example shown, the common-mode voltage VCM (not shown) has been selected to be equal to -(Vmax' + Vmin') / 2, where Vmax' represents the voltage level of the highest one of the three switch node voltages VA', VB', VC' at a specific moment, i.e., Vmax' = max{VA'; VB'; VC'}, and Vmin' represents the lowest one of the three switch node voltages at a specific moment, i.e., Vmin' = min{VA'; VB'; VC'}. In the steady state, the switch node voltages VA', VB', VC' follow the input voltages V1, V2, V3, and can be considered to be basically equal to the input voltages V1, V2, V3 (the inductor voltages VL1, VL2, VL3 are lower compared to the input voltages V1, V2, V3). To adjust the duty cycle, the PWM modulators 28 1 、28 2 、28 3 can each receive a common-mode voltage signal S representing the desired common-mode voltage VCM . This common-mode signal S VCMIt can be provided by a central controller (not shown). The central controller can be a microcontroller or the like.

[0077] In Figure 4 the method shown, the electronic switches Q1, Q2, Q3 in each of the bridge arms 1 1 、1 2 、1 3 are operated in PWM mode during the entire cycle of the input voltages V1, V2, V3. This type of operating mode is also referred to as the 3 / 3 mode below.

[0078] Referring to the above, the bridge arms 1 1 、1 2 、1 3 can be implemented in various ways. The following explains some examples for implementing each of the bridge arms 1 1 by referring to the first bridge arm 1 1 -1 3 The second and third bridge arms 1 2 、1 3 can be implemented in the same way as the first bridge arm 1 1 . Figure 7A Shows a first example of the first bridge arm 1 1 . In this example, the first bridge arm 1 1 is implemented in the manner described with reference to Figure 3 . That is, the bridge arm 1 1 includes a bidirectional blocking switch Q1 connected between the first switch node A' and the midpoint Y, a first rectifier element D11 connected between the first switch node A' and the first DC link node X, and a second rectifier element D12 connected between the second DC link node Z and the first switch node A'.

[0079] Figure 7B Shows a second example for implementing the first bridge arm 1 1 . In this example, the bridge arm 1 1 includes a first rectifier element D211 connected to the first DC link node X, a second rectifier element D212 connected to the second DC link node Z, a third rectifier element D213 connected between the switch node A' and the first rectifier element D211, a fourth rectifier element D214 connected between the switch node A' and the second rectifier element D212, a fifth rectifier element D215 connected between the midpoint Y and the first rectifier element D211, and a sixth rectifier element D216 connected between the midpoint Y and the second rectifier element D212. In addition, the electronic switch Q1 is connected between the first rectifier element D211 and the second rectifier element D212. The electronic switch Q1 can be a unidirectional electronic switch, such as a MOSFET. Refer to Figure 7B, the rectifier elements D211 - D216 can be implemented as diodes. These rectifier elements D211 - D216 are connected such that during the positive half - wave of the first input voltage V1, when the electronic switch Q1 is turned on, the inductor current I1 can flow from the first switch node A' through the third rectifier element D213, the electronic switch Q1, and the sixth rectifier element D216 to the mid - point Y. When the electronic switch Q1 is turned off, the inductor current I1 flows through the third rectifier element D213 and the first rectifier element D211. During the negative half - wave of the input voltage V1, when the electronic switch Q1 is turned on, the current flows from the mid - point Y through the fifth rectifier element D215 and the fourth rectifier element D214 to the first switch node A'. When the electronic switch Q1 is turned off, the current flows from the second DC - link node Z through the second rectifier element D212 and the fourth rectifier element D214 to the first switch node A'.

[0080] Figure 7C shows a first example of the first bridge arm 1 1 In this example, the first bridge arm 1 1 includes a first rectifier element D311 connected to the first DC - link node X, a second rectifier element D312 connected to the second DC - link node Z, a first switch Q311 connected between the first switch node A' and the first rectifier element D311, a second switch Q312 connected between the first switch node A' and the second rectifier element D312, a third rectifier element D313 connected between the mid - point Y and the first rectifier element D311, and a fourth rectifier element D314 connected between the mid - point Y and the second rectifier element D312.

[0081] For example, the electronic switches Q311 and Q312 can be unidirectional blocking switches, such as MOSFETs. The electronic switches Q311 and Q312 and the rectifier elements D311 - D314 can be connected such that during the positive half - wave of the input voltage V1, when the second electronic switch Q312 is conducting, the inductor current I1 flows from the switch node A' through the second electronic switch Q312 and the fourth rectifier element D314 to the mid - point Y. When the second electronic switch Q312 is turned off, the inductor current I1 flows from the first electronic switch Q311 and the first rectifier element D311 to the first DC - link node X. The first electronic switches Q311 and Q312 can be turned on and off simultaneously. In this case, during the off - period, the inductor current I1 flows through the body diode of the MOSFET forming the first electronic switch Q311 and the first rectifier element D311. According to another example, the first electronic switch Q311 and the second electronic switch Q312 are operated in a complementary manner such that only one switch is conducting at the same time. In this case, when the second switch Q312 is off, the first switch Q311 is on, so that the inductor current I1 flows through the conducting first electronic switch Q311 and the first rectifier element D311.

[0082] During the negative half - wave of the input voltage V1, when the first electronic switch Q311 is conducting, the inductor current I1 flows from the mid - point Y through the third rectifier element D313 and the first electronic switch Q311 to the first switch node A'. When the first electronic switch Q311 is turned off, the inductor current I1 flows from the second DC - link node Z through the second rectifier element D312 and the second electronic switch Q312 to the first switch node A'.

[0083] Figure 7D Shows the modification to Figure 7C the shown leg 1 1 In Figure 7D the example shown, the first switch Q311 is connected between the mid - point Y and the first rectifier element D311, the second switch Q312 is connected between the mid - point Y and the second rectifier element D312, the third rectifier element D313 is connected between the switch node A' and the first rectifier element D311, and the fourth rectifier element D314 is connected between the switch node A' and the second rectifier element D312.

[0084] Figure 7A 、 7B Each leg 1 shown in 7C and 7D 1 is configured to provide three different voltage levels at the first switch node A'. Using the leg 1 shown in Figures 7A to 7D the leg 1 shown in 1One of them, the average potential at the first switching node A' during a driving cycle is generated by two voltage levels, i.e., the potential VX at the first DC link node X and the potential VY at the midpoint Y during the positive half-wave of the input voltage V1, and the potential VZ at the second DC link node Z and the potential VY at the midpoint Y during the negative half-wave of the input voltage V1.

[0085] Figure 7E and Figure 7F shows a further example of the first arm 1 1 In these examples, the arm 1 1 also includes capacitors in addition to the DC link capacitors C1, C2. In these examples, in each of the positive and negative half-waves of the input voltage V1, there are more than two different voltage levels available for generating the switching node voltage VA' such that it exhibits an expected value. Figure 7E and Figure 7F The arm 1 shown in 1 is a so-called multilevel arm, where Figure 7E the arm 1 shown in 1 is a hybrid active neutral point clamped converter arm, while Figure 7F the arm 1 shown in 1 is a stacked multi-cell converter arm. These arms are known (for example, see G. Gateau, T. A. Meynard, H. Foch: “Stacked Multicell Converter (SMC): Properties and design”, 2001 IEEE 32 nd Annual Power Electronics Specialists Conference, Volume 3, pages 1583 - 1588), so no further explanation is needed for this. Basically, each of these arms can provide more than three different voltage levels, i.e., three voltage levels VX, VY, VZ and additional voltage levels for generating the switching node voltage VA'.

[0086] In Figures 7A-7F the example shown, the rectifier elements can be implemented as diodes (as shown). However, this is only an example. According to another example (not shown), these rectifier elements can be implemented as synchronous rectifier elements.

[0087] Referring to the above, operating Figure 1 and Figure 3 a power converter of the type shown can include, at each time of operation, for the arms 1 1 、1 2 、1 3The PWM (pulse width modulation) operation of each electronic switch in at least one electronic switch in each leg. However, operating switches Q1, Q2, Q3 in PWM mode is associated with switching losses. "Switching losses" refer to the losses that occur when turning on and off the corresponding switches Q1, Q2, Q3. To improve the efficiency of the power converter, it is desirable to reduce these switching losses.

[0088] According to one example, reducing switching losses includes operating the power converter in a reduced switching mode, where operating the power converter in a reduced switching mode includes deactivating at least one of the switches Q1, Q2, Q3 in leg 1 1 、1 2 、1 3 for a period significantly longer than the duration T of one drive cycle. According to one example, deactivating at least one switch includes deactivating at least one switch for more than 10, more than 100, or even more than 1000 drive cycles. Hereinafter, the leg in which at least one switch is deactivated is referred to as a deactivated leg. Referring to the above, the "at least one electronic switch" in leg 1 1 、1 2 、1 3 can include one electronic switch or several electronic switches. Figure 7A Leg 1 with one electronic switch is shown in 1 , where, as Figure 5 shown, one switch can include two transistors. Figures 7B-7F Leg 1 with several (unidirectional blocking) switches is shown in 1 . In a leg with several switches, "deactivating at least one switch" includes deactivating each of the several switches. Additionally, as used herein, the "at least one electronic switch" is a switch in the corresponding leg that is used to connect a switching node to the midpoint Y or to a circuit node having a voltage between the voltage at the midpoint Y and one of the first DC link node voltage VX and the second DC link node voltage VZ. For example, Figure 7E and Figure 7F show the voltage between the voltage at the midpoint Y and one of the first DC link node voltage VX and the second DC link node voltage VZ in the leg. Referring to the above, the rectifier elements that couple the switching nodes A', B', C' to the first DC link node X and the second DC link node Z can include electronic switches. Therefore, "deactivating at least one switch" does not include deactivating the electronic switches used as (synchronous) rectifiers.

[0089] Figure 8 shows an example of operating the power converter in a reduced switching mode, where Figure 8Shows the drive signals S1, S2, S3, the input voltages V1, V2, V3, the DC link voltage V4, the input currents I1, I2, I3, the current ID11, ID12, IQ11 in the first leg 1 1 and the voltage VQ1 across the first switch Q1 in the first leg 1 1 . The signal diagram will be described below. The operation mode shown in Figure 8 is called the 1 / 3 mode. In this operation mode, there is a period during which only one of the three legs 1 1 , 1 2 , 1 3 is operated in PWM mode while the other two legs 1 1 , 1 2 , 1 3 are disabled, that is, at least one of the electronic switches Q1, Q2, Q3 in the other two legs 1 1 , 1 2 , 1 3 is turned off. Hereinafter, the leg in which at least one electronic switch is operated in PWM mode is called the "enabled leg", and the leg in which at least one electronic switch is disabled is called the "disabled leg", although current can of course flow in the disabled leg between the corresponding switching node and one of the first DC link node X and the second DC link node Z.

[0090] In Figure 8 the example shown, the power converter operates in 1 / 3 mode throughout the entire cycle of the input voltages V1, V2, V3. That is, at each time in the cycle of the input voltages V1, V2, V3, only one leg 1 1 , 1 2 , 1 3 is enabled while the other two legs are disabled. This type of operation mode is hereinafter called the full 1 / 3 mode. However, this is only an example. According to another example explained further below, the power converter can also be operated such that it operates in 1 / 3 mode only during some time periods (at some phase angles in one cycle of the input voltages V1, V2, V3).

[0091] Referring to the above, the switching node voltage of the disabled leg is clamped at the DC link voltage VX at the first DC link node X or the DC link voltage VZ at the second DC link node Z. Therefore, in the 1 / 3 mode, the switching node voltage of one leg is clamped at the first DC link node voltage VX, while the switching node voltage of the other leg is clamped at the second DC link node voltage VZ. The disabled leg varies within one cycle of the input voltage system. This will be further explained below with reference to Figure 13 the signal diagram shown.

[0092] According to one example, the current through the two inductors connected to the deactivated arm is regulated by appropriately regulating the DC link voltage V4 by another power converter 5 connected to the DC link nodes X, Z of the power converter. Figure 9 A power converter device is shown in Figure 9 , which has a power converter of the type previously explained and another power converter 5 connected to the DC link nodes X, Z of the power converter. Hereinafter, the power converter 10 is also referred to as the first power converter, and the other power converter 5 is also referred to as the second power converter. The second power converter 5 can be configured to provide a constant output voltage V OUT or a constant output current I OUT that is different from the DC link voltage V4. When the second power converter 5 helps regulate the inductor currents I1, I2, I3 in the first power converter 10 by appropriately regulating the DC link voltage V4, the losses occurring in the second power converter 5 do not increase. However, the switching losses in the first power converter are significantly reduced. Therefore, there is a synergy between the control of the first power converter and the control of the second power converter 5.

[0093] Figure 10 An example of a control circuit 4 of a power converter device configured to operate Figure 9 the type shown in Figure 9 with a first power converter and a second power converter is shown. Figure 10 The control circuit 4 shown in Figure 10 includes two main branches (or sub - circuits), namely a first branch 40 configured to operate the first power converter and a second branch 6 configured to operate the second power converter 5. It should be noted that Figure 10 the block diagram shown in Figure 10 shows the functional blocks of the control circuit 4, rather than a specific implementation. These functional blocks can be implemented in various ways. According to one example, dedicated circuits are used to implement these functional blocks. According to another example, hardware and software are used to implement the control circuit 4. For example, the first control circuit includes a microcontroller and software executed by the microcontroller.

[0094] For the purpose of explanation, it is assumed that in Figure 9 the power converter device shown in Figure 9 , the output current I of the second power converter 5 is regulated OUT , and the output voltage V is defined by a load (not shown) that receives the output current OUT . The load can be a battery that receives the output current I OUT and defines the output voltage V OUT .

[0095] Figure 10 The first branch 40 of the control circuit 4 shown in Figure 10 is based on Figure 6 the control circuit shown in Figure 6 , where the same elements have the same reference numerals. Refer to Figure 10, the control circuit 4 receives the output current signal S IOUT , where the output current signal S IOUT represents the output current I OU T. To obtain the output current signal S IOUT , the output current I can be measured in a conventional manner by any kind of current measurement circuit (not shown) OUT . The control circuit 4 includes a first filter 41 that receives the output current signal S IOUT and the output current reference signal S IOUT_REF , where the output current reference signal S IOUT_REF represents the desired current level of the output current I OUT . For example, the first filter 41 subtracts the output current reference signal S IOUT from the output current signal S IOUT_REF , and filters the difference to generate the output signal S V51_REF . According to one example, this output signal S V51_REF represents the desired voltage V51 across the inductor 51 in the second power converter 5, where the inductor 51 carries the output current I OUT . Figure 9 shows an example of such an inductor 51.

[0096] The filter can have one of a proportional (P) characteristic, a proportional-integral (PI) characteristic, a proportional-integral-derivative (PID) characteristic, etc. The adder 42 receives the filter output signal S V51_REF and the output voltage signal S OUT that represents the output voltage V VOUT , where the multiplier 43 receives the output signal S42 of the adder 42 and the output current reference signal S IOUT_REF . The output signal S43 of the multiplier 43 represents the desired output power of the power converter device. By means of Figure 6 the divider 23 explained above divides the multiplier output signal S43 by a signal that represents 1.5 times the square of the amplitudes of the input voltages V1, V2, V3 The output signal S23 of the divider 23 represents the total desired input current of the first power converter. To generate three switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF , the output signal S23 of the divider is processed by three branches explained previously with reference to Figure 6 . It should be noted that the current control loop is the slowest one among the control loops explained in the context of Figure 10 .

[0097] Controlling the output current I by the control circuit 4 OUT is only an example. According to another example, controlling the output voltage VOUT In this example (not shown), the filter 41 receives the output voltage signal S VOUT and the output voltage reference signal S representing the desired voltage level of the output voltage V OUT . Further, the adder 42 is omitted, and the multiplier 43 receives the output signal from the filter 41 and the output voltage reference signal S VOUT_REF . VOUT_REF .

[0098] Reference Figure 10 , the PWM modulator 44 receives the switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF . From these switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF , the PWM modulator 44 (a) selects the largest and deactivates the leg associated with the largest voltage reference signal; (b) selects the smallest and deactivates the leg associated with the smallest voltage reference signal; and (c) operates the remaining legs in PWM mode. The "remaining legs" are the legs associated with the switch node reference signals between the largest and smallest switch node voltage reference signals. Hereinafter, this switch node voltage reference signal is referred to as the intermediate switch node voltage reference signal.

[0099] The second branch 6 of the control circuit also receives the three switch node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF , and is configured to control the operation of the second power converter 5 based on these signals S VA'_REF , S VB'_REF , S VC'_REF . An example of the second branch 6 of the control circuit is further explained in detail below.

[0100] Figure 11An example of the second power converter 5 is shown. In this example, the second power converter 5 includes a first converter stage 51 and a second converter stage 52, where each of the first converter stage 51 and the second converter stage 52 includes a first input node 511, 521, a second input node 512, 522, a first output node 513, 523, and a second output node 514, 524. The first input node 511 of the first converter stage 51 may be connected to the first DC link node X, the second input node 522 of the second converter stage 52 may be connected to the second DC link node Z, and the second input node 512 of the first converter stage 51 and the first input node 521 of the second converter stage 52 may be connected to each other and to the midpoint Y. In addition, the second output node 514 of the first converter stage 51 and the first output node 523 of the second converter stage 52 may be connected to each other. The output voltage VOUT is the voltage between the first output node 513 of the first converter stage 51 and the second output node 524 of the second converter stage 52.

[0101] The converter stages 51, 52 may each be implemented using one of a variety of different converter topologies. According to one example, each of the converter stages 51, 52 is implemented as an isolated DC-DC converter, i.e., the DC-DC converter includes a transformer between the respective inputs 511, 512 or 521, 522 and the respective outputs 513, 514 or 523, 534. According to another example, each of the converter stages 51, 52 is implemented as a non-isolated DC-DC converter, i.e., the DC-DC converter does not include a transformer between the respective inputs 511, 512 or 521, 522 and the respective outputs 513, 514 or 523, 534. Examples of different types of DC-DC converters suitable for use as the first converter stage 51 and the second converter stage 52 include, but are not limited to: flyback converters (isolated), LLC converters (isolated), dual active bridge (DAB) converters (isolated), phase-shifted full-bridge converters (isolated), buck-boost converters, boost-buck converters, etc. These types of converters are known and thus do not require further explanation here.

[0102] Figure 12 is shown configured to control Figure 11 An example of a second control circuit branch 6 configured to control the operation of the second power converter 5 of the type shown is shown. The control circuit 6 includes a maximum and minimum selector 61 that receives three switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF . The maximum and minimum selector 61 is configured to select the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REFthe maximum value in and the switching node voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF the minimum value in, and output a first signal S VA'_REF , S VB'_REF , S VC'_REF equal to the maximum value in the switching node voltage reference signal S MAX ', and a second signal S VA'_REF , S VB'_REF , S VC'_REF equal to the minimum value in the switching node voltage reference signal S MIN ', such that S MAX ' = max{S VA'_REF , S VB'_REF , S VC'_REF} and S MIN ' = min{S VA'_REF , S VB'_REF , S VC'_REF}. The first signal S MAX ' is also referred to as the maximum switching node voltage reference signal S MAX ', and the second signal S MIN ' is also referred to as the minimum switching node voltage reference signal. The intermediate switching node voltage reference signal is also referred to as S INT ' hereinafter.

[0103] The second control circuit branch 6 is configured to operate the second power converter 5 in such a way that the DC link voltage V4 is equal to the voltage represented by the difference between the maximum switching node voltage reference signal S MAX ' and the minimum switching node voltage reference signal S MIN '. Referring to the above, the switching nodes of the deactivated arm are clamped to the first DC link node voltage VX and the second DC link node voltage VZ respectively. By adjusting the DC link voltage V4 to be equal to the voltage represented by the difference between the maximum switching node voltage reference signal S MAX ' and the minimum switching node voltage reference signal S MIN ', the switching nodes clamped to the first DC link node X and the second DC link node Z receive the switching node voltages calculated by the first control circuit branch 40. Therefore, the inductor currents of those inductors connected to the deactivated arm have current levels represented by the corresponding input current reference signals calculated by the first control circuit branch 40.

[0104] Referring to Figure 12 , the second control circuit branch 6 includes a subtractor 62 that subtracts the minimum switching node voltage reference signal S MAX ' from the maximum switching node voltage reference signal S MIN', where the multiplier 63 multiplies the output signal of the subtractor by 0.5. The output signal of the multiplier forms the first capacitor voltage reference signal S VC1_REF and the second capacitor voltage reference signal S VC2_REF , where the first capacitor voltage reference signal S VC1_REF represents the expected value of the first capacitor voltage VC1, and the second capacitor voltage reference signal S VC2_REF represents the expected value of the second capacitor voltage VC2. The second control circuit branch 6 includes a first branch and a second branch. The first branch receives the first capacitor voltage reference signal S VC1_REF , and is configured to provide a first input current reference signal S I51_REF , where the first input current reference signal S I51_REF represents the expected input current I51 of the first converter stage 51. The second branch receives the second capacitor voltage reference signal S VC2_REF , and is configured to provide a second input current reference signal S I52_REF , where the second input current reference signal S I52_REF represents the expected input current I52 of the second converter stage 52.

[0105] The first branch includes a subtractor 64 1 , and the subtractor 64 1 subtracts the first capacitor voltage signal S VC1_REF representing the first capacitor voltage VC1 from the first capacitor voltage reference signal S CV1 . The output signal of the subtractor is filtered by a filter 65 1 , where the output signal S IC1_REF of the filter represents the expected current level of the current IX flowing into the first capacitor C1. The first input current reference signal S IX is given by the difference between the current signal S IC1_REF representing the current flowing into the first DC link node X (where the current IX is provided by the first power converter) and the filter output signal S I51_REF .

[0106] The second branch includes a subtractor 64 2 , and the subtractor 64 2 subtracts the second capacitor voltage signal S VC2_REF representing the second capacitor voltage VC2 from the second capacitor voltage reference signal S CV2 . The output signal of the subtractor is filtered by a filter 65 2 , where the output signal S IC2_REFRepresents the desired current level of the current IZ flowing into the second capacitor C2. The second input current reference signal S is given by the difference between a current signal S representing the current flowing into the second DC link node Z (where the current IZ is provided by the first power converter) IZ and the filter output signal S IC2_REF . I52_REF

[0107] Reference Figure 12 , the first PWM modulator 67 1 receives the first input current reference signal S I51_REF and the first input current signal S I51 , where the latter represents the first input current I51 and is configured to control the operation of one or more switches (not shown in the figure) included in the first converter stage 51 such that the first input current I51 has the current level represented by the first input current reference signal S I51_REF . Similarly, the second PWM modulator 67 2 receives the second input current reference signal S I52_REF and the second input current signal S I52 , where the latter represents the second input current I52 and is configured to control the operation of one or more switches (not shown in the figure) included in the second converter stage 52 such that the second input current I52 has the current level represented by the second input current reference signal S I52_REF . The specific implementation of the PWM modulators 67 1 、67 2 depends on the specific type of power converter used to implement the first converter stage 51 and the second converter stage 52. However, PWM modulators configured to control the input current in various DC-DC converters are known, and thus no further explanation is required for this.

[0108] Referring to the above, in the 1 / 3 mode, the PWM modulator 44 enables one of the three bridge arms 1 1 、1 2 、1 3 and disables the other two of the three bridge arms 1 1 、1 2 、1 3 depending on the switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF . The moments when two of these switch node voltage reference signals S VA'_REF 、S VB'_REF 、S VC'_REF are equal can be ignored, such that at each time, from these switch node voltage reference signals S VA'_REF 、S VB'_REF ​, S VC'_REF Among them, one forms the maximum switching node voltage reference signal S MAX ', one forms the intermediate switching node voltage reference signal S INT ', and one forms the minimum switching node voltage reference signal S MIN '. This will be explained in more detail with reference to Figure 13 the following content.

[0109] Figure 13 The signal diagrams of the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF are shown, where each of these signals represents the desired voltage value of the corresponding switching node voltages VA', VB', VC'. Figure 13 It is further shown at which time or phase angle which bridge arm is operated in the PWM mode. Referring to the above content and as Figure 13 shown, in the steady state, each switching node voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF follows the corresponding input voltage.

[0110] Referring to Figure 13 , the relationship between the respective switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF changes several times within one cycle. "Relationship" means the signal level of one of the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF with respect to the signal levels of the other two among the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF In the example shown in Figure 13 , there are six time periods P1 - P6, which are also referred to as operation phases hereinafter, in each of which the relationship between the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF does not change. (However, the signal levels of the switching node voltage reference signals S VA'_REF , S VB'_REF , S VC'_REF change in each operation phase P1 - P6.)

[0111] For example, in the first operation phase P1, the first switching node voltage reference signal S VA'_REF has the highest voltage level. That is, the voltage level of the first switching node voltage reference signal S VA'_REF is higher than that of the switching node voltage reference signal SVA'_REF , S VB'_REF , S VC'_REF the second switch node voltage reference signal S in VB'_REF the voltage level and the switch node voltage reference signal S VA'_REF , S VB'_REF , S VC'_REF the third switch node voltage reference signal S in VC'_REF the signal level. In addition, in the first operation phase P1, the second switch node voltage reference signal S VB'_REF has the lowest voltage level. That is, the voltage level of the second switch node voltage reference signal S VB'_REF is lower than the signal level of the first switch node voltage reference signal S VA'_REF and the signal level of the third switch node voltage reference signal S VC'_REF . In addition, the third switch node voltage reference signal S VC'_REF has a signal level between the signal level of the first switch node voltage reference signal S VA'_REF and the signal level of the second switch node voltage reference signal S VB'_REF . Therefore, in the first operation phase P1, the first switch node voltage reference signal S VA'_REF is the maximum switch node voltage reference signal S MAX ', the second switch node voltage reference signal S VB'_REF is the minimum switch node voltage reference signal S MIN ', and the third switch node voltage reference signal S VC'_REF is the intermediate switch node voltage reference signal S INT '. For example, in the second operation phase P2, the first switch node voltage reference signal S VA'_REF is the maximum switch node voltage reference signal S MAX ', the second switch node voltage reference signal S VB'_REF is the intermediate switch node voltage reference signal S INT ', and the third switch node voltage reference signal S VC'_REF is the minimum switch node voltage reference signal S MIN '.

[0112] Hereinafter, the input voltage having the highest voltage level is referred to as the maximum input voltage Vmax, the input voltage having the lowest voltage level is referred to as the minimum input voltage Vmin, and the input voltage having a voltage level between the highest voltage level and the lowest voltage level is referred to as the intermediate input voltage V INT . Then, the above line-to-line voltage V LL is given by V LL = Vmax - Vmin. Referring to the above, in the steady state, the switch node voltage reference signal S VA'_REF, S VB'_REF , S VC'_REF Basically follows the input voltages V1, V2, V3, so Figure 12 the output signal S of the subtractor 62 shown MAX '-S MIN ' basically represents the line-to-line voltage V LL . Figure 13 The subtractor output signal S is also shown in MAX '-S MIN '.

[0113] Reference Figure 13 , operating the power converter in 1 / 3 mode includes enabling the leg associated with the intermediate voltage reference signal S INT ' and disabling the legs associated with the maximum switch node voltage reference signal S MAX ' and the minimum switch node voltage reference signal S MIN '. That is, in the first operation phase P1, for example, the third leg 1 3 is enabled, and in the second operation phase P2, the second leg 1 2 is enabled, and so on.

[0114] Referring to the above, the legs 1 1 , 1 2 , 1 3 are enabled and disabled by the PWM modulator 44 in the control circuit 4. According to one example, the PWM circuit 44 is configured to calculate the duty cycles d1, d2, d3 based on the following equations:

[0115]

[0116]

[0117]

[0118] These equations are based on Equation (3c). In addition, in 1 / 3 mode, the common-mode voltage VCM represented by the common-mode signal S VCM received by the PWM modulator is selected such that

[0119]

[0120] Figure 13 The common-mode voltage signal S VCM representing the common-mode voltage VCM is also shown within one period of the input voltage. When adjusting the duty cycles d1, d2, d3 according to Equations (4A)-(4C) and (5), the maximum switch node voltage reference signal S MAX'The duty cycle of the associated leg is always "automatically" set to +1 during the corresponding operation phase, thereby clamping the corresponding switch node to VX. In addition, the minimum switch node voltage reference signal S MIN 'The duty cycle of the associated leg is always "automatically" set to -1 during the corresponding operation phase, thereby clamping the corresponding switch node to VZ. This will be explained below.

[0121] Hereinafter, dmax represents the duty cycle of the leg associated with the maximum switch node voltage reference signal S MAX 'during the corresponding operation phase, while dmin represents the duty cycle of the leg associated with the minimum switch node voltage reference signal S MIN 'during the corresponding operation phase. In addition, Vmax' represents the desired switch node voltage represented by the maximum switch node voltage reference signal S MAX ', while Vmin' represents the desired switch node voltage represented by the minimum switch node voltage reference signal S MIN '. Based on one of equations (4a)-(4c) and equation (5), and considering that the DC link voltage V4 is adjusted such that V4 = Vmax' - Vmin', the duty cycle dmax and the duty cycle dmin are given by the following

[0122]

[0123]

[0124] Referring to the above, when the first power converter 10 operates in the 1 / 3 mode, the DC link voltage V4 is adjusted by the second converter 5 such that it is equal to Vmax' - Vmin', where Vmax' is the maximum of the desired switch node voltages and Vmin' is the minimum of the desired switch node voltages. In the steady state, these desired switch node voltages Vmax', Vmin' are substantially equal to the maximum input voltage Vmax and the minimum input voltage Vmin, respectively, such that the varying DC link voltage V4 is substantially equal to the line-to-line voltage V LL . This is the lowest possible DC link voltage that enables sinusoidal input currents I1, I2, I3, where in this case the common-mode voltage VCM is different from zero and is given by equation (5).

[0125] Figure 9 The power converter device shown in is not limited to generating a DC link voltage V4 such that it is defined by S MAX '-S MIN 'and is substantially equal to the line-to-line voltage V LL . Figure 14shows an example of a second control circuit branch 6 that is configured to generate a DC link voltage V4 such that, during some time periods, it is defined by a subtractor output signal S62 (= S MAX '- S MIN '), and during some time periods is higher than that defined by the subtractor output signal S62. In this example, a maximum selector 68 receives the subtractor output signal S62 and a minimum DC link voltage signal S V4_MIN , where the minimum DC link voltage signal S V4_MIN represents the minimum value of the DC link voltage V4 that should be generated at the output of the first power converter 10. The maximum selector outputs the maximum of the two signals it receives to a multiplier 63. Hereinafter, the voltage represented by the minimum DC link voltage signal S V4_MIN will be referred to as the minimum desired DC link voltage V4 MIN .

[0126] When the minimum desired DC link voltage V4 MIN is the minimum value of the subtractor output signal S62 or lower, the DC link voltage is generated as described above, and the first power converter 10 operates in the full 1 / 3 mode, that is, the power converter always operates in the 1 / 3 mode in each of the six operation phases. Figure 15 Such an operation mode is shown again, where Figure 15 shows the operation of the power converter in the full 1 / 3 mode between a first moment t1 and a second moment t2.

[0127] When the minimum desired DC link voltage signal S V4_MIN is higher than the minimum value of the subtractor output signal S62, the DC link voltage V4 is generated such that during the time period when the subtractor output signal S62 is higher than the minimum desired DC link voltage signal S V4_MIN , the DC link voltage V4 is generated based on the subtractor output signal S62. During the remaining time, the DC link voltage V4 is generated based on the minimum desired DC link voltage signal S V4_MIN . In this type of operation, the power converter does not always operate in the 1 / 3 mode in each of the six operation phases. Instead, there are not only time periods when the first power converter operates in the 1 / 3 mode, but also time periods when each of the bridge arms 1 1 , 1 2 , 1 3 operates in the PWM mode. This is shown between the second moment t2 and the third moment t3 in Figure 15 .

[0128] Between these moments t2, t3, the minimum desired DC link voltage V4 MINis increased to illustrate how the operation of the power converter changes in accordance with the desired DC link voltage V4 MIN The minimum desired DC link voltage V4 MIN is the minimum value of the DC link voltage V4, which is also shown in Figure 15 Basically, as can be seen from Figure 15 the duration of the operation of the power converter in the 1 / 3 mode during one cycle of the input voltages V1, V2, V3 decreases as the minimum DC link voltage V4 MIN increases. The operating mode in which the power converter operates alternately in the 1 / 3 mode and the 3 / 3 mode (as shown between times t2 and t3 in Figure 15 ) is hereinafter referred to as the partial boost mode.

[0129] When calculating the duty cycles d1, d2, d3 according to equations (4a)-(4c), the power converter automatically changes between the 1 / 3 mode and the 3 / 3 mode because these duty cycles depend on the DC link voltage V4 adjusted by the second power converter 5. In the partial boost mode, the common-mode voltage VCM can be the same as in the full 1 / 3 mode. However, during those time periods in which the power converter operates in the 3 / 3 mode in the partial boost mode, the common-mode voltage VCM can be different from the common-mode voltage in the 1 / 3 mode. Only in the full 1 / 3 mode is the common-mode voltage VCM restricted to the value given in equation (5). However, in the partial boost mode and the full boost mode, there is some freedom to adjust the common-mode voltage VCM such that it is different from the value given in equation (5). The freedom available to adjust the common-mode voltage VCM in these operating modes can be used to adjust the common-mode voltage VCM such that the current IY entering the midpoint is minimized. This will be further explained in detail below.

[0130] Figure 16 shows different operating modes of the first power converter 10, which depend on the minimum desired DC link voltage signal S V4_MIN and the phase angles of the input voltages V1, V2, V3. More specifically, Figure 16 shows different operating modes in any one of six operating phases P1 - P6, where each of these operating phases covers 60° of one cycle of the input voltages V1, V2, V3. In Figure 16 , a phase angle of 0° represents the start of the corresponding operating phase, a phase angle of 60° represents the end of the corresponding operating phase, and a phase angle of 30° represents the middle of the corresponding operating phase, which is the moment when the input voltage crosses zero in the middle of the corresponding operating phase.

[0131] Referring to Figure 16 , when the minimum desired DC link voltage signal S V4_MINWhen below the minimum value of the subtractor output signal S62, the power converter operates in the full 1 / 3 mode. Referring to the above, in the steady state, the subtractor output signal S62 substantially represents the line-to-line voltage V LL , such that when the minimum desired DC link voltage V4 MIN is below the minimum line-to-line voltage V LL_MIN , the power converter operates in the full 1 / 3 mode.

[0132] In addition, referring to Figure 16 , when the minimum desired DC link voltage signal S V4_MIN is between the minimum value and the maximum value of the subtractor output signal S62, the power converter operates in the partial boost mode. In the steady state, the maximum value of the subtractor output signal S62 is substantially equal to the maximum line-to-line voltage V LL_MAX , such that when the DC link voltage V4 is between the minimum line-to-line voltage V LL_MIN and the maximum line-to-line voltage V LL_MAX , the power converter operates in the partial boost mode. In the partial boost mode, the portion of the power converter operating in the 3 / 3 mode in the operating phase increases as the minimum desired DC link voltage V4 MIN increases, and the portion of the power converter operating in the 1 / 3 mode in the operating phase decreases as the minimum desired DC link voltage V4 MIN increases.

[0133] Referring to Figure 16 , when the minimum desired DC link voltage signal S V4_MIN is above the maximum value of the subtractor output signal S62, the power converter operates in the full 3 / 3 mode. In this operating mode, the DC link voltage V4 is substantially constant and depends only on the minimum desired DC link voltage signal S V4_MIN .

[0134] In the control circuit shown in Figure 12 and Figure 14 , the control input currents I51, I52 are controlled such that each of the first capacitor voltage VC1 and the second capacitor voltage VC2 is equal to 50% of the desired DC link voltage V4. However, this is only an example. According to Figure 17Another example shown is to control the input currents I51 and I52 such that the first capacitor voltage is equal to k1 times the desired DC link voltage V4, and the second capacitor voltage is equal to k2 times the desired DC link voltage V4, where k1 + k2 = 1, k1 > 0, and k2 > 0. In this case, the first capacitor voltage VC1 and the second capacitor voltage VC2 are different. In this case, the duty cycles d1, d2, and d3 can be calculated by the PWM modulator 44 in the control circuit 4 based on equations (3a) and (3b). Optionally, the second control circuit branch 6 can include a reference Figure 14 selector of the type explained.

[0135] In Figure 12 , Figure 14 and Figure 17 the example shown, the first converter stage 51 and the second converter stage 52 not only regulate the DC link voltage V4, but also regulate the first capacitor voltage VC1 and the second capacitor voltage VC2. According to Figure 18 another example shown, the balancing circuit 7 regulates the ratio of the first capacitor voltage VC1 to the second capacitor voltage VC2. In this case, the first converter stage 51 and the second converter stage 52 only regulate the DC link voltage V4. Additionally, in this case, the two converter stages 51, 52 can be replaced by one converter stage.

[0136] Referring to Figure 19 , the balancing circuit can include a first switch 71 connected between the first DC link node X and an inductor 73 connected to the midpoint Y, and a second switch 72 connected between the second DC link node Z and the inductor 73. The control circuit 74 receives the first capacitor voltage signal S VC1 and the second capacitor voltage signal S VC2 , and is configured to control the operation of the first switch 71 and the second switch 72 such that a predefined ratio, such as 1:1 or k1:k2, exists between these voltages VC1, VC2. By appropriately turning on and off the first switch 71 and the second switch 72, energy can be transferred between the first DC link capacitor C1 and the second DC link capacitor C2. For example, when the first switch is turned on (while the second switch 72 is turned off), energy is taken from the first DC link capacitor C1, stored in the inductor 73, and transferred to the second DC link capacitor C2 when the first switch is turned off and the second switch 72 is turned on. The duty cycles of operating the two switches 71, 72 define the ratio of the capacitor voltages VC1, VC2, where the capacitor voltages VC1, VC2 are substantially equal when the duty cycles of the two switches 71, 72 are 50%.

[0137] Referring to the above, in Figure 9In the power converter device shown, the DC link voltage is adjusted by the second power converter 5, where the output voltage V OUT of the second power converter can be defined by a load such as a battery charged by the power converter device. In addition, the DC link voltage V4 can be adjusted by the above-mentioned minimum DC link voltage signal S V4_MIN . Adjusting the DC link voltage V4 can help achieve a high converter efficiency of the second power converter. Basically, the smaller the difference between the input voltage and the output voltage of the power converter, the higher the efficiency. Therefore, according to one example, the minimum DC link voltage signal S OUT can be adjusted based on the output voltage V V4_MIN , such that the minimum desired DC link voltage V4 MIN increases as the output voltage V OUT increases.

[0138] Another example of reducing the switching mode is called the 2 / 3 + PWM mode and is explained below. In this type of operating mode, the power converter 10 operates either in the 2 / 3 mode or in the 3 / 3 mode (PWM mode). In the 2 / 3 mode, one of the bridge arms 1 1 、1 2 、1 3 is deactivated, and the other two of the bridge arms 1 1 、1 2 、1 3 are enabled, while in the 3 / 3 mode (PWM mode), each of the bridge arms 1 1 、1 2 、1 3 is enabled. Basically, in the Figure 1 and Figure 3 types of power converters 10 shown, the sum of the input currents I1, I2, I3 is zero, i.e., I1 + I2 + I3 = 0. Therefore, by adjusting two of the three input currents I1, I2, I3, the third of the three input currents I1, I2, I3 is automatically adjusted. Therefore, the power converter can be operated such that each time one of the bridge arms 1 1 、1 2 、1 3 is deactivated. One of the bridge arms 1 1 、1 2 、1 3 can be deactivated alternately, each for a predefined period of time. This type of operating mode can be called the full 2 / 3 mode. However, in the full 2 / 3 mode, the midpoint current IY (i.e., the current entering the midpoint Y) may be relatively high. However, the latter can have an adverse effect on the power conversion loss.

[0139] In the 3 / 3 mode, the midpoint current IY (also referred to hereinafter as the common-mode current) can be reduced by appropriately selecting the common-mode voltage VCM. If the insertable common-mode voltage is high enough, the midpoint current IY can even be reduced to zero by appropriately selecting the common-mode voltage. Hereinafter, VCMzmc represents the zero midpoint current (ZMC) common-mode voltage, which is the common-mode voltage when the midpoint current IY is zero. The ZMC common-mode voltage VCMzmc is given by:

[0140]

[0141] where min_abs{VA′; VB′; VC′} (also referred to as Vmin_abs') is the desired switching node voltage among the desired switching node voltages VA', VB', VC' having the lowest absolute value. For example, if |VA'| < |VB'| and |VA'| < |VC'|, then Vmin_abs' = VA'. Thus, the absolute value of Vmin_abs' is equal to the absolute value of the switching node voltage having the lowest absolute value, |Vmin_abs'| = min{|VA'|; |VB'|; |VC'|}, and the sign of Vmin_abs' is equal to the sign of the switching node voltage having the lowest absolute value, so Vmin_abs' can be positive or negative. Similarly, max_abs{VA′; VB′; VC′} (also referred to as Vmax_abs') is the desired switching node voltage among the desired switching node voltages VA', VB', VC' having the highest absolute value. For example, if |VA'| > |VB'| and |VA'| > |VC'|, then Vmax_abs' = VA'.

[0142] On the other hand, in order to achieve sinusoidal input currents I1, I2, I3, there are constraints on the first DC link node voltage VX and the second DC link node voltage VZ such that the first DC link node voltage VX is equal to or higher than the maximum value Vmax' of the desired switching node voltages VA', VB', VC', and the second DC link node voltage VZ is equal to or lower than the minimum value Vmin' of the desired switching node voltages VA', VB', VC', i.e.,

[0143] VX ≥ Vmax' (8a)

[0144] VZ ≤ Vmin' (8b).

[0145] Referring to the above, and Therefore, based on equations (8a) and (8b), it can be shown that the common-mode voltage VCM must satisfy the following inequality in order to obtain sinusoidal input currents:

[0146]

[0147]

[0148] Below,

[0149]

[0150] which represents the maximum allowable common-mode voltage, and

[0151]

[0152] which represents the minimum allowable common-mode voltage.

[0153] To achieve zero neutral-point current and sinusoidal input voltage, the common-mode voltage VCM should satisfy the following conditions,

[0154] VCM = VCMzmc (11a)

[0155] VCMmin ≤ VCM ≤ VCMmax (11b).

[0156] However, especially when the DC-link voltage V4 is close to the maximum line-to-line voltage V LL_MAX , the two conditions (11a), (11b) cannot be satisfied simultaneously.

[0157] According to an example, operating the power converter in 2 / 3 + PWM mode includes:

[0158] (a) As long as the ZMC common-mode voltage VCMzmc is within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, i.e., as long as:

[0159] VCMmin ≤ VCMzmc ≤ VCMmax (12a),

[0160] then operate the power converter in 3 / 3 mode; and

[0161] (b) As long as the ZMC common-mode voltage VCMzmc is outside the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, i.e., as long as:

[0162] VCMzmc > VCMmax (12b),

[0163] or

[0164] VCMzmc < VCMmin (12c),

[0165] then operate the power converter in 2 / 3 mode.

[0166] According to one example, in 3 / 3 mode, the common-mode voltage VCM is adjusted to be equal to the ZMC common-mode voltage VCMzmc. In 2 / 3 mode, the common-mode voltage VCM can be adjusted in various ways such that it is within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin. According to one example, the common-mode voltage VCM is adjusted such that when the ZMC common-mode voltage VCMzmc is greater than the maximum common-mode voltage VCMmax, it is equal to the maximum common-mode voltage VCMmax, and such that when the ZMC common-mode voltage VCMzmc is less than the minimum common-mode voltage VCMmin, it is equal to the minimum common-mode voltage VCMmin.

[0167] Figure 20 A signal diagram is shown which shows the operation of a power converter in 2 / 3 + PWM mode according to one example. In particular, Figure 20 the DC link voltage V4, the input voltages V1, V2, V3, the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the ZMC common-mode voltage VCMzmc, the common-mode voltage VCM, and the drive signals S1, S2, S3 are shown. As can be seen from Figure 20 it, as long as the ZMC common-mode voltage VCMzmc is within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the power converter operates in PWM mode (3 / 3 mode), where the common-mode voltage VCM is adjusted such that it is equal to the ZMC common-mode voltage VCMzmc. When the ZMC common-mode voltage VCMzmc is outside the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the power converter operates in 2 / 3 mode, where the common-mode voltage VCM is adjusted such that when the ZMC common-mode voltage VCMzmc is greater than the maximum common-mode voltage VCMmax, it is equal to the maximum common-mode voltage VCMmax, and such that when the ZMC common-mode voltage VCMzmc is less than the minimum common-mode voltage VCMmin, it is equal to the minimum common-mode voltage VCMmin. Additionally, referring to Figure 20 , one of the leg 1 1 、1 2 、1 3 is alternately deactivated. That is, when the power converter enters 2 / 3 mode, one of the leg 1 1 、1 2 、1 3 is deactivated and remains deactivated as long as 2 / 3 mode prevails. The next time the power converter enters 2 / 3 mode, another one of the leg 1 1 、1 2 、1 3 is deactivated. In this way, the same leg is deactivated every other time the power converter enters 2 / 3 mode.

[0168] According to one example, when the duty cycles d1, d2, and d3 are calculated according to equations (4a), (4b), and (4c) and the common-mode voltage VCM is limited to VCMmax or VCMmin, this deactivation strategy is automatically implemented, that is, when the ZMC common-mode voltage VCMzmc is greater than the maximum common-mode voltage VCMmax, the common-mode voltage VCM is adjusted to be equal to the maximum common-mode voltage VCMmax, and when the ZMC common-mode voltage VCMzmc is less than the minimum common-mode voltage VCMmin, the common-mode voltage VCM is adjusted to be equal to the minimum common-mode voltage VCMmin. When the common-mode voltage VCM is limited to VCMmax, the duty cycle of the arm with the maximum switching node voltage Vmax' becomes +1, thereby automatically deactivating the corresponding arm. Similarly, when the common-mode voltage VCM is limited to VCMmin, the duty cycle of the arm with the minimum switching node voltage Vmin' becomes -1, thereby automatically deactivating the corresponding arm.

[0169] Figure 20 The midpoint current IY is further shown. As can be seen, the midpoint current IY is zero in the 3 / 3 mode and is non-zero only in those time periods (at those phase angles) when the power converter operates in the 2 / 3 mode.

[0170] Basically, the duration of the time period during which the power converter operates in the 2 / 3 mode in one cycle of the input voltage depends on the DC link voltage V4. This is shown in Figure 21 and Figure 22 is shown.

[0171] Figure 21 Shows the different operating modes of the first power converter 10 depending on the DC link voltage V4 and the phase angles of the input voltages V1, V2, and V3. More specifically, Figure 21 shows the different operating modes in any one of the six operating phases P1 - P6, where each of these operating phases covers 60° of one cycle of the input voltages V1, V2, and V3. In Figure 21 0° phase angle represents the start of the corresponding operating phase, 60° phase angle represents the end of the corresponding operating phase, and 30° phase angle represents the middle of the corresponding operating phase, which is the moment when the middle input voltage crosses zero in the corresponding operating phase.

[0172] Referring to the above, when the DC link voltage V4 is greater than the maximum line-to-line voltage V LL_MAX the power converter can operate in the 2 / 3 + PWM mode. In the 2 / 3 + PWM mode, the portion of the power converter that operates in the 3 / 3 mode in the operating phase increases as the DC link voltage V4 increases, and the portion of the power converter that operates in the 2 / 3 mode in the operating phase decreases as the minimum desired DC link voltage V4 MINdecreases as it increases. In addition, when the DC link voltage V4 causes the ZMC common-mode voltage VCMzmc to always be within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin during one cycle of the input voltages V1, V2, V3, the power converter operates in the full 3 / 3 mode. The DC link voltage threshold V4 when the power converter changes from the 2 / 3 + PWM mode to the full 3 / 3 mode FULL _ 3_3 is greater than the maximum line-to-line voltage V LL_MAX and less than twice the amplitude of the input voltages V1, V2, V3.

[0173] Referring to the above, the power converter can be operated in the 2 / 3 mode at each DC link voltage V4 higher than the maximum line-to-line voltage V LL_MAX . Therefore, the power converter can be operated in the 2 / 3 mode or the 2 / 3 + PWM mode at a DC link voltage higher than V4 FULL _ 3_3 . However, this will increase the midpoint current IY, so this is not desirable. However, operating the power converter in the 2 / 3 + PWM mode at a DC link voltage between the maximum line-to-line voltage V LL_MAX and V4 FULL _ 3_3 helps to reduce losses.

[0174] Figure 22 Signal diagrams showing the drive signals S1, S2, S3, the input voltages and input currents I1, I2, I3, and the DC link voltage in the 2 / 3 + PWM mode and the full 3 / 3 mode are shown. As can also be seen from these signal diagrams, the duration of the period during which the power converter operates in the 2 / 3 mode decreases as the DC link voltage V4 increases.

[0175] Figure 1 or Figure 3 The type of power converter shown can be operated in the 2 / 3 + PWM mode by the control circuit shown Figure 23 . This control circuit is based on the control circuit shown Figure 6 and includes a PWM modulator 44 of the type described previously herein, which generates the duty cycles of the drive signals S1, S2, S3 according to equations (4a)-(4c). In addition, a common-mode signal generator 45 is configured to generate a common-mode voltage signal S VCM received by the PWM modulator such that (a) when the ZMC common-mode voltage VCMzmc is within the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the common-mode voltage signal S VCMThe represented common-mode voltage VCM is equal to the ZMC common-mode voltage VCMzmc; and (b) when the ZMC common-mode voltage VCMzmc is outside the range given by the maximum common-mode voltage VCMmax and the minimum common-mode voltage VCMmin, the common-mode voltage VCM is within this range. In order to calculate the maximum common-mode voltage VCMmax, the minimum common-mode voltage VCMmin, and the ZMC common-mode voltage VCM according to equations (7), (10a), and (10b) zmc The common-mode signal generator 45 receives a DC-link voltage signal S representing the DC-link voltage V4 V4 and switch-node voltage reference signals S representing the desired switch-node voltages VA', VB', VC' VA'_REF 、S VB'_REF 、S VC'_REF ,。

[0176] In the above explanation, it is assumed that when the DC-link voltage V4 is higher than the maximum line-to-line voltage V LL_MAX , the (first) power converter 10 can operate in the 2 / 3+PWM mode. When the DC-link voltage V4 is higher than the maximum line-to-line voltage V LL_MAX , the power converter operates in the full boost mode. However, when the power converter 10 operates in the above partial boost mode, the 2 / 3+PWM mode can also be used. This is described below with reference to Figure 24 and Figure 25 This is illustrated below.

[0177] Figure 24 Shows the different operating modes of the first power converter 10 depending on the DC-link voltage V4 and the phase angles of the input voltages V1, V2, V3 in any one of the six operating phases P1 - P6. Referring to the above, when the DC-link voltage V4 is substantially between the minimum line-to-line voltage V LL_MIN and the maximum line-to-line voltage V LL_MAX , the power converter operates in the partial boost mode. In the example shown in Figure 24 , in the partial boost mode, the power converter operates in the 1 / 3 mode, 2 / 3 mode, or 3 / 3 mode, where as the DC-link voltage V4 increases, the phase angle range (duration of the time period) in which the power converter operates in the 1 / 3 mode decreases, and the phase angle ranges in which the power converter operates in the 2 / 3 or 3 / 3 modes increase.

[0178] Figure 25 Shows the corresponding signal diagrams for operating the power converter in the partial boost mode and the 2 / 3+PWM mode.

[0179] When generating a common-mode voltage signal S using a common-mode voltage signal generator 45 of the type explained with reference to Figure 22 , it can be done through VCM When generating a common-mode voltage signal S using a common-mode voltage signal generator 45 of the type explained with reference to Figure 10implemented by a control circuit of the type shown to Figure 24 and Figure 25 operate the first power converter 10 in a partial boost mode of the type shown. In this case, when the second power converter 5 generates a DC link voltage V4 such that it is equal to the voltage represented by Smax'-Smin', the common-mode voltage signal generator 45 automatically generates a common-mode signal so that the common-mode voltage VCM complies with Equation (5), i.e., the common-mode voltage used in the 1 / 3 mode.

Claims

1. A method, comprising: operating a power converter (10) in a reduced switching mode, wherein the power converter is configured to be connected to another power converter (5), and wherein the power converter comprises: three input nodes (A, B, C), each input node being configured to receive a respective one of three input voltages (V1, V2, V3); two DC link nodes (X, Z), configured to provide a DC link voltage (V4); a midpoint (Y), coupled to each of the two DC link nodes (X, Z); three inductors (L1, L2, L3), each inductor being connected to a respective one of the three input nodes (A, B, C); and Rectifier bridge (1), comprising three bridge arms (1 1 、1 2 、1 3 ), each bridge arm being coupled to a respective one of the three input nodes (A, B, C) by a respective one of the three inductors (L1, L2, L3) and being connected to a respective one of the three inductors (L1, L2, L3) at a respective switching node (A', B', C'), wherein each of the three bridge arms (1 1 、1 2 、1 3 ) is connected to the two DC link nodes (X, Z) and the midpoint (Y) and comprises at least one electronic switch (Q1, Q2, Q3), wherein operating the power converter in the reduced switching mode comprises operating the power converter in a 1 / 3 mode, wherein operating the power converter in the 1 / 3 mode comprises: Calculate the expected switching node voltages (VA', VB', VC') of each of the said bridge arms (1 1 , 1 2 , 1 3 ), and During at least a specific part of the period of the input voltages (V1, V2, V3), one associated with the maximum value (Vmax') of the desired switch node voltages (VA', VB', VC') and one associated with the minimum value (Vmin') of the desired switch node voltages (VA', VB', VC') in the arm are deactivated, and the remaining arms in the three arms (1 1 、1 2 、1 3 ) are activated, and wherein the method further comprises: regulating the DC link voltage (V4) by the other power converter (5) that receives the DC link voltage (V4), and The regulated output current (I OUT ) or the regulated output voltage (V OUT ) different from the DC link voltage (V4) is provided by the said further power converter (5). wherein each of the desired switch node voltages (VA', VB', VC') depends on a respective one of the input voltages (V1, V2, V3) and the output parameters (I OUT , V OUT ) of the other power converter (5). wherein regulating the DC link voltage (V4) by the other power converter (5) comprises regulating the DC link voltage (V4) based on a difference between a maximum value (Vmax') of the desired switch node voltages (VA', VB', VC') and a minimum value (Vmin') of the desired switch node voltages (VA', VB', VC'), and wherein the method further comprises: adjusting a switch node voltage of an enabled leg by switching-mode operation of at least one electronic switch in the enabled leg according to the desired switch node voltage associated with the enabled leg.

2. The method according to claim 1, further comprising: operating the power converter in the 1 / 3 mode throughout a period of the three input voltages (V1, V2, V3).

3. The method according to claim 1, further comprising: operating the power converter in the 1 / 3 mode during a specific portion of a period of the three input voltages (V1, V2, V3).

4. The method according to claim 3, further comprising: operating the power converter in a 3 / 3 mode during a remaining time of a period of the three input voltages (V1, V2, V3), in which no leg is deactivated in the 3 / 3 mode.

5. The method according to claim 3, further comprising: operating the power converter in a 2 / 3 mode or in a 3 / 3 mode during a remaining time of a period of the three input voltages (V1, V2, V3), in which one of the legs is deactivated in the 2 / 3 mode, while no leg is deactivated in the 3 / 3 mode.

6. The method according to any one of claims 1 - 5, wherein, The output parameter is the output current (I OUT ) of the other power converter (5).

7. The method according to any one of claims 1 - 5, wherein, the output parameter is an output voltage of the other power converter (5).

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