Drivers for driving capacitive loads

Abstract

A circuit includes a first bipolar junction transistor (BJT) (Q1) and a second BJT (Q2). The first BJT (Q1) includes a first base, a first collector, and a first emitter. The first collector is connected to a first power supply voltage node (115). The second BJT (Q2) includes a second base, a second collector, and a second emitter. The second collector is connected to the first emitter at an output node (118). The circuit also includes a capacitor (CI) including a first capacitor terminal and a second capacitor terminal. The first capacitor terminal is connected to the second emitter of the second BJT (Q2), and the second capacitor terminal is connected to a second power supply voltage node (116). A current source device (II) is connected in parallel with the capacitor (CI).

Description

Background Art

[0001] Certain types of loads are driven using driver circuits that produce relatively large pulsed currents to the loads, these types of loads have capacitive input impedances (e.g., passive mixers) and require relatively high slew rate drivers for certain performance requirements. Such driver circuits should be designed for high voltage swings and high slew rates to achieve adequate linearity and noise performance. Complementary metal oxide semiconductor field effect transistor (CMOS) drivers typically have fairly high power efficiency but lack adequate speed performance. Bipolar junction transistor (BJT) drivers are typically faster than CMOS drivers, but require high current levels and therefore consume more power than CMOS drivers. Summary of the invention

[0002] In one example, a circuit includes a first bipolar junction transistor (BJT) and a second BJT, the first BJT including a first base, a first collector, and a first emitter, the first collector being connected to a first power supply voltage node, the second BJT including a second base, a second collector, and a second emitter, the second collector being connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being connected to the second emitter of the second BJT, and the second capacitor terminal being connected to the second power supply voltage node. A current source device connected in parallel with the capacitor is also included.

[0003] In another example, a circuit includes a first BJT, a second BJT, a capacitor connected to an emitter of the second BJT, and a second supply voltage node. The circuit also includes a current source device connected in parallel with the capacitor. The control circuit is coupled to receive a first control signal for the first base and opposite to the logic state of the first control signal to generate a second control signal for the second base.

[0004] In yet another example, a circuit includes a first BJT, a second BJT, and a current source device connected to an emitter of the second BJT at a second node and configured to be coupled to a capacitor in parallel with the current source device at the second node. A control circuit is coupled to receive a first control signal for the first base and opposite to the logic state of the first control signal to generate a second control signal for the second base. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A driver for driving a capacitive load according to one example is shown.

[0006] Figure 2 A timing diagram is provided that illustrates the operation of the driver described herein.

[0007] Figure 3 Including depiction and Figure 1 A flowchart of a method associated with a driver.

[0008] Figure 4 Another example of a driver for driving a capacitive load is shown.

[0009] Figure 5 Including depiction and Figure 4 A flowchart of a method associated with a driver.

[0010] Figure 6 Yet another example of a driver for driving a capacitive load is shown.

[0011] Figure 7 Including depiction and Figure 6 A flowchart of a method associated with a driver. DETAILED DESCRIPTION

[0012] The disclosed examples relate to a push-pull BJT driver with capacitive boost that supports capacitive load current with lower total power consumption than at least some other drivers. The disclosed driver can drive a load such as a capacitive load. In one application, the load is a passive mixer that is driven by a high slew rate square wave control signal, so that during the rising transition of the control signal in the first operating state of the driver (charging phase), the driver delivers a current pulse to the capacitive load. During the subsequent falling transition of the control signal (discharging phase), the driver receives a current pulse of similar size from the load. More specifically, in one embodiment, in one operating state of the driver, the driver charges the capacitive load very quickly through a first transistor (e.g., BJT). In the subsequent operating state, the first transistor is turned off and the second transistor is turned on to quickly discharge the charge from the capacitive load through a parallel combination of a current source device and a capacitor. Part of the current from the capacitive load charges the capacitor, and the current through the current source device includes the remainder of the current from the capacitive load. Then, when the second transistor is turned off and the first transistor is turned on, the first operating state of the driver is restored, the charge on the capacitor (previously received from the capacitive load) is discharged through the current source device, and the capacitive load is charged again through the first transistor as described above. The driver shown is capable of high speed operation at a high slew rate at a lower power consumption level than at least some other drivers.

[0013] Figure 1An example of a driver 100 for driving a capacitive load 150 is shown. The capacitive load 150 is represented by a capacitor CL, and the capacitive load is also referred to as a capacitive load CL in this article. The capacitive load CL includes, for example, a passive mixer or other types of loads whose input impedance is capacitive. The driver 100 includes transistors Q1 and Q2, a capacitor C1, a current source device I1, a control circuit 110, and a register group 120. In this example, Q1 is a bipolar junction transistor (BJT), and is specifically an NPN BJT. In other examples, metal oxide semiconductor field effect transistors (MOS) can be used to implement Q1 and Q2. The collector of Q1 is connected to a fixed power supply voltage (VDD) node 115. The base of Q1 is coupled to receive an input control signal CTL1. CTL1 is also provided to the control circuit 110. The emitter of Q1 is connected to the collector of Q2 at an output node 118. Q1 is configured as a voltage follower and therefore generates a voltage on the emitter of Q1 based on CTL1 and provides that voltage to a capacitive load CL which is coupled to the driver 100 at the output node 118. Q2 is also configured as a voltage follower which follows the voltage of CTL2 during its rising transition and high state.

[0014] In one example, register set 120 includes a single externally accessible register. In other examples, register set 120 includes two or more externally accessible registers. Register set 120 is programmable, so one or more adjustment values ​​can be loaded by an external device. These adjustment values ​​are used to adjust one or more electrical characteristics of the disclosed circuits described herein. Register set 120 is accessible to be read by control circuit 110 for reading. In some examples, control circuit 110 can also write to the register set.

[0015] The components of driver 100 including Q1, Q2, C1, I1, control circuit 110 and register set 120 are formed on a common semiconductor die 102, i.e., Q1, Q2, C1, I1, control circuit 110 and register set 120 are on the same chip. In this example, capacitive load CL is not on the same semiconductor die 102, but in other examples, capacitive load CL is on the same semiconductor die as driver 100.

[0016] exist Figure 1In the example of , Q1 is an NPN BJT, but in other examples it can be a different type of transistor (e.g., a PNP BJT, a metal oxide semiconductor field effect transistor (MOSFET), etc.). The control circuit 110 generates another control signal CTL2 to control the on / off state and voltage transition of Q2. Q2 is also coupled to one terminal of capacitor C1, and the other terminal of capacitor C1 is connected to another fixed power supply voltage node 116 (e.g., ground). The current source device I1 is coupled in parallel with C1. Sometimes, the code "I1" is used in this article to refer to the current source device, and at other times refers to the current through the current source device. Node 125 represents the node interconnecting the emitter of Q2, capacitor C1, and current source device I1. The current source device I1 may include one or more transistors, resistors, Zener diodes, and / or other circuit components, and typically causes a predetermined amount of current to flow through the current source device in the direction of the arrow.

[0017] In this example, control signals CTL1 and CTL2 generally include periodic signals (e.g., clock signals) and are complementary to each other. That is, when CTL1 is logic high, CTL2 is logic low, and vice versa. In addition, this means that when CTL1 rises, CTL2 falls, and vice versa (i.e., their transitions are also complementary). Control circuit 110 receives CTL1 and generates CTL2 that is complementary to CTL1.

[0018] Now refer to Figure 1 and Figure 2 The corresponding timing diagram is used to explain Figure 1 of the drive operation. Figure 1 The driver 100 has two operating states controlled by CTL1 and CTL2. One operating state is a charging state and occurs when CTL1 is logic high and CTL2 is logic low. The other operating state is a discharging state and occurs when CTL1 is logic low and CTL2 is logic high. Figure 2 Example waveforms for CTL1 and CTL2 are shown. The period of CTL1 is represented as T, and the rise time (and fall time) of CTL1 is represented as Ttr. The peak-to-peak voltage of CTL1 is shown as VPP. CTL2 is a similar waveform, but its peak-to-peak voltage is proportional to the VPP of CTL1. As shown, the peak-to-peak voltage of CTL2 is β*VPP, so β ​​is the ratio of the peak-to-peak voltage of CTL2 to the peak-to-peak voltage of CTL1. The period and rise and fall times of CTL2 are the same as those of CTL1.

[0019] In the charging state (starting at 201), Q1 is turned on and Q2 is turned off. Because Q1 is turned on, the voltage on the output node 118 and therefore the voltage across the capacitive load CL increases sharply toward VDD. Since the voltage across the capacitive load CL changes sharply, the load current ILOAD flows into CL. The magnitude of ILOAD is given by the following equation (1):

[0020]

[0021] ILOAD waveform Figure 2 , and the magnitude of ILOAD during the Ttr time period is identified at 202. During the time period when Q1 is on and the voltage on the output node 118 is constant without variation, ILOAD is zero and CL has been charged by the sudden ILOAD pulse current.

[0022] Reference numeral 203 identifies the start of the discharge state, at which point Q2 is turned on and Q1 is turned off, as shown. Q2 provides a current path for CL to discharge through the combination of C1 and I1. The discharge current from CL is Figure 1 is shown as I2, and the I2 waveform is Figure 2 . The magnitude of I2 at 204 during the rise time Ttr of CTL2 is generally the same as the magnitude of ILOAD at 202 during the charging state. The amount of charge transferred from CL during the rise time of CTL2 is generally equal to the amount of charge received by CL during the rise time of CTL1. The ILOAD current during the discharge state is indicated at 209 as a negative value, indicating that the direction of the ILOAD current is the same as that of the Figure 1 The direction is opposite to that shown by the arrow associated with ILOAD through CL.

[0023] I2 is divided between C1 and I1. Thus, part of the charge from CL is used to charge C1, and the current through I1 represents the remaining discharge current from CL. Once CL is discharged and the rise time Ttr of CTL2 has ended, the magnitude of I2 drops to the level of I1, as indicated at 205. The voltage on node 125 is Figure 2 206 in FIG. 1 and represents the voltage on C1 because C1 has been charged by CL.

[0024] During the next charging phase starting at 207, Q1 is turned on again to charge CL, and Q2 is turned off, as described above. While CL is charging and Q2 is turned off, C1 releases its charge (which was received by C1 from CL when Q2 was previously turned on) through current source device I1, as shown in FIG. Figure 1The magnitude of I1 is configured so that the discharge of C1 is slower than the charge and discharge of CL. The discharge rate of C1 is Figure 2 208 in FIG. 1 is indicated as the falling voltage of node 125. Typically, C1 discharges within a time period TDISCH, which is approximately half of the period T of control signals CTL1 and CTL2. "Approximately" means plus or minus 10%.

[0025] As in Figure 2 As can be seen in FIG. 1 , during a portion of its period T, the I2 current through Q2 is zero and I1 remains continuously on. However, the disclosed circuit consumes less power than circuits such as a BJT emitter-follower in which the current source connected to the emitter is continuously on and at a level higher than I1. I1 is less than the current in previous BJT emitter-follower implementations because Figure 1 The disclosed circuit uses a majority of the period T to discharge C1 using I1.

[0026] The following discussion provides the mathematical relationships between several circuit parameters. Equation (1) above defines the current flowing to CL during the charging and discharging states of CL. The capacitance of C1 does not have to be the same as the capacitance of CL. The ratio of C1 to CL is represented as α (i.e., C1 = α * CL). The discharge current from CL during its discharge phase is the combined current of I1 and the current flowing to C1, i.e.:

[0027]

[0028] As mentioned above, it is expected that C1 will then discharge through the current source device I1 in half the time of T, so when C1 is discharged, I1 is:

[0029]

[0030] Combining equations (1), (2) and (3) yields:

[0031]

[0032] The product of α and β is expressed as:

[0033]

[0034] where γ is the ratio of Ttr to T. Therefore, I1 can be expressed as:

[0035]

[0036] And therefore, based on equation (1),

[0037]

[0038] Equation (5) relates α (the ratio of C1 to CL), β (the ratio of the peak-to-peak voltage of CTL2 to the peak-to-peak voltage of CLT1), and γ (the ratio of Ttr to T). Therefore, if any two of α, β, and γ are known, the third value can be calculated.

[0039] The foregoing mathematical analysis and relationships are used in the following embodiments. Figure 1 C1 is shown implemented on the same semiconductor die 102 as Q1, Q2, current source device I1, and other components. In this example, C1 has a fixed capacitance value and is therefore known to the user of the driver 100. The magnitude of I1 is adjustable under the control of the control circuit 110. In one example, I1 is implemented as a set of current sources controlled by switches that can be programmed to select one or more current sources. The switches can be programmed via a register set 120. The user has knowledge of the load 150 to be driven, and therefore has knowledge of the capacitance value of CL. In this way, the user can calculate α (the ratio of C1 to CL). The user also knows the timing of the control signal CTL1 to be used to provide the driver 100, and therefore knows T and Ttr. The user can calculate γ (the ratio of Ttr to T). Knowing α and γ allows the user to use equation (5) to calculate β, which indicates the peak-to-peak voltage of CTL2 to be generated by the control circuit 110 to drive Q2.

[0040] Figure 3 Shown to be applicable to Figure 1 An example of a method of driving 100 is provided. Figure 3 The operations in the embodiment may be performed in the order shown or in a different order. In addition, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0041] At 302, the method includes programming adjustment values ​​into the register set 120, and the control circuit 110 adjusts I1 by these adjustment values. According to equation (6), I1 is a function of γ, CL, Ttr and VPP, and γ is a function of Ttr and T. In operation 302, in one example, the adjustment values ​​include Ttr, T, CL and VPP, or values ​​indicating Ttr, T, CL and VPP. According to some or all of these values, the control circuit 110 adjusts I1.

[0042] exist Figure 3 In the example of and other examples described below, programming values ​​into register set 120 in some examples includes transmitting the values ​​from a device external to the driver through a wired interface to driver 100. The external device can be a device on the same circuit board as driver 100, or can be on a different circuit board.

[0043] At 304, the value of α is calculated as the ratio of C1 to CL. At 306, the value of β (Ttr / T) based on α and γ is calculated using equation (5). Then, at 308, the value of β is programmed into register set 120. Finally, at 310, the method includes the control circuit adjusting the peak-to-peak voltage of CTL2 based on β and the previously programmed adjustment value of the peak-to-peak voltage of CTL1. The control circuit may include or be coupled to a circuit that generates a voltage for driving the base of Q2. The circuit may be capable of generating a variable voltage configured by control circuit 110. The variable voltage may be generated using a voltage divider, which may be implemented using a switched resistor or a switched capacitor.

[0044] Figure 4 Another example of a driver 400 for driving a capacitive load 150 is shown. Driver 400 includes transistors Q1 and Q2, capacitor C1, current source device I1, control circuit 410, and register set 415. The collector of Q1 is connected to a fixed supply voltage node 115. The base of Q1 is coupled to receive an input control signal CTL1, and CTL1 is also provided to control circuit 410. The emitter of Q1 is connected to the collector of Q2 at an output node 118. Capacitive load CL is coupled to driver 400 at output node 118.

[0045] The components of driver 100 including Q1, Q2, C1, I1, control circuit 410 and register set 415 are formed on a common semiconductor die 402, i.e., Q1, Q2, C1, I1, control circuit 110 and register set 415 are on the same chip. In this example, capacitive load CL is not on the same semiconductor die 402, but in other examples, capacitive load CL is on the same semiconductor die as driver 400.

[0046] The control circuit 410 generates a control signal CTL2 to control the on / off state of Q2. Q2 is also coupled to one terminal of capacitor C1, and the other terminal of capacitor C1 is connected to another fixed supply voltage node 116. A current source device I1 is coupled in parallel with C1.

[0047] Figure 4 An example similar to Figure 1 The difference between the two examples is that in Figure 1 In the example, C1 has a fixed capacitance, but in Figure 4 In the example, C1 has a variable capacitance. Figure 4In the example of , I1 has an adjustable current magnitude, and C1 is also adjustable. In one example, C1 can be implemented as capacitors coupled in parallel, and each such capacitor can be selected by a switch controlled by the control circuit 410. Each capacitor can have the same or different capacitor value as the other capacitors in the parallel capacitor bank. The operation of the driver 400 is largely as described above with reference to the driver 100.

[0048] Figure 5 Shows that it can be combined Figure 4 The following are examples of methods used by the driver 400. The following may be performed in the order shown or in a different order. Figure 5 Furthermore, the operations may be performed sequentially, or two or more operations may be performed simultaneously.

[0049] At 502, the method includes programming adjustment values ​​into the register set 120, and the control circuit 110 adjusts I1 by these adjustment values. Operation 502 is the same as Figure 3 Operation 302 in is largely the same. According to equation (6), I1 is a function of γ, CL, Ttr, and VPP, and γ is a function of Ttr and T. In operation 502, in one example, the adjustment values ​​include Ttr, T, CL, and VPP. Based on some or all of these values, control circuit 110 adjusts I1. At 504, the value of α is calculated as 1 / (β(2γ+1)), and at 506, the value of α is programmed into register set 415.

[0050] At 508, C1 is adjusted by the control circuit 410 based on the values ​​of α and CL. C1 is α multiplied by CL, and is therefore a scaled version of CL. Figure 4 In the example of , the value of β is fixed (e.g., stored in an unmodifiable portion of register group 415, set by a logic gate within control circuit 410, etc.) and is therefore used by control circuit 410 at 510 to adjust the peak-to-peak voltage of CTL2 based on the value of VPP programmed into register group 415 at 502.

[0051] Figure 6 Shown are similar to Figure 1 Drive 100 or Figure 1 and Figure 4 Another example of driver 400 is driver 600 . Figure 6 The driver 600 includes a control circuit 600 to drive CTL2 to Q2 based on CTL1. The driver 600 also includes a register set 615, which can be programmed with adjustment values ​​by an external device as described above.

[0052] The differences between the drive 600 and the drives 100 and 400 are: Figure 6 Capacitor C1 in is external to semiconductor die 602, which additionally includes control circuit 610, register set 615, Q1, Q2, and current source device I1. In this example, the user selects C1 and places C1 on the same printed circuit board (PCB) that may contain driver 600, for example.

[0053] Figure 7 Shows that it can be combined Figure 6 The following are examples of methods used by the driver 600. The following may be performed in the order shown or in a different order. Figure 7 In addition, the operations may be performed sequentially, or two or more operations may be performed simultaneously. At 702, the method includes programming adjustment values ​​into register group 615, and control circuit 610 adjusts I1 by these adjustment values. Operation 702 is the same as Figure 3 Operation 302 in is largely the same. According to equation (6), I1 is a function of γ, CL, Ttr, and VPP, and γ is a function of Ttr and T. In operation 702, in one example, the adjustment values ​​include Ttr, T, CL, and VPP. Based on some or all of these values, the control circuit 410 adjusts I1. At 704, the value of α is calculated as 1 / (β(2γ+1)), where β is fixed.

[0054] At 706, the method includes selecting a value for C1 based on the values ​​of CL and α. In one example, C1 can be calculated as the product of α and CL (C1 = α * CL). Then, a capacitor with the approximately calculated capacitance is mounted on the PCB along with the driver 600 and connected as shown in FIG. Figure 6 Shown connected to node 125.

[0055] Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. A circuit comprising: A first bipolar junction transistor, namely a first BJT, comprising a first base, a first collector and a first emitter, wherein the first collector is connected to a first power supply voltage node; a second BJT including a second base, a second collector, and a second emitter, the second collector being connected to the first emitter at an output node; a capacitor comprising a first capacitor terminal connected to the second emitter of the second BJT and a second capacitor terminal connected to a second supply voltage node; a current source device connected in parallel with the capacitor, wherein the current source device comprises at least one of a transistor or a Zener diode; a control circuit coupled to receive a first control signal for the first base and to generate a second control signal for the second base opposite to the logic state of the first control signal; and A set of programmable registers accessible to the control circuit, the set of programmable registers being programmed with adjustment values, wherein the control circuit is configured to read the adjustment values ​​from the registers and adjust the peak-to-peak voltage of the second control signal based on at least one of the adjustment values.

2. The circuit of claim 1 , wherein the first BJT is an NPN BJT.

3. The circuit of claim 1, wherein the magnitude of the current generated by the current source device causes the capacitor to be fully discharged within a period of approximately half of a period of the first control signal when the second BJT is turned off.

4. The circuit of claim 1, wherein: During the rising time of the rising edge of the first control signal, the first BJT is turned on, so that the charging current flows through the first BJT to the output node; and When the second control signal is low, the second BJT is turned off, so that the charge on the capacitor is discharged through the current source device. 5 . The circuit of claim 4 , further comprising a capacitive load connected to the output node, and the charging current through the first BJT flows to the capacitive load. 6 . The circuit of claim 4 , wherein during a rising time of a rising edge of the second control signal, the second BJT is turned on, thereby causing current to flow from the output node to both the capacitor and the current source device.

7. The circuit of claim 6, wherein the magnitude of the current provided by the current source device is less than the magnitude of the charging current flowing through the first BJT to the output node.

8. The circuit of claim 1 further comprising a semiconductor die, wherein the capacitor and the first and second BJTs are formed on the semiconductor die.

9. The circuit of claim 8, wherein: The capacitor is adjustable; A first value and a second value are storable in the programmable register set; and The control circuit reads the first value and the second value from the programmable register set and uses the first value and the second value to adjust the capacitor.

10. The circuit of claim 8, wherein: The capacitor has a fixed capacitance value; A third value is storable in the programmable register set; and The control circuit reads the third value from the programmable register set and uses the third value to adjust a magnitude of a voltage of a control signal to be provided to the second base.

11. A circuit comprising: a first bipolar junction transistor, i.e., a first BJT, comprising a first base, a first collector, and a first emitter, wherein the first collector is connected to a first supply voltage node, and the first base is coupled to receive a first control signal; a second BJT including a second base, a second collector, and a second emitter, the second collector being connected to the first emitter at an output node; a capacitor comprising a first capacitor terminal connected to the second emitter of the second BJT and a second capacitor terminal connected to a second supply voltage node; a current source device connected in parallel with the capacitor, wherein the current source device comprises at least one of a transistor or a Zener diode; a control circuit coupled to receive the first control signal for the first base and to generate a second control signal for the second base opposite to the logic state of the first control signal; and A programmable register set accessible to the control circuit, the programmable register set being programmed with adjustment values, wherein the control circuit is configured to read the adjustment values ​​from the registers and adjust the peak-to-peak voltage of the second control signal based on at least one of the adjustment values, and adjust the capacitance value of the capacitor based on at least one other adjustment value.

12. The circuit of claim 11 , wherein the adjustment value comprises at least one of: a value indicating a period of the first control signal; a value indicating a rise time or a fall time of the first control signal; Indicates the value of the capacitance of the capacitive load; a value indicative of a current through the first BJT when charging the capacitive load; and Indicates a value of a peak-to-peak voltage of the first control signal.

13. The circuit of claim 11, wherein the control circuit adjusts a magnitude of current through the current source device based on at least one of the adjustment values ​​read from the programmable register set.

14. The circuit of claim 11, wherein: when the first control signal is asserted to a first logic state and the second control signal is asserted to a second logic state, the first BJT is turned on to conduct current from the first supply voltage node to the output node, and the second BJT is turned off, and the capacitor is discharged through the current source device; as well as During at least a portion of the time that the first control signal is asserted at the second logic state and the second control signal is asserted at the first logic state, the first BJT is turned off, the second BJT is turned on, and a discharge current flows into the output node and through the second BJT and is distributed between the current source device and the capacitor.

15. A circuit comprising: A first bipolar junction transistor, namely a first BJT, comprising a first base, a first collector and a first emitter, wherein the first collector is connected to a first power supply voltage node; a second BJT including a second base, a second collector, and a second emitter, the second collector being connected to the first emitter at an output node; a current source device comprising at least one of a transistor or a Zener diode, wherein the current source device is connected to the second emitter at a second node and is configured to be coupled to a capacitor at the second node in parallel with the current source device; a control circuit coupled to receive a first control signal for the first base and to generate a second control signal for the second base opposite to the logic state of the first control signal; and A set of programmable registers accessible to the control circuit, the set of programmable registers being programmed with adjustment values, wherein the control circuit is configured to read the adjustment values ​​from the registers and adjust the peak-to-peak voltage of the second control signal based on at least one of the adjustment values.

16. The circuit of claim 15, wherein the at least one of the adjustment values ​​comprises a first value indicative of a peak-to-peak voltage of the first control signal, and at least another one of the adjustment values ​​comprises a second value for adjusting the current source device.

17. The circuit of claim 15, wherein the first BJT, the second BJT, the current source device, and the control circuit are fabricated on a same semiconductor die, and the capacitor is not fabricated on the same semiconductor die.

18. The circuit of claim 15, wherein: when the first control signal is asserted to a first logic state and the second control signal is asserted to a second logic state, the first BJT is turned on to conduct current from the first supply voltage node to the output node, and the second BJT is turned off, and the capacitor is discharged through the current source device; as well as When the first control signal is asserted to the second logic state and the second control signal is asserted to the first logic state, the first BJT is turned off, the second BJT is turned on, and a discharge current flows into the output node and passes through the second BJT and the current source device.

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