A composite film layer tabletop protection structure and its film layer production process

By designing a composite film layer structure on the semiconductor device table, including sipos layer I, phosphorus-doped silica layer, chlorine-doped silica layer and sipos layer II, and a PN junction is provided below, the problem of large leakage current in the sipos film in the prior art is solved, and efficient leakage current reduction and high voltage and high temperature characteristics are achieved.

CN111710654BActive Publication Date: 2025-06-20SHANDONG XINNUO ELECTRONIC TECH CO LTD
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Patent Information

Application Number
CN202010579391.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2020-06-23
Publication Date
2025-06-20
Estimated Expiration
2040-06-23

AI Technical Summary

Technical Problem

In the prior art, the leakage current of the sipos film is too large, which is difficult to effectively reduce, affecting the realization of high withstand voltage and high temperature characteristics.

Method used

A composite film layer structure is adopted, including a trench on the table of semiconductor devices. The sipos layer I, a phosphorus-doped silica layer, a chlorine-doped silica layer and a sipos layer II are arranged in sequence outside the trench, and a PN junction is provided below the trench. The film layer thickness and composition are adjusted through the deposition process to achieve a reduction in leakage current.

Benefits of technology

The leakage current is effectively reduced to less than half of the conventional method, while maintaining high voltage and high temperature characteristics, solving the problem of large leakage current in the prior art.

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Abstract

The present invention discloses a composite film layer mesa protection structure and its film layer production process, belonging to the technical field of semiconductor devices. It includes a semiconductor device mesa, and there are grooves on the semiconductor device mesa. It is characterized in that: an SIPOS layer I, a phosphorus-doped silicon dioxide layer, a chlorine-doped silicon dioxide layer, and an SIPOS layer II are sequentially arranged outside the grooves, and a PN junction is arranged below the grooves, which can realize the protection of the thyristor PN junction. A phosphorus-doped silicon dioxide layer with strong gettering ability and a chlorine-doped silicon dioxide with strong ability to fix impurities are deposited in the middle, so that the phosphorus-doped silicon dioxide layer and the chlorine-doped silicon dioxide layer play an effective role in reducing the leakage current near its working point, ensuring both high breakdown voltage and high temperature characteristics, and taking into account the leakage current problem. The leakage current using this method can be reduced to about half of the conventional method. The problems existing in the prior art are solved.
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Description

Technical Field

[0001] A composite film layer mesa protection structure and its film layer production process of the present invention belong to the technical field of semiconductor devices. Background Art

[0002] As Figure 1 shown, in the prior art, the sipos film is a commonly used special passivation film that controls charges through the oxygen ratio to achieve high breakdown voltage and high temperature characteristics. The drawback is that the leakage current is relatively large. The conventional Sipos film is formed according to the Si X O Y ratio (generally about 45% of O:Si), and can be considered a semi-insulating film, so the leakage current will be relatively large. Therefore, how to effectively reduce the leakage current has become an urgent technical problem to be solved at present. Summary of the Invention

[0003] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a composite film layer mesa protection structure and its film layer production process, which solve the problems in the prior art.

[0004] A composite film layer mesa protection structure of the present invention includes a semiconductor device mesa, and there are grooves on the semiconductor device mesa. It is characterized in that: an outer side of the groove is sequentially provided with a sipos layer I, a phosphorus-doped silicon dioxide layer, a chlorine-doped silicon dioxide layer, and a sipos layer II, and a PN junction is provided below the groove.

[0005] Further, a glass layer is provided outside the sipos layer II.

[0006] Further, the film layer thickness of the sipos layer I is

[0007] Further, the film layer thickness of the phosphorus-doped silicon dioxide layer is

[0008] Further, the film layer thickness of the chlorine-doped silicon dioxide layer is

[0009] Further, the film layer thickness of the sipos layer II is

[0010] A production process of a composite film layer of the present invention includes the following steps:

[0011] Step 1, deposit the sipos layer I, with the temperature T = 680°C, the deposition pressure TTL = 300 mtorr, the SiH4 flow rate: 500 * 47% = 235 cc / min, the N2O flow rate: 300 * 17% = 51 cc / min, and the deposition time t = 20 min;

[0012] Step 2: Deposit a phosphorus-doped silicon dioxide layer at a temperature T = 680 °C, a deposition pressure TTL = 230 mtorr, a SiH4 flow rate: 200 * 45% = 90 cc / min, an O2 flow rate: 200 * 28% = 56 cc / min, a PH3 flow rate: 100 * 10% = 10 cc / min, and a deposition time t = 6 min;

[0013] Step 3: Deposit a chlorine-doped silicon dioxide layer at a temperature T = 680 °C, a deposition pressure TTL = 300 mtorr, a SiH4 flow rate: 500 * 38% = 190 cc / min, an N2O flow rate: 300 * 25% = 75 cc / min, an HCL flow rate: 30 cc / min, and a deposition time t = 8 min;

[0014] Step 4: Deposit a sipos layer II at a temperature T = 680 °C, a deposition pressure TTL = 300 mtorr, a SiH4 flow rate: 500 * 47% = 235 cc / min, an N2O flow rate: 300 * 17% = 51 cc / min, and a deposition time t = 40 min.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] A composite film layer mesa protection structure and its film layer production process according to the present invention can achieve the protection of the thyristor PN junction. At the same time, the sipos layer is made into a sandwich biscuit type, with a phosphorus-doped silicon dioxide layer with strong gettering ability and a chlorine-doped silicon dioxide with strong fixed impurity ability deposited in the middle, so that the phosphorus-doped silicon dioxide layer and the chlorine-doped silicon dioxide layer near its working point play an effective role in reducing the leakage current, ensuring both high breakdown voltage and high temperature characteristics, and taking into account the leakage current problem. The leakage current using this method can be reduced to less than half of the conventional method. The problems in the prior art are solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Is a structural diagram of the prior art;

[0018] Figure 2 Is a structural diagram of an embodiment of the present invention;

[0019] Figure 3 Is a structural diagram of the composite film layer in an embodiment of the present invention;

[0020] In the figure: 1, sipos layer I; 2, phosphorus-doped silicon dioxide layer; 3, chlorine-doped silicon dioxide layer; 4, sipos layer II; 5, glass layer. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be further described below with reference to the drawings and embodiments:

[0022] Example 1:

[0023] As shown in Figure 2 the figure, a composite film layer mesa protection structure according to the present invention includes a semiconductor device mesa, a trench is provided on the semiconductor device mesa, an sipos layer I1, a phosphorus-doped silicon dioxide layer 2, a chlorine-doped silicon dioxide layer 3 and an sipos layer II4 are sequentially provided outside the trench, and a PN junction is provided below the trench.

[0024] A glass layer 5 is provided outside the sipos layer II4.

[0025] The film thickness of the sipos layer I1 is

[0026] The film thickness of the phosphorus-doped silicon dioxide layer 2 is

[0027] The film thickness of the chlorine-doped silicon dioxide layer 3 is

[0028] The film thickness of the sipos layer II4 is

[0029] The working principle of this embodiment is as follows: A phosphorus-doped silicon dioxide layer 2 with strong impurity absorption ability and a chlorine-doped silicon dioxide layer 3 with strong fixed impurity ability are deposited in the middle of the composite film layer, so that the phosphorus-doped silicon dioxide layer 2 and the chlorine-doped silicon dioxide layer 3 play an effective role in reducing the leakage current near its working point, ensuring both high breakdown voltage and high temperature characteristics, and taking into account the leakage current problem. The leakage current using this method can be reduced to less than half of the conventional method.

[0030] The thickness of the sipos layer I1 can be finely adjusted according to the product type. The thinner this layer is, the smaller the leakage current is, and the breakdown voltage value will be slightly lower. And the thicker this layer is, the breakdown voltage value will increase, but the leakage current will increase. Adjust the thickness of this layer appropriately according to the actual product requirements and customer requirements to achieve the protection of the thyristor breakdown voltage junction (PN junction).

[0031] Embodiment 2:

[0032] A production process of a composite film layer according to the present invention includes the following steps:

[0033] Step 1, deposit the sipos layer I1, the temperature T = 680 °C, the deposition pressure TTL = 300 mtorr, the SiH4 flow rate: 500 * 47% = 235 cc / min, the N2O flow rate: 300 * 17% = 51 cc / min, and the deposition time t = 20 min;

[0034] Step 2: Deposit the phosphorus-doped silicon dioxide layer 2 at a temperature T = 680°C, deposition pressure TTL = 230 mtorr, SiH4 flow rate: 200 * 45% = 90 cc / min, O2 flow rate: 200 * 28% = 56 cc / min, PH3 flow rate: 100 * 10% = 10 cc / min, deposition time t = 6 min;

[0035] Step 3: Deposit the chlorine-doped silicon dioxide layer 3 at a temperature T = 680°C, deposition pressure TTL = 300 mtorr, SiH4 flow rate: 500 * 38% = 190 cc / min, N2O flow rate: 300 * 25% = 75 cc / min, HCL flow rate: 30 cc / min, deposition time t = 8 min;

[0036] Step 4: Deposit the sipos layer II4 at a temperature T = 680°C, deposition pressure TTL = 300 mtorr, SiH4 flow rate: 500 * 47% = 235 cc / min, N2O flow rate: 300 * 17% = 51 cc / min, deposition time t = 40 min.

[0037] In Step 1, the film thickness of the sipos layer I1 is

[0038] In Step 2, the film thickness of the phosphorus-doped silicon dioxide layer 2 is

[0039] In Step 3, the film thickness of the chlorine-doped silicon dioxide layer 3 is

[0040] In Step 4, the film thickness of the sipos layer II4 is

[0041] The working principle of this embodiment is as follows: The phosphorus-doped silicon dioxide layer 2 contains phosphorus atoms, which carry negative charges by themselves and are very effective in fixing charges and reducing leakage current. Due to the presence of chloride ions (Cl-), the chlorine-doped silicon dioxide can effectively fix active metal ions such as sodium ions (Na+) and potassium ions (K+), reducing the leakage current. The phosphorus-doped silicon dioxide layer 2 and the chlorine-doped silicon dioxide layer 3 can significantly reduce the leakage current. With the assistance of the sipos layer, the combination of the three in a certain proportion can maximize the advantages of all three.

[0042] Table 1: Data comparison table

[0043]

[0044] The data in the above table shows that the technical solution of the embodiment of the present invention can effectively fix active metal ions such as sodium ions (Na+) and potassium ions (K+), reduce the leakage current, and effectively improve the product performance.

[0045] A composite film layer mesa protection structure and its film layer production process according to the embodiments of the present invention described above in conjunction with the accompanying drawings can achieve the protection of the thyristor withstand voltage junction (PN junction), high withstand voltage and high temperature characteristics, and also take into account the leakage current problem, solving the problems that occur in the prior art. However, the present invention is not limited to the described embodiments, and changes, modifications, substitutions, and deformations made to these embodiments without departing from the principles and spirit of the present invention still fall within the protection scope of the present invention.

Claims

1. A production process of a composite film layer, applied to a table protection structure of a composite film layer. The structure includes a semiconductor device tabletop, and there are grooves on the semiconductor device tabletop. It is characterized in that: An SIPOS layer I (1), a phosphorus-doped silicon dioxide layer (2), a chlorine-doped silicon dioxide layer (3), and an SIPOS layer II (4) are sequentially provided outside the groove, and a PN junction is provided below the groove; a glass layer (5) is provided outside the SIPOS layer II (4); the film thickness of the SIPOS layer I (1) is The film thickness of the phosphorus-doped silicon dioxide layer (2) is The film thickness of the chlorine-doped silicon dioxide layer (3) is The film thickness of the SIPOS layer II (4) is The process includes the following steps: Step 1, deposit the SiPOS layer I (1), temperature T = 680 °C, deposition pressure TTL = 300 mtorr, SiH4 flow rate: 500 * 47% = 235 cc / min, N2O flow rate: 300 * 17% = 51 cc / min, deposition time t = 20 min; Step 2, deposit the phosphorus-doped silica layer (2), temperature T = 680 °C, deposition pressure TTL = 230 mtorr, SiH4 flow rate: 200 * 45% = 90 cc / min, O2 flow rate: 200 * 28% = 56 cc / min, PH3 flow rate: 100 * 10% = 10 cc / min, deposition time t = 6 min; Step 3, deposit the chlorine-doped silica layer (3), temperature T = 680 °C, deposition pressure TTL = 300 mtorr, SiH4 flow rate: 500 * 38% = 190 cc / min, N2O flow rate: 300 * 25% = 75 cc / min, HCL flow rate: 30 cc / min, deposition time t = 8 min; Step 4, deposit the SiPOS layer II (4), temperature T = 680 °C, deposition pressure TTL = 300 mtorr, SiH4 flow rate: 500 * 47% = 235 cc / min, N2O flow rate: 300 * 17% = 51 cc / min, deposition time t = 40 min.

Citation Information

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