Ultra-low voltage trigger device and its manufacturing method

Abstract

Ultra-low voltage trigger device, including a back metal electrode, a P+ substrate layer, an N-type epitaxial layer, an insulating dielectric layer, and a front metal layer from bottom to top in sequence. A P+ isolation layer, an N+ polysilicon, and a P-type base region are arranged in sequence from one side to the other side of the end face of the N-type epitaxial layer; the P+ isolation layer penetrates through to the P+ substrate layer; P+ source regions and N+ source regions are arranged in both the N+ polysilicon and the P-type base region. A manufacturing method of the ultra-low voltage trigger device includes the following steps: depositing an N-type epitaxial layer; performing high-temperature diffusion to form a P+ isolation layer; depositing N+ polysilicon to expose the N-type epitaxial layer; pushing the junction to form a P-type base region; in the regions of the N+ polysilicon and the P-type base region, forming P+ source regions, and then performing photolithography and injecting high-concentration N-type impurities to form N+ source regions; depositing an insulating dielectric layer and completing the front metal layer; depositing the back metal electrode. The present invention effectively reduces costs and trigger voltage, and has an ultra-low trigger voltage and a strong charge discharge capacity.

Description

Technical Field

[0001] The present invention belongs to the field of electronic science and technology, and particularly relates to an ultra-low voltage trigger device and a manufacturing method thereof. Background Art

[0002] Electrostatic discharge (ESD) phenomena widely exist in the daily environment. It is a fatal threat to precision integrated circuits and is one of the important reasons for damage or even failure of integrated circuit products. Integrated circuit products are extremely vulnerable to ESD during their production, manufacturing, assembly, and operation processes, resulting in internal damage to the products and reduced reliability. Moreover, their application environments also have corresponding requirements for parameters such as capacitance, breakdown voltage, and clamping characteristics.

[0003] Nowadays, the era of artificial intelligence combined with the Internet of Things has officially arrived, and smart homes are also playing an increasingly important role in life. With the continuous development of technology, the chips required for the Internet of Things are further developed towards higher integration and lower power consumption, which requires further reduction in the line width of their manufacturing processes. The narrow line width and low power consumption also make the chips more vulnerable and sensitive when suffering from the electrostatic discharge effect, resulting in more stringent electrostatic discharge tests. As the power consumption is further reduced, its power supply voltage is also further reduced, and there are further requirements for ESD devices with low trigger voltage and strong discharge ability.

[0004] According to the characteristics of the low operating voltage of low-power systems. There are requirements for low-voltage ESD protection devices with voltage levels such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, 3.3V, etc. For most of the existing low-voltage system ESD protection devices at present, their breakdown voltages are between 5V and 10V, and true low-voltage ESD protection has not been achieved. Devices commonly used for ESD protection include diodes, GGNMOS (gate-grounded NMOS), BJTs (bipolar junction transistors), SCRs (silicon controlled rectifiers), etc. Low-voltage ESD protection devices often use SCRs to obtain strong discharge ability. However, due to the increasing requirements for the size of ESD devices, it is becoming increasingly important to improve the ESD discharge ability at a certain size. Summary of the Invention

[0005] The purpose of the present invention is to provide an ultra-low voltage trigger device and a manufacturing method thereof with low trigger voltage and high discharge current ability in view of the deficiencies in the existing longitudinal SCR product structure. The snapback voltage of the SCR is reduced by injecting a trigger current into the SCR base region. The trigger current is provided by a forward-biased PN string, and the level of the trigger voltage can be achieved by adjusting the number of forward-biased PN strings. And a polysilicon resistor is integrated to limit the current in the diode path to prevent overcurrent burning in the trigger region and losing the low trigger characteristic.

[0006] Ultra-low voltage trigger device, including a back metal electrode, on which a P+ substrate layer is provided, an N-type epitaxial layer is deposited on the P+ substrate layer, and the end face of the N-type epitaxial layer is advanced at high temperature from one side to the other side to form a P+ isolation layer, deposit N+ polysilicon, and push the junction to form a P-type base region; the P+ isolation layer penetrates through to the P+ substrate layer; P+ source regions are provided in both the N+ polysilicon and P-type base region areas, and then N-type impurities are implanted on the side of the P+ source region between the P+ isolation layer and N+ polysilicon and in the N+ polysilicon and P-type base region areas to form N+ source regions; an insulating dielectric layer is deposited on the N-type epitaxial layer, and a front metal layer is etched on the insulating dielectric layer.

[0007] Further, a thermal oxide layer is provided between the N+ polysilicon and the N-type epitaxial layer.

[0008] Further, the insulating dielectric layer is located between the N-type epitaxial layer and the front metal layer.

[0009] Further, the P+ substrate layer and the N-type epitaxial layer form D1, the P+ source region and the N+ source region form D2, and D1 and D2 form a diode string.

[0010] Further, the P+ substrate layer, the N-type epitaxial layer, the P-type base region, and the N+ source region between the P+ isolation layer and N+ polysilicon form a PNPN thyristor.

[0011] Fabrication method of an ultra-low voltage trigger device, including the following steps:

[0012] 1. Prepare a P+ substrate layer material and deposit an N-type epitaxial layer material;

[0013] 2. Photolithograph and implant boron ions on the surface of the N-type epitaxial layer, and advance at high temperature so that the boron ions diffuse to form a P+ isolation layer with the P+ substrate layer;

[0014] 3. Deposit a mask layer on the silicon wafer surface, photolithograph and etch a groove to form a deep groove, and remove the etch mask layer; the depth of the groove is 1 - 5 μm; after the groove etching is completed, grow a thermal oxide layer of 3000 - 8000 Å by wet oxidation, and the thermal oxidation temperature is between 950 - 1150 °C; then deposit 3 - 5 μm of in-situ doped N+ polysilicon; then perform CMP planarization until the unetched area exposes the N-type epitaxial layer;

[0015] 4. After CMP is completed, perform pre-oxygen growth, photolithograph and implant P-type impurities and form a P-type base region by pushing the junction, the pushing junction temperature is 1150 °C - 1250 °C, and the pushing junction time is 60 min - 300 min; the preferred pushing junction conditions are 1200 °C and 150 min.

[0016] V. In the N+ polysilicon and P-type base regions, P-type impurities are implanted by lithography and then a P+ source region is formed. Subsequently, N-type impurities are implanted by lithography to form an N+ source region. The implantation dose of the P-type impurities is 1E15~1E16 cm-2, and the preferred implementation dosage is 2E15 cm-2. The implantation dose of the N-type impurities is 1E15~1E16 cm-2, and the preferred implementation dosage is 5E15 cm-2.

[0017] VI. Subsequently, an insulating dielectric layer is deposited; reflow densification is adopted, the temperature is 800°C~900°C, and the drive-in time is 15 min~60 min; the preferred implementation drive-in conditions are 850°C and 30 min; the contact hole area is etched by lithography; a metal layer is deposited, and the front metal layer is completed by lithography, etching, and alloying;

[0018] VII. Subsequently, the P+ substrate layer is thinned, and a back metal electrode is deposited.

[0019] Furthermore, for the high-temperature drive-in in step II, the temperature used is 1200°C~1270°C, and the drive-in time is 300 min~600 min. The preferred implementation drive-in conditions are 1250°C and 480 min.

[0020] Furthermore, the energy of the P-type impurities is 30 kev~90 kev.

[0021] The beneficial effects of the present invention are as follows:

[0022] I. The present invention adopts an isolation method of depositing polysilicon in the trench oxidation layer, effectively avoiding the generation of parasitic devices.

[0023] II. As a forward-biased diode string for small-current triggering, the polysilicon diodes formed by the diodes and the four corner regions are utilized, effectively improving the chip utilization rate and reducing the chip cost.

[0024] III. The N+ polysilicon is located behind the thermal oxidation layer grown after deep trench etching, forming effective electrical isolation. After the N+ polysilicon deposition is completed, CMP planarization treatment is carried out. The structure formation in the polysilicon is compatible with the subsequent conventional processes. And the trigger current of the trigger region is introduced into the P-type base region from the first layer, and the trigger current flows into the base trigger region through the shortest path. A series of ultra-low trigger voltage devices are manufactured while minimizing area loss.

[0025] IV. The present invention adopts a forward-biased diode string, which can reduce the snapback current of the SCR to 1.5 V. By adjusting the number of forward-biased diodes in the polysilicon region, trigger voltages of 1.4 V, 2.1 V, 2.8 V, 3.5 V, etc. can be achieved. Ultra-low voltage trigger devices with operating voltages of 1.2 V, 1.8 V, 2 V, 2.5 V, 2.8 V, 3.3 V, etc. voltage levels can be realized.

[0026] V. The method for manufacturing the ultra-low voltage trigger device of the present invention can achieve ultra-low residual voltage by optimizing the device size. Description of the Drawings

[0027] Figure 1 It is a schematic layout diagram of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

[0028] Figure 2 It is an equivalent circuit diagram of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

[0029] Figure 3 It is a schematic diagram of the A-A' cross-section position of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

[0030] Figure 4 It is a longitudinal structure schematic diagram of the A-A' cross-section of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

[0031] Figure 5 It is another implementation structure of the low-voltage ESD protection device based on the vertical SCR structure of the present invention.

[0032] Figure 6 It is the first process step of the A-A' cross-section of the present invention, the growth of the P+ substrate layer material and the N-type epitaxial layer.

[0033] Figure 7 It is the second process step of the A-A' cross-section of the present invention, the implantation and drive-in of the through P+ isolation layer.

[0034] Figure 8 It is the third process step of the A-A' cross-section of the present invention, the etching of the isolation groove and the growth of the isolation oxide layer, the deposition of polysilicon, the surface CMP planarization treatment, and finally the exposure of the silicon material surface.

[0035] Figure 9 It is the fourth process step of the A-A' cross-section of the present invention, the implantation and push of the P-type base region.

[0036] Figure 10 It is the fifth process step of the A-A' cross-section of the present invention, the implantation and push of the N+ source region and the P+ source region.

[0037] Figure 11 It is the sixth process step of the A-A' cross-section of the present invention, the lithography formation of the insulating dielectric layer and the top surface metal layer.

[0038] Figure 12 It is the seventh process step of the A-A' cross-section of the present invention, the thinning of the back P+ substrate layer and the metallization treatment of the back metal electrode.

[0039] Figure 13 This is the TLP test result diagram of the present invention.

[0040] In the figure, 101 is the P+ substrate layer, 102 is the N-type epitaxial layer, 103 is the P+ isolation layer, 104 is the thermal oxide layer, 105 is the N+ polysilicon, 106 is the P-type base region, 107 is the P+ source region, 108 is the N+ source region, 109 is the insulating dielectric layer, 110 is the front metal layer, and 111 is the back metal electrode. Detailed implementation manners

[0041] The present invention will be further described in detail below in conjunction with the accompanying drawings and implementation manners. Taking a P-type substrate material and a 1.2V voltage level as examples for detailed description. The technical solutions described in the present invention are only a part of the implementation examples of the present invention. For the low-voltage ESD protection device of the longitudinal SCR that introduces a forward-biased diode string in the isolated area to control the snapback voltage of the SCR, the number of diode strings can be between 1 and 10, and they are formed by one process, all of which belong to the protection scope of the present invention.

[0042] As Figure 1 shown in the layout diagram of the present invention, the gray area in the figure is the metal layer, the outermost circle is the isolation potential contact area, and the central area is the GND electrode area.

[0043] As Figure 2 shown in the equivalent circuit diagram, the ESD discharge current direction of the present invention is: CH to GND. This channel includes a small current path L1 via the forward-biased diodes D1, D2 and resistors R2, R1, and a large current discharge path L2 of the PNPN SCR. When the two current paths are independent, the turn-on voltage of the small current path is the forward bias voltage of the two diodes, 1.4V. The turn-on voltage of the large current path PNPN transistor is mainly determined by the base region PN junction, and its avalanche breakdown voltage BV>6V. When a voltage pulse impacts the CH port, due to the low turn-on voltage of the small current path, the current I1 first passes through the path L1. The current I1 is injected into the P base region of the NPN transistor and flows through the base short-circuit resistor R1. When I1·R1>0.7V, the NPN in the SCR conducts, and its current I2 is injected into the N-type base region of the PNP transistor, and then the SCR is turned on to quickly discharge the pulse charge. Among them, R2 is a series resistor integrated on the L1 path to prevent excessive shunting of this path under large current, causing the path to burn out.

[0044] As Figure 3 、 4As shown in the figure, the ultra-low voltage trigger device includes a back metal electrode 111. A P+ substrate layer 101 is provided on the back metal electrode 111. An N-type epitaxial layer 102 is deposited on the P+ substrate layer 101. The end face of the N-type epitaxial layer 102 is sequentially subjected to high-temperature diffusion from left to right to form a P+ isolation layer 103, deposit an N+ polysilicon 105, and push the junction to form a P-type base region 106. The P+ isolation layer 103 penetrates through to the P+ substrate layer 101. P+ source regions 107 are provided in both the N+ polysilicon 105 and the P-type base region 106. Then, N-type impurities are implanted on the side of the P+ source region 107 in the region between the P+ isolation layer 103 and the N+ polysilicon 105 and in the region of the N+ polysilicon 105 and the P-type base region 106 to form N+ source regions 108. An insulating dielectric layer 109 is deposited on the N-type epitaxial layer 102, and a front metal layer 110 is etched on the insulating dielectric layer 109.

[0045] The insulating dielectric layer 109 is located between the N-type epitaxial layer 102 and the front metal layer 110.

[0046] The P+ substrate layer 101 and the N-type epitaxial layer 102 form D1, the P+ source regions 107 and the N+ source regions 108 form D2, and D1 and D2 form a diode string.

[0047] The P+ substrate layer 101, the N-type epitaxial layer 102, the P-type base region 106, the P+ isolation layer 103, and the N+ source regions 108 between the N+ polysilicon 105 form a PNPN thyristor.

[0048] Furthermore, it can be seen that the four front metals M1 to M4 are the four front metals in the A-A' direction. M4 is the GND electrode. The back is the back metal electrode CH, and the current has a longitudinal direction. The front metal regions of M1 to M3 are located in the edge region of the layout, and are area-matched according to the current demand, with the potential floating, making the most reasonable use of the chip area.

[0049] Among them, the N+ polysilicon 105 and the N-type epitaxial layer 102 are separated by a thermal oxide layer 104. The P+ source regions 107 and the N+ source regions 108 in the polysilicon form a diode string. When the pulsed voltage exceeds 1.5V, after the polysilicon diode string is turned on, the current flows into the trigger region, the P-type base region 106 of the SCR, through the metal layer, thus triggering the SCR to conduct. Since the trigger current can be adjusted by adjusting the resistance R1 of the P-type base region 106, it is usually controlled within 50 mA. And the integrated polysilicon resistance can be adjusted by adjusting the polysilicon concentration and spacing to prevent the residual voltage from rising under a large current after the SCR conducts and the diode path passing through a large current.

[0050] Furthermore, the N+ polysilicon is located behind the thermal oxide layer grown after deep trench etching, forming an effective electrical isolation, and CMP planarization treatment is performed after the deposition of the N+ polysilicon 105. The structure formation in the polysilicon is compatible with subsequent conventional processes.

[0051] As Figures 6 - 12 shown, a manufacturing method of an ultra-low voltage trigger device includes the following steps:

[0052] I. Prepare the P+ substrate layer 101 material and deposit the N-type epitaxial layer 102 material.

[0053] II. Photolithograph and implant boron ions on the surface of the N-type epitaxial layer 102, and perform high-temperature drive-in so that the boron ions diffuse to form the P+ isolation layer 103 with the P+ substrate layer 101.

[0054] III. Deposit a mask layer on the silicon wafer surface, photolithograph and etch a groove to form a deep groove, and remove the etch mask layer; the depth of the groove is 1 - 5 μm; after the groove etching is completed, grow a thermal oxide layer of 3000 - 8000 Å by wet oxidation, and the thermal oxidation temperature is between 950 - 1150 °C; then deposit 3 - 5 μm of in-situ doped N+ polysilicon 105; then perform CMP planarization until the unetched area exposes the N-type epitaxial layer 102.

[0055] IV. After CMP is completed, perform pre-oxidation growth, photolithograph and ion implant P-type impurities and form the P-type base region 106 by pushing the junction.

[0056] V. In the N+ polysilicon 105 and P-type base region 106 areas, photolithograph and implant high-concentration P-type impurities to form the P+ source region 107, and then photolithograph and implant N-type impurities to form the N+ source region 108.

[0057] VI. Then deposit the insulating dielectric layer 109, after densification, photolithograph and etch the contact hole area. Deposit a metal layer, and complete the front metal layer 110 by photolithography, etching, and alloying.

[0058] VII. Then thin the P+ substrate layer 101 and deposit the back metal electrode 111.

[0059] Furthermore, for the high-temperature drive-in in step II, the temperature is 1250 °C, the pushing-junction time is 300 min, and the punch-through well isolation is adopted to ensure the two-way withstand voltage of the chip and improve the device reliability.

[0060] In step III, the groove etching and thermal oxidation require a small wafer stress to avoid warping caused by excessive wafer stress. Furthermore, after CMP planarization, the high consistency of the effective thickness of polysilicon within the wafer is ensured.

[0061] For the P+ source region 107 and N+ source region 108 in step V, high-concentration ion implantation is adopted, and the energy is 30 kev - 90 kev. By adopting a lower implantation energy combined with a rapid thermal annealing process, a shallower junction depth is achieved to reduce the cell size and improve the current density per unit area of the chip.

[0062] After the via holes are etched in Step 6, a layer of Ti / TiN is deposited and then the metal layer AlSiCu alloy is grown. This can effectively reduce the failure rate of metal overheating while reducing the contact resistance.

[0063] In Step 7, the back metal serves as the back electrode with a longitudinal current path, reducing the package resistance.

[0064] The N+ polysilicon 105 and the N-type epitaxial layer 102 are separated by the thermal oxide layer 104. The diode string is formed by D1 formed by the P+ substrate layer 101 and the N-type epitaxial layer 102 and D2 formed by the P+ source region 107 and the N+ source region 108 in the polysilicon.

[0065] The P+ substrate layer 101, the N-type epitaxial layer 102, the P-type base region 106, and the N+ source region 108 form a PNPN thyristor with an interlayer resistance R1. The resistance of the base region interlayer resistance R1 determines the turn-on current of the SCR. Its trigger current is provided by the forward-biased diode string.

[0066] The thermal oxide layer 104, the P+ substrate layer 101, and the N+ polysilicon 105 do not exist in other parts of the material surface and are removed in the CMP planarization step.

[0067] The insulating dielectric layer 109 is located between the N-type epitaxial layer 102 and the front metal layer 110.

[0068] By adjusting the layout of the P+ source region 107 and the N+ source region 108 in the polysilicon and increasing the spacing to introduce a series polysilicon resistance, it is beneficial to limit the current in the small current path and avoid the overcurrent failure of the small current path due to excessive current.

[0069] The P-type base region 106 can be used to replace the thermal oxide layer 104 and the N+ polysilicon 105 to simplify the process.

[0070] The N-type doping ions can also be phosphorus, arsenic, and antimony particles.

[0071] The manufacturing process of the present invention is as follows:

[0072] First, a phosphorus-doped P-type substrate wafer with a resistivity of 0.001 - 0.005 Ω·cm is used, preferably 0.002 Ω·cm, and the crystal orientation is <111>. Then, a phosphorus-doped N-type epitaxy with a resistivity of 10 - 50 Ω·cm is grown on the surface, with a thickness of 10 - 30 μm. Preferably, the resistivity is 20 Ω·cm and the thickness is 20 μm.

[0073] On the epitaxial deposition mask layer, deep trenches are formed by photolithography and etching, and the etching mask layer is removed. The depth of the trenches is 1 - 5 μm, preferably 3 μm. If the trench depth is too deep, it will cause excessive stress on the original wafer and increase costs. After trench etching is completed, a thermal oxide layer with a thickness of 3000 - 8000 Å is grown by wet oxidation, with a preferred thickness of 5000 Å, and the thermal oxidation temperature is between 950 - 1150 °C.

[0074] Subsequently, 3 - 5 μm of in-situ doped N+ polysilicon 105 is deposited. The preferred thickness is 3 μm. Then, CMP planarization is carried out until the unetched area exposes the N-type material.

[0075] After CMP is completed, pre-oxygen growth is carried out, and P-type boron impurities are implanted by photolithography. The implantation dose is 1E13 - 1E14 cm-2, preferably 5E14 cm-2. High-temperature diffusion is carried out to form a junction depth of 3 - 5 μm.

[0076] In the N+ polysilicon, N-type base region, and P-type base region, high-concentration P-type impurities are implanted by photolithography to form a P+ source region, and then high-concentration N-type impurities are implanted by photolithography to form an N+ source region. The dose of the P+ source region and N+ source region junction depth is 2E15 - 1E16 cm-2, preferably a dose of 5E15 cm-2, and the junction depth is about 0.5 μm.

[0077] Subsequently, an isolation dielectric layer is deposited. A 7000 Å dielectric layer is deposited using the low-pressure tetraethoxysilane growth process (LPTEOS). After refluxing, contact hole etching is carried out. Another layer of TI / TIN is deposited, and then the metal layer AlSiCu alloy is grown. It can effectively reduce the failure ratio of metal overheating while reducing the contact resistance.

[0078] Subsequently, the substrate 101 is thinned to a thickness of 100 - 300 μm, preferably 140 μm, and a back metal electrode 111 is deposited.

[0079] Using the manufacturing method of the low-voltage ESD protection device of the present invention, by simply adjusting the number of series-connected forward-biased diodes in the diode region, the snapback voltage of the SCR can be adjusted, and it can be applied to the ESD protection of low-voltage systems such as 1.2V, 1.8V, 2V, 2.5V, 2.8V, 3.3V, etc. Adjusting the base resistance R1 of the P-type base region can adjust the snapback current of the SCR. At the same time, by adjusting the junction depth and the high-resistance region spacing, ultra-low residual voltage low-voltage ESD protection can be achieved.

[0080] Figure 5 It is a cross-sectional view of an improved A - A' structure of the present invention. Changing the filling of polysilicon after oxidation in the etching trench to PN junction isolation can also achieve the same performance.

[0081] The TLP test results of the ultra-low voltage trigger device of the present invention are as Figure 13 shown.

Claims

1. Ultra-low voltage trigger device, Characterized in that: It includes a back metal electrode (111), a P+ substrate layer (101) is provided on the back metal electrode (111), and an N-type epitaxial layer (102) is deposited on the P+ substrate layer (101); a P+ isolation layer (103) is provided on the left edge of the N-type epitaxial layer (102), and a P-type base region (106) formed by pushing the junction is provided on the right side of the N-type epitaxial layer (102); an N+ polysilicon (105) is provided between the P+ isolation layer (103) and the P-type base region (106), and a thermal oxide layer (104) is provided between the N-type epitaxial layer (102) and the N+ polysilicon (105); the P+ isolation layer (103) penetrates through to the P+ substrate layer (101); P+ source regions (107) are provided in both the N+ polysilicon (105) and the P-type base region (106) regions, and then N-type impurities are implanted on the P+ source region (107) side between the P+ isolation layer (103) and the N+ polysilicon (105) and in the regions of the N+ polysilicon (105) and the P-type base region (106) to form N+ source regions (108); an insulating dielectric layer (109) is deposited on the N-type epitaxial layer (102), and a front metal layer (110) is etched on the insulating dielectric layer (109); the P+ substrate layer (101) and the N-type epitaxial layer (102) form D1, the P+ source region (107) and the N+ source region (108) form D2, and D1 and D2 form a diode string; the P+ substrate layer (101), the N-type epitaxial layer (102), the P-type base region (106), the P+ isolation layer (103) and the N+ source region (108) between the N+ polysilicon (105) form a PNPN thyristor.

2. The ultra-low voltage trigger device according to claim 1, Characterized in that: The insulating dielectric layer (109) is located between the N-type epitaxial layer (102) and the front metal layer (110).

3. A manufacturing method of an ultra-low voltage trigger device, Characterized in that, It includes the following steps: I. Prepare the P+ substrate layer (101) material and deposit the N-type epitaxial layer (102) material; II. Photolithograph and implant boron ions on the surface of the N-type epitaxial layer (102), and perform high-temperature pushing of the junction so that the boron ions diffuse to form the P+ isolation layer (103) with the P+ substrate layer (101); III. Deposit a mask layer on the silicon wafer surface, photolithograph and etch a groove to form a deep groove, and remove the etching mask layer; the depth of the groove is 1 - 5 μm; After the groove etching is completed, grow a thermal oxide layer of 3000 - 8000 Å by wet oxidation, and the thermal oxidation temperature is between 950 - 1150 °C; then deposit 3 - 5 μm of in-situ doped N+ polysilicon (105); then perform CMP planarization until the unetched area exposes the N-type epitaxial layer (102); IV. After CMP is completed, perform pre-oxygen growth, photolithograph and ion implant P-type impurities and form the P-type base region (106) by pushing the junction, the pushing temperature is 1150 °C - 1250 °C, and the pushing time is 60 min - 300 min; V. In the N+ polysilicon (105) and P-type base region (106) areas, P-type impurities are implanted by photolithography and then a P+ source region (107) is formed. Subsequently, N-type impurities are implanted by photolithography to form an N+ source region (108); the P-type impurity implantation dose is 1E15 - 1E16 cm-2; the N-type impurity implantation dose is 1E15 - 1E16 cm-2; VI. Subsequently, an insulating dielectric layer (109) is deposited; reflow densification is carried out at a temperature of 800°C to 900°C, and the drive-in time is 15 min to 60 min; the preferred drive-in conditions are 850°C and 30 min; the contact hole area is etched by photolithography; a metal layer is deposited, and the front metal layer (110) is completed by photolithography, etching, and alloying; VII. Subsequently, the P+ substrate layer (101) is thinned, and a back metal electrode (111) is deposited.

4. The manufacturing method of the ultra-low voltage trigger device according to claim 3, characterized in that: for the high-temperature drive-in in step II, the temperature used is 1200°C to 1270°C, and the drive-in time is 300 min to 600 min.

5. The manufacturing method of the ultra-low voltage trigger device according to claim 3, characterized in that: the energy of the P-type impurities in step IV is 30 kev to 90 kev.

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