Display device

Abstract

A display device is provided. The display device includes: a main area including a display area; a sub-area including a pad; and a substrate having a curved area arranged between the main area and the sub-area, wherein at least one of two outer contours of the curved area includes a curved portion. The curved area includes a structure arranged side by side with the curved portion.

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] With the development of multimedia, the importance of display devices is increasing. Accordingly, various display devices such as liquid crystal display (LCD) and organic light emitting display (OLED) are being used. Among them, organic light emitting display devices are self-luminous elements with excellent viewing angles, and therefore have attracted much attention as the next generation of display devices.

[0003] Generally, a display device has a display area located on a substrate. In such a display device, at least a portion is bent, so that visibility can be improved at various angles or the area of ​​the non-display area can be reduced.

[0004] However, when the display device is bent, cracks may occur due to continuous pressure, and there is a problem that the cracks may propagate inward toward the display area. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a structure of a crack prevention platform and a crack prevention groove arranged in a curved area of ​​a display device to minimize the propagation of cracks.

[0006] The subject of the present invention is not limited to the subject mentioned above, and those skilled in the art should be able to clearly understand other technical subjects not mentioned based on the following description.

[0007] In order to solve the above-mentioned problem, a display device according to an embodiment includes: a main area including a display area; a sub-area including a pad; and a substrate having a curved area arranged between the main area and the sub-area, at least one of two outer contours of the curved area including a curved portion. The curved area includes a structure arranged side by side with the curved portion.

[0008] The distance between two outer contours of the curved region may gradually decrease from the main region toward the sub-region.

[0009] The structure may include a plurality of crack preventing stages arranged in parallel with the curved portion of the bending region, and the substrate may be exposed between the plurality of crack preventing stages.

[0010] The crack preventing stage may be composed of at least one inorganic layer.

[0011] The inorganic layer may include any one of a first insulating layer, a second insulating layer, and a third insulating layer disposed on the substrate.

[0012] The bending region may include a signal wiring region, and a first organic layer may be included on the signal wiring region.

[0013] A plurality of wirings electrically connecting the main region and the sub-region may be included on the first organic layer.

[0014] A second organic layer disposed on the first organic layer may also be included.

[0015] The crack preventing stage may include at least one of the first organic layer and the second organic layer.

[0016] The crack preventing stage may include at least one inorganic layer, and may further include at least one of the first organic layer and the second organic layer on the at least one inorganic layer.

[0017] The structure may further include a crack prevention region between the plurality of wirings and the crack prevention stage.

[0018] The crack prevention area may expose the substrate.

[0019] The substrate may be exposed in a region where the crack prevention groove is arranged.

[0020] The plurality of crack preventing stages may extend in a first direction, and may be spaced apart in a second direction intersecting the first direction.

[0021] The plurality of crack preventing stages may have an island shape that is spaced apart in the first direction.

[0022] The plurality of crack preventing stages may be in a trapezoidal shape in a plane, and may be arranged to be staggered with each other in the first direction.

[0023] In order to solve the above-mentioned problem, a manufacturing method of a display device involved in an embodiment includes: a step of forming at least one barrier layer on a substrate, wherein a main area having a display area and a curved area extending from one side of the main area and having at least one of two sides including a curved portion are defined on the substrate; a step of forming at least one inorganic layer on the barrier layer; a step of etching the at least one barrier layer and the at least one inorganic layer in the curved area to form a plurality of crack prevention stages including at least one barrier layer and at least one inorganic layer; and a step of cutting between the plurality of crack prevention stages using a laser on the substrate.

[0024] The step of forming the crack preventing stage may further include: forming a planarization film on the etched at least one inorganic layer; and etching the planarization film in the curved region to form the plurality of crack preventing stages.

[0025] The step of forming the plurality of crack preventing stages may further include: forming a pixel definition film on the etched at least one planarization film; and etching the pixel definition film in the curved region to form the plurality of crack preventing stages.

[0026] The method comprises at least one crack preventing groove arranged between the plurality of crack preventing stages, wherein the area where the crack preventing groove is arranged exposes the substrate.

[0027] According to a display device according to an embodiment of the present invention, the crack propagation can be minimized by the crack prevention stage and the crack prevention groove structure disposed in the curved region of the display device.

[0028] The effects of the present invention are not limited to the above-exemplified contents, and more effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a plan view of a display device according to an embodiment.

[0030] Figure 2 It is a schematic partial cross-sectional view of a display device according to an embodiment.

[0031] Figure 3 FIG. 1 is a diagram showing the arrangement of signal wiring in a curved region of a panel according to an embodiment of the present invention.

[0032] Figure 4 FIG. 1 is a diagram showing the arrangement of signal wirings in the entire display panel according to an embodiment of the present invention.

[0033] Figure 5 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0034] Figure 6 and Figure 7 is a partial cross-sectional view of a display panel according to an embodiment of the present invention.

[0035] Figure 8 It is along Figure 3 A cross-sectional view taken along region II' is shown.

[0036] Fig. 9 It is magnified Figure 4 A floor plan of area A is shown.

[0037] Fig.10 Another embodiment involves an enlarged Figure 4 A floor plan of area A is shown.

[0038] Fig.11 Yet another embodiment involves an enlarged Figure 4 A floor plan of area A is shown.

[0039] Fig.12 Another embodiment involves the following Figure 3 A cross-sectional view taken along region II' is shown.

[0040] Fig.13 Another embodiment involves Figure 3 A cross-sectional view taken along region II' is shown.

[0041] Fig.14 is a flowchart showing a method for manufacturing a display device according to an embodiment.

[0042] Fig.15 It is a cross-sectional view showing the stacking order of the main region and the bending region according to one embodiment.

[0043]

Explanation of symbols

[0044] DD: display device; DM: display panel; IC: driver chip; FPC: printed circuit board; GD: gate drive circuit; DL: data line; SL: signal wiring; CP: first structure; CD: anti-crack table; CG: anti-crack groove; CR: anti-crack area; SLR: signal wiring area. DETAILED DESCRIPTION

[0045] By reference and attachment Figure 1 The advantages, features and methods of achieving the advantages and features of the present invention should be clear from the detailed embodiments described below. However, the present invention is not limited to the embodiments disclosed below, and can be implemented in various different forms. This embodiment is only provided to make the disclosure of the present invention complete and to fully inform the technical personnel of the technical field to which the present invention belongs of the scope of the invention. The present invention is defined only by the scope of the claims.

[0046] When an element or layer is "on" or "over" another element or layer, it includes not only the case where it is directly on the other element or layer, but also the case where other layers or other elements are sandwiched therebetween. Conversely, referring to an element as being "directly on" or "directly over" means that there are no other elements or layers therebetween.

[0047] Spatially relative terms such as "below", "beneath", "lower", "above", "on", "upper", etc. can be used to easily understand the relationship between an element or constituent element in the diagram and other elements or constituent elements. Spatially relative terms should be understood as terms that include different directions of elements when used or working with the direction of the diagram. For example, in the case of flipping the illustrated elements, the elements recorded as "below" other elements can be located "above" other elements. Therefore, "below" as an illustrative term can include the directions of up and down. Elements can also be oriented along other directions, in which case, the spatially relative terms can be interpreted along the orientation.

[0048] Throughout the specification, the same symbols are used for the same or similar parts.

[0049] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] Figure 1 is a plan view of a display device according to an embodiment of the present invention. Figure 2 is a schematic partial cross-sectional view of a display device according to an embodiment, Figure 3 FIG. 1 is a diagram showing the arrangement of signal wiring in a curved region of a panel according to an embodiment of the present invention.

[0051] exist Figure 1 In the plan view of FIG. 1 , for the convenience of explanation, the directions of up, down, left, and right are defined. The up and down direction is the longitudinal or column direction, and the left and right direction is the transverse or row direction. The directions mentioned in the embodiments should be understood as referring to relative directions, and the embodiments are not limited to the mentioned directions.

[0052] Reference Figures 1 to 3The display device DD is a device for displaying dynamic images or static images. The display device DD can be used not only in portable electronic devices such as mobile phones, smart phones, desktop PCs (Personal Computers), smart watches, watch phones, mobile communication terminals, electronic manuals, electronic books, PMPs (Portable Multimedia Players), navigators, UMPCs (UltraMobile PCs), etc., but also as a display screen for various products such as televisions, notebook computers, monitors, billboards, and the Internet of Things. Examples of the display device DD include organic light-emitting display devices, liquid crystal display devices, plasma display devices, field emission display devices, electrophoretic display devices, electrowetting display devices, quantum dot display devices, and micro-light-emitting diode display devices. In the following, an organic light-emitting display device is used as an example for explanation as a display device, but the present invention is not limited to this.

[0053] The display device DD may include a display panel DM. The display panel DM may include a flexible substrate including a flexible polymer material such as polyimide, etc. Therefore, the display panel DM may be bent, curved, folded, or rolled.

[0054] The display panel DM may include a main region MR and a bending region BD extending from one side of the main region MR. The display panel DM may further include a sub region SR connected to the bending region BD and overlapping the main region MR in a thickness direction.

[0055] In the display panel DM, when the portion displaying the picture is defined as the display area DA and the portion not displaying the picture is defined as the non-display area NDA, the display area DA of the display panel DM is located in the main region MR. In addition to the remaining portion of the display area DA belonging to the non-display area NDA of the display panel DM, in one embodiment, in the main region MR, the peripheral edge portion of the display area DA, the entire bending area BD, and the entire sub-area SR may be the non-display area NDA. However, this is not limited to this, and the bending area BD and / or the sub-area SR may also include the display area DA.

[0056] The main region MR may generally have a shape similar to the outer shape on the plane of the display device DD. The main region MR may be a flat region located on one plane. However, this is not limited thereto, and in the main region MR, at least one edge among the remaining edges except the edge (side) connected to the bending region BD may form a curved surface or be bent in a vertical direction.

[0057] The display area DA of the display panel DM may be arranged in the central part of the main area MR. The display area DA may include a plurality of pixels. Each pixel may include a light-emitting layer and a circuit layer for controlling the light emission of the light-emitting layer. The circuit layer may include display wiring, display electrodes, and at least one transistor. The light-emitting layer may include an organic light-emitting substance. The light-emitting layer may be sealed by a packaging film. The specific structure of each pixel will be described later.

[0058] The display area DA may have a rectangular shape or a rectangular shape with rounded corners, but is not limited thereto, and the display area DA may have various shapes such as a square, other polygonal shapes, or a circular, elliptical, or the like.

[0059] In the main region MR, when at least one of the remaining edges except the edge (side) connected to the bending area BD forms a curved surface or is bent, the display area DA may also be arranged on the corresponding edge. However, the present invention is not limited thereto, and a non-display area NDA where no screen is displayed may be arranged on the curved or bent edge or may be arranged together with the display area DA.

[0060] In the main region MR, a non-display area NDA may be provided around the display area DA. The non-display area NDA of the main region MR may be located in a region extending from the outer boundary of the display area DA to the edge of the display panel DM. In the non-display area NDA of the main region MR, a signal wiring SL or a gate driving circuit GD (see FIG. 1 ) for applying a signal to the display area DA may be provided. Figure 4 ). In addition, the outermost black matrix may be disposed in the non-display area NDA of the main region MR, but the present invention is not limited thereto.

[0061] The curved region BD is disposed between the main region MR and the sub-region SR, and at least one of the two outer contour lines OT-L may include a curved portion. For example, in the curved region BD, the two outer contour lines OT-L connecting one side of the main region MR and one side of the sub-region SR may be curved portions having the same curvature. Figure 4 ) can gradually decrease from the main region MR toward the sub-region SR.

[0062] In the curved region BD, the display panel DM may be curved with a certain curvature along the thickness direction toward the lower direction, in other words, toward the opposite direction of the display surface. The curved region BD may have a certain radius of curvature, but is not limited thereto, and may have different radii of curvature in each section. As the display panel DM is curved in the curved region BD, the surface of the display panel DM is reversed. That is, the following change may be made: a surface of the display panel DM facing upward is directed outward through the curved region BD, and then directed downward again.

[0063] The sub-region SR extends from the bending region BD. The sub-region SR may start to extend in a direction parallel to the main region MR after the bending is completed. The sub-region SR may overlap with the main region MR in the thickness direction of the display panel DM when the bending region BD is bent. The sub-region SR may overlap with the non-display area NDA at the edge of the main region MR, and may further overlap with the display area DA of the main region MR.

[0064] The width of the sub-region SR may be the same as the width of the bending region BD, but is not limited thereto.

[0065] A driver chip IC may be configured on the sub-region SR of the display panel DM. The driver chip IC may include an integrated circuit that drives the display panel DM. In one embodiment, the integrated circuit may be a data driver integrated circuit that generates a data signal to provide it, but is not limited thereto. The driver chip IC may be mounted on the display panel DM in the sub-region SR. The driver chip IC is mounted on one surface of the display panel DM that is the same surface as the display surface, but as the bending area BD is bent and flipped as described above, the driver chip IC is mounted on the surface of the display panel DM facing downward in the thickness direction, so that the upper surface of the driver chip IC may face downward.

[0066] The driver chip IC may be attached to the display panel DM through an anisotropic conductive film, or may be attached to the display panel DM through ultrasonic bonding. The lateral width of the driver chip IC may be smaller than the lateral width of the display panel DM. The driver chip IC may be arranged in the lateral central portion of the sub-region SR, and the left edge and the right edge of the driver chip IC may be respectively away from the left edge and the right edge of the sub-region SR.

[0067] A pad portion PAD may be provided at an end of the sub-region SR of the display panel DM, and a printed circuit board FPC may be connected to the pad portion PAD. The printed circuit board FPC may be a flexible printed circuit board or a film.

[0068] A plurality of signal wirings SL may be configured in the sub-region SR, the bending region BD, and the main region MR. The signal wiring SL may extend from the sub-region SR through the bending region BD to the main region MR. A portion of the signal wiring SL (for example, the initialization voltage line, the voltage line, and the control signal line) may extend from the end of the sub-region SR to the bending region BD and to the main region MR without passing through the driver chip IC. Another portion of the signal wiring SL (for example, the data line DL) may proceed from the end of the sub-region SR to the bending region BD and to the main region MR via the driver chip IC. If the signal wiring SL is passed through the driver chip IC, in order to cover the entire main region MR having a width wider than that of the driver chip IC, a fan-out region (fan-out) may be formed that becomes wider as it proceeds from the sub-region SR and / or the bending region BD to the main region MR side. The signal wiring SL that does not pass through the driver chip IC may proceed along the outside of the signal wiring SL that passes through the driver chip IC.

[0069] The signal wiring SL passing through the bending area BD is bent along with the panel and may be subjected to bending pressure. The bending pressure may cause cracks or disconnection of the signal wiring SL. To prevent the bending pressure, the signal wiring SL passing through the bending area BD may be formed of a more flexible material.

[0070] The bending region BD may include a first structure CP. The first structure CP may prevent the crack from spreading toward the signal wiring SL when a crack occurs. The first structure CP may be disposed adjacent to a curved portion of the panel bending region.

[0071] Figure 4 FIG. 1 is a diagram showing the arrangement of signal wirings in the entire display panel according to an embodiment of the present invention.

[0072] Reference Figure 4 , the display panel DM may include a main region MR, a bending region BD and a sub-region SR. The main region MR includes a display area DA and a non-display area NDA on a plane. The main region MR includes a plurality of pixels PX. An area configured with a plurality of pixels PX is defined as a display area DA. In the present embodiment, the non-display area NDA may be defined along an edge of the display area DA.

[0073] The main region MR includes a plurality of gate lines GL, data lines DL, light lines EL, control signal lines SL-D, initialization voltage lines SL-Vint, and voltage lines SL-VDD. Each gate line GL is connected to a corresponding pixel PX in a plurality of pixels PX, and each data line DL is connected to a corresponding pixel PX in a plurality of pixels PX. Each light line EL can be arranged side by side with a corresponding gate line in each gate line GL. The control signal line SL-D can provide a control signal to the gate drive circuit GD. The initialization voltage line SL-Vint can provide an initialization voltage to a plurality of pixels PX. The voltage line SL-VDD is connected to a plurality of pixels PX and can provide a first voltage to the plurality of pixels PX. The voltage line SL-VDD can include a plurality of lines extending in a first direction DR1 and a plurality of lines extending in a second direction DR2.

[0074] A gate driving circuit GD connected to the gate line GL and the light emitting line EL may be disposed on one side of the non-display area NDA. Some of the gate lines GL, data lines DL, light emitting lines EL, control signal lines SL-D, initialization voltage lines SL-Vint, and voltage lines SL-VDD are disposed on the same layer, and some are disposed on different layers.

[0075] The bending area BD may include two outer contour lines OT-L, a plurality of signal wirings SL, and a first structure CP. The two outer contour lines OT-L are contour lines extending along the first direction DR1, and may be contour lines connecting the main area MR and the sub-area SR. The signal wiring SL may connect the wiring of the main area MR and the wiring of the sub-area SR. The first structure CP may be configured between each of the two outer contour lines OT-L and the plurality of signal wirings SL.

[0076] exist Figure 4 2 shows the state before both ends of the bending region BD and the main region MR are bent. In this case, the main region MR, the bending region BD, and the sub-region SR may be arranged in sequence along the first direction DR1. The first width WT1 of the main region MR parallel to the second direction DR2 may be greater than the second width WT2 of the bending region BD parallel to the second direction DR2.

[0077] On the other hand, Figure 4 The shape of the original substrate SUB_pre before cutting shown by the dotted line in FIG. 1 may be a rectangular shape. In order to form a display device DD in which the four corners are chamfered and the connection between the main region MR and the curved region BD of the panel has an L-shaped cut shape, a laser LS (see FIG. 1 ) may be used to cut the display device DD along the cutting line CL. Fig.15 ) to cut. The cut line CL can be cut by a laser cutting method or the like. The first structure CP can prevent the signal wiring SL from being damaged by cracks generated when the cut line CL is cut by laser cutting or the like.

[0078] Figure 5 2 is an equivalent circuit diagram of a pixel PX according to an embodiment of the present invention.

[0079] exist Figure 5 FIG. 2 illustrates a pixel PX connected to a certain gate line GL, a certain data line DL, and a voltage line SL-VDD. The structure of the pixel PX is not limited to this, and the structure can be changed to implement.

[0080] The pixel PX includes an organic light emitting diode OLED as a display element. The organic light emitting diode OLED may be a front light emitting diode or a back light emitting diode. The pixel PX may include a first transistor TFT1 (or a switching transistor), a second transistor TFT2 (or a driving transistor), and a capacitor CAP as a circuit portion for driving the organic light emitting diode OLED.

[0081] The first transistor TFT1 outputs a data signal to be applied to the data line DL in response to a scan signal applied to the gate line GL. The capacitor CAP charges a voltage corresponding to the data signal received from the first transistor TFT1.

[0082] The second transistor TFT2 is connected to the organic light emitting diode OLED. The second transistor TFT2 controls the driving current flowing through the organic light emitting diode OLED in accordance with the amount of charge stored in the capacitor CAP. The organic light emitting diode OLED emits light during the on period of the second transistor TFT2.

[0083] Figure 6 as well as Figure 7 FIG. 1 is a partial cross-sectional view of a display panel DM according to an embodiment of the present invention.

[0084] Figure 6 Shown with Figure 5 FIG. 4 is a cross-section of a portion corresponding to the first transistor TFT1 and the capacitor CAP of the equivalent circuit shown. Figure 7 Shown with Figure 5 The cross section of the second transistor TFT2 and the corresponding part of the organic light emitting diode OLED of the equivalent circuit shown.

[0085] like Figure 6 as well as Figure 7As shown, a barrier layer 10 is arranged on the substrate SUB. The barrier layer 10 may include a first layer 11 to a third layer 13. The first layer 11 to the third layer 13 may be an inorganic layer. The inorganic layer may include at least any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and aluminum oxide. However, this is only an example, and the barrier layer 10 may be omitted, and may include an organic layer, or may have more than two layers. The organic layer may include a polymer, for example, may include an acrylic organic layer. However, this is only an example, and the present invention is not limited to this.

[0086] The circuit layer DP-CL is disposed on the barrier layer 10. The semiconductor pattern AL1 of the first transistor TFT1 (hereinafter referred to as the first semiconductor pattern) and the semiconductor pattern AL2 of the second transistor TFT2 (hereinafter referred to as the second semiconductor pattern, see Fig.15 The first semiconductor pattern AL1 and the second semiconductor pattern AL2 may be selected from amorphous silicon, polysilicon, and metal oxide semiconductors to be the same as or different from each other.

[0087] A first insulating layer 20 covering the first semiconductor pattern AL1 and the second semiconductor pattern AL2 is disposed on the substrate SUB. The first insulating layer 20 includes an organic layer and / or an inorganic layer. In particular, the first insulating layer 20 may include an inorganic thin film. The inorganic thin film may include at least any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. However, this is only an example, and the present invention is not limited thereto.

[0088] A control electrode GE1 (hereinafter referred to as the first control electrode) of the first transistor TFT1 and a control electrode GE2 (hereinafter referred to as the second control electrode, see also FIG. 2 ) of the second transistor TFT2 may be disposed on the first insulating layer 20. Fig.15 The first control electrode GE1, the second control electrode GE2 and the first electrode E1 can be connected to each gate line GL (refer to Figure 4 In other words, the first electrode E1 is made of the same material as the gate lines GL, may have the same stacked structure, and may be arranged on the same layer.

[0089] A second insulating layer 30 covering the first control electrode GE1, the second control electrode GE2 and the first electrode E1 is arranged on the first insulating layer 20. The second insulating layer 30 includes an organic layer and / or an inorganic layer. In particular, the second insulating layer 30 may include an inorganic film. The inorganic film may include at least any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and aluminum oxide. However, this is only an example, and the present invention is not limited thereto. The second electrode E2 may be arranged on the second insulating layer 30. A third insulating layer 40 covering the second electrode E2 is arranged on the second insulating layer 30. The third insulating layer 40 includes an organic layer and / or an inorganic layer. In particular, the third insulating layer 40 may include an inorganic film. The inorganic film may include at least any one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide and aluminum oxide. However, this is only an example, and the present invention is not limited thereto.

[0090] Each data line DL may be disposed on the third insulating layer 40 (see Figure 4 An input electrode SE1 (hereinafter referred to as a first input electrode) and an output electrode DE1 (hereinafter referred to as a first output electrode) of the first transistor TFT1 are arranged on the third insulating layer 40. An input electrode SE2 (hereinafter referred to as a second input electrode, see Fig.15 The symbol SE2 in FIG. 1 ) and the output electrode DE2 (hereinafter referred to as the second output electrode, refer to FIG. Fig.15 The first input electrode SE1 is branched from the corresponding data line among the data lines DL. Figure 6 2 illustrates a case where the second electrode E2 is disposed between the second insulating layer 30 and the third insulating layer 40, but the present invention is not limited thereto, and the second electrode E2 of the capacitor CAP may be disposed on the third insulating layer 40. In this case, the second electrode E2 may be manufactured by the same photolithography process as the data lines DL and the power lines, may be composed of the same material, may have the same stacked structure, and may be disposed on the same layer.

[0091] The first input electrode SE1 and the first output electrode DE1 are connected to the first semiconductor pattern AL1 through the first through hole CH1 and the second through hole CH2 penetrating the first insulating layer 20 to the third insulating layer 40, respectively. The first output electrode DE1 can be electrically connected to the first electrode E1. For example, the first output electrode DE1 can be connected to the first electrode E1 through a through hole (not shown) penetrating the second insulating layer 30 and the third insulating layer 40. The second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern AL2 through the third through hole CH3 and the fourth through hole CH4 penetrating the first insulating layer 20 to the third insulating layer 40, respectively. On the other hand, in other embodiments of the present invention, the first transistor TFT1 and the second transistor TFT2 can be changed to a bottom gate structure for implementation.

[0092] A fourth insulating layer 50 covering the first input electrode SE1, the first output electrode DE1, the second input electrode SE2, and the second output electrode DE2 is disposed on the third insulating layer 40. The fourth insulating layer 50 includes an organic layer and / or an inorganic layer. In particular, the fourth insulating layer 50 may include an organic substance in order to provide a flat surface. The organic substance may include a polymer, for example, an acrylic organic layer. However, this is only an example, and the present invention is not limited thereto.

[0093] Any one of the first insulating layer 20 to the fourth insulating layer 50 may be omitted according to the circuit structure of the pixel. The first insulating layer 20 to the third insulating layer 40 may be defined by an interlayer insulating layer. The interlayer insulating layer is disposed between a conductive pattern disposed at a lower portion and a conductive pattern disposed at an upper portion with reference to the interlayer insulating layer, thereby insulating the conductive pattern.

[0094] The light emitting element layer DP-OLED is disposed on the fourth insulating layer 50. The pixel definition layer PDL, the spacer SPC and the organic light emitting diode OLED are disposed on the fourth insulating layer 50.

[0095] The anode AE ​​is disposed on the fourth insulating layer 50. The anode AE ​​is connected to the second output electrode DE2 via a fifth through hole CH5 penetrating the fourth insulating layer 50 (see Fig.15 ). An opening OP is defined in the pixel definition film PDL and the spacer SPC. The opening OP exposes at least a portion of the anode AE. The pixel definition film PDL and the spacer SPC include an organic layer and / or an inorganic layer. In particular, the pixel definition film PDL and the spacer SPC may include an organic substance in order to provide a flat surface. The organic substance may include a polymer, for example, an acrylic organic layer. However, this is only an example, and the present invention is not limited to this.

[0096] The spacer SPC is disposed on the pixel definition film PDL and can play a role in supporting a mask used when forming an organic light emitting diode OLED, etc. The spacer SPC is formed in the same manner as the pixel definition film PDL, but the present invention is not limited thereto. The spacer SPC can be formed only on a partial area of ​​the pixel definition film PDL, or the spacer SPC can be omitted.

[0097] The light emitting element layer DP-OLED includes a light emitting region PXA and a non-light emitting region NPXA adjacent to the light emitting region PXA. The non-light emitting region NPXA may surround the light emitting region PXA. The light emitting region PXA may be defined corresponding to a partial region of the anode AE ​​exposed through the opening OP.

[0098] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. Although not shown separately, a common layer such as the hole control layer HCL may be commonly formed in a plurality of pixels PX (see Figure 4 )middle.

[0099] The organic light emitting layer EML is disposed on the hole control layer HCL. The organic light emitting layer EML may be disposed only in a region corresponding to the opening OP. That is, the organic light emitting layer EML may be separately formed in each of the plurality of pixels PX.

[0100] An electron control layer ECL is disposed on the organic light emitting layer EML. A cathode CE is disposed on the electron control layer ECL. The cathode CE is commonly disposed in a plurality of pixels PX.

[0101] In the present embodiment, a patterned organic light emitting layer EML is exemplified, but the organic light emitting layer EML may be commonly configured in a plurality of pixels PX. In this case, the organic light emitting layer EML may generate white light. In addition, the organic light emitting layer EML may have a multi-layer structure.

[0102] In this embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In one embodiment of the present invention, a cover layer covering the cathode CE may also be configured. In this case, the thin film encapsulation layer TFE directly covers the cover layer. The thin film encapsulation layer TFE may include a plurality of inorganic thin films IOL1, IOL2 and an organic thin film OL.

[0103] Figure 8 It is along Figure 3 The cross-sectional view taken in the II' region is shown. Figure 6 , Figure 7 as well as Figure 8 The bending region BD may include a first structure CP and a signal wiring region SLR. The first structure CP may include a plurality of crack prevention stages CD, at least one crack prevention groove CG disposed between the plurality of crack prevention stages CD, and a crack prevention region CR.

[0104] The first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 including inorganic materials may not be disposed in the crack prevention region CR and the signal wiring region SLR. Therefore, the pressure applied to the bending region BD bent toward the back side of the display unit can be reduced.

[0105] A plurality of crack prevention stages CD including at least one of the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 may be configured in a partial area of ​​the first structure CP. The first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 may be inorganic layers. However, the constituent materials of the plurality of crack prevention stages CD are not limited thereto. For example, at least one of the fourth insulating layer 50 and the pixel definition film PDL may be further included on at least one of the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40. The fourth insulating layer 50 and the pixel definition film PDL may be organic layers. At least one crack prevention groove CG configured between the plurality of crack prevention stages CD may be included. The area where the crack prevention groove CG is configured may expose the substrate SUB.

[0106] A plurality of crack prevention stages CD may be disposed between the outer contour line OT-L and the signal wiring SL. The plurality of crack prevention stages CD may be manufactured by the same photolithography process as the barrier layer 10 and the circuit layer DP-CL. In other words, the plurality of crack prevention stages CD are composed of the same material as the barrier layer 10 and the circuit layer DP-CL and may have the same stacked structure. According to one embodiment, a plurality of crack prevention stages CD including an inorganic layer may be formed simultaneously in the process of forming the third through hole CH3 and the fourth through hole CH4 penetrating the first insulating layer 20 to the third insulating layer 40 so that the second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern AL2.

[0107] Next, the fourth insulating layer 50 may be applied as a planarization film on the plurality of crack prevention stages CD formed of an inorganic layer. At this time, the upper surfaces of the plurality of crack prevention stages CD formed of an inorganic layer may be completely submerged in the fourth insulating layer 50. In the process of forming the fifth through hole CH5 penetrating the fourth insulating layer 50 so that the anode AE ​​and the second output electrode DE2 are connected, the plurality of crack prevention stages CD including an organic layer may be formed simultaneously. At this time, the fourth insulating layer 50 may be arranged on the signal wiring region SLR of the bending region BD, and the signal wiring SL may be arranged on the fourth insulating layer 50. Thus, the signal wiring SL arranged on the main region MR and the sub-region SR having a height difference due to the removal of the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40 may be arranged on the same plane.

[0108] Next, an organic layer forming a pixel definition film PDL may be coated on the plurality of crack prevention stages CD including the fourth insulating layer 50. At this time, the upper surfaces of the plurality of crack prevention stages CD including the fourth insulating layer 50 may be completely submerged in the organic layer forming the pixel definition film PDL. The plurality of crack prevention stages CD including an organic layer for forming a pixel definition film PDL may be formed simultaneously in the process of forming the opening OP of the light emitting area PXA. At this time, the organic layer forming the pixel definition film PDL may be arranged on the signal wiring SL arranged on the fourth insulating layer 50. Thus, the signal wiring SL may be prevented from being exposed to the outside.

[0109] When the outer contour line OT-L is formed by the laser cutting process, cracks may occur in the main region MR, the bending region BD, and the sub-region SR. In addition, the bending region BD is a bent region different from the main region MR and the sub-region SR, and the cracks that occur may continue to grow and spread. When a plurality of crack prevention stages CD and at least one crack prevention groove CG arranged between the plurality of crack prevention stages are arranged side by side with the outer contour line OT-L, the cracks that occur can be prevented from spreading toward the signal wiring SL. That is, the defects caused by the pressure applied to the bending region BD can be reduced, and the reliability and manufacturing yield of the product can be improved.

[0110] Fig. 9 It is magnified Figure 4 A floor plan of area A is shown.

[0111] Reference Fig. 9 , on a plane, the first structure CP may be arranged between the signal wiring SL and the outer contour line OT-L. On a plane, the first structure CP may be arranged separately from the outer contour line OT-L. In this case, it is possible to prevent cracks that may occur in the process of forming the outer contour line OT-L from spreading toward the signal wiring SL. Among the two outer contour lines OT-L, at least one may include a curved portion. For example, the distance between the two outer contour lines OT-L of the curved area BD may gradually decrease from the main area MR toward the sub-area SR. The first structure CP may include a crack prevention stage CD and a crack prevention groove CG extending along the outer contour line OT-L having a curved portion. The crack prevention stage CD and the crack prevention groove CG may be arranged along a second direction DR2 intersecting the first direction DR1. Since the first structure CP includes a crack prevention stage CD and a crack prevention groove CG in a slit shape, even if a part of the pattern in the first structure CP is cracked, the crack can be prevented from being propagated.

[0112] exist Fig. 9, the first structure CP includes three crack prevention stages CD and two crack prevention grooves CG, but the present invention is not limited thereto. The first structure CP may further include a crack prevention region CR between the crack prevention stages CD and the signal wiring SL. The crack prevention region CR may be a region where inorganic layers such as the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40 are removed to expose the substrate SUB.

[0113] Fig.10 Another embodiment involves an enlarged Figure 4 A floor plan of area A is shown.

[0114] Reference Fig.10 In the plane, the first structure CP_1 can be arranged between the signal wiring SL and the outer contour line OT-L.

[0115] The first structure CP_1 includes a plurality of crack prevention stages CD_1, and the plurality of crack prevention stages CD_1 may be arranged side by side along the outer contour line OT-L including the curved portion. Thus, the plurality of crack prevention stages CD_1 may be arranged in an island shape. The plurality of crack prevention grooves CG_1 may be arranged along the first direction DR1 and the second direction DR2, in which case the plurality of crack prevention stages CD_1 may have a dotted line shape adjacent to the outer contour line OT-L.

[0116] and Fig. 9 compared to, Fig.10 The crack prevention stage CD_1 is island-shaped and has a shape arranged along the first direction DR1. Fig.10 Such an island-shaped crack prevention platform CD_1 can further reduce the stress generated when the bending area BD is bent.

[0117] Fig.11 Yet another embodiment involves an enlarged Figure 4 A floor plan of area A is shown.

[0118] Reference Fig.11 , on a plane, the first structure CP_2 may be arranged between the signal wiring SL and the outer contour line OT-L. The first structure CP_2 may be arranged side by side along the outer contour line OT-L including the curved portion. The first structure CP_2 may include: a first crack prevention stage CD_21 extending along the first direction DR1; and a second crack prevention stage CD_22 separated from the first crack prevention stage CD_21 in the second direction DR2 and extending along the first direction DR1.

[0119] The first crack preventing stage CD_21 and the second crack preventing stage CD_22 may be in a trapezoidal shape in a plane.

[0120] The first crack prevention stage CD_21 and the second crack prevention stage CD_22 may be arranged alternately along the second direction DR2. One end of the first crack prevention stage CD_21 and the other end of another first crack prevention stage CD_21 adjacent to the first crack prevention stage CD_21 in one direction may overlap the adjacent second crack prevention stage CD_22. That is, the first crack prevention stage CD_21 and the second crack prevention stage CD_22 may be arranged to be staggered with each other in the first direction DR1. Thus, when the bending area BD is bent, the pressure generated can be further reduced, and the crack passing between two first crack prevention stages CD_21 adjacent to each other in the first direction DR1 can be prevented from spreading toward the signal wiring SL due to the second crack prevention stage CD_22 adjacent to each other in the second direction DR2.

[0121] Fig.12 Another embodiment involves the following Figure 3 The cross-sectional view taken in the II' region is shown. Figure 6 , Figure 7 as well as Fig.12 , and a plurality of anti-crack CDs including inorganic and / or organic materials are shown Figure 8 The difference is that the plurality of crack prevention stages CD_3 include a first layer 11 containing inorganic matter, a second layer 12, a third layer 13, a first insulating layer 20, a second insulating layer 30 and a third insulating layer 40.

[0122] Specifically, the bending region BD may include a first structure CP_3 and a signal wiring region SLR. The first structure CP_3 may include a plurality of crack prevention stages CD_3, at least one crack prevention groove CG_3 disposed between the plurality of crack prevention stages CD_3, and a crack prevention region CR_3.

[0123] The first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 including inorganic materials may not be arranged in the crack prevention region CR_3 and the signal wiring region SLR. Thus, the pressure applied to the bending region BD bent toward the back side of the main region MR can be reduced.

[0124] A plurality of crack prevention stations CD_3 including at least one of the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 may be configured in a partial area of ​​the first structure CP_3. The first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30 and the third insulating layer 40 may be inorganic layers. At least one crack prevention groove CG_3 configured between the plurality of crack prevention stations CD_3 may be included. The area where the crack prevention groove CG_3 is configured may expose the substrate SUB. The plurality of crack prevention stations CD_3 may be configured between the outer contour line OT-L and the signal wiring SL. The plurality of crack prevention stations CD_3 may be manufactured by the same photolithography process as the barrier layer 10 and the circuit layer DP-CL. In other words, the plurality of crack prevention stations CD_3 are composed of the same material as the barrier layer 10 and the circuit layer DP-CL and may have the same stacked structure. According to an embodiment, a plurality of crack preventing mesas CD_3 may be simultaneously formed during the process of forming the third through hole CH3 and the fourth through hole CH4 penetrating the first insulating layer 20 to the third insulating layer 40 so that the second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern AL2 .

[0125] Fig.13 Another embodiment involves Figure 3 A cross-sectional view taken along region II' is shown.

[0126] Reference Figure 6 , Figure 7 as well as Fig.13 , and a plurality of anti-crack CDs including inorganic and / or organic materials are shown Figure 8 The difference is that the plurality of crack preventing stages CD_4 only include a fourth insulating layer 50 containing organic matter and one layer of the pixel definition layer PDL.

[0127] Specifically, the bending region BD may include a first structure CP_4 and a signal wiring region SLR. The first structure CP_4 may include a plurality of crack prevention stages CD_4, at least one crack prevention groove CG_4 disposed between the plurality of crack prevention stages CD_4, and a crack prevention region CR_4.

[0128] The first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40 including inorganic materials may not be disposed in the first structure CP_4 and the signal wiring region SLR. That is, the entire region of the bending region BD may not include an inorganic layer. Thus, the pressure applied to the bending region BD that is bent toward the back side of the display unit can be reduced.

[0129] A plurality of crack prevention stages CD_4 including at least one of the fourth insulating layer 50 and the pixel definition film PDL may be disposed in a partial region of the first structure CP_4. The fourth insulating layer 50 and the pixel definition film PDL may be organic layers. At least one crack prevention groove CG_4 disposed between the plurality of crack prevention stages CD_4 may be included. The region where the crack prevention groove CG_4 is disposed may expose the substrate SUB.

[0130] A plurality of crack prevention stages CD_4 may be disposed between the outer contour line OT-L and the signal wiring SL. According to one embodiment, the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40 as the inorganic layers on the bending area BD may be completely removed during the process of forming the third through hole CH3 and the fourth through hole CH4 penetrating the first insulating layer 20 to the third insulating layer 40 so that the second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern AL2.

[0131] Next, a fourth insulating layer 50 may be applied as a planarization film on the substrate SUB. A plurality of crack prevention stages CD_4 including an organic layer may be simultaneously formed in the process of forming a fifth through hole CH5 penetrating the fourth insulating layer 50 so that the anode AE ​​and the second output electrode DE2 are connected. At this time, the fourth insulating layer 50 may be arranged on the signal wiring region SLR of the bending region BD, and the signal wiring SL may be arranged on the fourth insulating layer 50. Thus, the signal wiring SL arranged on the main region MR and the sub-region SR, which have height differences due to the removal of the first layer 11, the second layer 12, the third layer 13, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40, etc., may be arranged on the same plane.

[0132] Next, an organic layer forming a pixel definition film PDL may be coated on the plurality of crack prevention stages CD_4 including the fourth insulating layer 50. At this time, the upper surfaces of the plurality of crack prevention stages CD_4 including the fourth insulating layer 50 may be completely submerged in the organic layer forming the pixel definition film PDL. The plurality of crack prevention stages CD_4 including an organic layer for forming a pixel definition film PDL may be formed simultaneously in the process of forming the opening OP of the light emitting area PXA. On the other hand, the organic layer forming the pixel definition film PDL may be arranged on the signal wiring SL arranged on the fourth insulating layer 50. Thus, it is possible to prevent the signal wiring SL from being exposed to the outside.

[0133] Fig.14 is a flowchart showing a method for manufacturing a display device according to an embodiment. Fig.15 It is a cross-sectional view showing the stacking order of the main region and the bending region according to one embodiment.

[0134] Reference Figure 4 , Fig.14 as well as Fig.15 , may include a step (S100) of forming at least one barrier layer 10 on a substrate SUB, defining on the substrate SUB: a main region MR having a display area DA; and a curved region BD extending from one side of the main region MR and having at least one outer contour line of two outer contour lines OT-L including a curved portion.

[0135] exist Figure 4 The shape of the original substrate SUB_pre before cutting shown by the dotted line in FIG. 1 may be a rectangular shape. The barrier layer 10 may be coated integrally on the original substrate SUB_pre. The barrier layer 10 may include a first layer 11 to a third layer 13. The first layer 11 to the third layer 13 may be an inorganic layer. The inorganic layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0136] A step of forming at least one inorganic layer on the barrier layer 10 may be included ( S110 ).

[0137] A semiconductor pattern AL2 is configured on the barrier layer 10 of the display area DA. The semiconductor pattern AL2 can be selected from amorphous silicon, polycrystalline silicon, and metal oxide semiconductors, which are the same as or different from each other. A first insulating layer 20 can be configured on the semiconductor pattern AL2. A control electrode GE2 of the second transistor TFT2 can be configured on the first insulating layer 20. The control electrode GE2 can be made of the same material as the gate line GL. A second insulating layer 30 and a third insulating layer 40 can be sequentially configured on the control electrode GE2. The first insulating layer 20 to the third insulating layer 40 may include an inorganic layer. The inorganic layer may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. On the other hand, the first insulating layer 20, the second insulating layer 30, and the third insulating layer 40 can be stacked sequentially on the bending area BD.

[0138] A step of etching at least one barrier layer 10 and at least one inorganic layer in the bending region BD to form a crack preventing mesa CD including at least one barrier layer 10 and at least one inorganic layer may be included ( S120 ).

[0139] According to one embodiment, in the process of forming a third through hole CH3 and a fourth through hole CH4 that penetrate the first insulating layer 20 to the third insulating layer 40 in the display area DA so that the second input electrode SE2 and the second output electrode DE2 are connected to the second semiconductor pattern AL2, a plurality of anti-crack stages CD and an anti-crack groove CG including the first insulating layer 20 to the third insulating layer 40 of the inorganic layer serving as the bending area BD can be simultaneously formed.

[0140] The step S120 of forming the crack preventing stage may further include the steps of coating a planarization film (eg, the fourth insulating layer 50 ) on the etched at least one inorganic layer and etching the planarization film in the bending region BD to form the crack preventing stage.

[0141] The fourth insulating layer 50 may be coated as a planarization film on the plurality of crack preventing mesas CD formed of the inorganic layer. At this time, the upper surfaces of the plurality of crack preventing mesas CD formed of the inorganic layer may be completely submerged by the fourth insulating layer 50 .

[0142] In the process of forming the fifth through hole CH5 penetrating the fourth insulating layer 50 in the display area DA so as to connect the anode AE ​​and the second output electrode DE2, a plurality of crack prevention stages CD and crack prevention grooves CG including the fourth insulating layer 50 as an organic layer are simultaneously formed in the bending area BD. At this time, the fourth insulating layer 50 may also be disposed on the signal wiring area SLR of the bending area BD, and the signal wiring SL may be disposed on the fourth insulating layer 50.

[0143] The step S120 of forming the crack preventing stage may further include the steps of coating a pixel definition film PDL on the etched at least one planarization film and etching the pixel definition film PDL in the bending region BD to form the crack preventing stage CD.

[0144] An organic layer forming the pixel definition film PDL may be coated on the plurality of crack preventing stages CD including the fourth insulating layer 50. At this time, upper surfaces of the plurality of crack preventing stages CD including the fourth insulating layer 50 may be completely submerged by the organic layer forming the pixel definition film PDL.

[0145] In the process of forming the opening OP of the light emitting area PXA in the display area DA, a plurality of crack prevention stages CD and crack prevention grooves CG including an organic layer for forming a pixel definition film PDL may be simultaneously formed in the bending area BD. On the other hand, an organic layer for forming a pixel definition film PDL may be disposed on the signal wiring SL disposed on the fourth insulating layer 50.

[0146] A step ( S130 ) may be included before the substrate SUB is cut the crack prevention stage CD using the laser LS.

[0147] In order to form a display device DD having four chamfered corners and an L-shaped cut shape at the connection between the main region MR and the curved region BD of the panel from the original substrate SUB_pre, cutting can be performed along the cutting line CL using a laser LS. The cutting line CL can be cut by a laser cutting method or the like. The laser can be used with Green / CO 2 .

[0148] The plurality of crack prevention stages CD and the crack prevention grooves CG formed between the plurality of crack prevention stages CD can be formed symmetrically with respect to the cutting line CL. Thus, the crack can be prevented from spreading toward the original substrate SUB_pre that is removed without forming the display device DD. That is, the first structure CP can prevent the signal wiring SL from being damaged by the crack that occurs when the cutting line CL is cut by laser cutting or the like.

[0149] The embodiments of the present invention are described above with reference to the accompanying drawings, but those skilled in the art should be able to understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above are illustrative in all aspects and should not be understood as restrictive.

Claims

1. A display device, comprising: The main area includes the display area; sub-regions, including pads; and The substrate comprises a curved region disposed between the main region and the sub-region, wherein at least one of two outer contours of the curved region includes a curved portion, The distance between the two outer contour lines of the curved region measured along a direction intersecting the direction from the main region toward the sub-region gradually decreases from the main region toward the sub-region, The curved region includes a structure arranged side by side with the curved portion, A width of the main region measured along a direction perpendicular to a direction from the main region toward the sub-region is greater than a width of the sub-region.

2. The display device according to claim 1, wherein: The structure includes a plurality of crack preventing stages arranged in parallel with the curved portion of the bending region, and the substrate is exposed between the plurality of crack preventing stages.

3. The display device according to claim 2, wherein: The crack preventing stage is composed of at least one inorganic layer.

4. The display device according to claim 3, wherein: The inorganic layer includes any one of a first insulating layer, a second insulating layer, and a third insulating layer disposed on the substrate.

5. The display device according to claim 2, wherein: The bending region includes a signal wiring region, and a first organic layer is included on the signal wiring region.

6. The display device according to claim 5, wherein: A plurality of wirings electrically connecting the main region and the sub-region are included on the first organic layer.

7. The display device according to claim 6, wherein: The display device further includes a second organic layer disposed on the first organic layer.

8. The display device according to claim 7, wherein: The crack preventing stage includes at least one of the first organic layer and the second organic layer.

9. The display device according to claim 7, wherein: The crack preventing stage includes at least one inorganic layer, and further includes at least one of the first organic layer and the second organic layer on the at least one inorganic layer.

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