Display devices

Abstract

A display device is provided, comprising a substrate including a display area having a plurality of pixel circuits spaced apart from one another. An inorganic material layer is disposed in the display area and includes grooves between adjacent pixel circuits. An organic filler is disposed in the grooves. The inorganic material layer includes an etch stop layer and at least one insulating material layer. The etch stop layer includes a semiconductor material or a conductive material. The etch stop layer is disposed on a portion of a sidewall or a bottom surface of the groove.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2019-0031775 filed on March 20, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to a display apparatus. Background Art

[0003] A display device generally includes a display device and a plurality of electronic devices for controlling electrical signals applied to the display device. The electronic devices may include thin film transistors (TFTs), storage capacitors, and a plurality of wirings.

[0004] The number of thin-film transistors electrically connected to a display device and the number of wirings that transmit electrical signals to the thin-film transistors can be increased to precisely control whether the display device emits or not, as well as the degree of emission of the display device. Therefore, a great deal of research has been conducted on achieving high integration of display devices and thereby reducing errors. Summary of the Invention

[0005] One or more exemplary embodiments provide a display apparatus that is robust against external shock and is flexible.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0007] According to one or more exemplary embodiments, a display device includes a substrate having a display area with a plurality of pixel circuits spaced apart from each other. An inorganic material layer is disposed in the display area and includes grooves between adjacent ones of the plurality of pixel circuits. An organic filler is disposed in the grooves. The inorganic material layer includes an etch stop layer and at least one insulating material layer. The etch stop layer includes a semiconductor material or a conductive material. The etch stop layer is disposed on a portion of a sidewall or a bottom surface of the groove.

[0008] In an exemplary embodiment, the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode, and the etch stop layer may be provided on the same layer as the semiconductor layer and include the same material as that of the semiconductor layer.

[0009] In an exemplary embodiment, the plurality of pixel circuits each include a thin film transistor including a semiconductor layer and a gate electrode, and the etch stop layer may be provided on the same layer as the gate electrode and include the same material as that of the gate electrode.

[0010] In an exemplary embodiment, each of the plurality of pixel circuits may include a driving thin film transistor and a storage capacitor. The driving thin film transistor and the storage capacitor may be arranged to overlap each other, and the etch stop layer may be provided on the same layer as the electrode of the storage capacitor and include the same material as the electrode of the storage capacitor.

[0011] In exemplary embodiments, the inorganic material layer may include a barrier layer disposed on the substrate, and the barrier layer may be continuously disposed throughout the plurality of pixel circuits.

[0012] In exemplary embodiments, an organic filler may be arranged to surround at least a portion of the plurality of pixel circuits.

[0013] In exemplary embodiments, the organic filler may extend to an upper surface of the inorganic material layer.

[0014] In an exemplary embodiment, the display device may further include a first connection wiring overlapped with the plurality of pixel circuits and arranged on the organic filler.

[0015] In an exemplary embodiment, adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction. A first scan line of the first pixel circuit and a second scan line of the second pixel circuit are separated by an organic filler. The first scan line and the second scan line are connected to each other via a first connection wiring.

[0016] In an exemplary embodiment, an elongation rate of the first connection wiring may be greater than an elongation rate of the scan line.

[0017] In an exemplary embodiment, the display device may further include: an interlayer insulating layer covering the first connection wiring; and a second connection wiring arranged on the interlayer insulating layer and connecting the plurality of pixel circuits to each other.

[0018] In exemplary embodiments, the first connection wiring and the second connection wiring may extend in different directions, respectively.

[0019] In exemplary embodiments, the insulating material layer may be etched by a fluoride-based gas, and the etch stop layer may be etched by a chloride-based gas.

[0020] In an exemplary embodiment, the display device may further include an encapsulation layer that seals the display area and includes at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0021] According to an exemplary embodiment of the present inventive concept, a display device includes a substrate having a display area with a plurality of pixel circuits spaced apart from each other. An inorganic material layer is disposed in the display area and includes a groove in a region between adjacent pixel circuits. An organic filler is disposed in the groove. A recess is positioned on a sidewall of the groove.

[0022] In exemplary embodiments, the inorganic material layer may include a barrier layer disposed on the substrate, and the barrier layer may be disposed under the groove and continuously disposed throughout the plurality of pixel circuits.

[0023] In exemplary embodiments, an organic filler may be arranged to surround at least a portion of the plurality of pixel circuits.

[0024] In an exemplary embodiment, the display device may further include a first connection wiring overlapped with the plurality of pixel circuits and arranged on the organic filler.

[0025] In an exemplary embodiment, adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction. A first scan line of the first pixel circuit and a second scan line of the second pixel circuit are separated by an organic filler. The first scan line and the second scan line are connected to each other via a first connection wiring.

[0026] In an exemplary embodiment, an elongation rate of the first connection wiring may be greater than an elongation rate of the scan line.

[0027] In another exemplary embodiment of the present invention, a method for manufacturing a display device having a plurality of pixel circuits includes forming a lower inorganic material layer on a substrate, the lower inorganic material layer including a barrier layer. Forming an etch stop layer on the lower inorganic material layer. The etch stop layer has a first etching condition. Forming an upper inorganic material layer on the etch stop layer. The upper inorganic material layer has an etching condition different from that of the etch stop layer. Performing a first etching process on an area of ​​the upper inorganic material layer located between adjacent pixel circuits among the plurality of pixel circuits to form a first opening in the upper inorganic material layer. Performing a second etching process on an area of ​​the etch stop layer located between adjacent pixel circuits to form a second opening in the etch stop layer. Performing a third etching process on an area of ​​the lower inorganic material layer located between adjacent pixel circuits to form a third opening in the lower inorganic material layer, the third opening exposing the barrier layer. The first opening, the second opening, and the third opening form a groove. An organic filler is formed in the groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] These and / or other aspects will become apparent and more readily understood from the following description of exemplary embodiments taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1is a top plan view illustrating a display device according to an exemplary embodiment of the present inventive concept;

[0030] Figure 2 is a block diagram illustrating a display device according to an exemplary embodiment of the present inventive concept;

[0031] Figure 3 is an equivalent circuit diagram of a pixel provided in a display device according to an exemplary embodiment of the inventive concept;

[0032] Figure 4 is a plan view illustrating positions of a plurality of thin film transistors and storage capacitors in adjacent pixel circuits according to an exemplary embodiment of the inventive concept;

[0033] Figure 5A is along the exemplary embodiment according to the present inventive concept Figure 4 A sectional view taken along line II' and line II-II';

[0034] Figure 5B is along the exemplary embodiment according to the present inventive concept Figure 4 A sectional view taken along line III-III';

[0035] Figure 5C According to another exemplary embodiment of the present invention Figure 4 A sectional view taken along line III-III';

[0036] Figures 6A to 6F are cross-sectional views sequentially illustrating processes of forming a display device according to an exemplary embodiment of the present inventive concept;

[0037] Figure 7 is along the exemplary embodiment according to the present inventive concept Figure 4 A sectional view taken along line II' and line II-II';

[0038] Figure 8 is along the exemplary embodiment according to the present inventive concept Figure 4 A sectional view taken along line II' and line II-II';

[0039] Figure 9 is along the exemplary embodiment according to the present inventive concept Figure 4 sectional views taken along lines II' and II-II'; and

[0040] Figure 10 is along the exemplary embodiment according to the inventive concept Figure 4 Cross-sectional views taken along line II' and line II-II'. DETAILED DESCRIPTION

[0041] Reference will now be made in detail to the exemplary embodiments shown in the accompanying drawings, wherein like reference numerals always represent like elements. In this regard, the present exemplary embodiments may have different forms and should not be construed as being limited to the description set forth herein. Therefore, exemplary embodiments are described below solely with reference to the drawings to explain various aspects of this specification. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. When a statement such as "at least one of..." is placed after a column of elements, the entire column of elements is modified without modifying the individual elements in the column.

[0042] Hereinafter, exemplary embodiments of the present inventive concept will be described more fully with reference to the accompanying drawings. Like reference numerals designate like or corresponding elements, and thus their description will be omitted.

[0043] In the exemplary embodiments set forth herein, terms such as “first,” “second,” etc. are used to distinguish one component from another component and are not intended to limit the components.

[0044] In exemplary embodiments, an expression used in the singular includes the expression in the plural unless it has a clearly different meaning in the context.

[0045] In exemplary embodiments, terms such as “including” and “having” are intended to indicate the presence of the features or components disclosed in the specification, but are not intended to exclude the possibility that one or more other features or components may exist or be added.

[0046] In exemplary embodiments, when a layer, region, or component is referred to as being "on" another layer, region, or component (for example, disposed on, arranged on, positioned on, etc.), the layer, region, or component can be directly on the other layer, region, or component, or intermediate layers, regions, or components may be present therebetween.

[0047] For the convenience of explanation, the sizes of the components in the drawings may be exaggerated. In other words, since the sizes and thicknesses of the components in the drawings may be arbitrarily shown for the convenience of explanation, the following exemplary embodiments are not limited thereto.

[0048] When a certain exemplary embodiment can be implemented differently, the specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in a reverse order from the described order.

[0049] In the following exemplary embodiments, when a layer, region, or component is connected to another layer, region, or component, the layer, region, or component may be directly connected to the another layer, region, or component, or may be indirectly connected to the another layer, region, or component with another layer, region, or component disposed therebetween. For example, in the specification, when a layer, region, or component is electrically connected to another layer, region, or component, the layer, region, or component may be directly electrically connected to the another layer, region, or component, or may be indirectly electrically connected to the another layer, region, or component with another layer, region, or component disposed therebetween.

[0050] Figure 1 is a top plan view illustrating a display device according to an exemplary embodiment of the inventive concept.

[0051] Reference Figure 1 , pixels PX included in various types of display devices such as organic light-emitting devices (OLEDs, hereinafter also referred to as organic light-emitting diodes) can be arranged in the display area DA of the substrate 110. Various types of wiring for providing electrical signals to the display area DA can be positioned in the peripheral area PA of the substrate 110. Hereinafter, for convenience of explanation, a display device including an OLED as a display device is described. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, the present inventive concept can be applied to various types of display devices such as liquid crystal display devices, electrophoretic display devices, inorganic EL display devices, etc.

[0052] Figure 2 is a block diagram illustrating a display device according to an exemplary embodiment of the inventive concept.

[0053] Reference Figure 2 , a display device according to an exemplary embodiment includes a display unit 10 including a plurality of pixels PX, a scan driver 20 , a data driver 30 , an emission control driver 40 , and a controller 50 .

[0054] The display unit 10 is arranged in the display area DA and includes a plurality of pixels PX positioned at the intersection of a plurality of scan lines SL1 to SLn+1, a plurality of data lines DL1 to DLm, and a plurality of emission control lines EL1 to ELn, which are arranged approximately in a matrix. The plurality of scan lines SL1 to SLn+1 and the plurality of emission control lines EL1 to ELn extend in a second direction, which is the row direction, and are arranged in a first direction, which is the column direction. The plurality of data lines DL1 to DLm and the drive voltage line ELVDDL extend in a first direction and are arranged in a second direction. "n" and "m" are natural numbers. However, in a pixel line, the n value of the plurality of scan lines SL1 to SLn+1 may be different from the n value of the plurality of emission control lines EL1 to ELn. In addition, in other exemplary embodiments, the scan lines, data lines, and emission control lines may have various different arrangements.

[0055] exist Figure 2 In the exemplary embodiment shown in FIG, each pixel PX is connected to three scan lines among a plurality of scan lines SL1 to SLn+1. The scan driver 20 generates three scan signals and supplies the three scan signals to each pixel PX through the plurality of scan lines SL1 to SLn+1. The scan driver 20 may sequentially supply the scan signals to the scan lines SL2 to SLn, the previous scan lines SL1 to SLn-1, or the next scan lines SL3 to SLn+1.

[0056] The initialization voltage line IL can receive an initialization voltage applied from an external power source VINT and provide the initialization voltage to each pixel PX. Hereinafter, reference numerals "121," "122," "123," "151," "131," and "152" are used to represent a scan line, a previous scan line, an emission control line, a data line, an initialization voltage line, and a drive voltage line, respectively. "Drive voltage" may also be referred to as "drive power voltage."

[0057] In addition, each pixel PX is connected to a data line among a plurality of data lines DL1 to DLm. Each pixel PX is also connected to an emission control line among a plurality of emission control lines EL1 to ELn.

[0058] The data driver 30 supplies a data signal to each pixel PX through a plurality of data lines DL1 to DLm. Each time a scan signal is supplied to the scan lines SL2 to SLn, the data signal is supplied to the pixel PX selected by the scan signal.

[0059] The emission control driver 40 generates an emission control signal and provides the emission control signal to each pixel PX through a plurality of emission control lines EL1 to ELn. The emission control signal controls the emission period of the pixel PX. However, in some exemplary embodiments, the emission control driver 40 may be omitted depending on the internal structure of the pixel PX.

[0060] The controller 50 converts the plurality of image signals IR, IG, and IB into a plurality of image data signals DR, DG, and DB, and provides the image data signals DR, DG, and DB to the data driver 30. Furthermore, the controller 50 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a clock signal MCLK and generates control signals to control the operations of the scan driver 20, the data driver 30, and the emission control driver 40. The controller 50 provides the control signals to the scan driver 20, the data driver 30, and the emission control driver 40, respectively. For example, the controller 50 generates and provides a scan drive control signal SCS to control the scan driver 20, generates and provides a data drive control signal DCS to control the data driver 30, and generates and provides an emission drive control signal ECS to control the emission control driver 40.

[0061] Each of the plurality of pixels PX receives a driving power voltage ELVDD and a common power voltage ELVSS from an external source (e.g., an external device). The driving power voltage ELVDD may be a high-level voltage, and the common power voltage ELVSS may be a voltage lower than the driving power voltage ELVDD or a ground voltage. The driving power voltage ELVDD is supplied to each pixel PX via a driving voltage line ELVDDL.

[0062] Each of the plurality of pixels PX emits light having a certain brightness by a driving current supplied to the display device in response to a data signal provided through the plurality of data lines DL1 to DLm.

[0063] Figure 3 is an equivalent circuit diagram of a pixel provided in a display device according to an exemplary embodiment of the inventive concept.

[0064] Reference Figure 3 Each pixel PX includes signal lines including a scan line 121, a previous scan line 122, an emission control line 123, and a data line 151. Each pixel PX also includes an initialization voltage line 131, a pixel circuit PC connected to a drive voltage line 152, and a display device, such as an organic light emitting diode (OLED), connected to the pixel circuit PC.

[0065] The pixel circuit PC includes a plurality of thin film transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 and a storage capacitor Cst.

[0066] Figure 3An exemplary embodiment in which a signal line, an initialization voltage line 131, and a driving voltage line 152 are provided in each pixel PX is shown. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, in another exemplary embodiment, at least one of the signal lines and / or the initialization voltage line 131 may be shared by adjacent pixels.

[0067] The plurality of thin film transistors may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0068] The signal lines include: a scan line 121, which provides a scan signal Sn; a previous scan line 122, which provides a previous scan signal Sn-1 to the first initialization thin-film transistor T4 and the second initialization thin-film transistor T7; an emission control line 123, which provides an emission control signal En to the operation control thin-film transistor T5 and the emission control thin-film transistor T6; and a data line 151, which intersects the scan line 121 and provides a data signal Dm. A driving voltage line 152 provides a driving power voltage ELVDD to the driving thin-film transistor T1, and an initialization voltage line 131 supplies an initialization voltage Vint for initializing the driving thin-film transistor T1 and the pixel electrode.

[0069] The driving gate electrode G1 of the driving thin film transistor T1 is connected to the first electrode Cst1 of the storage capacitor Cst. The driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line 152 via the operation control thin film transistor T5. The driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting device OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and converts the driving current I OLED Supplied to the organic light emitting device OLED.

[0070] A switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line 121. A switching source electrode S2 of the switching thin film transistor T2 is connected to the data line 151. A switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is also connected to the driving voltage line 152 via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to the scan signal Sn provided through the scan line 121, and performs a switching operation to provide the data signal Dm provided through the data line 151 to the driving source electrode S1 of the driving thin film transistor T1.

[0071] The compensation gate electrode G3 of the compensation thin-film transistor T3 is connected to the scan line 121. The compensation source electrode S3 of the compensation thin-film transistor T3 is connected to the drive drain electrode D1 of the drive thin-film transistor T1 and is also connected to the pixel electrode of the organic light-emitting diode OLED via the emission control thin-film transistor T6. The compensation drain electrode D3 of the compensation thin-film transistor T3 is connected to the first electrode Cst1 of the storage capacitor Cst, the first initialization source electrode S4 of the first initialization thin-film transistor T4, and the drive gate electrode G1 of the drive thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn provided via the scan line 121 and electrically connects the drive gate electrode G1 and the drive drain electrode D1 of the drive thin-film transistor T1 to each other, thereby diode-connecting the drive thin-film transistor T1.

[0072] A first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to the previous scan line 122. A first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and to the initialization voltage line 131. A first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to the compensation drain electrode D3 of the compensation thin film transistor T3 and the drive gate electrode G1 of the drive thin film transistor T1. The first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 provided via the previous scan line 122, and supplies the initialization voltage Vint to the drive gate electrode G1 of the drive thin film transistor T1, thereby performing an initialization operation to initialize the voltage of the drive gate electrode G1 of the drive thin film transistor T1.

[0073] An operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line 123. An operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line 152. An operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0074] The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line 123. The emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3. The emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0075] The operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En provided through the emission control line 123, so that the driving power voltage ELVDD is provided to the organic light emitting diode OLED and the driving current I OLED Flows through the organic light-emitting diode OLED.

[0076] A second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line 122. A second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the pixel electrode of the organic light emitting diode OLED. A second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization drain electrode D4 of the first initialization thin film transistor T4 and the initialization voltage line 131. The second initialization thin film transistor T7 is turned on in response to the previous scan signal Sn-1 provided through the previous scan line 122, and initializes the pixel electrode of the organic light emitting diode OLED.

[0077] exist Figure 3 , the first initialization thin film transistor T4 and the second initialization thin film transistor T7 are connected to the previous scan line 122. However, the exemplary embodiment is not limited thereto. In another exemplary embodiment, the first initialization thin film transistor T4 may be connected to the previous scan line 122 and driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be connected to another signal line (for example, the next scan line) and driven in response to the signal provided to the signal line. However, the positions of the source electrodes S1 to S7 and the drain electrodes D1 to D7 may be interchanged with each other depending on the type of transistor (p-type or n-type). In addition, in other exemplary embodiments, Figure 3 The exemplary embodiment shown in modifies the number of transistors, their function and arrangement.

[0078] Specific operations of the corresponding pixel PX according to an exemplary embodiment are as follows:

[0079] In the initialization period, when the previous scan signal Sn- 1 is supplied through the previous scan line 122 , the first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn- 1 , and the driving thin film transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line 131 .

[0080] In the data programming period, when the scan signal Sn is supplied through the scan line 121, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the scan signal Sn. At this time, the driving thin film transistor T1 is diode-connected through the turned-on compensation thin film transistor T3 and biased in the forward direction.

[0081] A compensation voltage Dm+Vth (Vth is a negative value) which is a value obtained by subtracting a threshold voltage Vth of the driving thin film transistor T1 from a data signal Dm supplied from the data line 151 is applied to the driving gate electrode G1 of the driving thin film transistor T1 .

[0082] The driving power voltage ELVDD and the compensation voltage Dm+Vth are respectively applied to both ends of the storage capacitor Cst, and charges corresponding to the difference between the driving power voltage ELVDD and the compensation voltage Dm+Vth are stored in the storage capacitor Cst.

[0083] In the emission period, the operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on in response to the emission control signal En supplied from the emission control line 123. A driving current I depending on the voltage difference between the gate electrode G1 of the driving thin film transistor T1 and the driving power voltage ELVDD is generated. OLED . Drive current I OLED The light is supplied to the organic light emitting diode OLED through the emission control thin film transistor T6.

[0084] Figure 4 is a plan view illustrating the positions of a plurality of thin film transistors and storage capacitors in adjacent pixel circuits. Figure 5A It is along Figure 4 Cross-sectional views taken along line II' and line II-II'.

[0085] Reference Figure 4 and Figure 5A , a display device according to an exemplary embodiment of the inventive concept includes an inorganic material layer having a groove GR in an area between a plurality of pixel circuits (e.g., a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3), and an organic filler 161 disposed in the groove GR and filling the groove GR. An etch stop layer ES is disposed on a portion of a sidewall or a bottom surface of the groove GR.

[0086] The display device according to an exemplary embodiment may include a first connection wiring 140 disposed on the organic filler 161 and crossing the organic filler 161 in a first direction and / or a second connection wiring 150 disposed on the organic filler 161 and crossing the organic filler 161 in a second direction.

[0087] In an exemplary embodiment of the present inventive concept, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES are arranged below the first connection wiring 140 and include an inorganic material. The barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, and the etch stop layer ES may be collectively referred to as an inorganic material layer. The inorganic material layer includes a groove GR in a region between adjacent pixels. For example, as Figure 4 and Figure 5A As shown in FIG, the groove GR may be located in a region between the first pixel circuit PX1 and the second pixel circuit PX2 in the first direction. The groove GR may also be located in a region between the first pixel circuit PX1 and the third pixel circuit PX3 in the second direction.

[0088] In an exemplary embodiment of the present inventive concept, the etch stop layer ES may refer to a layer having an etching rate different from that of other layers included in the inorganic material layer (e.g., the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114). The etch stop layer ES may also refer to a layer etched by etching conditions different from those of the above-mentioned layers.

[0089] In some exemplary embodiments, the etch stop layer ES may include a semiconductor material or a metal. In these embodiments, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include a material such as silicon oxide (SiO x ), silicon nitride (SiN x ) or silicon oxynitride (SiON) insulating material.

[0090] Figure 5A An exemplary embodiment in which the inorganic material layer includes a groove GR is shown. For example, the barrier layer 101 may be continuously formed over the first and second pixel circuits PC1 and PC2 adjacent to each other. The buffer layer 111, the etch stop layer ES, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may have openings 111a, ESa, 112a, 113a, and 114a, respectively, in the region between adjacent pixels to form a portion of the groove GR in this region.

[0091] Therefore, the inorganic material layer including the barrier layer 101, the buffer layer 111, the etch stop layer ES, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include a groove GR in a region between adjacent pixels. The groove GR may refer to a trench formed in the inorganic material layer.

[0092] In other exemplary embodiments of the present inventive concept, the inorganic material layer may include Figure 5A The shape of the groove GR shown in FIG. 1 is different from the shape of the groove GR, and the groove GR may be modified variously. For example, in one embodiment, the bottom of the buffer layer 111 may remain, and the opening 111 a may be formed in a region above the bottom of the buffer layer 111 .

[0093] In an exemplary embodiment, the width GRW of the groove GR in the inorganic material layer may be several μm. For example, the width GRW of the groove GR in the inorganic material layer may be about 5 μm to about 10 μm.

[0094] The groove GR may be formed by using an additional mask process and an etching process after forming the third gate insulating layer 114. In this exemplary embodiment, an etching stop layer ES may be provided for accuracy of the etching process. The etching stop layer ES and the steps of forming the groove GR by the etching process will be described later.

[0095] The groove GR in the inorganic material layer may be filled with the organic filler 161. The first and second connection wirings 140 and 150 may be arranged on (eg, directly on or directly over) the organic filler 161 in the region where the organic filler 161 is located.

[0096] The groove GR of the inorganic material layer and the organic filler 161 may be at least partially located between the plurality of pixel circuits. Figure 4 , the groove GR of the inorganic material layer and the organic filler 161 are positioned to surround each of the first pixel circuit PC1 and the second pixel circuit PC2 (for example, in a plane formed by the first direction and the second direction). For example, the organic filler 161 is arranged to surround the outer periphery of the first pixel circuit PC1 and the outer periphery of the second pixel circuit PC2 to form a series of connected rectangular shapes surrounding the pixel. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0097] For example, the groove GR of the inorganic material layer and the organic filler 161 therein may be formed to extend from the area between the first pixel circuit PC1 and the second pixel circuit PC2 along the second direction without surrounding each of the first pixel circuit PC1 and the second pixel circuit PC2. In addition, the groove GR of the inorganic material layer and the organic filler 161 may be modified differently. For example, the groove GR of the inorganic material layer and the organic filler 161 may be formed to extend from the area between the plurality of pixel circuits along the first direction.

[0098] The groove GR of the inorganic material layer and the organic filler 161 can minimize the impact on the display device caused by external vibration. Since the inorganic material layer has a higher durability than the organic filler 161, there is a high possibility that cracks will be generated due to external vibration. When cracks are generated in the inorganic material layer, cracks may also be generated in various signal lines arranged in the middle or top portion of the inorganic material layer. Therefore, there is a high possibility that defects such as disconnection will be generated due to cracks in the inorganic material layer.

[0099] However, in the display device according to the exemplary embodiment of the present inventive concept, since the inorganic material layer has the groove GR including the organic filler 161 in the region between the plurality of pixels, there is a low possibility of crack propagation when there is external vibration. In addition, since the organic filler 161 is less durable than the inorganic material layer, the organic filler 161 can absorb stress caused by external vibration and effectively minimize any stress directed to the first connection wiring 140 and the second connection wiring 150 located on the organic filler 161.

[0100] The first connection wiring 140 and the second connection wiring 150 disposed on the organic filler 161 may connect a plurality of pixel circuits to each other. Figure 5A As shown in FIG, the first connection wiring 140 can connect the first pixel PX1 to the adjacent second pixel PX2. The first connection wiring 140 and the second connection wiring 150 can be arranged on the inorganic material layer in an area where the organic filler 161 is not located. The first connection wiring 140 and the second connection wiring 150 can serve as lines for providing electrical signals to a plurality of pixel circuits.

[0101] The first connection wiring 140 and the second connection wiring 150 may extend longer than other lines (e.g., the first connection wiring 140 in a first direction and the second connection wiring 150 in a second direction). Therefore, stress on the display device due to vibration is more likely to be applied to the first connection wiring 140 and the second connection wiring 150 than to other components of the display device.

[0102] In an exemplary embodiment, the first connection wiring 140 and the second connection wiring 150 include a material having a high elongation. For example, the first connection wiring 140 and the second connection wiring 150 may include aluminum. However, exemplary embodiments of the present invention are not limited thereto. Therefore, the first connection wiring 140 and the second connection wiring 150 including a material having a high elongation can absorb shock while preventing errors such as cracks or disconnections from occurring. The first connection wiring 140 and the second connection wiring 150 may have a multilayer structure as needed. In some exemplary embodiments, a stacked structure including Ti / Al / Ti may be applied to the first connection wiring 140 and the second connection wiring 150. In some exemplary embodiments, the elongation of the first connection wiring 140 and the second connection wiring 150 may be higher than the elongation of the material of the layer arranged below them.

[0103] In the following, reference is made to Figure 4 and Figure 5A , a display device according to an exemplary embodiment will be described in detail.

[0104] The substrate 110 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. For example, in an embodiment in which the substrate 110 is flexible or bendable, the substrate 110 may include a high molecular weight resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose acetate propionate, or a combination thereof. However, exemplary embodiments of the present invention are not limited thereto. The substrate 110 may have a single layer or multilayer structure including the materials mentioned above. In an embodiment having a multilayer structure, the substrate 110 may further include an inorganic layer. In some exemplary embodiments, the substrate 110 may have a structure including a combination of an organic material and an inorganic material.

[0105] The display device may further include a barrier layer 101 located between the substrate 110 and the buffer layer 111. For example, Figure 5A As shown in the exemplary embodiment of FIG, the barrier layer 101 can be directly provided on the substrate 110. The barrier layer 101 can prevent impurities (such as impurities from the substrate 110) from penetrating into the semiconductor layer, or minimize impurities (such as impurities from the substrate 110) penetrating into the semiconductor layer. In exemplary embodiments, the barrier layer 101 can include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material. The barrier layer 101 can include a single-layer structure or a multi-layer structure including an inorganic material and an organic material.

[0106] The buffer layer 111 may be provided on the barrier layer 101. For example, Figure 5AAs shown in the exemplary embodiment of FIG, the buffer layer 111 may be directly disposed on the barrier layer 101. The buffer layer 111 may improve the smoothness of the upper surface of the substrate 110. In the exemplary embodiment, the buffer layer 111 may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon oxynitride. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0107] The semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6 and the second initialization thin film transistor T7 are arranged on the buffer layer 111. For example, Figure 5A As shown in the exemplary embodiment of FIG, the semiconductor layer can be directly arranged on the buffer layer 111. In the exemplary embodiment, the semiconductor layers can include the same material. For example, the semiconductor layers can include polycrystalline silicon, amorphous silicon, or an oxide semiconductor. However, the exemplary embodiments of the present inventive concept are not limited thereto. The semiconductor layers can be connected to each other and can be bent in various shapes.

[0108] The semiconductor layer may include a channel region, a source region, and a drain region. Figure 5A As shown in , the semiconductor layers of the driving thin film transistor T1 and the emission control thin film transistor T6 may include respective channel regions A1 and A6, respective source regions S1 and S6, and respective drain regions D1 and D6. The source regions S1 and S6 and the drain regions D1 and D6 are arranged on the sides adjacent to the channel regions A1 and A6, respectively. The source region and the drain region may be doped with impurities, which may include n-type impurities or p-type impurities. The source region and the drain region correspond to the source electrode and the drain electrode, respectively. Hereinafter, the terms "source region" and "drain region" will be used instead of the source electrode and the drain electrode.

[0109] The first gate insulating layer 112 is positioned on the semiconductor layer. Figure 5A As shown in the exemplary embodiment of FIG, the first gate insulating layer 112 may be directly disposed on the semiconductor layer. The first gate insulating layer 112 may include an inorganic material including an oxide material or a nitride material. For example, the first gate insulating layer 112 may include silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zinc oxide (ZnO), etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0110] In this embodiment, the semiconductor layers of the plurality of pixel circuits are formed separately from each other. For example, the semiconductor layer of the first pixel circuit PC1 is spaced apart from the semiconductor layer of the second pixel circuit PC2 (e.g., spaced apart in the first direction). However, in other exemplary embodiments of the present inventive concept, at least one semiconductor layer may be integrally formed between the plurality of pixel circuits.

[0111] The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are arranged on the first gate insulating layer 112. The scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 are arranged on the same layer and include the same material. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 may include molybdenum (Mo), copper (Cu), titanium (Ti), etc., and may each include a single layer or multiple layers. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0112] The driving gate electrode G1 is an island-shaped electrode and is arranged to cover the driving channel region A1 in the driving semiconductor layer (e.g., in the thickness direction of the substrate 110). The driving gate electrode G1 can serve not only as a gate electrode of the driving thin film transistor T1 but also as a first electrode Cst1 of the storage capacitor Cst. For example, the driving gate electrode G1 and the first electrode Cst1 can be formed integrally.

[0113] Portions or protrusions of the scan line 121 , the previous scan line 122 , and the emission control line 123 correspond to gate electrodes of the thin film transistors T2 to T7 .

[0114] For example, the portions of scan line 121 that overlap with the switching channel region and the compensation channel region correspond to the switching gate electrode G2 and the compensation gate electrode G3, respectively. In the preceding scan line 122, the regions that overlap with the first initialization channel region and the second initialization channel region correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. In the emission control line 123, the regions that overlap with the operation control channel region and the emission control channel region correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0115] In the present exemplary embodiment, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of each of the plurality of pixel circuits are formed separately from one another. For example, the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of the first pixel circuit PC1 may be formed to be discontinuous or spaced apart (e.g., discontinuous or spaced apart in the first direction) from the scan line 121, the previous scan line 122, the emission control line 123, and the driving gate electrode G1 of the second pixel circuit PC2.

[0116] In this embodiment, the scan line 121, the previous scan line 122 and the emission control line 123 of the first pixel circuit PC1 can be respectively connected to the scan line 121, the previous scan line 122 and the emission control line 123 of the second pixel circuit PC2 through the first connection wiring 140 arranged on another layer.

[0117] The second gate insulating layer 113 is arranged on the scan line 121, the previous scan line 122, the emission control line 123 and the driving gate electrode G1. For example, the second gate insulating layer 113 can be directly arranged on the scan line 121, the previous scan line 122, the emission control line 123 and the driving gate electrode G1. The second gate insulating layer 113 may include an inorganic material including an oxide material or a nitride material. For example, the second gate insulating layer 113 may include SiO2, SiN x , SiON, Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 , ZnO, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0118] The second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 are positioned on the second gate insulating layer 113. The second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 are arranged on the same layer and include the same material. For example, the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131 may include a material including Mo, Cu, Ti, etc., and may be formed as a multilayer or single layer including the above-mentioned materials. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0119] In the present exemplary embodiment, the second electrode Cst2 of the storage capacitor Cst of each of the plurality of pixel circuits and the initialization voltage line 131 are discontinuous and spaced apart from each other. For example, the second electrode Cst2 of the storage capacitor Cst of the first pixel circuit PC1 and the second electrode Cst2 of the storage capacitor Cst of the second pixel circuit PC2 are spaced apart from each other (e.g., spaced apart from each other in the first direction) and separated from each other. The initialization voltage line 131 of the first pixel circuit PC1 and the initialization voltage line 131 of the second pixel circuit PC2 are spaced apart from each other (e.g., spaced apart from each other in the first direction) and separated from each other.

[0120] The third gate insulating layer 114 is disposed on the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131. For example, the third gate insulating layer 114 may be directly disposed on the second electrode Cst2 of the storage capacitor Cst and the initialization voltage line 131. The third gate insulating layer 114 may include an inorganic material including an oxide material or a nitride material. For example, the third gate insulating layer 114 may include SiO2, SiN x, SiON, Al 2 O 3 , TiO 2 , Ta 2 O 5 , HfO 2 , ZnO, etc. However, exemplary embodiments of the inventive concept are not limited thereto.

[0121] The first connection wiring 140 extending in the first direction is arranged on the third gate insulating layer 114. Figure 5A As shown in FIG, the first connection wiring 140 may be directly disposed on the third gate insulating layer 114. The first connection wiring 140 extends from the first pixel circuit PC1 to the second pixel circuit PC2 and connects these pixel circuits to each other. The first connection wiring 140 may connect a plurality of pixel circuits arranged in the first direction.

[0122] In this exemplary embodiment, the conductive layers of the semiconductor layer, scan line 121, previous scan line 122, emission control line 123, initialization voltage line 131, first electrode Cst1 and second electrode Cst2 of storage capacitor Cst, etc. are formed discontinuously and separately in each pixel circuit. Therefore, it is possible to prevent stress that may be generated in one pixel circuit from propagating to another pixel circuit. In addition, since the first connection wiring 140 may be made of a material with high elongation, it is possible to minimize errors caused by stress.

[0123] The first connection wiring 140 may include an emission control connection line 141, a mesh connection line 142, a scan connection line 143, a previous scan connection line 144, and an initialization voltage connection line 145. Figure 5A Line II′ shows the mesh connection line 142 with respect to the first connection wiring 140 , but a similar structure may be used for the emission control connection line 141 , the scan connection line 143 , the previous scan connection line 144 , and the initialization voltage connection line 145 .

[0124] The emission control connection line 141 connects the emission control line 123 of the first pixel circuit PC1 with the emission control line 123 of the second pixel circuit PC2 through contact holes CNT1a and CNT2a formed to penetrate the third gate insulating layer 114 and the second gate insulating layer 113. The emission control connection line 141 may overlap the emission control line 123 of the first pixel circuit PC1 and the emission control line 123 of the second pixel circuit PC2 (e.g., overlap in a direction of the thickness of the substrate 110) and extend in the first direction.

[0125] The grid connection line 142 connects the second electrode Cst2 of the first pixel circuit PC1 to the second electrode Cst2 of the second pixel circuit PC2 via contact holes CNT3a and CNT2b formed through the third gate insulating layer 114. Since the second electrode Cst2 of the storage capacitor Cst is connected to the driving voltage line 152 and receives the driving voltage, the grid connection line 142 can transmit the driving voltage to a plurality of pixels arranged in the first direction. Therefore, the grid connection line 142 can form a grid structure of driving voltage lines without requiring additional area to accommodate separate driving voltage lines extending in the first direction. This configuration thus provides additional area for the storage capacitor Cst, thereby providing a high-definition display device.

[0126] The scan connection line 143 connects the scan line 121 of the first pixel circuit PC1 to the scan line 121 of the second pixel circuit PC2 through contact holes CNT4a and CNT4b formed through the third gate insulating layer 114 and the second gate insulating layer 113. The scan connection line 143 may overlap the scan line 121 of the first pixel circuit PC1 and the scan line 121 of the second pixel circuit PC2 (e.g., overlap in the direction of the thickness of the substrate 110) and extend in the first direction.

[0127] The previous scan connection line 144 connects the previous scan line 122 of the first pixel circuit PC1 to the previous scan line 122 of the second pixel circuit PC2 via contact holes CNT5a and CNT5b formed through the third gate insulating layer 114 and the second gate insulating layer 113. The previous scan connection line 144 may overlap with the previous scan line 122 of the first pixel circuit PC1 and the previous scan line 122 of the second pixel circuit PC2 (e.g., in a thickness direction of the substrate 110).

[0128] The initialization voltage connection line 145 connects the initialization voltage line 131 of the first pixel circuit PC1 and the initialization voltage line 131 of the second pixel circuit PC2 through contact holes CNT6a and CNT6b formed through the third gate insulating layer 114. The initialization voltage connection line 145 may overlap the initialization voltage line 131 of the first pixel circuit PC1 and the initialization voltage line 131 of the second pixel circuit PC2 (e.g., in a thickness direction of the substrate 110) and extend in the first direction.

[0129] As described above, in a region on or above the organic filler 161 arranged between adjacent pixel circuits, the first connection wiring 140 can supply electrical signals to a plurality of pixel circuits by connecting adjacent pixel circuits (eg, the first pixel circuit PC1 and the second pixel circuit PC2 ).

[0130] The interlayer insulating layer 115 is disposed on the first connection wiring 140. For example, the interlayer insulating layer 115 may be directly disposed on the first connection wiring 140. The interlayer insulating layer 115 may include an inorganic material including an oxide material or a nitride material. For example, the interlayer insulating layer 115 may include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, ZnO, etc. However, exemplary embodiments of the present inventive concept are not limited thereto. In some exemplary embodiments, the interlayer insulating layer 115 may include an organic material such as benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane. In exemplary embodiments in which the interlayer insulating layer 115 includes an organic material, stress applied to wiring arranged above and below the interlayer insulating layer 115 may be reduced.

[0131] The second connection wiring 150 extending in the second direction is positioned on the interlayer insulating layer 115. The second connection wiring 150 is insulated from the first connection wiring 140 by the interlayer insulating layer 115. For example, Figure 5A As shown in FIG, the second connection wiring 150 may be directly disposed on the interlayer insulating layer 115. The second connection wiring 150 may include a data line 151, a driving voltage line 152, a first node connection line 153, a second node connection line 154, and an intermediate connection line 155.

[0132] The data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the intermediate connection line 155 are arranged on the same layer and include the same material. For example, the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154, and the intermediate connection line 155 may include a conductive material with high elongation.

[0133] although Figure 5A Line II-II′ shows the intermediate connection line 155 with respect to the second connection wiring 150 , but a similar structure may be used for the data line 151 , the driving voltage line 152 , the first node connection line 153 , and the second node connection line 154 .

[0134] The data line 151 is connected to the switching thin film transistor T2 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The data line 151 can connect a plurality of pixel circuits arranged in the second direction.

[0135] The driving voltage line 152 is connected to the operation control thin film transistor T5 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. In addition, the driving voltage line 152 is connected to the second electrode Cst2 of the storage capacitor Cst via a contact hole penetrating the interlayer insulating layer 115 and the third gate insulating layer 114. The driving voltage line 152 can connect a plurality of pixel circuits arranged in the second direction.

[0136] The first node connection line 153 is connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The first node connection line 153 is also connected to the initialization voltage line 131 via a contact hole penetrating the interlayer insulating layer 115 and the third gate insulating layer 114.

[0137] The second node connection line 154 connects the driving gate electrode G1 to the compensation drain region of the compensation thin film transistor T3 via the contact hole. The driving gate electrode G1 is an island-shaped electrode that can be electrically connected to the compensation thin film transistor T3.

[0138] The intermediate connection line 155 may be connected to the second initialization thin film transistor T7 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. Figure 5A As shown in FIG, the intermediate connection line 155 may be connected to the emission control thin film transistor T6 via a contact hole penetrating the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112.

[0139] The data line 151 , the driving voltage line 152 , and the intermediate connection line 155 may connect pixel circuits (eg, the first pixel circuit PC1 and the third pixel circuit PC3 ) adjacent to each other in the second direction and cross the groove GR and the organic filler 161 therebetween.

[0140] The planarization layer 116 is arranged on the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154 and the intermediate connection line 155. For example, the planarization layer 116 can be directly set on the data line 151, the driving voltage line 152, the first node connection line 153, the second node connection line 154 and the intermediate connection line 155. The planarization layer 116 may include an organic material such as acryl, BCB, PI or HMDSO. However, exemplary embodiments of the present inventive concept are not limited thereto. Alternatively, the planarization layer 116 may include an inorganic material. The planarization layer 116 may have the function of roughly planarizing the upper portion of the protective film covering the thin film transistors T1 to T7. The planarization layer 116 may be provided as a single layer or multiple layers.

[0141] Reference Figure 5A The organic filler 161 is arranged to at least partially fill the groove GR of the inorganic material layer between the first pixel circuit PC1 and the second pixel circuit PC2. The organic filler 161 may not completely fill the groove GR. In addition, the organic filler 161 may not be included in some grooves GR.

[0142] However, in an exemplary embodiment, the organic filler 161 completely fills the groove GR to increase absorption of external impact. In some exemplary embodiments, the organic filler 161 may be formed to extend to the upper surface of the inorganic material layer. In this embodiment, considering the properties of the organic filler 161, the upper surface of the organic filler 161 may be configured to have a convex shape. For example, the maximum height h of the organic filler 161 may extend from the upper surface of the barrier layer 101 to above the third gate insulating layer 114. The maximum height h of the organic filler 161 may be formed to be greater than the depth d of the groove GR extending from the upper surface of the barrier layer 101 to the upper surface of the third gate insulating layer 114.

[0143] The angle of the line extending from the upper surface of the organic filler 161 to the upper surface of the inorganic material layer can be within 45 degrees. For example, the angle of the line extending from the upper surface of the organic filler 161 to the upper surface of the inorganic material layer can be in the range of 10° to 45°. When the slope of the boundary area between the inorganic material layer and the upper surface of the organic filler 161 is not gentle, the conductive material of the first connection wiring 140 may remain in the boundary area without being removed when performing the process of forming the first connection wiring 140 by patterning the conductive layer. Therefore, the conductive material retained due to the uneven slope of the boundary area between the inorganic material layer and the upper surface of the organic filler 161 may cause a short circuit between other conductive layers. Therefore, preferably, the upper surface of the organic filler 161 is formed to have a gentle slope relative to the upper surface of the inorganic material layer.

[0144] In an exemplary embodiment, the organic filler 161 may include one or more materials selected from the group consisting of acrylic resin, metacrylic resin, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0145] The organic filler 161 may be arranged in the groove GR of the inorganic material layer in the region between the first pixel circuit PC1 and the second pixel circuit PC2, and may separate the first pixel circuit PC1 and the second pixel circuit PC2 from each other in a portion below the first connection wiring 140. The groove GR and the organic filler 161 therein prevent stress from propagating from the first pixel circuit PC1 to the second pixel circuit PC2 and / or prevent cracks from forming from the first pixel circuit PC1 to the second pixel circuit PC2.

[0146] The organic light emitting diode OLED includes a pixel electrode 310, an opposite electrode 330, and an intermediate layer 320 positioned between the pixel electrode 310 and the opposite electrode 330. The intermediate layer 320 includes an emission layer (EML). The organic light emitting diode OLED may be disposed on the planarization layer 116.

[0147] The pixel electrode 310 is connected to the intermediate connection line 155 via a contact hole CNT1 b defined in the planarization layer 116 , and is connected to the emission control drain region D6 of the emission control thin film transistor T6 through the intermediate connection line 155 .

[0148] A pixel-defining layer 117 may be disposed on the planarization layer 116. The pixel-defining layer 117 defines pixels by having openings corresponding to each sub-pixel. For example, the openings expose at least the central region of the pixel electrode 310. The pixel-defining layer 117 also prevents arcing, etc., at the edge of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. The pixel-defining layer 117 may include an organic material, such as PI, HMDSO, etc. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0149] The intermediate layer 320 of the organic light emitting diode OLED may include a low molecular weight material or a high molecular weight material. When the intermediate layer 320 includes a low molecular weight material, the hole injection layer (HIL), the emission layer (EML), the electron transport layer (ETL), the electron injection layer (EIL), etc. may all have a single layer structure or a multilayer stacked structure, and the low molecular weight material may include various organic materials such as copper phthalocyanine (CuPc), N, N'-di(naphthalene-1-yl)-N, N'-diphenyl-benzidine (NPB), and tris(8-hydroxyquinoline) aluminum (Alq3). Such a layer may be formed by a vacuum deposition method. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0150] In an exemplary embodiment in which the intermediate layer 320 includes a high molecular weight material, the intermediate layer 320 may generally have a structure including a hole transport layer (HTL) and an emission layer (EML). In this embodiment, the HTL may include poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a high molecular weight material such as polyphenylene vinylene and polyfluorene. The intermediate layer 320 may be formed using a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, or the like.

[0151] However, the intermediate layer 320 is not limited thereto and may have various structures. In addition, the intermediate layer 320 may include a layer integrally formed over the plurality of pixel electrodes 310 and may further include a layer patterned to correspond to each of the pixel electrodes 310 .

[0152] The opposing electrode 330 is disposed in an upper portion of the display area DA (eg, in an upper portion in a thickness direction of the substrate 110). The opposing electrode 330 may be disposed to cover the display area DA. Figure 5A For example, the counter electrode 330 may be integrally formed with respect to the organic light emitting diodes OLED of a plurality of pixel circuits.

[0153] Since the organic light emitting diode OLED may be easily damaged by moisture or oxygen from the outside, the encapsulation layer 400 may be used to protect and cover the organic light emitting diode OLED. The encapsulation layer 400 may cover the display area DA and extend to the outer area of ​​the display area DA. In an exemplary embodiment, the encapsulation layer 400 may include a first inorganic encapsulation layer 410, an organic encapsulation layer 420, and a second inorganic encapsulation layer 430. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0154] The first inorganic encapsulation layer 410 may cover the counter electrode 330 and include ceramics, metal oxides (e.g., indium oxide (In2O3), tin oxide (SnO2), indium tin oxide (ITO)), metal nitrides, metal carbides, metal oxynitrides, silicon oxide, silicon nitride and / or silicon oxynitride, etc. However, exemplary embodiments of the present invention are not limited thereto. In certain embodiments, an additional layer (e.g., a capping layer, etc.) may be provided between the first inorganic encapsulation layer 410 and the counter electrode 330 as needed. Since the first inorganic encapsulation layer 410 is formed on a structure having an uneven thickness, the upper surface of the first inorganic encapsulation layer 410 is unevenly formed.

[0155] The organic encapsulation layer 420 covers the first inorganic encapsulation layer 410. The upper surface of the organic encapsulation layer 420 may be approximately flat (e.g., approximately smooth). The upper surface of the organic encapsulation layer 420 may be approximately smooth in a portion corresponding to the display area DA. The organic encapsulation layer 420 may include one or more materials selected from acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0156] The second inorganic encapsulating layer 430 may cover the organic encapsulating layer 420. The second inorganic encapsulating layer 430 may include ceramics, metal oxides (e.g., In2O3, SnO2, ITO), metal nitrides, metal carbides, metal oxynitrides, silicon oxide, silicon nitride, and / or silicon oxynitride, etc. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0157] As described above, the encapsulation layer 400 includes the first inorganic encapsulation layer 410, the organic encapsulation layer 420, and the second inorganic encapsulation layer 430. This multi-layer structure can prevent cracks occurring in the encapsulation layer 400 from being connected between the first inorganic encapsulation layer 410 and the organic encapsulation layer 420 or between the organic encapsulation layer 420 and the second inorganic encapsulation layer 430. Therefore, it is possible to prevent or minimize the formation of a path through which external moisture or oxygen may penetrate into the display area DA.

[0158] Spacers for preventing mask cracking may be further provided on the pixel defining layer 117. In addition, various functional layers such as a polarizing layer and a black matrix that reduce reflection of external light, a color filter, and / or a touch screen layer including touch electrodes may be provided on the encapsulation layer 400.

[0159] In this embodiment, the groove GR is provided in the inorganic material layer disposed between the pixel circuits adjacent to each other. In this embodiment, the etch stop layer ES is provided on a portion of the sidewall or the bottom surface of the groove GR.

[0160] The etch stop layer ES may refer to a layer having an etching rate different from that of other layers included in the inorganic material layer (e.g., the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114). The etch stop layer ES may also refer to a layer having an etching condition different from that of other layers included in the inorganic material layer.

[0161] In some exemplary embodiments, the etch stop layer ES may include a semiconductor material or a metal. In this embodiment, the barrier layer 101, the buffer layer 111, the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 may include a material such as SiO x 、SiN x Or SiON insulating material.

[0162] Reference Figure 5A The etch-stop layer ES and the semiconductor layer of the driving thin film transistor T1 can be provided on the same layer and include the same material. For example, the etch-stop layer ES can be provided on the buffer layer 111 to form a portion of the sidewall of the groove GR. Alternatively, the etch-stop layer ES can be provided in another layer to surround the groove GR and / or the organic filler 161. The width ESW of the etch-stop layer ES from a first side edge to an opposite second side edge can be greater than the width GRW of the groove GR.

[0163] The etch stop layer ES may include an opening ESa corresponding to the groove GR. The opening ESa may form a portion of the groove GR.

[0164] In the present exemplary embodiment, the etch stop layer ES may be used to prevent damage to the barrier layer 101 by adjusting the depth of the groove GR. For example, the etch stop layer ES may be provided for accuracy of an etching process performed to form the groove GR.

[0165] Figure 5B According to another exemplary embodiment Figure 4 A cross-sectional view taken along line III-III'.

[0166] Reference Figure 5BA first end of the intermediate connection line 155 can be connected to the first semiconductor layer ACT1 of the first pixel circuit PC1 through a contact hole CNT14 that penetrates the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The region of the first semiconductor layer ACT1 connected to the intermediate connection line 155 can serve as a second initialization source region of the second initialization thin film transistor T7 of the first pixel circuit PC1.

[0167] An opposite second end of the intermediate connection line 155 may be connected to the third semiconductor layer ACT3 of the third pixel circuit PC3 via a contact hole CNT15 that penetrates the interlayer insulating layer 115, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. A region of the third semiconductor layer ACT3 connected to the intermediate connection line 155 may serve as an emission control drain region of the emission control thin film transistor T6 of the third pixel circuit PC3.

[0168] The intermediate connection line 155, which is one of the second connection wirings 150, passes over the organic filler 161 arranged in the groove GR between the first pixel circuit PC1 and the third pixel circuit PC3, and connects the first pixel circuit PC1 and the third pixel circuit PC3, which are spaced apart in the second direction. The organic filler 161 can be arranged in the groove GR in the region of the inorganic material layer between the first pixel PX1 and the third pixel PX3, and can separate the first pixel circuit PC1 from the third pixel circuit PC3 in the region below the intermediate connection line 155, thereby preventing the propagation of stress or cracks.

[0169] The etch stop layer ES is disposed on a portion of the sidewall and / or the bottom surface of the groove GR and may prevent the barrier layer 101 from being damaged.

[0170] Figure 5C According to another exemplary embodiment Figure 4 1 is a cross-sectional view of the display device taken along line III-III'.

[0171] Reference Figure 5C, the display device according to the exemplary embodiment may further include an interlayer insulating layer 115 having an opening 115a in a region between the plurality of pixel circuits. The opening 115a includes an upper organic filler 163 disposed therein to fill the opening 115a. The upper organic filler 163 may overlap with the organic filler 161 in the thickness direction of the substrate 110. The upper organic filler 163 may be disposed directly on the organic filler 161. Therefore, the second connection wiring 150 including the intermediate connection line 155 passes over the organic filler 161 and the upper organic filler 163 disposed between the first pixel circuit PC1 and the third pixel circuit PC3, and may connect the first pixel circuit PC1 and the third pixel circuit PC3, which are spaced apart in the second direction.

[0172] When the interlayer insulating layer 115 includes the openings 115a formed in the region between the plurality of pixels PX, the stress applied to the interlayer insulating layer 115 can be prevented from spreading. In addition, since the upper organic filler 163 is filled in the openings 115a, the upper organic filler 163 can absorb the stress applied to the display device.

[0173] The upper organic filler 163 may include the same material as that of the organic filler 161. The upper organic filler 163 may include one or more materials selected from acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0174] In the following, reference will be made to Figures 6A to 6F The function of the etch stop layer ES is described. Figures 6A to 6F 2 is a cross-sectional view sequentially illustrating processes including forming the groove GR and forming the first connection wiring 140 .

[0175] Reference Figure 6A First, an etch stop layer ES is formed in each of the first pixel circuit PC1, the second pixel circuit PC2, and the region between the first pixel circuit PC1 and the second pixel circuit PC2. In some exemplary embodiments, the etch stop layer ES and the semiconductor layer of the driving thin film transistor T1 may be arranged on the same layer and include the same material.

[0176] In some exemplary embodiments, the etch stop layer ES may include polysilicon or amorphous silicon. In other exemplary embodiments, the etch stop layer ES may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). However, exemplary embodiments of the present inventive concept are not limited thereto. A first gate insulating layer 112, a second gate insulating layer 113, and a third gate insulating layer 114 are sequentially stacked on the etch stop layer ES.

[0177] A photoresist (PR) pattern is formed on the third gate insulating layer 114 to form a groove GR. The groove GR may be formed in a region corresponding to the etch stop layer ES.

[0178] Reference Figure 6B , by using the PR pattern formed on the third gate insulating layer 114 as a mask, openings 114a, 113a and 112a are formed in the third gate insulating layer 114, the second gate insulating layer 113 and the first gate insulating layer 112, respectively, by a first etching. In this embodiment, the first etching can be a dry etching using a fluoride-based gas. For example, the gas used for the first etching can be a combination gas of carbon tetrafluoride (CF4) and H2, trifluoromethane (CHF3), hexafluoroethane (C2F6), octafluoropropane (C3F8), octafluorocyclobutane (C4F8) or a combination gas thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0179] Since the third gate insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride, the third gate insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 may have the same etching conditions.

[0180] In contrast, since the etch stop layer ES includes a material having an etching condition different from those of the third to first gate insulating layers 114 , 113 , and 112 , the etch stop layer ES may not be etched according to the first etching condition.

[0181] Reference Figure 6C , and then the etch stop layer ES is etched by a second etching process to form an opening ESa. The second etching process may be dry etching using a chloride (Cl)-based gas or a combination of a chloride-based gas and an oxygen-based gas. However, exemplary embodiments of the present inventive concept are not limited thereto. In this embodiment, only the etch stop layer ES may react with the second etching conditions and be removed.

[0182] Reference Figure 6D, then the buffer layer 111 is etched by a third etching process to form an opening 111a exposing the barrier layer 101, thereby completing the groove GR. In this embodiment, the third etching process may be a dry etching process using a fluoride (F)-based gas. For example, the gas used for the third etching process may be a combined gas of CF4 and H2, CHF3, C2F6, C3F8, C4F8, or a combined gas thereof. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0183] Since the thickness of the buffer layer 111 is much thinner than the sum of the thicknesses of the first, second, and third gate insulating layers 112, 113, and 114, the opening 111a of the buffer layer 111 can be easily formed while minimizing damage to the barrier layer 101 due to the third etching.

[0184] When etching the buffer layer 111 to the third gate insulating layer 114 simultaneously without using an etch stop layer ES, the etched thickness is large and the overetching rate is high. Therefore, when etching all layers simultaneously, there is a high risk of accidentally etching the barrier layer 101. When etching the barrier layer 101 and forming an opening in the barrier layer 101, impurities or moisture may penetrate into the barrier layer 101 through the substrate 110 and cause degradation of the semiconductor, etc.

[0185] However, exemplary embodiments of the present inventive concept include the etch stop layer ES, which allows the depth of the groove GR to be precisely adjusted when forming the groove GR. Therefore, the barrier layer 101 can be prevented from being damaged (eg, etched) during the process of forming the groove GR.

[0186] like Figure 6E As shown in , the groove GR is then filled by coating an organic filler 161 on the substrate 110. External shock applied to the display device can be absorbed by the organic filler 161. The organic filler 161 may include one or more materials selected from acrylic resin, methacrylic resin, polyester, polyethylene, polypropylene, PET, PEN, polycarbonate, PI, PES, polyoxymethylene, polyarylate, and hexamethyldisiloxane. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0187] like Figure 6F As shown in FIG, a first connection wiring 140 is then formed on the organic filler 161 and the third gate insulating layer 114. The first connection wiring 140 may be connected to the conductive layer. For example, the first connection wiring 140 may be connected to the second electrode Cst2 of the storage capacitor Cst disposed below the third gate insulating layer 114 through the contact holes CNT3a and CNT2b penetrating the third gate insulating layer 114.

[0188] Can Figure 6FFor example, the contact holes CNT3a and CNT2b may be formed simultaneously when the groove GR is formed, or alternatively, the contact holes CNT3a and CNT2b may be formed before or after the groove GR is formed.

[0189] A display device according to an exemplary embodiment can be used to provide a flexible display device, which includes an inorganic material layer and wiring, wherein the inorganic material layer has a groove GR and an organic filler 161 filling the groove GR in a region between a plurality of pixel circuits, the wiring being included in the pixel circuits, and the pixel circuits being connected by a connection wiring arranged on the organic filler 161.

[0190] Furthermore, when forming the groove GR, using the etch stop layer ES allows the depth of the groove GR to be finely adjusted. Therefore, damage to the barrier layer 101 can be minimized.

[0191] Figure 7 According to another exemplary embodiment Figure 4 A cross-sectional view of the display device taken along line II' and line II-II'. Figure 7 In, due to Figure 5A The same reference numerals as those in the accompanying drawings denote the same components, so their description will be omitted.

[0192] according to Figure 7 The display device of the exemplary embodiment includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., a first pixel circuit PC1 and a second pixel circuit PC2) and an organic filler 161 filling the groove GR. In this embodiment, the inorganic material layer includes insulating material layers (i.e., a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, and a third gate insulating layer 114) having different etching conditions, and an etch stop layer ES provided on a portion of a sidewall or a bottom surface of the groove GR.

[0193] exist Figure 7 In an exemplary embodiment, the etch stop layer ES may form the bottom surface of the groove GR. In other words, the etch stop layer ES may be disposed in the region between the first pixel circuit PC1 and the second pixel circuit PC2, and the groove GR may be formed as an opening of the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112. The bottom surface of the groove GR may be located between the lowest portion of the first gate insulating layer 112 and the highest portion of the first gate insulating layer 112.

[0194] exist Figure 7In the exemplary embodiment shown in , the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES may include a material having an etching condition different from that of the insulating materials. For example, in an exemplary embodiment, the etch stop layer ES may include a semiconductor layer.

[0195] In some exemplary embodiments, the third gate insulating layer 114 , the second gate insulating layer 113 , and the first gate insulating layer 112 may be etched by a fluoride-based gas, and the etch stop layer ES may be etched by a chloride-based gas.

[0196] As described above, the etch stop layer ES protects the barrier layer 101 thereunder from being etched, and may minimize the penetration of foreign substances through the substrate 110 through the barrier layer 101 .

[0197] The display device according to the exemplary embodiment may be used to provide a flexible display device including the organic filler 161 filling the groove GR and wirings included in the pixel circuit connected through the connection wirings disposed on the organic filler 161 .

[0198] Figure 8 According to another exemplary embodiment Figure 4 A sectional view taken along line II' and line II-II'. Figure 8 In, with Figure 5A The same reference numerals as those in the accompanying drawings denote the same components, and description thereof will be omitted.

[0199] according to Figure 8 The display device of the exemplary embodiment includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., a first pixel circuit PC1 and a second pixel circuit PC2) and an organic filler 161 filling the groove GR. In this embodiment, the inorganic material layer includes insulating material layers having different etching conditions (i.e., a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, and a third gate insulating layer 114) and an etch stop layer ES'. The etch stop layer ES' is provided on a portion of the sidewall or bottom surface of the groove GR.

[0200] Reference Figure 8 The etch stop layer ES' and the gate electrodes G1 and G6 may be arranged on the same layer and include the same material. For example, the etch stop layer ES' may be arranged between the first gate insulating layer 112 and the second gate insulating layer 113. In addition, the etch stop layer ES' may include Mo, Cu, Ti, etc., and may include a single layer or multiple layers.

[0201] The etch stop layer ES' may form a portion of the sidewall of the groove GR. For example, the etch stop layer ES' may form a portion of the sidewall of the groove GR that is higher than the bottom portion of the groove GR (for example, in the direction of the thickness of the substrate 110). The etch stop layer ES' may be understood to be arranged to surround the groove GR or the organic filler 161.

[0202] In the present exemplary embodiment, the third gate insulating layer 114, the second gate insulating layer 113, and the first gate insulating layer 112 include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES' may include a material having an etching condition different from that of the insulating materials. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0203] In some exemplary embodiments, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 may be etched by a fluoride-based gas, and the etch stop layer ES' may be etched by a chloride-based gas. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0204] As described above, damage to the barrier layer 101 under the etch stop layer ES′ may be minimized by the etch stop layer ES′, and thus, permeation of foreign substances through the substrate 110 may be minimized.

[0205] The display device according to the exemplary embodiment may be used to provide a flexible display device including the organic filler 161 filling the groove GR and wirings included in the pixel circuit connected through the connection wirings disposed on the organic filler 161 .

[0206] Figure 9 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Figure 9 In, due to Figure 5A The same reference numerals as those in the accompanying drawings denote the same components, so their description will be omitted.

[0207] according to Figure 9 The display device of the exemplary embodiment includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (e.g., a first pixel circuit PC1 and a second pixel circuit PC2) and an organic filler 161 filling the groove GR. The inorganic material layer includes insulating material layers (i.e., a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, and a third gate insulating layer 114) having different etching conditions, and an etch stop layer ES'' provided on a portion of a sidewall or a bottom surface of the groove GR.

[0208] In this exemplary embodiment, the etch stop layer ES″ may be arranged on the same layer as the second electrode Cst2 of the storage capacitor Cst and include the same material as the second electrode Cst2 of the storage capacitor Cst. The etch stop layer ES″ may be arranged between the second gate insulating layer 113 and the third gate insulating layer 114. In addition, the etch stop layer ES″ may include Mo, Cu, Ti, etc., and may include a single layer or multiple layers.

[0209] The etch stop layer ES″ can form a portion of the side wall of the groove GR. For example, the etch stop layer ES″ can form the middle portion of the side wall of the groove GR (for example, the middle portion in the direction of the thickness of the substrate 110). The etch stop layer ES″ can be understood as being arranged to surround the groove GR or the organic filler 161.

[0210] In the present exemplary embodiment, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and the etch stop layer ES″ may include a material having an etching condition different from that of the insulating materials. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0211] In some exemplary embodiments, the third gate insulating layer 114, the second gate insulating layer 113, the first gate insulating layer 112, and the buffer layer 111 may be etched by a fluoride-based gas, and the etch stop layer ES" may be etched by a chloride-based gas.

[0212] As described above, damage to the barrier layer 101 under the etch stop layer ES″ may be minimized by the etch stop layer ES″, and thus, penetration of foreign matter through the substrate 110 may be minimized. However, exemplary embodiments of the present inventive concept are not limited thereto.

[0213] The display device according to the exemplary embodiment may be used to provide a flexible display device including the organic filler 161 filling the groove GR and wirings included in the pixel circuit connected through the connection wirings disposed on the organic filler 161 .

[0214] Figure 10 is a cross-sectional view showing a portion of a display device according to another exemplary embodiment. Figure 10 In, due to Figure 5A The same reference numerals as those in the reference numerals in FIG. Figure 5A The components are the same as those of , so their description will be omitted.

[0215] Reference Figure 10, the display device according to an exemplary embodiment includes an inorganic material layer having a groove GR in a region between a plurality of pixel circuits (eg, a first pixel circuit PC1 and a second pixel circuit PC2 ) and an organic filler 161 filling the groove GR.

[0216] In this embodiment, a recess GRh extending parallel to the upper surface of the substrate 110 may be provided on the sidewall of the groove GR. Figure 10 In the embodiment, the recess GRh is arranged between the buffer layer 111 and the first gate insulating layer 112. However, exemplary embodiments of the present inventive concept are not limited thereto. For example, the recess GRh may be arranged between the first gate insulating layer 112 and the second gate insulating layer 113. The recess GRh may also be arranged between the second gate insulating layer 113 and the third gate insulating layer 114.

[0217] After the depth of the groove GR is precisely controlled using the etch stop layer, the recess GRh can be formed by removing the etch stop layer. Since the etch stop layer may include a semiconductor material or a metal layer and can be etched by a chloride-based gas, the etch stop layer can be completely removed according to the etching conditions. Therefore, the recess GRh can be formed in the area where the etch stop layer has been removed.

[0218] The recess GRh may form a portion of the groove GR. Since the groove GR is filled with the organic filler 161 , the recess GRh may also be filled with the organic filler 161 .

[0219] The display device according to the exemplary embodiment may be used to provide a flexible display device including the organic filler 161 filling the groove GR and wirings included in the pixel circuit connected through the connection wirings disposed on the organic filler 161 .

[0220] As described above, since the display device according to the exemplary embodiment includes the inorganic material layer having the grooves in the region between the plurality of pixels and the organic filler filling the grooves, the display device may be strong and flexible in response to external shocks.

[0221] Furthermore, since the groove includes the etch stop layer, the depth of the groove can be easily controlled.

[0222] The scope of the exemplary embodiments is not limited to the above-mentioned advantages.

[0223] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments. Although one or more exemplary embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope as defined by the claims.

Claims

1. A display device, comprising: a substrate including a display area having a plurality of pixel circuits spaced apart from each other; an inorganic material layer arranged in the display area and having a groove between adjacent pixel circuits among the plurality of pixel circuits, wherein the groove extends in one direction between the adjacent pixel circuits; as well as an organic filler disposed in the groove, Wherein, the inorganic material layer includes an etching stop layer and at least one insulating material layer, The etch stop layer comprises a semiconductor material or a conductive material, and The etch stop layer is disposed on a portion of a sidewall or a bottom surface of the groove.

2. The display device according to claim 1, wherein: Each of the plurality of pixel circuits includes a thin film transistor including a semiconductor layer and a gate electrode; and The etch stop layer is provided on the same layer as the semiconductor layer and includes the same material as that of the semiconductor layer.

3. The display device according to claim 1, wherein: Each of the plurality of pixel circuits includes a thin film transistor including a semiconductor layer and a gate electrode; and The etch stop layer is provided on the same layer as the gate electrode and includes the same material as that of the gate electrode.

4. The display device according to claim 1, wherein: Each of the plurality of pixel circuits includes a driving thin film transistor and a storage capacitor, the driving thin film transistor and the storage capacitor being arranged to overlap each other; and The etch stop layer is provided on the same layer as the electrode of the storage capacitor and includes the same material as that of the electrode of the storage capacitor.

5. The display device according to claim 1, wherein: The inorganic material layer includes a barrier layer disposed on the substrate; and The barrier layer is continuously disposed throughout the plurality of pixel circuits. The display device according to claim 1 , wherein: The organic filler extends to the upper surface of the inorganic material layer. 7 . The display device according to claim 1 , further comprising a first connection wiring overlapped with the plurality of pixel circuits and arranged on the organic filler.

8. The display device according to claim 7, wherein: The adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction; The first scan line of the first pixel circuit and the second scan line of the second pixel circuit are separated by the organic filler; and The first scan line and the second scan line are connected to each other through the first connection wiring.

9. The display device according to claim 8, wherein An elongation rate of the first connection wiring is greater than an elongation rate of the first scanning line and an elongation rate of the second scanning line.

10. The display device according to claim 9, further comprising: an interlayer insulating layer covering the first connecting wiring; as well as A second connection wiring is arranged on the interlayer insulating layer and is configured to connect the plurality of pixel circuits to each other.

11. The display device according to claim 10, further comprising: an opening located in the interlayer insulating layer, wherein the opening exposes the organic filler; as well as an organic filler disposed in the opening, The first connecting wiring and the second connecting wiring extend in different directions.

12. The display device according to claim 1, wherein An upper surface of the organic filler has a convex shape.

13. A display device, comprising: a substrate including a display area having a plurality of pixel circuits spaced apart from each other; an inorganic material layer arranged in the display area and having a groove in a region between adjacent pixel circuits among the plurality of pixel circuits, the groove extending in one direction between the adjacent pixel circuits; an organic filler disposed in the groove; as well as A recess is positioned on a sidewall of the groove.

14. The display device according to claim 13, wherein: The inorganic material layer includes a barrier layer disposed on the substrate; and The barrier layer is disposed below the groove and is continuously disposed across the plurality of pixel circuits.

15. The display device according to claim 13, wherein The organic filler is arranged to surround at least a portion of the plurality of pixel circuits. 16 . The display device according to claim 13 , further comprising a first connection wiring overlapped with the plurality of pixel circuits and arranged on the organic filler.

17. The display device according to claim 16, wherein: The adjacent pixel circuits include a first pixel circuit and a second pixel circuit adjacent to each other in a first direction; The first scan line of the first pixel circuit and the second scan line of the second pixel circuit are separated by the organic filler; and The first scan line and the second scan line are connected to each other through the first connection wiring.

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