Semiconductor epitaxial wafer, method for manufacturing the same, and semiconductor device

Abstract

The present invention provides a semiconductor epitaxial wafer, a semiconductor device, and a method for manufacturing a semiconductor epitaxial wafer, which suppress variations in device characteristics within a plane parallel to the main surface of the semiconductor wafer. The semiconductor epitaxial wafer includes a semiconductor wafer and a first-conductivity-type semiconductor epitaxial layer disposed on the main surface of the semiconductor wafer and containing impurities of the first conductivity type. There is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer within a plane parallel to the main surface of the semiconductor wafer.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor epitaxial wafer, a semiconductor device, and a method for manufacturing a semiconductor epitaxial wafer. Background Art

[0002] Silicon carbide (SiC) is a semiconductor material having a large bandgap and high hardness compared to silicon (Si). SiC is applied to power devices such as switching devices and rectifying devices, for example. A power device using SiC has an advantage of being able to reduce power loss compared to a power device using Si, for example.

[0003] Representative semiconductor devices using SiC are a Metal-Insulator-Semiconductor Field-Effect Transistor (MISFET) and a Schottky-Barrier Diode (SBD). A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a kind of MISFET.

[0004] A semiconductor device using SiC (hereinafter referred to as "SiC semiconductor device") is formed using a SiC epitaxial layer formed on a main surface of a SiC wafer. Generally, a plurality of SiC semiconductor devices (chips) are fabricated from one SiC wafer. In each SiC semiconductor device, the SiC epitaxial layer includes a drift layer.

[0005] In the present specification, a "SiC wafer" refers to a substrate obtained by cutting and polishing a single crystal SiC produced by the improved Lely method, sublimation method, or the like into a given size. In addition, a substrate having a SiC epitaxial layer formed thereon is referred to as a "SiC epitaxial wafer". The SiC epitaxial wafer has been disclosed in Patent Document 1, for example.

[0006] In this specification, the "silicon carbide epitaxial wafer" also includes a substrate on which a silicon carbide wafer having a silicon carbide epitaxial layer formed thereon has a plurality of silicon carbide semiconductor elements (e.g., SiC-MISFETs) formed thereon or only a part of its element structure formed thereon. In addition, the silicon carbide epitaxial wafer having a plurality of silicon carbide semiconductor elements formed thereon is then cut (diced) into a given chip size, whereby the plurality of silicon carbide semiconductor elements are separated from each other. Further, in this specification, wafers of semiconductors such as SiC and gallium nitride (GaN) are collectively referred to as "semiconductor wafers", and substrates having semiconductor layers such as SiC and GaN formed thereon are collectively referred to as "semiconductor epitaxial wafers". The semiconductor epitaxial wafer also includes a substrate on which a plurality of semiconductor elements are formed or only a part of its element structure is formed.

[0007] Prior art documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-052674

[0010] Between semiconductor elements (between chips) or within a semiconductor element (within a chip) formed on a semiconductor epitaxial wafer, it is required to reduce variations in characteristics such as avalanche breakdown voltage and on-resistance Ron. In this specification, variations in element characteristics that occur between semiconductor elements or within a semiconductor element, that is, variations in element characteristics that occur in the plane of the semiconductor wafer, are referred to as "in-plane variations". Summary of the invention

[0011] Problems to be solved by the invention

[0012] One embodiment of the present disclosure provides a semiconductor epitaxial wafer or a semiconductor element capable of reducing variations in characteristics in a plane parallel to the main surface of a semiconductor wafer.

[0013] Means for solving the problems

[0014] A semiconductor epitaxial wafer according to one embodiment of the present disclosure includes: a semiconductor wafer; and a semiconductor epitaxial layer of a first conductivity type, disposed on the main surface of the semiconductor wafer and containing impurities of the first conductivity type. Moreover, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer.

[0015] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor substrate, a semiconductor epitaxial layer, a body region, a source region, and a gate electrode. The semiconductor epitaxial layer is disposed on the main surface of the semiconductor substrate and has a first conductivity type containing impurities of the first conductivity type. The body region is in contact with the semiconductor epitaxial layer and has a second conductivity type. The source region is in contact with the body region and has the first conductivity type. The gate electrode is disposed on the semiconductor epitaxial layer with a gate insulating film interposed therebetween. Moreover, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor substrate.

[0016] A semiconductor device according to another embodiment of the present disclosure includes: a semiconductor substrate, a semiconductor epitaxial layer, a first electrode, and a second electrode. The semiconductor epitaxial layer is disposed on the main surface of the semiconductor substrate and has a first conductivity type containing impurities of the first conductivity type. The first electrode is disposed on the semiconductor epitaxial layer and is in contact with the semiconductor epitaxial layer. The second electrode is disposed on the surface of the semiconductor substrate opposite to the main surface and is in contact with the semiconductor substrate. Moreover, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor substrate.

[0017] A method for manufacturing a semiconductor epitaxial wafer according to an embodiment of the present disclosure includes: (A) a step of preparing a semiconductor wafer; and (B) a step of forming a semiconductor epitaxial layer of a first conductivity type containing impurities of the first conductivity type by epitaxially growing a semiconductor on the main surface of the semiconductor wafer. In step (B), the conditions for epitaxial growth are controlled such that there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer.

[0018] Advantageous Effects of the Invention

[0019] According to one aspect of the present disclosure, a semiconductor epitaxial wafer or a semiconductor device capable of reducing the deviation of element characteristics in a plane parallel to the main surface of a semiconductor wafer can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a plan view illustrating a silicon carbide epitaxial wafer.

[0021] Figure 2 is a plan view illustrating a silicon carbide semiconductor device.

[0022] Figure 3 is a cross-sectional view illustrating a unit cell in a silicon carbide semiconductor device.

[0023] Figure 4A is a diagram illustrating the thickness and impurity concentration distributions of a silicon carbide epitaxial layer on a straight line passing through the center of a silicon carbide epitaxial wafer.

[0024] Figure 4B It is a diagram illustrating the thickness and the distribution of impurity concentration of a silicon carbide epitaxial layer on a straight line passing through the center of a silicon carbide epitaxial wafer.

[0025] Figure 4C It is a diagram illustrating the thickness and the distribution of impurity concentration of a silicon carbide epitaxial layer on a straight line passing through the center of a silicon carbide epitaxial wafer.

[0026] Figure 5 It is a diagram illustrating the thickness and the distribution of impurity concentration of a silicon carbide epitaxial layer on a straight line passing through the center of a silicon carbide semiconductor device.

[0027] Figure 6 It is a diagram showing the relationship between the deviation amounts of the thickness and the impurity concentration of a silicon carbide epitaxial layer from set values and the breakdown voltage of a silicon carbide semiconductor device.

[0028] Figure 7 It is a diagram showing the relationship between the ratio VC / VT of the amplitude VC of an impurity concentration distribution to the amplitude VT of a thickness distribution and the deviation amplitude VB of the breakdown voltage.

[0029] Figure 8 It is a schematic cross-sectional view showing an example of an epitaxial growth apparatus.

[0030] Figure 9 It is a diagram for explaining a film formation distribution generated in a reactor of an epitaxial growth apparatus.

[0031] Figure 10 It is a diagram showing the relationship between a film formation distribution and an in-plane distribution of the thickness of a silicon carbide epitaxial layer.

[0032] Figure 11 It is a diagram showing the relationship between a film formation distribution and an in-plane distribution of the thickness of a silicon carbide epitaxial layer.

[0033] Figure 12 It is a top view showing measurement positions of an in-plane distribution of a silicon carbide epitaxial wafer.

[0034] Figure 13A It is a diagram showing an in-plane distribution of the thickness and the impurity concentration of a silicon carbide epitaxial layer in an example.

[0035] Figure 13B It is a diagram showing an in-plane distribution of the thickness and the impurity concentration of a silicon carbide epitaxial layer in a comparative example.

[0036] Figure 14A It is a diagram showing the difference between the maximum value and the minimum value of the breakdown voltage in an example and a comparative example.

[0037] Figure 14B It is a diagram showing the difference between the maximum value and the minimum value of the drift resistance in an example and a comparative example.

[0038] Figure 15A It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0039] Figure 15B It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0040] Figure 15C It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0041] Figure 15D It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0042] Figure 15E It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0043] Figure 15F It is a cross-sectional view for explaining a method of manufacturing a silicon carbide semiconductor device.

[0044] Figure 16 It is a cross-sectional view showing another example of a silicon carbide semiconductor device.

[0045] Figure 17A It is a graph exemplifying the relationship between the impurity concentration and thickness of a silicon carbide epitaxial layer and the breakdown voltage of a silicon carbide semiconductor device.

[0046] Figure 17B It is a graph exemplifying the relationship between the impurity concentration and thickness of a silicon carbide epitaxial layer and the drift resistance of a silicon carbide semiconductor device.

[0047] Description of Reference Numerals

[0048] 100: Unit cell;

[0049] 101: Silicon carbide substrate;

[0050] 102: Drift region;

[0051] 103: Body region;

[0052] 104: Source region;

[0053] 105: Contact region;

[0054] 106: Channel layer;

[0055] 107: Gate insulating film;

[0056] 108: Gate electrode;

[0057] 109: Source electrode;

[0058] 110: Silicon carbide epitaxial layer;

[0059] 111: Interlayer insulating layer;

[0060] 112: Source wiring;

[0061] 114: Drain electrode;

[0062] 120: Region;

[0063] 200: Silicon carbide semiconductor device (MISFET);

[0064] 201: Source pad;

[0065] 202: Gate pad;

[0066] 300: Silicon carbide epitaxial wafer;

[0067] 301: Silicon carbide wafer;

[0068] 400: Schottky diode;

[0069] 410: First electrode;

[0070] 420: Second electrode;

[0071] 700: Epitaxial growth apparatus;

[0072] 701: Substrate holder;

[0073] 702: Shaft;

[0074] 703: Gas inlet tube;

[0075] 705: Gas;

[0076] 707: Seal;

[0077] d1, d2: Film formation distribution;

[0078] e1, e2: End;

[0079] e3, e4: End;

[0080] Rc: Element region;

[0081] Ru: Unit cell formation region. Detailed implementation mode

[0082] The on-resistance and avalanche breakdown voltage of a semiconductor device formed using a semiconductor epitaxial wafer are determined by various parameters related to the materials and structures of the semiconductor epitaxial wafer and the semiconductor device. Therefore, it is considered that if these parameters can be made substantially uniform within the semiconductor wafer surface, the deviation of the on-resistance and avalanche breakdown voltage within the semiconductor wafer surface (in-plane deviation) can be reduced. However, among the parameters, there are parameters that have a distribution within the semiconductor wafer surface (in-plane distribution) due to, for example, the manufacturing process of the semiconductor device, and it is difficult to make such parameters uniform within the semiconductor wafer surface.

[0083] In this regard, the present inventors focused on two parameters, namely, the impurity concentration (carrier concentration) and thickness of the semiconductor epitaxial layer, among the parameters that determine the on-resistance and avalanche breakdown voltage, and obtained the following insight: by controlling the correlation of the in-plane distribution of these parameters, the in-plane deviation of the on-resistance and avalanche breakdown voltage can be reduced.

[0084] Hereinafter, taking a silicon carbide semiconductor device as an example, the insight that forms the basis of the present invention regarding the characteristics of the semiconductor device will be described.

[0085] <Avalanche breakdown voltage V AVA >

[0086] In a silicon carbide semiconductor device formed using a silicon carbide epitaxial wafer, the avalanche breakdown voltage (hereinafter simply referred to as "breakdown voltage") V AVA depends on the impurity concentration (carrier concentration) Nd of the silicon carbide epitaxial layer and the thickness td of the silicon carbide epitaxial layer. Specifically, the lower the impurity concentration Nd of the silicon carbide epitaxial layer and the greater the thickness td thereof, the higher the breakdown voltage V AVA can be obtained. The impurity concentration Nd is, for example, the concentration of n-type impurities.

[0087] Figure 17A is a diagram showing an example of the relationship between the impurity concentration Nd and the thickness td of the silicon carbide epitaxial layer and the breakdown voltage V AVA of the silicon carbide semiconductor device. Figure 17A is the calculation result of the breakdown voltage V AVA of the silicon carbide semiconductor device calculated based on the following formula (1).

[0088] [Mathematical formula 1]

[0089]

[0090] Nd: Impurity concentration of silicon carbide epitaxial layer

[0091] td: Thickness of silicon carbide epitaxial layer

[0092] ε SiC : Dielectric constant of SiC (= εr × ε0 = 9.7 × 8.85 × 10-14 )

[0093] Nb: Impurity concentration of the buffer layer

[0094] Ec: Insulation breakdown electric field strength

[0095] In addition, ε0 is the permittivity of vacuum, and εr is the relative permittivity of the material.

[0096] The insulation breakdown electric field strength Ec in Equation (1) varies according to the impurity concentration Nd as shown in the following Equation (1A), for example.

[0097] [Mathematical formula 2]

[0098]

[0099] In addition, the buffer layer is a silicon carbide semiconductor layer formed between the silicon carbide epitaxial layer and the silicon carbide wafer. The silicon carbide semiconductor device may not have a buffer layer. In this case, Nb becomes the impurity concentration of the silicon carbide wafer.

[0100] <On-resistance Ron>

[0101] The on-resistance Ron of the silicon carbide semiconductor device includes: the resistance component R1 of the silicon carbide epitaxial wafer and the resistance component R2 based on the device structure formed on the silicon carbide epitaxial wafer. The resistance component R1 is mainly the resistance of the silicon carbide wafer (substrate resistance) and the drift resistance Rdrift generated in the silicon carbide epitaxial layer. In the case where the silicon carbide semiconductor device is a MISFET, the resistance component R2 based on the device structure includes the contact resistance between the drift electrode (back electrode) and the silicon carbide substrate, the resistance of the source region, the resistance of the JFET (Junction FET) region, the contact resistance between the source electrode and the silicon carbide epitaxial layer (source contact resistance), the channel resistance, etc.

[0102] Silicon carbide semiconductor devices such as MISFETs sometimes operate at high temperatures in applications such as automotive use. If the SiC-MISFET operates at a high temperature (e.g., 175°C), the on-resistance Ron increases compared to operating at room temperature (25°C). This is because, among the above resistance components, especially the drift resistance Rdrift increases. As a result, during the high-temperature operation of the SiC-MISFET, the drift resistance Rdrift sometimes accounts for more than 40% of the entire on-resistance Ron.

[0103] Thus, since the proportion of the drift resistance Rdrifi in the entire on-resistance Ron is high, the on-resistance Ron can be efficiently controlled by controlling the drift resistance Rdrift generated in the silicon carbide epitaxial layer.

[0104] The drift resistance \(R_{drift}\) is determined by the impurity concentration \(N_d\) and the thickness \(t_d\) of the silicon carbide epitaxial layer. Specifically, the higher the impurity concentration \(N_d\) of the semiconductor epitaxial layer and the smaller the thickness \(t_d\), the lower the drift resistance \(R_{drift}\).

[0105] Figure 17B FIG. is an example showing the relationship between the impurity concentration \(N_d\) and the thickness \(t_d\) of the silicon carbide epitaxial layer and the drift resistance \(R_{drift}\) of the silicon carbide semiconductor device. Figure 17B It is the calculation result of calculating the drift resistance \(R_{drift}\) based on the following formula (2).

[0106] [Mathematical formula 3]

[0107]

[0108] \(\rho\): Resistivity of the silicon carbide epitaxial layer

[0109] \(t_d\): Thickness of the silicon carbide epitaxial layer

[0110] \(A_{chip}\): Area of the silicon carbide semiconductor device (chip area)

[0111] The resistivity \(\rho\) in formula (2) depends on the impurity concentration \(N_d\) (\(\rho = 1 / \mu N_d\), where \(\mu\) is the carrier mobility). In addition, the carrier mobility \(\mu\) also depends on the impurity concentration \(N_d\). Specifically, as the impurity concentration \(N_d\) increases, the scattering caused by impurities increases, so the carrier mobility \(\mu\) decreases. Here, the resistivity \(\rho\) is calculated based on the measured value, and the drift resistance \(R_{drift}\) is calculated.

[0112] <In-plane deviation of device characteristics>

[0113] It is known that when forming a silicon carbide epitaxial layer on a silicon carbide wafer, the impurity concentration \(N_d\) and the thickness \(t_d\) are distributed (in-plane distribution) in the plane of the silicon carbide wafer. As described above, the breakdown voltage \(V\) of the semiconductor device AVA and the drift resistance \(R_{drift}\) depend on the impurity concentration \(N_d\) and the thickness \(t_d\) of the silicon carbide epitaxial layer. Therefore, if the impurity concentration \(N_d\) and the thickness \(t_d\) of the silicon carbide epitaxial layer have an in-plane distribution, the breakdown voltage \(V\) AVA and the drift resistance \(R_{drift}\) may deviate (in-plane deviation) between or within the semiconductor devices formed on the silicon carbide wafer.

[0114] If the in-plane deviation of the device characteristics is large, for example, the breakdown voltage \(V\) of some silicon carbide semiconductor devices AVA may not satisfy the given value (specification of the semiconductor device), which becomes a major cause of the decrease in the yield. To avoid this phenomenon, if the silicon carbide semiconductor device is designed considering the in-plane deviation of the device characteristics so that the breakdown voltage \(V\) is uniform across the plane of the semiconductor wafer AVAIf a given value is satisfied, it is possible that the drift resistance Rdrift increases (i.e., the on-resistance Ron increases).

[0115] Hereinafter, an example of a design method of a silicon carbide epitaxial layer when manufacturing a silicon carbide semiconductor device with a breakdown voltage of 1200V will be described.

[0116] Referring again to Figure 17A and Figure 17B . As shown at point p1 in the figure, for example, the design value of the thickness td of the silicon carbide epitaxial layer is set to 9μm, and the design value of the impurity concentration Nd is set to 1×10 16 / cm 3 . The target value of the breakdown voltage V AVA of the silicon carbide semiconductor device is 1420V, and the target value of the drift resistance Rdrift is 0.7mΩ·cm 2 .

[0117] The actual thickness td of the formed silicon carbide epitaxial layer can have an in-plane distribution of ±10% with respect to the design value, and the impurity concentration Nd can have an in-plane distribution of 20% with respect to the design value. If such an in-plane distribution occurs, as Figure 17A shown, within the silicon carbide wafer plane, the breakdown voltage V AVA has a deviation within a range Hb of about 1250V to 1600V. In addition, as Figure 17B shown, within the silicon carbide wafer plane, the drift resistance Rdrift has a deviation within a range Hd of about 0.5mΩ / cm 2 to about 1.1mΩ / cm 2 . In this example, since the entire range Hb is 1200V or more, it can be seen from the above design values that a given breakdown voltage (here 1200V) can be satisfied over the entire silicon carbide wafer surface.

[0118] Thus, in order to satisfy a given breakdown voltage (1200V) over the entire silicon carbide wafer surface, it is necessary to set the target value of the breakdown voltage V AVA high enough above 1200V so that the entire range Hd of the breakdown voltage deviation is 1200V or more. In order to increase the target value of the breakdown voltage V AVA , it is possible to consider increasing the design value of the thickness td of the silicon carbide epitaxial layer or reducing the design value of the impurity concentration Nd. However, if the thickness td is increased or the impurity concentration Nd is decreased, the drift resistance Rdrifi becomes higher. As a result, the on-resistance Ron of the silicon carbide semiconductor device increases, and it may be difficult to achieve a large current and a small chip size for the silicon carbide semiconductor device. This may be a major cause of an increase in device cost.

[0119] In order to reduce the deviation of device characteristics, it is preferable to form a more uniform silicon carbide epitaxial layer in the plane of the silicon carbide wafer. For example, the aforementioned Patent Document 1 discloses the following content, that is, by feedback controlling the flow rate of the source gas based on the rotation speed of the silicon carbide wafer during silicon carbide epitaxial growth, the in-plane uniformity of the impurity concentration and thickness is improved.

[0120] However, the inventors have studied and found that depending on the epitaxial growth method and growth conditions, there are limitations even if one wants to reduce the in-plane distribution of the impurity concentration and thickness generated in the silicon carbide epitaxial layer. In particular, the larger the maximum diameter of the silicon carbide wafer (for example, 6 inches or more, or 8 inches or more), the more difficult it is to suppress the in-plane distribution of the impurity concentration and thickness to be small. In addition, this problem may also occur in semiconductor devices using semiconductors other than silicon carbide.

[0121] Therefore, the inventors have studied a method for reducing the in-plane deviation of device characteristics caused by the in-plane distribution of the thickness and impurity concentration of a semiconductor epitaxial layer (such as a silicon carbide epitaxial layer). As a result, the inventors have found the following, that is, by controlling the correlation between the in-plane distribution of the thickness of the semiconductor epitaxial layer and the in-plane distribution of the impurity concentration, the in-plane deviation of device characteristics such as breakdown voltage and on-resistance Ron can be reduced. According to one aspect of the present disclosure, the in-plane distribution of the thickness of the semiconductor epitaxial layer and the in-plane distribution of the impurity concentration have a positive correlation, so that the amount of change in device characteristics caused by the in-plane distribution of thickness and the amount of change in device characteristics caused by the in-plane distribution of impurity concentration can be offset. Therefore, a semiconductor epitaxial wafer or a semiconductor device with reduced in-plane deviation of device characteristics can be provided.

[0122] The outline of one aspect of the present disclosure is as follows.

[0123] A semiconductor epitaxial wafer according to an embodiment of the present disclosure includes: a semiconductor wafer, and a semiconductor epitaxial layer of a first conductivity type. The semiconductor epitaxial layer is disposed on the main surface of the semiconductor wafer and contains impurities of the first conductivity type. The thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer have a positive correlation.

[0124] In a certain embodiment, if the maximum thickness in the thickness distribution of the semiconductor epitaxial layer is set as Tmax, the minimum thickness is set as Tmin, and the average thickness is set as Tave, the amplitude VT (%) of the thickness distribution with respect to the average thickness Tave is represented by the following formula (3).

[0125] VT = [{(Tmax - Tmin) / 2} / Tave] × 100 (%) (3)

[0126] In addition, if the maximum concentration in the concentration distribution of the semiconductor epitaxial layer is set as Cmax, the minimum concentration is set as Cmin, and the average concentration is set as Cave, then the amplitude VC (%) of the concentration distribution with respect to the average concentration Cave is represented by the following formula (4).

[0127] VC = [{(Cmax - Cmin) / 2} / Cave] × 100 (%) (4)

[0128] Alternatively, the amplitude VT of the thickness distribution may be 5% or more and 20% or less, and the amplitude VC of the concentration distribution may be 10% or more and 40% or less.

[0129] In a certain embodiment, the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer, for example, satisfy 0.5 ≤ VC / VT ≤ 3.0.

[0130] In a certain embodiment, the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer, for example, satisfy 1.0 ≤ VC / VT ≤ 2.5.

[0131] In a certain embodiment, alternatively, if the thicknesses of the semiconductor epitaxial layer at two points a and b in a plane parallel to the main surface of the semiconductor wafer are set as Da and Db, and the impurity concentrations of the semiconductor epitaxial layer are set as Ca and Cb, then when Da > Db, Ca > Cb, or when Da < Db, Ca < Cb.

[0132] In a certain embodiment, alternatively, the thickness of the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer is smaller in the central portion of the semiconductor wafer than in the peripheral portion, and the impurity concentration of the semiconductor epitaxial layer is lower in the central portion of the semiconductor wafer than in the peripheral portion.

[0133] In a certain embodiment, alternatively, the thickness of the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer is larger in the central portion of the semiconductor wafer than in the peripheral portion, and the impurity concentration of the semiconductor epitaxial layer is higher in the central portion of the semiconductor wafer than in the peripheral portion.

[0134] In a certain embodiment, the average concentration Cave of the semiconductor epitaxial layer is, for example, 3×10 15 / cm 3 or more and 3×10 16 / cm 3 or less, and the average thickness Tave is, for example, 4 μm or more and 40 μm or less.

[0135] In some embodiments, the semiconductor epitaxial wafer may also have a plurality of element regions. Each of the plurality of element regions may also include a semiconductor element having: a body region of a second conductivity type in contact with the semiconductor epitaxial layer, a source region of a first conductivity type in contact with the body region, and a gate electrode disposed on the semiconductor epitaxial layer with a gate insulating film therebetween.

[0136] In some embodiments, the semiconductor epitaxial wafer may also have a plurality of element regions. Each of the plurality of element regions may also include a semiconductor element having: a first electrode disposed on and in contact with the semiconductor epitaxial layer, and a second electrode disposed on the surface of the semiconductor wafer opposite to the main surface and in contact with the semiconductor wafer.

[0137] In some embodiments, if the maximum value of the avalanche breakdown voltage of the semiconductor elements in each of the plurality of element regions is Bmax, the minimum value is Bmin, and the average value is Bave, then the deviation amplitude VB(%) of the avalanche breakdown voltage of the semiconductor elements among the plurality of element regions with respect to the average value Bave is represented by the following formula (5).

[0138] VB(%) = [((Bmax - Bmin) / 2) / Bave] × 100 (%) (5)

[0139] If the maximum value of the drift resistance of the semiconductor elements in each of the plurality of element regions is Dmax, the minimum value is Dmin, and the average value is Dave, then the deviation amplitude VD(%) of the drift resistance of the semiconductor elements among the plurality of element regions with respect to the average value Dave is represented by the following formula (6).

[0140] VD(%) = [((Dmax - Dmin) / 2) / Dave] × 100 (%) (6)

[0141] The amplitude VB and the amplitude VD may also be 0% or more and 10% or less.

[0142] In some embodiments, the semiconductor wafer may be a silicon carbide wafer, and the semiconductor epitaxial layer may be a silicon carbide semiconductor layer.

[0143] A semiconductor device according to an embodiment of the present disclosure includes: a semiconductor substrate, a semiconductor epitaxial layer, a body region, a source region, a gate insulating film, and a gate electrode. The semiconductor epitaxial layer is disposed on a main surface of the semiconductor substrate and has a first conductivity type containing impurities of the first conductivity type. The body region is in contact with the semiconductor epitaxial layer and has a second conductivity type. The source region is in contact with the body region and has the first conductivity type. The gate electrode is disposed on the semiconductor epitaxial layer with the gate insulating film interposed therebetween. In a plane parallel to the main surface of the semiconductor substrate, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer.

[0144] A semiconductor device according to another embodiment of the present disclosure includes: a semiconductor substrate, a semiconductor epitaxial layer, a first electrode, and a second electrode. The semiconductor epitaxial layer is disposed on a main surface of the semiconductor substrate and has a first conductivity type containing impurities of the first conductivity type. The first electrode is disposed on the semiconductor epitaxial layer and is in contact with the semiconductor epitaxial layer. The second electrode is disposed on a surface of the semiconductor substrate opposite to the main surface and is in contact with the semiconductor substrate. In a plane parallel to the main surface of the semiconductor substrate, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer.

[0145] A method for manufacturing a semiconductor epitaxial wafer according to an embodiment of the present disclosure includes: (A) a step of preparing a semiconductor wafer; and (B) a step of forming a first-conductivity-type semiconductor epitaxial layer containing impurities of the first conductivity type by epitaxially growing a semiconductor on the main surface of the semiconductor wafer. In step (B), the conditions for epitaxial growth are controlled such that in a plane parallel to the main surface of the semiconductor wafer, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of impurities in the semiconductor epitaxial layer.

[0146] In a certain embodiment, if the maximum thickness in the thickness distribution of the semiconductor epitaxial layer is set as Tmax, the minimum thickness is set as Tmin, and the average thickness is set as Tave, then the amplitude VT (%) of the thickness distribution with respect to the average thickness Tave is represented by the following formula (7).

[0147] VT = [{(Tmax - Tmin) / 2} / Tave] × 100 (%) (7)

[0148] If the maximum concentration in the concentration distribution of the semiconductor epitaxial layer is set as Cmax, the minimum concentration is set as Cmin, and the average concentration is set as Cave, then the amplitude VC (%) of the concentration distribution with respect to the average concentration Cave is represented by the following formula (8).

[0149] VC = [{(Cmax - Cmin) / 2} / Cave] × 100 (%) (8)

[0150] In step (B), the conditions for epitaxial growth may also be controlled such that the amplitude VT of the thickness distribution is 5% or more and 20% or less, and the amplitude VC of the concentration distribution is 10% or more and 40% or less.

[0151] In a certain embodiment, in step (B), the conditions for epitaxial growth are controlled such that the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer, for example, satisfy 0.5 ≤ VC / VT ≤ 3.0.

[0152] In a certain embodiment, in step (B), the conditions for epitaxial growth are controlled such that the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer, for example, satisfy 1.0 ≤ VC / VT ≤ 2.5.

[0153] In a certain embodiment, the semiconductor wafer may be a silicon carbide wafer, and the semiconductor epitaxial layer may be a silicon carbide semiconductor layer.

[0154] (First Embodiment)

[0155] Hereinafter, with reference to the drawings, a first embodiment of a semiconductor epitaxial wafer and a semiconductor device will be described by taking a silicon carbide epitaxial wafer and a silicon carbide semiconductor device (MISFET) as an example. Here, a MISFET having an n-type conductivity type as the first conductivity type and a p-type conductivity type as the second conductivity type will be described as an example, but the silicon carbide semiconductor device of the present embodiment may also be a MISFET having a p-type conductivity type as the first conductivity type and an n-type conductivity type as the second conductivity type.

[0156] Figure 1 FIG. is a plan view illustrating a silicon carbide epitaxial wafer 300 of the present embodiment. The silicon carbide epitaxial wafer 300 includes: a silicon carbide wafer 301 of the first conductivity type, and a silicon carbide semiconductor layer (not shown) disposed on the silicon carbide wafer 301. The silicon carbide semiconductor layer is an epitaxial layer formed by epitaxial growth. The diameter of the silicon carbide wafer 301 may be, for example, 3 inches or more, or 6 inches or more. The silicon carbide epitaxial wafer 300 has a plurality of element regions Rc arranged two-dimensionally. The whole or a part of the silicon carbide semiconductor device 200 may be formed in each element region Rc.

[0157] Figure 2is a top view illustrating the silicon carbide semiconductor device 200. Each silicon carbide semiconductor device 200 is composed of a plurality of unit cells (not shown) arranged two-dimensionally. In each silicon carbide semiconductor device 200, on the main surface side of the silicon carbide wafer 301, a source pad 201 and a gate pad 202 are provided above the plurality of unit cells. The source pad 201 and the gate pad 202 are insulated from each other. In addition, in this specification, the region where each unit cell is formed in the silicon carbide semiconductor device 200 may be referred to as the "unit cell formation region Ru".

[0158] Figure 3 is a cross-sectional view illustrating two unit cells 100 in the silicon carbide semiconductor device 200.

[0159] Each unit cell 100 includes: a silicon carbide semiconductor substrate of the first conductivity type (hereinafter simply referred to as "silicon carbide substrate") 101, and a silicon carbide epitaxial layer (drift layer) 110 disposed on the main surface of the silicon carbide substrate 101.

[0160] The silicon carbide substrate 101 is a part of the silicon carbide wafer 301. The silicon carbide substrate 101 is, for example, an n + substrate (n + SiC substrate).

[0161] A body region 103 of the second conductivity type is disposed in the silicon carbide epitaxial layer 110. The region of the silicon carbide epitaxial layer 110 where the body region 103 is not disposed is a drift region 102 of the first conductivity type. The region 120 sandwiched between two adjacent body regions 103 in the surface portion of the drift region 102 functions as a JFET region. In the present embodiment, the drift region 102 is of the n - type, and the body region 103 is of the p type. The impurity concentration and thickness of the drift region 102 can be appropriately changed according to the withstand voltage required for the semiconductor device.

[0162] In the present embodiment, although the first conductivity type is the n type and the second conductivity type is the p type, the n type and the p type may be interchanged with each other. In addition, the superscript "+" or "-" mark in the symbol of "n + " or "n - " indicates the relative concentration of the dopant. "n + " means that the n-type impurity concentration is higher than that of "n", and "n - " means that the n-type impurity concentration is lower than that of "n".

[0163] A source region 104 of the first conductivity type (here, the n + type) is disposed in the body region 103. In addition, a second conductivity type (here, the p +The contact region 105 of the (type). The contact region 105 is formed to reduce the contact resistance between the body region 103 and the source electrode 109. Additionally, the contact region 105 may not be formed. In this case, a part of the body region 103 is configured to be directly connected to the source electrode 109.

[0164] A source electrode 109 is provided on the source region 104. The source electrode 109 is in electrical contact with both the n + -type source region 104 and the p + -type contact region 105.

[0165] A channel layer 106 may also be formed on the silicon carbide epitaxial layer 110 in contact with the body region 103. The channel layer 106 is mainly composed of silicon carbide semiconductor and contains impurities of the first conductivity type. The channel layer 106 is formed to connect the source region 104 and the JFET region 120. The channel layer 106 may be formed, for example, by epitaxial growth on the silicon carbide epitaxial layer 110. A part of the channel layer 106 located between the body region 103 and the gate electrode 108 and in contact with the body region 103 functions as a channel region. Additionally, the channel layer 106 may not be formed.

[0166] A gate insulating film 107 is disposed on the silicon carbide epitaxial layer 110 (on the channel layer 106 in the case where the channel layer 106 is formed). The thickness of the gate insulating film 107 can be appropriately selected according to the voltage applied to the gate electrode 108. A gate electrode 108 is provided on the gate insulating film 107. The gate electrode 108 is disposed to cover at least a part of the surface of the body region 103 located between the JFET region 120 and the source region 104.

[0167] The gate electrodes 108 of the plurality of unit cells 100 are formed integrally and electrically connected to each other, for example. The gate electrode 108 is electrically connected to the Figure 2 gate pad 202 shown. Although not shown, a source wiring is provided on the source electrode 109. The source electrodes 109 of the plurality of unit cells 100 are electrically connected to each other through the source wiring. The source wiring is electrically connected to the Figure 2 source pad 201 shown. On the other hand, a drain electrode 114 is disposed on the back surface of the silicon carbide substrate 101.

[0168] [Relationship between thickness distribution and impurity concentration distribution in the silicon carbide epitaxial layer 110]

[0169] In the silicon carbide epitaxial wafer 300 of the present embodiment, in the plane of the silicon carbide wafer 301, there is a positive correlation between the thickness distribution and the impurity concentration distribution in the silicon carbide epitaxial layer 110. Further, in each of the silicon carbide semiconductor elements 200 formed on the silicon carbide epitaxial wafer, in the plane of the silicon carbide substrate 101, there is a positive correlation between the thickness distribution and the impurity concentration distribution in the silicon carbide epitaxial layer 110.

[0170] The so-called "positive correlation" means, for example, when taking two points a and b with different thicknesses of the silicon carbide epitaxial layer 110 in a plane parallel to the silicon carbide wafer 301 or the silicon carbide substrate 101, and setting the thicknesses of the silicon carbide epitaxial layer 110 at points a and b as Da and Db respectively, and setting the concentrations of the first conductivity type impurities in the silicon carbide epitaxial layer 110 as Ca and Cb respectively, it refers to the case where Ca > Cb when Da > Db, or Ca < Cb when Da < Db.

[0171] If the silicon carbide epitaxial layer 110 is thick, the breakdown voltage and the drift resistance become high. If the impurity concentration of the silicon carbide epitaxial layer 110 is high, the breakdown voltage and the drift resistance become low. Therefore, if the impurity concentration is increased at the point where the silicon carbide epitaxial layer 110 is thick among two points a and b in the plane so as to be higher than the other point, the variation amounts of the breakdown voltage and the drift resistance between the two points a and b caused by the thickness distribution are compensated by the variation amounts between the two points a and b caused by the impurity concentration distribution. As a result, the difference (absolute value) in the breakdown voltage and the difference (absolute value) in the drift resistance between the two points a and b can be reduced.

[0172] Thus, according to the present embodiment, in the silicon carbide epitaxial wafer 300 or the silicon carbide semiconductor element 200, the variation amounts of the breakdown voltage and the drift resistance caused by the thickness distribution of the silicon carbide epitaxial layer 110 and the variation amounts of the breakdown voltage and the drift resistance caused by the impurity concentration distribution of the silicon carbide epitaxial layer 110 can be offset. Therefore, the deviation of the element characteristics due to the in-plane distribution of the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 can be reduced. In addition, the "offset" mentioned here may also mean that the variation amounts of the breakdown voltage and the drift resistance caused by the thickness distribution of the silicon carbide epitaxial layer 110 and the variation amounts of the breakdown voltage and the drift resistance caused by the impurity concentration distribution of the silicon carbide epitaxial layer 110 are not completely eliminated. As long as one of these parameters is compensated by the other and the result is that the total variation amount of the breakdown voltage and the total variation amount of the drift resistance become smaller. In the present embodiment, even when the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 have a relatively large in-plane distribution (the amplitude VT, VB of the distribution described later is 5% or more), the in-plane deviation of the element characteristics can be reduced.

[0173] In the past, as shown in reference to Figure 17A 、 Figure 17BAs described above, in device design, sometimes a relatively large margin is set in consideration of the in-plane deviation of element characteristics. For example, in order to ensure breakdown voltage over the entire surface of the silicon carbide wafer, sometimes the impurity concentration of the silicon carbide epitaxial layer is set low or the thickness is set large, and the on-resistance Ron may increase. In contrast, in the present embodiment, since the in-plane deviation of element characteristics can be reduced, the margin can be decreased. Therefore, it is possible to ensure a given breakdown voltage while suppressing an increase in the on-resistance Ron. Since the on-resistance Ron can be reduced, it is possible to increase the current and reduce the chip size of the silicon carbide semiconductor element 200, and the device cost can be reduced.

[0174] Figures 4A to 4C These are schematic views illustrating the thickness and impurity concentration distributions of the silicon carbide epitaxial layer 110 on a straight line passing through the center of the silicon carbide epitaxial wafer 300, respectively. Figure 5 It is a schematic view illustrating the thickness and impurity concentration distributions of the silicon carbide epitaxial layer 110 on a straight line passing through the center of the silicon carbide semiconductor element 200.

[0175] It may also be as Figure 4A As illustrated, in the plane of the silicon carbide wafer 301, the thickness of the silicon carbide epitaxial layer 110 has a concentric circular distribution that is smaller in the central portion than in the peripheral portion, and the impurity concentration of the silicon carbide epitaxial layer 110 has a concentric circular distribution that is lower in the central portion than in the peripheral portion. In this specification, the shape of the concentric circular distribution that is lower in the central portion than in the peripheral portion is referred to as "concave". In this example, the minimum thickness Tmin and the minimum concentration Cmin are located near the central portion of the silicon carbide wafer, and the maximum thickness Tmax and the maximum concentration Cmax are located near the peripheral portion of the silicon carbide wafer.

[0176] It may also be as Figure 4B As shown, in the plane of the silicon carbide wafer 301, the thickness of the silicon carbide epitaxial layer 110 has a concentric circular distribution that is larger in the central portion than in the peripheral portion, and the impurity concentration of the silicon carbide epitaxial layer 110 has a concentric circular distribution that is higher in the central portion than in the peripheral portion. In this specification, the shape of the concentric circular distribution that is higher in the central portion than in the peripheral portion is referred to as "convex". In this example, the minimum thickness Tmin and the minimum concentration Cmin are located near the peripheral portion of the silicon carbide wafer, and the maximum thickness Tmax and the maximum concentration Cmax are located near the central portion of the silicon carbide wafer.

[0177] The distributions of the thickness and the impurity concentration may not be concentric circular. In the plane of the silicon carbide wafer 301, as long as there is at least one direction in which the thickness distribution and the impurity concentration distribution of the silicon carbide epitaxial layer 110 have a positive correlation. For example, as Figure 4CAs shown, the impurity concentration of the silicon carbide epitaxial layer 110 has a distribution that decreases from one end e1 toward the other end e2, and the silicon carbide epitaxial layer 110 has a distribution that thins from the end e1 toward the end e2. That is, the maximum thickness Tmax and the maximum concentration Cmax are near the end e1 of the silicon carbide wafer 301, and the minimum thickness Tmin and the minimum concentration Cmin are near the end e2 of the silicon carbide wafer 301.

[0178] Even in the silicon carbide semiconductor device 200, similarly, as long as there is at least one channel layer 106 in the plane of the silicon carbide substrate 101, the thickness distribution and the impurity concentration distribution only need to have a positive correlation direction. For example, it can also be as Figure 5 shown, the silicon carbide epitaxial layer 110 has a distribution that thins from one end e3 toward the other end e4, and the impurity concentration of the silicon carbide epitaxial layer 110 has a distribution that decreases from the end e3 toward the end e4.

[0179] In this specification, the magnitudes VT and VC (%) of the in-plane distribution relative to the average value represent the thickness distribution and the impurity concentration distribution of the silicon carbide epitaxial layer 110 in the plane of the silicon carbide wafer 301, respectively. If the maximum thickness in the thickness distribution is set as Tmax, the minimum thickness is set as Tmin, and the average thickness is set as Tave, then for example, the magnitude VT (%) of the thickness distribution is represented by the following formula (9).

[0180] VT (%) = [{(Tmax - Tmin) / 2} / Tave] × 100 (%) (9)

[0181] Similarly, if the maximum concentration in the impurity concentration distribution is set as Cmax, the minimum concentration is set as Cmin, and the average concentration is set as Cave, then for example, the magnitude VC (%) of the impurity concentration distribution is represented by the following formula (10).

[0182] VC (%) = [{(Cmax - Cmin) / 2} / Cave] × 100 (%) (10)

[0183] In addition, in the case of a silicon carbide device with a breakdown voltage of, for example, 600V to 3300V, the average concentration Cave of the silicon carbide epitaxial layer 110 is, for example, 3×10 15 / cm 3 or more and 3×10 16 / cm 3 or less. The average thickness Tave of the silicon carbide epitaxial layer 110 is, for example, 4μm or more and 40μm or less.

[0184] In addition, in this specification, the magnitudes of the in-plane deviations with respect to the average value (hereinafter simply referred to as "deviation magnitudes") VB and VD (%) represent the magnitudes of the deviations (in-plane deviations) of the breakdown voltage and the drift resistance between the silicon carbide semiconductor elements 200 formed on the silicon carbide epitaxial wafer 300, that is, between the plurality of element regions Rc. If the maximum value of the breakdown voltage in each of the plurality of element regions Rc is Bmax, the minimum value is Bmin, and the average value is Bave, the deviation magnitude VB of the breakdown voltage is represented by the following formula (11).

[0185] VB(%) = [{(Bmax - Bmin) / 2} / Bave]×100 (%) (11)

[0186] Similarly, if the maximum value of the drift resistance in each of the plurality of element regions Rc is Dmax, the minimum value is Dmin, and the average value is Dave, the deviation magnitude VD of the drift resistance is represented by the following formula (12).

[0187] VD(%) = [{(Dmax - Dmin) / 2} / Dave]×100 (%) (12)

[0188] Preferably, the magnitude VT of the thickness distribution is, for example, 5% or more and 20% or less, and the magnitude VC of the concentration distribution is, for example, 10% or more and 40% or less. If the magnitudes VT and VC of the in-plane distributions of the thickness and the impurity concentration are within the above ranges, respectively, the variation amounts of the breakdown voltage and the drift resistance can be compensated for each other more effectively. As a result, the deviation magnitudes VB and VD of the breakdown voltage and the drift resistance can be reduced. Preferably, the deviation magnitude VB of the breakdown voltage is, for example, 0% or more and 10% or less. Preferably, the deviation magnitude VD of the drift resistance is, for example, 0% or more and 10% or less.

[0189] Here, even if the amplitude VT of the thickness distribution is less than 5% and the amplitude VC of the concentration distribution is less than 10%, the same effect can be obtained. However, in order to suppress the amplitude VT of the thickness distribution to less than 5% and the amplitude VC of the concentration distribution to less than 10%, very strict adjustment and management of the epitaxial growth apparatus are required. In addition, in this case, if the state of the epitaxial growth apparatus changes during the epitaxial growth process, the relationship between the thickness distribution and the impurity concentration distribution of the channel layer 106 may easily change from a positive correlation to a negative correlation, and it may sometimes be difficult to control the correlation. On the other hand, if the amplitude VT of the thickness distribution is set to 5% or more and the amplitude VC of the concentration distribution is set to 10% or more, the relationship between the thickness distribution and the impurity concentration distribution can be controlled with good reproducibility. For example, even when the state of the epitaxial growth apparatus changes during the epitaxial growth process, since the positive correlation between the thickness distribution and the impurity concentration distribution of the channel layer 106 is maintained, the deviation amplitude VB of the breakdown voltage and the deviation amplitude VD of the drift resistance can be more reliably suppressed.

[0190] <Relationship between the amplitude VT of the thickness distribution and the amplitude VC of the impurity concentration distribution>

[0191] By controlling the relationship between the amplitude VT of the thickness distribution and the amplitude VC of the impurity concentration distribution of the silicon carbide epitaxial layer 110, the variation amount of the device characteristics can be further efficiently offset. Regarding the relationship between these distribution amplitudes VT and VC, the research results of the present inventors will be described below.

[0192] Figure 6 It is a graph showing the relationship between the deviation amount (%) from the set value of the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 and the breakdown voltage of the silicon carbide semiconductor device. Figure 6 It is the calculation result using the above formula (1).

[0193] The line Lt in the figure represents the relationship between the deviation amount and the breakdown voltage when the thickness deviates in the direction of decreasing breakdown voltage, that is, when the deviation occurs in the direction of decreasing thickness. The line Lc represents the relationship between the deviation amount and the breakdown voltage when the impurity concentration deviates in the direction of decreasing breakdown voltage, that is, when the deviation occurs in the direction of increasing impurity concentration.

[0194] According to Figure 6 the calculation results shown, the slope of the line Lt is larger (about twice) than the slope of the line Lc, and the variation amount of the breakdown voltage due to the deviation amount of the thickness is larger than the variation amount of the breakdown voltage due to the deviation amount of the impurity concentration.

[0195] Figure 7It is a graph showing the relationship between the ratio VC / VT of the amplitude VC of the impurity concentration distribution to the amplitude VT of the thickness distribution and the deviation amplitude VB of the breakdown voltage. The horizontal axis is the ratio of the amplitude VC of the impurity concentration distribution to the amplitude VT of the thickness distribution (hereinafter referred to as "distribution amplitude ratio") VC / VT when the amplitude VT of the thickness distribution is 10% (constant). Here, for two cases, namely the case where there is a positive correlation between the in-plane distribution of the thickness and the in-plane distribution of the impurity concentration, and the case where there is a negative correlation, the deviation amplitude VB of the breakdown voltage is calculated differently with different distribution amplitude ratios VC / VT.

[0196] As Figure 7 shown by the results, when there is a positive correlation between the in-plane distribution of the thickness and the in-plane distribution of the impurity concentration, the deviation amplitude VB of the breakdown voltage can be reduced compared to the case where there is a negative correlation.

[0197] In the case of a negative correlation, as the distribution amplitude ratio VC / VT increases, the deviation amplitude VB of the breakdown voltage increases. The reason can be considered as follows. When there is a negative correlation between the in-plane distribution of the thickness and the in-plane distribution of the impurity concentration, the absolute value of the change in the breakdown voltage caused by the impurity concentration distribution is added to the absolute value of the change in the breakdown voltage caused by the thickness distribution (here, since the amplitude VT of the thickness distribution is 10% (fixed), it is fixed). Therefore, as the distribution amplitude ratio VC / VT increases (that is, as the amplitude VC of the impurity concentration distribution increases), the change in the breakdown voltage caused by the impurity concentration distribution becomes larger, and as a result, the deviation amplitude VB of the breakdown voltage increases.

[0198] In contrast, when there is a positive correlation between the in-plane distribution of the thickness and the in-plane distribution of the impurity concentration, the change in the breakdown voltage caused by the impurity concentration distribution compensates for the change in the breakdown voltage caused by the thickness distribution (fixed). Therefore, as the distribution amplitude ratio VC / VT increases (that is, as the amplitude VC of the impurity concentration distribution increases), the deviation amplitude VB of the breakdown voltage gradually decreases and becomes the smallest when the distribution amplitude ratio VC / VT is approximately 2. This can be considered because when the distribution amplitude ratio VC / VT is approximately 2, the change in the breakdown voltage caused by the impurity concentration distribution and the change in the breakdown voltage caused by the thickness distribution are effectively compensated (refer to Figure 6 ). If the distribution amplitude ratio VC / VT further increases, the change in the breakdown voltage caused by the impurity concentration distribution becomes excessive with respect to the change in the breakdown voltage caused by the thickness distribution, so the deviation amplitude VB of the breakdown voltage increases.

[0199] Furthermore, as Figure 7From the results shown, there is a positive correlation between the in-plane distribution of the thickness and the in-plane distribution of the impurity concentration. Moreover, by controlling the ratio VC / VT of the distribution amplitudes of the thickness and the impurity concentration to be, for example, 0.5 or more and 3.0 or less (0.5 ≤ VC / VT ≤ 3.0), the deviation amplitude VB of the breakdown voltage can be reduced to 10% or less (6% or less in this calculation example). Furthermore, by controlling the ratio VC / VT of the distribution amplitudes to be, for example, 1.0 or more and 2.5 or less (1.0 ≤ VC / VT ≤ 2.5), the deviation amplitude VB of the breakdown voltage can be further effectively reduced (4% or less in this calculation example). The ratio VC / VT of the distribution amplitudes may also be greater than 1.0 and less than 2.5.

[0200] [Control of the In-Plane Distribution of the Thickness and Impurity Concentration of the Silicon Carbide Epitaxial Layer 110]

[0201] The in-plane distribution of the thickness and the impurity concentration in the silicon carbide epitaxial layer 110 can be controlled according to the epitaxial growth conditions of silicon carbide. Hereinafter, specific examples of the control method for the in-plane distribution of the thickness and the impurity concentration will be described.

[0202] <Epitaxial Growth Apparatus>

[0203] First, an epitaxial growth apparatus for forming the silicon carbide epitaxial layer 110 by epitaxial growth will be described. Here, a horizontal rotation and revolution type epitaxial growth apparatus is used in which a plurality of silicon carbide wafers 301 are arranged horizontally, each silicon carbide wafer 301 revolves, and the silicon carbide wafer 301 itself rotates about the center of the silicon carbide wafer 301.

[0204] Figure 8 is a schematic cross-sectional view showing an example of the epitaxial growth apparatus.

[0205] The epitaxial growth apparatus 700 includes: a reactor (not shown), a susceptor 701 disposed in the reactor, and a gas introduction pipe 703 for supplying a gas 705 containing a source gas and a carrier gas into the reactor. The susceptor 701 holds a plurality of silicon carbide wafers 301. A seal 707 is disposed above the susceptor 701, and the gas introduction pipe 703 is provided, for example, at the center of the seal 707. The susceptor 701 is, for example, disk-shaped. A shaft 702 for rotating the susceptor 701 is provided below the susceptor 701.

[0206] In this example, the silicon carbide wafers 301 are arranged on the susceptor 701 at intervals around the shaft 702. The silicon carbide wafers 301 are placed on a rotatable accessory (not shown) disposed on the susceptor 701.

[0207] When using the epitaxial growth apparatus 700, each silicon carbide wafer 301 can revolve by the rotation of the susceptor 701 and rotate by the rotation of the accessory, and at the same time, epitaxial growth of SiC can be performed on the silicon carbide wafer 301 (rotation-revolution type).

[0208] The gas 705 introduced from the gas inlet pipe 703 includes: a source gas containing a silicon-based gas (e.g., silane gas), a carbon-based gas (e.g., propane gas), and an impurity gas (e.g., nitrogen gas); and a carrier gas (e.g., hydrogen gas). The gas 705 is supplied from the gas inlet pipe 703 into the reactor and decomposes / react while moving from the central part of the susceptor 701 toward the peripheral part. Thus, a silicon carbide epitaxial layer containing nitrogen as an impurity is formed on each silicon carbide wafer 301.

[0209] <Relationship between epitaxial growth conditions and in-plane distribution of thickness and impurity concentration>

[0210] When using Figure 8 In the case of forming a silicon carbide epitaxial layer using the rotation-revolution type epitaxial growth apparatus 700 as shown, the in-plane distribution of the thickness or impurity concentration of the silicon carbide epitaxial layer 110 varies according to the epitaxial growth conditions. It is considered that this is because, according to the epitaxial growth conditions, the position where the decomposition / reaction of the source gas preferentially occurs in the reactor of the epitaxial growth apparatus changes, and as a result, the schematic film formation distribution in the plane of the susceptor 701 changes. The epitaxial growth conditions include, for example, parameters such as carrier gas flow rate, supply ratio of reaction gases, growth pressure, and growth temperature (hereinafter referred to as "epitaxial control factors").

[0211] Hereinafter, the research results of the present inventors on the relationship between epitaxial growth conditions and the in-plane distribution of thickness and impurity concentration will be described.

[0212] · Research Example 1 (Relationship between carrier gas flow rate and thickness distribution)

[0213] Since the film formation distribution in the reactor and the thickness distribution of the silicon carbide epitaxial layer 110 were studied when increasing or decreasing the carrier gas flow rate, which is one of the epitaxial control factors, the results will be described.

[0214] Figure 9 It is a diagram illustrating the film formation distributions d1 and d2 in the reactor of the epitaxial growth apparatus 700. The film formation distribution d1 illustrates the film formation distribution in the reactor when the carrier gas flow rate is increased, and the film formation distribution d2 illustrates the film formation distribution in the reactor when the carrier gas flow rate is decreased.

[0215] If the carrier gas flow rate is decreased, the supply rate of the gas 705 from the gas introduction pipe 703 to the reactor becomes smaller. Therefore, the raw material gas supplied into the reactor reaches the decomposition temperature at a position closer to the supply port of the gas introduction pipe 703 and undergoes reaction / decomposition. In this example, the peak of the film formation distribution d2 (the point with the highest growth rate), for example, is located on the more upstream side (the supply port side of the gas introduction pipe 703) with respect to the direction of flow of the gas 705 as compared to the silicon carbide wafer 301. On the other hand, if the carrier gas flow rate is increased, the supply rate of the gas 705 becomes larger. Therefore, the raw material gas supplied into the reactor reaches the decomposition temperature on the more downstream side and undergoes reaction / decomposition. Thus, the position of the peak in the film formation distribution d1 is shifted to the more downstream side (here, the side wall of the reactor) with respect to the direction of flow of the gas 705 as compared to the position of the peak in the film formation distribution d2. In this example, the peak of the film formation distribution d1 is located, for example, near the central portion of the silicon carbide wafer 301.

[0216] The present inventors adjusted the carrier gas flow rate in order to obtain the film formation distributions d1 and d2 as described above, formed a silicon carbide epitaxial layer 110 on a 6-inch (about 150 mm) diameter silicon carbide wafer 301, and measured the in-plane distribution of its thickness.

[0217] Here, with respect to the thickness of the silicon carbide epitaxial layer 110, measurements were made at five points at intervals along a straight line passing through the center of the silicon carbide wafer 301, from the upstream end e1 to the downstream end e2 of the gas 705. The measurement points are represented by the distance x (mm) from the center of the silicon carbide wafer 301. The distance x is set to be positive in the direction from the center of the silicon carbide wafer 301 toward the downstream end e2.

[0218] The measurement results of the thickness at each measurement point are shown in Table 1 and Figure 10 . Further, based on the measurement results, the maximum thickness Tmax, minimum thickness Tmin, average thickness Tave, the amplitude VT of the thickness distribution with respect to the average thickness, and the shape of the in-plane distribution were obtained. The results are shown together in Table 1.

[0219] [Table 1]

[0220]

[0221] Based on the results shown in Table 1 and Figure 10 it was confirmed that by adjusting the film formation distribution in the reactor according to epitaxial control factors such as the carrier gas flow rate, it is possible to control the shape and amplitude VT of the thickness distribution of the silicon carbide epitaxial layer 110. Further, it was found that by performing epitaxial growth while rotating the silicon carbide wafer 301, it is possible to control the in-plane distributions of the thickness and impurity concentration of the silicon carbide epitaxial layer 110 to be concentric (concave or convex).

[0222] For example, if the epitaxial control factors are adjusted such that the peak of the film formation distribution is located near the central portion of the silicon carbide wafer 301 (film formation distribution d1), and epitaxial growth is performed while the silicon carbide wafer 301 is rotated, the in-plane distribution of the thickness can be controlled to be convex. Alternatively, the epitaxial control factors can be adjusted such that the peak of the film formation distribution is located at the peripheral portion of the silicon carbide wafer 301 or outside the silicon carbide wafer 301 (film formation distribution d2), and epitaxial growth is performed while the silicon carbide wafer 301 is rotated. In this case, although it also depends on the shape of the film formation distribution, the in-plane distribution of the thickness can be controlled to be concave.

[0223] In the above, an example in which the silicon carbide wafer 301 is rotated during epitaxial growth has been described, but the silicon carbide wafer 301 may not be rotated. For example, in the epitaxial growth apparatus 700, instead of rotating the accessory on which the silicon carbide wafer 301 is placed, only the susceptor 701 may be rotated (revolution type).

[0224] The results of measuring the in-plane distribution of the thickness of the silicon carbide epitaxial layer 110 formed under the same conditions as above without rotating the silicon carbide wafer 301 are shown in Table 2 and Figure 11 .

[0225] [Table 2]

[0226]

[0227] From the results shown in Table 2 and Figure 11 , it can be seen that, for example, when the epitaxial control factors are adjusted such that the peak of the film formation distribution is located near the central portion of the silicon carbide wafer 301 (film formation distribution d1), even without rotating the silicon carbide wafer 301, the in-plane distribution of the thickness can be controlled to a shape close to convex. In addition, it can be seen that when the epitaxial control factors are adjusted such that the peak of the film formation distribution is located at the peripheral portion of the silicon carbide wafer 301 or outside the silicon carbide wafer 301 (film formation distribution d2) and the silicon carbide wafer 301 is not rotated, the thickness in the plane of the silicon carbide wafer 301 decreases from one end of the silicon carbide wafer 301 (in this example, the upstream end e1) to the other end (in this example, the downstream end e2). Thus, even without rotating the silicon carbide wafer 301, it is possible to control such that the thickness or impurity concentration of the silicon carbide epitaxial layer 110 has a distribution that increases or decreases from one end of the silicon carbide wafer 301 to the other end.

[0228] · Study Example 2 (Relationship between epitaxial control factors and thickness and impurity concentration distributions)

[0229] The present inventor investigated how the thickness of the silicon carbide epitaxial layer and the in-plane distribution of the impurity concentration changed according to each epitaxial control factor by the same method as in the above-described Research Example 1. Here, epitaxial growth was performed while rotating the silicon carbide wafer 301.

[0230] First, under the standard conditions of the epitaxial growth apparatus 700 used, a silicon carbide epitaxial layer was formed, and the in-plane distribution of its thickness and impurity concentration was determined. The obtained distribution was set as the "reference in-plane distribution".

[0231] Next, a silicon carbide epitaxial layer was formed by varying one epitaxial control factor from the standard value in the positive or negative direction. The thickness of the obtained silicon carbide epitaxial layer and the in-plane distribution of the impurity concentration were measured, and the change with respect to the reference in-plane distribution was investigated. The change in the in-plane distribution was also investigated in the same manner for other epitaxial control factors.

[0232] The results are shown in Table 3. In Table 3, the "(-) condition" and "(+) condition" of each epitaxial control factor are values different from the standard value in the positive and negative directions, respectively. In addition, the "change in in-plane distribution" is the change with respect to the reference in-plane distribution. When a change occurred in the direction where the wafer peripheral portion was lower than the central portion (convex shape) with respect to the reference in-plane distribution by changing a certain epitaxial control factor, it was recorded as "convex", when a change occurred in the direction where the wafer peripheral portion was higher than the central portion (concave shape), it was recorded as "concave", and when there was no change in the relationship between the wafer peripheral portion and the central portion, it was recorded as "no change".

[0233] In addition, the in-plane distribution of the impurity concentration is greatly affected by the temperature distribution generated in the plane of the silicon carbide wafer 301. This is because the decomposition temperatures of the source gases (for example, silane gas, propane gas, nitrogen gas) are different, so the effective C / Si ratio in the plane of the silicon carbide wafer 301 changes according to the temperature distribution, and the intake rate of the impurity gas taken into the silicon carbide epitaxial layer 110 changes. As factors affecting the temperature distribution of the silicon carbide wafer 301, in addition to the epitaxial control factors, warping of the silicon carbide wafer 301 itself, the material and shape of the susceptor holding the silicon carbide wafer 301, etc. can be cited. Therefore, depending on the type of source gas and the apparatus used, the direction of the change in the in-plane distribution of the impurity concentration caused by each epitaxial control factor may be different from the experimental results shown in Table 3.

[0234] [Table 3]

[0235]

[0236] Here, slm is a unit of flow rate. 1 slm represents the flow rate of a gas flowing one liter in one minute under standard conditions (0 °C, one atmosphere).

[0237] (1) Growth temperature (temperature of the silicon carbide wafer 301 in epitaxial growth)

[0238] If the growth temperature is set high (for example, exceeding 1500 °C and being 1600 °C or less, here it is 1585 °C), the thickness of the silicon carbide epitaxial layer 110 and the in-plane distribution of the impurity concentration both change in such a way that they are smaller (concave shape) in the central part of the silicon carbide wafer 301 than in the peripheral part. Conversely, if the growth temperature is set low (for example, 1400 °C or more and 1500 °C or less, here it is 1470 °C), the thickness of the silicon carbide epitaxial layer 110 and the in-plane distribution of the impurity concentration both change in such a way that they are larger (convex shape) in the central part of the silicon carbide wafer 301 than in the peripheral part.

[0239] Regarding the change in the in-plane distribution of the thickness, it is considered that due to the in-plane distribution of the growth temperature, the position where the raw material gas decomposes / react s preferentially changes in the reactor of the epitaxial growth apparatus (that is, the film formation distribution changes), thereby resulting in a change in the in-plane distribution of the thickness. Specifically, if the growth temperature is lowered, the decomposition / react ion of the raw material gas becomes slower, and the peak of the film formation distribution moves downstream with respect to the direction of flow of the gas 705. Thus, for example, like Figure 9 the film formation distribution d1 illustrated, a film formation distribution having a peak near the central part of the wafer can be obtained. By adjusting to such a film formation distribution and performing epitaxial growth while rotating the silicon carbide wafer 301, it is possible to change the in-plane distribution of the thickness of the silicon carbide epitaxial layer 110 in a convex shape.

[0240] On the other hand, if the growth temperature is raised, the decomposition / react ion of the raw material gas becomes faster, so the peak of the film formation distribution moves upstream. Thus, for example, like Figure 9 the film formation distribution d2 illustrated, a film formation distribution having a peak on the upstream side of the upstream end e1 of the wafer can be obtained. By adjusting to such a film formation distribution and performing epitaxial growth while rotating the silicon carbide wafer 301, it is possible to change the in-plane distribution of the thickness of the silicon carbide epitaxial layer 110 in a concave shape.

[0241] Regarding the in-plane distribution of the impurity concentration and its relationship with the growth temperature (substrate temperature), since the decomposition temperatures of the respective source gases (e.g., silane gas, propane gas, nitrogen gas) are different, it cannot be explained in a general way, but it can be considered as follows. If the temperature distribution within the silicon carbide wafer 301 changes due to different growth temperatures (and other main reasons), the effective C / Si ratio within the silicon carbide wafer 301 changes, and thus the in-plane distribution of the intake rate of the impurity gas incorporated into the silicon carbide epitaxial layer 110 changes. As a result, it can be considered that the in-plane distribution of the impurity concentration can change. In the experimental results of this time, regarding the in-plane distribution of the impurity concentration, if the growth temperature is low, it changes in a convex shape, and if the growth temperature is high, it changes in a concave shape.

[0242] (2) Growth pressure (pressure within the chamber during epitaxial growth)

[0243] If the growth pressure is set high (here, 200 hPa), the impurity concentration of the silicon carbide epitaxial layer 110 changes in such a way that it is smaller (concave shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. Conversely, if the growth pressure is set low (here, 100 hPa), the impurity concentration of the silicon carbide epitaxial layer 110 changes in such a way that it is larger (convex shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. This is because the decomposition pressures of the respective source gases (e.g., silane gas, propane gas, nitrogen gas) are different. Therefore, if the growth pressure is different, the effective C / Si ratio changes in the plane, and the in-plane distribution of the intake amount of the impurity gas changes.

[0244] On the other hand, even if the growth pressure is changed, the in-plane distribution of the thickness hardly changes. In the experimental results of this case, the change amount is small, but if the growth pressure is high, it changes in a convex shape, and if the growth pressure is low, it changes in a concave shape. It is considered that this is because within the range of the growth pressure from 100 hPa to 200 hPa, the film formation distribution within the reactor of the epitaxial growth apparatus 700 is not changed significantly.

[0245] (3) Carrier gas flow rate (pressure within the chamber during epitaxial growth)

[0246] If the carrier gas flow rate is increased (here, 180 slm), the thickness of the silicon carbide epitaxial layer 110 changes in such a way that it is larger (convex shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. Conversely, if the carrier gas flow rate is decreased (here, 130 slm), the thickness of the silicon carbide epitaxial layer 110 all changes in such a way that it is smaller (concave shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. Regarding the mechanism, refer to Figures 9 to 11 As described above.

[0247] On the other hand, even if the carrier gas flow rate is changed, the in-plane distribution of the impurity concentration hardly changes. Although the change amount is small, if the carrier gas flow rate is increased, it can change in a concave shape, and if the carrier gas flow rate is decreased, it can change in a convex shape. This is considered because even if the carrier gas flow rate is changed, the effective C / Si ratio does not change, and the in-plane distribution of the intake amount of nitrogen as the impurity gas does not change.

[0248] (4) C / Si ratio in the source gas

[0249] If the C / Si ratio is set high (here it is 1.4), the impurity concentration of the silicon carbide epitaxial layer 110 changes in such a way that it is smaller (concave shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. Conversely, if the C / Si ratio is set low (here it is 1.1), the impurity concentration of the silicon carbide epitaxial layer 110 changes in such a way that it is larger (convex shape) at the central part of the silicon carbide wafer 301 than at the peripheral part. This is considered because due to the balance between the amount of C (carbon) supplied (for example, the supply amount of propane gas) and the amount of C supplied from the workpiece in the reactor (usually a carbon-based workpiece), the effective C / Si ratio of the silicon carbide wafer 301 changes, and thus the in-plane distribution of the intake amount of the impurity gas (nitrogen) changes.

[0250] On the other hand, even if the C / Si ratio is changed, the in-plane distribution of the thickness does not change. When the C / Si ratio is 1 or more, C (carbon) is in a state of being supplied in excess, and the supply of Si (silicon) becomes rate-limiting. Therefore, the film formation distribution does not depend on the amount of C (for example, the supply amount of propane gas). Since the film formation distribution does not change, it can be considered that the in-plane distribution of the thickness has not changed.

[0251] In addition, the epitaxial control factors are not limited to the factors illustrated in Table 3. Furthermore, since multiple epitaxial control factors affect each other, the shape of the in-plane distribution is not determined based on the value of a single epitaxial control factor. For example, it is considered that due to the balance between the temperature distribution in the wafer plane and the source gas flow rate, the C / Si ratio in the source gas, etc., the effective C / Si ratio in the wafer plane changes, so that the in-plane distributions of the thickness and the impurity concentration can change in a concave shape or a convex shape. Furthermore, these in-plane distributions can also be changed according to the structure of the epitaxial growth apparatus used (whether the wafer rotates, the positional relationship between the source gas supply port and the wafer, the shape and material of the workpiece in the reactor, etc.).

[0252] <Adjustment method of epitaxial control factors>

[0253] In the present embodiment, by adjusting the epitaxial control factors, a given in-plane distribution of the thickness or the impurity concentration of the silicon carbide epitaxial layer 110 is generated. Hereinafter, the adjustment method of the epitaxial control factors will be described.

[0254] (Process A)

[0255] First, using the epitaxial growth apparatus 700 employed, an epitaxial layer is formed on a silicon carbide wafer under the standard epitaxial growth conditions of the apparatus. Thereby, the thickness distribution and the impurity concentration distribution (in-plane distribution of the reference plane) within the silicon carbide wafer surface are obtained.

[0256] (Step B)

[0257] Next, the epitaxial control factors are adjusted such that one of the thickness distribution and the impurity concentration distribution has a desired shape (e.g., convex or concave), and the amplitude of its distribution falls within a given range.

[0258] (Step C)

[0259] Then, the epitaxial control factors are adjusted such that the other of the thickness distribution and the impurity concentration distribution has a positive correlation with the in-plane distribution of the one controlled in the above step (B), and the amplitude of its distribution falls within a given range. At this time, it is preferable to adjust only the epitaxial control factors that are likely to affect the in-plane distribution to be controlled. For example, when controlling the thickness distribution in this step, it is preferable to adjust the carrier gas flow rate. When controlling the impurity concentration distribution in this step, it is preferable to adjust the C / Si ratio in the source gas, the growth pressure, or both.

[0260] (Step D)

[0261] Finally, the above epitaxial control factors or other epitaxial growth conditions are finely adjusted such that the amplitude VT of the thickness distribution and the amplitude VC of the impurity concentration distribution respectively fall within given ranges.

[0262] <Examples and Comparative Examples>

[0263] Since silicon carbide epitaxial wafers of examples and comparative examples were fabricated and the in-plane deviation of the silicon carbide epitaxial layer 110 was evaluated, this method and the results are described.

[0264] As an example, using the above-described method for adjusting epitaxial control factors, a silicon carbide epitaxial wafer was fabricated by forming a silicon carbide epitaxial layer 110 on a silicon carbide wafer 301 with a diameter of 6 inches (about 150 mm). The design values of the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 were set to 9 μm and 1×10 16 / cm 3 . Further, the growth temperature during the epitaxial growth of the silicon carbide epitaxial layer 110 was set to 1530 °C, the growth pressure was set to 200 hPa, the carrier gas (H2 gas) flow rate was set to 130 slm, and the supply ratio (C / Si ratio) of the source gas was set to 1.30.

[0265] In addition, as a comparative example, a silicon carbide epitaxial wafer of the comparative example was fabricated by the same method as in the example, except that the flow rate of the carrier gas (H2 gas) was set to 180 slm and the supply ratio of the source gas (C / Si ratio) was set to 1.20.

[0266] Next, in the example and the comparative example, the thickness distribution and the impurity concentration distribution of the silicon carbide epitaxial layer 110 in the 301 plane of the silicon carbide wafer were measured. Here, as Figure 12 shown, along a straight line passing through the center of the silicon carbide wafer 301, the thickness and the impurity concentration at 17 points from one end e1 to the other end e2 were measured, and the distribution was obtained.

[0267] Figure 13A is a diagram showing the in-plane distribution of the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 in the example. In addition, in Figure 13A , "●" represents the thickness of the silicon carbide epitaxial layer 110 at a given distance from the center of the silicon carbide wafer 301. In addition, in Figure 13A , "○" represents the impurity concentration of the silicon carbide epitaxial layer 110 at a given distance from the center of the silicon carbide wafer 301. Figure 13B is a diagram showing the in-plane distribution of the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 in the comparative example. In addition, in Figure 13B , "▲" represents the thickness of the silicon carbide epitaxial layer 110 at a given distance from the center of the silicon carbide wafer 301. In addition, in Figure 13A , "○" represents the impurity concentration of the silicon carbide epitaxial layer 110 at a given distance from the center of the silicon carbide wafer 301.

[0268] As Figure 13A shown, in the silicon carbide epitaxial wafer of the example, both the thickness and the impurity concentration of the silicon carbide epitaxial layer 110 have a concave in-plane distribution. That is, these in-plane distributions have a positive correlation. On the other hand, as Figure 13B shown, in the silicon carbide epitaxial wafer of the comparative example, the in-plane distribution of the thickness of the silicon carbide epitaxial layer 110 is convex, and the in-plane distribution of the impurity concentration is concave, and these in-plane distributions have a negative correlation.

[0269] In addition, in either the example or the comparative example, the amplitude VT of the thickness distribution of the silicon carbide epitaxial layer 110 is 10%, and the amplitude VC of the impurity concentration distribution is 20%.

[0270] Next, the deviation amplitudes VB and VD of the breakdown voltage and the drift resistance of the silicon carbide semiconductor device were obtained when semiconductor devices (SiC-MISFETs) were formed using the silicon carbide epitaxial wafers of the example and the comparative example. Here, based on Figure 13A and Figure 13BBased on the measured results shown and the aforementioned formulas (1) and (2), the maximum values Bmax and Dmax, minimum values Bmin and Dmin, and average values Bave and Dave of the breakdown voltage and drift resistance in the plane of the silicon carbide wafer are calculated respectively. In addition, the difference ΔB (= Bmax - Bmin) between the maximum and minimum values of the breakdown voltage, the deviation range VB (%) of the breakdown voltage (= (ΔB / 2) / Bave × 100), the difference ΔD = (Dmax - Dmin) between the maximum and minimum values of the drift resistance, and the deviation range VD (%) of the drift resistance (= (ΔD / 2) / Dave × 100) are obtained respectively.

[0271] The average values Bave and Dave of the breakdown voltage and drift resistance and the deviation ranges VB and VD are shown in Table 4. In addition, the difference ΔB between the maximum and minimum values of the breakdown voltage in the examples and comparative examples is shown in Figure 14A . The difference ΔD between the maximum and minimum values of the drift resistance in the examples and comparative examples is shown in Figure 14B .

[0272] [Table 4]

[0273]

[0274] In the comparative examples, the deviation ranges VB and VD of the breakdown voltage and drift resistance of the semiconductor element both exceed 10%. It is considered that this is because there is a negative correlation between the impurity concentration distribution and the thickness distribution of the silicon carbide epitaxial layer 110, and the change amounts (absolute values) of the breakdown voltage and drift resistance caused by the thickness distribution and the change amounts (absolute values) of the breakdown voltage and drift resistance caused by the impurity concentration distribution are added together. As a result, the differences ΔB and ΔD between the maximum and minimum values of the breakdown voltage and drift resistance and the deviation ranges VB and VD increase.

[0275] In contrast, in the examples, compared with the comparative examples, the differences ΔB and ΔD between the breakdown voltage and drift resistance and the deviation ranges VB and VD are reduced. The deviation ranges VB and VD in the examples are both 10% or less. It is considered that this is because there is a positive correlation between the impurity concentration distribution and the thickness distribution of the silicon carbide epitaxial layer 110, and the change amounts of the breakdown voltage and drift resistance caused by the thickness distribution and the change amounts of the breakdown voltage and drift resistance caused by the impurity concentration distribution compensate each other.

[0276] <Manufacturing method of silicon carbide semiconductor device 200>

[0277] Next, the manufacturing method of the silicon carbide semiconductor device 200 of the present embodiment will be described with reference to the drawings.

[0278] Figures 15A to 15F is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device 200. Figure 15AA silicon carbide epitaxial wafer 300 is shown. Figures 15B to 15F One unit cell formation region Ru in the silicon carbide epitaxial wafer 300 is shown.

[0279] First, if Figure 15A As shown, a silicon carbide epitaxial layer 110 of the first conductivity type (n type) is grown on a main surface of a silicon carbide wafer 301 by epitaxial growth, thereby obtaining a silicon carbide epitaxial wafer 300 .

[0280] As the silicon carbide wafer 301, for example, a substrate with a 4H-SiC (0001) plane tilted 4° toward the [11-20] direction is used. The diameter of the silicon carbide wafer 301 is, for example, 6 inches (about 150 mm). The silicon carbide wafer 301 is n-type, and the impurity concentration in the silicon carbide wafer 301 is, for example, 5×10 18 ~1×10 19 cm -3 degree.

[0281] The silicon carbide epitaxial layer 110 is formed, for example, using the reference Figure 8 The aforementioned rotation-revolution type or revolution type epitaxial growth apparatus. In addition, as described above, the epitaxial growth conditions (epitaxial control factors) are set so that the silicon carbide epitaxial layer 110 can have a desired thickness distribution and impurity concentration distribution.

[0282] First, a silicon carbide wafer 301 is placed in a reactor, and the temperature of the silicon carbide wafer 301 is increased before epitaxial growth. During this temperature increase process, the raw material gas is not supplied into the reactor, and the silicon carbide wafer 301 is heated in an atmosphere containing at least hydrogen. At the time when the temperature of the silicon carbide wafer 301 (wafer temperature) reaches a given growth temperature (here 1600°C), the supply of a mixed gas of raw material gas and carrier gas is started. The raw material gas includes, for example, monosilane gas, propane gas, and nitrogen as an impurity gas. In this way, a silicon carbide epitaxial layer 110 having a thickness of, for example, 5 to 100 μm (for example, 9 μm) is formed on the main surface of the silicon carbide wafer 301. The n-type impurity concentration of the silicon carbide epitaxial layer 110 is set to be lower than the n-type impurity concentration of the silicon carbide wafer 301, for example, 1×10 14 cm -3 Above and 1×10 17 cm -3 Below (for example 1×10 16 cm -3 ). Although not shown in the figure, a 1×10 17 cm -3 Above and 1×10 19 cm-3 The following buffer layer (e.g., 1×10 18 cm -3 ).

[0283] Then, as shown Figure 15B , in the unit cell formation region Ru, p-type or n-type impurity ions are implanted into the selected region within the silicon carbide epitaxial layer 110, thereby forming the body region 103, the source region 104, and the contact region 105.

[0284] Specifically, a mask (not shown) made of, for example, SiO2 is formed on the silicon carbide epitaxial layer 110, and p-type impurity ions (e.g., Al ions or B ions) are implanted into the region where the mask is not formed to form the body region 103. The width of the body region 103 is, for example, 5 to 10 μm. The concentration of the p-type impurity in the body region 103 is, for example, 1×10 17 or more and 1×10 20 cm -3 or less.

[0285] Furthermore, n-type impurity ions (e.g., nitrogen ions) are implanted into the contact region 105 to form the source region 104. The concentration of the n-type impurity in the source region 104 is, for example, 1×10 18 cm -3 or more and 1×10 21 cm -3 or less.

[0286] In addition, p-type impurity ions are implanted into the body region 103 to form the contact region 105. The concentration of the p-type impurity in the contact region 105 is, for example, 1×10 19 cm -3 or more and 1×10 21 cm -3 or less.

[0287] After the ion implantation, the mask is removed, and activation annealing is performed. The activation annealing is performed, for example, at a temperature of about 1700°C for about 30 minutes in an inert atmosphere.

[0288] Next, as shown Figure 15C , a channel layer 106 can also be formed by epitaxial growth on the entire surface of the silicon carbide epitaxial layer 110 including the body region 103, the source region 104, and the contact region 105. In this embodiment, nitrogen gas is supplied as the impurity gas to form the channel layer 106. The average concentration of the channel layer 106 is, for example, about 1×10 18 / cm 3 or more and 1×10 19 / cm 3Next, the average thickness of the channel layer 106 is, for example, 20 nm or more and 100 nm or less. Alternatively, the channel layer 106 may not be formed.

[0289] Next, as Figure 15D shown, for example, the surface portion of the channel layer 106 is thermally oxidized to form a gate insulating film 107 on the surface of the silicon carbide epitaxial layer 110. The gate insulating film 107 may also be an oxide film, a nitride oxide film, or a stacked film of these films. Here, as the gate insulating film 107, for example, the surface of the silicon carbide epitaxial layer 110 is thermally oxidized at a temperature of 1100 to 1400 °C to form a thermally oxidized (SiO2) film. The thickness of the gate insulating film 107 is, for example, 40 nm or more and 80 nm or less. Alternatively, an SiO2 film may be formed on the silicon carbide epitaxial layer 110 by CVD instead of the thermally oxidized film.

[0290] Next, as Figure 15E shown, a gate electrode 108 is formed on the gate insulating film 107. The gate electrode 108 can be formed, for example, by depositing phosphorus-doped polysilicon (poly-Si film) on the gate insulating film 107 using an LPCVD (low pressure chemical vapor deposition) apparatus.

[0291] Next, as Figure 15F shown, a source electrode 109 and a drain electrode 114 are formed.

[0292] First, for example, an interlayer insulating layer 111 is deposited by CVD so as to cover the gate electrode 108. The interlayer insulating layer 111 may also be composed of SiO2. Then, an opening for the source electrode is formed in the interlayer insulating layer 111. Next, a source electrode 109 is formed in the opening of the interlayer insulating layer 111. Here, first, a nickel film having a thickness of, for example, about 50 to 100 nm is formed in the opening, and heat treatment is performed at, for example, 950 °C for 5 minutes in an inert atmosphere to react nickel with the silicon carbide surface. Thereby, a source electrode 109 made of nickel silicide is formed. The source electrode 109 forms an ohmic contact with a part of the source region 104 and the contact region 105. In addition, a drain electrode 114 is formed on the back surface of the silicon carbide substrate 101. For example, titanium having a thickness of about 150 nm is deposited on the back surface of the silicon carbide substrate 101, and the same heat treatment is performed to react titanium with the silicon carbide surface. Thereby, a drain electrode 114 made of titanium silicide is formed. The drain electrode 114 forms an ohmic contact with the silicon carbide substrate 101. Then, a source wiring 112 that is connected to the source electrode 109 in the opening is formed on the interlayer insulating layer 111 and in the opening of the interlayer insulating layer 111.

[0293] Through the above processes, a device structure including a plurality of unit cells 100 is formed in the device region Rc of each of the silicon carbide epitaxial wafers 300. Although not shown, the silicon carbide epitaxial wafer 300 is then cut for each device (chip). Thereby, a plurality of silicon carbide semiconductor devices (MISFETs) 200 are obtained.

[0294] The silicon carbide semiconductor device in the present embodiment is not limited to a vertical MISFET having a planar structure, and may also be a vertical MISFET having a trench structure. Alternatively, it may be a horizontal MISFET in which a source electrode and a drain electrode are disposed on the main surface of the silicon carbide wafer. Alternatively, it may be a junction field effect transistor (JFET) or the like. Furthermore, an insulated gate bipolar transistor (IGBT) can also be manufactured using a silicon carbide wafer having a conductivity type different from that of the silicon carbide epitaxial layer 110.

[0295] The semiconductor device in the present embodiment may also be a diode such as a Schottky barrier diode (SBD), a junction barrier diode (JBD), or a PN diode (PND). The diode includes: a semiconductor substrate; a semiconductor epitaxial layer of a first conductivity type disposed on the main surface of the semiconductor substrate; a first electrode disposed on the semiconductor epitaxial layer and in contact with the semiconductor epitaxial layer; and a second electrode disposed on the surface (back surface) of the semiconductor substrate opposite to the main surface and in contact with the semiconductor substrate. In the diode, the proportion of the drift resistance component in the on-resistance is higher than that in the transistor. Therefore, if the present embodiment is applied to a diode or a semiconductor epitaxial wafer for forming a diode, a more remarkable effect can be obtained.

[0296] Figure 16 FIG. is a schematic cross-sectional view illustrating a Schottky diode as an example of the semiconductor device in the present embodiment. The Schottky diode 400 includes: a silicon carbide substrate 101 of a first conductivity type; a silicon carbide epitaxial layer 110 disposed on the main surface of the silicon carbide substrate 101; a first electrode 410 disposed on the silicon carbide epitaxial layer 110; and a second electrode 420 formed on the back surface of the silicon carbide substrate 101. The silicon carbide substrate 101 is a part of the silicon carbide wafer 301. The silicon carbide epitaxial layer 110 includes a drift layer of a first conductivity type. The first electrode 410 forms a Schottky junction with the silicon carbide epitaxial layer 110. The second electrode 420 forms an ohmic junction with the silicon carbide substrate 101. In the Schottky diode 400, the thickness distribution of the silicon carbide epitaxial layer 110 and the concentration distribution of impurities in the silicon carbide epitaxial layer 110 also have a positive correlation in a plane parallel to the silicon carbide substrate 101.

[0297] Furthermore, in addition to silicon carbide, the present embodiment can also be applied to semiconductor epitaxial wafers and semiconductor devices using other wide-bandgap semiconductors such as gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. In addition, it can also be applied to semiconductor epitaxial wafers and semiconductor devices using silicon.

[0298] Industrial availability

[0299] The technology disclosed in this specification is useful, for example, in applications of semiconductor devices for power converters. In particular, it is useful in applications of power semiconductor devices for power converters mounted in vehicles, industrial equipment, etc.

Claims

1. A semiconductor epitaxial wafer, comprising: A semiconductor wafer; and A semiconductor epitaxial layer of a first conductivity type, disposed on a main surface of the semiconductor wafer and containing impurities of the first conductivity type, In a plane parallel to the main surface of the semiconductor wafer, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer, If the thicknesses of the semiconductor epitaxial layer at two points a and b in a plane parallel to the main surface of the semiconductor wafer are respectively set as Da and Db, and the concentrations of the impurities in the semiconductor epitaxial layer are set as Ca and Cb, then when Da > Db, Ca > Cb, or when Da < Db, Ca < Cb.

2. The semiconductor epitaxial wafer according to claim 1, wherein, If the maximum thickness in the thickness distribution of the semiconductor epitaxial layer is set as Tmax, the minimum thickness is set as Tmin, and the average thickness is set as Tave, then the amplitude VT (%) of the thickness distribution with respect to the average thickness Tave is represented by the following formula, VT = { (Tmax - Tmin) / 2} / Tave × 100 (%) If the maximum concentration in the concentration distribution of the semiconductor epitaxial layer is set as Cmax, the minimum concentration is set as Cmin, and the average concentration is set as Cave, then the amplitude VC (%) of the concentration distribution with respect to the average concentration Cave is represented by the following formula, VC = { (Cmax - Cmin) / 2} / Cave × 100 (%) The amplitude VT of the thickness distribution is 5% or more and 20% or less, The amplitude VC of the concentration distribution is 10% or more and 40% or less.

3. The semiconductor epitaxial wafer according to claim 2, wherein, The amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer satisfy 0.5 ≤ VC / VT ≤ 3.

0.

4. The semiconductor epitaxial wafer according to claim 3, wherein, The amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer satisfy 1.0 ≤ VC / VT ≤ 2.

5.

5. The semiconductor epitaxial wafer according to claim 1, wherein, The thickness of the semiconductor epitaxial layer at the central portion of the main surface is less than the thickness of the semiconductor epitaxial layer at the peripheral portion of the main surface, and the concentration of the impurities in the semiconductor epitaxial layer at the central portion is lower than the concentration of the impurities in the semiconductor epitaxial layer at the peripheral portion.

6. The semiconductor epitaxial wafer according to claim 1, wherein, The thickness of the semiconductor epitaxial layer at the central portion of the main surface is greater than the thickness of the semiconductor epitaxial layer at the peripheral portion of the main surface, and the concentration of the impurities in the semiconductor epitaxial layer at the central portion is higher than the concentration of the impurities in the semiconductor epitaxial layer at the peripheral portion.

7. The semiconductor epitaxial wafer according to claim 1, wherein, If the average thickness in the thickness distribution of the semiconductor epitaxial layer is set as Tave, and the average concentration in the concentration distribution of the semiconductor epitaxial layer is set as Cave, then the average concentration Cave of the semiconductor epitaxial layer is 3×10 15 / cm 3 or more and 3×10 16 / cm 3 or less, and the average thickness Tave is 4 μm or more and 40 μm or less.

8. The semiconductor epitaxial wafer according to claim 1, wherein, The semiconductor epitaxial wafer has a plurality of element regions, Each of the plurality of element regions includes a semiconductor element having: a body region of a second conductivity type, which is in contact with the semiconductor epitaxial layer; a source region of a first conductivity type, which is in contact with the body region; and a gate electrode, which is disposed on the semiconductor epitaxial layer with a gate insulating film therebetween.

9. The semiconductor epitaxial wafer according to claim 1, wherein the semiconductor epitaxial wafer has a plurality of element regions, each of the plurality of element regions includes a semiconductor element having: a first electrode, which is disposed on the semiconductor epitaxial layer and is in contact with the semiconductor epitaxial layer; and a second electrode, which is disposed on a surface of the semiconductor wafer opposite to the main surface and is in contact with the semiconductor wafer.

10. The semiconductor epitaxial wafer according to claim 8, wherein if the maximum value of the avalanche breakdown voltage of the semiconductor element in each of the plurality of element regions is Bmax, the minimum value is Bmin, and the average value is Bave, then the deviation amplitude VB (%) of the avalanche breakdown voltage of the semiconductor element between the plurality of element regions with respect to the average value Bave is represented by the following formula: VB (%) = { (Bmax - Bmin) / 2} / Bave × 100 if the maximum value of the drift resistance of the semiconductor element in each of the plurality of element regions is Dmax, the minimum value is Dmin, and the average value is Dave, then the deviation amplitude VD (%) of the drift resistance of the semiconductor element between the plurality of element regions with respect to the average value Dave is represented by the following formula: VD (%) = { (Dmax - Dmin) / 2} / Dave × 100 The amplitude VB and the amplitude VD are 0% or more and 10% or less.

11. The semiconductor epitaxial wafer according to claim 1, wherein the semiconductor wafer is a silicon carbide wafer, and the semiconductor epitaxial layer is a silicon carbide semiconductor layer.

12. A semiconductor element, comprising: a semiconductor substrate; a first-conductivity-type semiconductor epitaxial layer, which is disposed on the main surface of the semiconductor substrate and contains a first-conductivity-type impurity; a second-conductivity-type body region, which is in contact with the semiconductor epitaxial layer; a first-conductivity-type source region, which is in contact with the body region; and a gate electrode, which is disposed on the semiconductor epitaxial layer with a gate insulating film therebetween, the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurity in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor substrate have a positive correlation, if the thicknesses of the semiconductor epitaxial layer at two points a and b in a plane parallel to the main surface of the semiconductor substrate are respectively Da and Db, and the concentration of the impurity in the semiconductor epitaxial layer is Ca and Cb, then when Da > Db, Ca > Cb, or when Da < Db, Ca < Cb.

13. A semiconductor element, comprising: a semiconductor substrate; a first-conductivity-type semiconductor epitaxial layer, which is disposed on the main surface of the semiconductor substrate and contains a first-conductivity-type impurity; A first electrode, disposed on the semiconductor epitaxial layer and in contact with the semiconductor epitaxial layer; and A second electrode, disposed on the surface of the semiconductor substrate opposite to the main surface and in contact with the semiconductor substrate, In a plane parallel to the main surface of the semiconductor substrate, there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer, If the thicknesses of the semiconductor epitaxial layer at two points a and b in a plane parallel to the main surface of the semiconductor substrate are respectively denoted as Da and Db, and the concentrations of the impurities in the semiconductor epitaxial layer are denoted as Ca and Cb, then when Da>Db, Ca>Cb, or when Da<Db, Ca<Cb.

14. A method for manufacturing a semiconductor epitaxial wafer, comprising: (A) A step of preparing a semiconductor wafer; and (B) A step of forming a first-conductivity-type semiconductor epitaxial layer containing impurities of a first conductivity type by epitaxially growing a semiconductor on the main surface of the semiconductor wafer, In the step (B), the conditions of epitaxial growth are controlled such that there is a positive correlation between the thickness distribution of the semiconductor epitaxial layer and the concentration distribution of the impurities in the semiconductor epitaxial layer in a plane parallel to the main surface of the semiconductor wafer, If the thicknesses of the semiconductor epitaxial layer at two points a and b in a plane parallel to the main surface of the semiconductor wafer are respectively denoted as Da and Db, and the concentrations of the impurities in the semiconductor epitaxial layer are denoted as Ca and Cb, then when Da>Db, Ca>Cb, or when Da<Db, Ca<Cb.

15. The method for manufacturing a semiconductor epitaxial wafer according to claim 14, wherein, If the maximum thickness in the thickness distribution of the semiconductor epitaxial layer is denoted as Tmax, the minimum thickness is denoted as Tmin, and the average thickness is denoted as Tave, then the amplitude VT (%) of the thickness distribution with respect to the average thickness Tave is represented by the following formula, VT = { (Tmax - Tmin) / 2} / Tave × 100 (%) If the maximum concentration in the concentration distribution of the semiconductor epitaxial layer is denoted as Cmax, the minimum concentration is denoted as Cmin, and the average concentration is denoted as Cave, then the amplitude VC (%) of the concentration distribution with respect to the average concentration Cave is represented by the following formula, VC = { (Cmax - Cmin) / 2} / Cave × 100 (%) In the step (B), the conditions of epitaxial growth are controlled such that the amplitude VT of the thickness distribution is 5% or more and 20% or less, and the amplitude VC of the concentration distribution is 10% or more and 40% or less.

16. The method for manufacturing a semiconductor epitaxial wafer according to claim 15, wherein, In the step (B), the conditions of epitaxial growth are controlled such that the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer satisfy 0.5 ≤ VC / VT ≤ 3.

0.

17. The method for manufacturing a semiconductor epitaxial wafer according to claim 16, wherein, In the step (B), the conditions for epitaxial growth are controlled such that the amplitude VT of the thickness distribution and the amplitude VC of the concentration distribution in the semiconductor epitaxial layer satisfy 1.0 ≤ VC / VT ≤ 2.

5.

18. The method for manufacturing a semiconductor epitaxial wafer according to any one of claims 14 to 17, wherein the semiconductor wafer is a silicon carbide wafer, and the semiconductor epitaxial layer is a silicon carbide semiconductor layer.

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