Semiconductor device and method for manufacturing the same

Abstract

The semiconductor device comprises a semiconductor portion, a first electrode and a second electrode provided on the back and surface of the semiconductor portion, a control electrode and a field plate provided inside a groove on the surface side. The semiconductor portion comprises a first layer and a third layer of a first conductivity type, and a second layer of a second conductivity type. The second layer is provided between the first layer and the second electrode, and the third layer is selectively provided between the second layer and the second electrode. The field plate is electrically insulated from the semiconductor portion by a first insulating film and a second insulating film. The control electrode is electrically insulated from the semiconductor portion via the first insulating film. The second insulating film is located between the first insulating film and the field plate, and has a dielectric constant lower than that of the first insulating film.

Description

Technical Field

[0001] Embodiments relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Among trench gate MOSFETs, which are one type of semiconductor devices, there is a trench gate MOSFET having a structure in which a gate electrode and a field plate are arranged inside a gate trench.

[0003] For example, in order to reduce the channel resistance of MOSFET, it is preferred to make the trench gate high-density and make the inversion channel wider, but the current flow path between the trench gates becomes narrower, resulting in an increase in on-resistance. In this regard, the increase in on-resistance can be avoided by increasing the impurity concentration of the drift layer, but the withstand voltage of the MOSFET in the off state is reduced. Therefore, in order to achieve low on-resistance and high withstand voltage, a field plate is configured inside the gate trench. However, if a field plate is configured, the parasitic capacitance between the drain source electrode becomes larger.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2017-162909 Summary of the invention

[0007] Embodiments provide a semiconductor device capable of reducing source-drain capacitance in a trench gate structure including a field plate and a method for manufacturing the same.

[0008] According to one embodiment, a semiconductor device comprises: a semiconductor portion including a first semiconductor layer of a first conductivity type; a first electrode provided on the back side of the semiconductor portion; a second electrode provided on the surface of the semiconductor portion; a control electrode disposed between the second electrode and the semiconductor portion and disposed inside a groove disposed on the surface side of the semiconductor portion and electrically insulated from the semiconductor portion via a first insulating film; and a field plate disposed inside the groove. The field plate is located between the first electrode and the control electrode, electrically insulated from the semiconductor portion by the first insulating film and the second insulating film, and electrically insulated from the control electrode via a third insulating film. The semiconductor portion further comprises: a second semiconductor layer of a second conductivity type disposed between the first semiconductor layer and the second electrode and opposite to the control electrode via the first insulating film; and a third semiconductor layer of a first conductivity type selectively disposed between the second semiconductor layer and the second electrode. The first insulating film includes a portion located between the first semiconductor layer and the second insulating film. The second insulating film is located between the first insulating film and the field plate and has a dielectric constant lower than that of the first insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0010] Figure 2 It is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment.

[0011] Figure 3 It means succession Figure 2 Schematic cross-sectional view of the subsequent manufacturing process.

[0012] Figure 4 It means succession Figure 3 Schematic cross-sectional view of the subsequent manufacturing process.

[0013] Figure 5 It means succession Figure 4 Schematic cross-sectional view of the subsequent manufacturing process.

[0014] Figure 6 It means succession Figure 5 Schematic cross-sectional view of the subsequent manufacturing process.

[0015] Figure 7 It means succession Figure 6 Schematic cross-sectional view of the subsequent manufacturing process.

[0016] Figure 8 It is a schematic cross-sectional view showing a semiconductor device according to a modified example of the embodiment.

[0017] Explanation of symbols

[0018] 1, 2…semiconductor device, 10…semiconductor portion, 11…n-type drift layer, 13…p-type diffusion layer, 15…n-type source layer, 17…p-type contact layer, 19…n-type drain layer, 20…drain electrode, 30…source electrode, 30e…contact portion, 40…gate electrode, 40f, 50f…conductive film, 45, 55, 57…insulating film, 47…interlayer insulating film, 50…field plate, 100…silicon wafer, CT…contact trench, GT…gate trench. DETAILED DESCRIPTION

[0019] Hereinafter, the implementation method will be described with reference to the accompanying drawings. The same part in the drawings is given the same symbol and its detailed description is appropriately omitted, and the different parts are described. In addition, the drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. may not be the same as the actual one. In addition, even when representing the same part, there is a case where the size and ratio of each other are represented differently according to the drawings.

[0020] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, there is a case where the Z direction is described as the upper direction and the opposite direction thereof is described as the lower direction.

[0021] Figure 1 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a power MOSFET and has a trench gate structure.

[0022] like Figure 1 As shown, the semiconductor device 1 includes a semiconductor portion 10, a drain electrode 20, a source electrode 30, a gate electrode 40 and a field plate 50. The semiconductor portion 10 is, for example, silicon. The drain electrode 20 is provided on the back surface of the semiconductor portion 10. The source electrode 30 is provided on the front surface of the semiconductor portion 10.

[0023] The gate electrode 40 is arranged between the semiconductor portion 10 and the source electrode 30. The gate electrode 40 is arranged inside the gate trench GT provided on the surface side of the semiconductor portion 10. The gate electrode 40 is electrically insulated from the semiconductor portion 10 via the insulating film 45. In addition, the gate electrode 40 is electrically insulated from the source electrode 30 via the interlayer insulating film 47.

[0024] The field plate 50 is arranged inside the gate trench GT and is located between the drain electrode 20 and the gate electrode 40. The field plate 50 is electrically insulated from the semiconductor portion 10 by an insulating film having a stacked structure including an insulating film 45 and an insulating film 55. The insulating film 55 has a dielectric constant lower than that of the insulating film 45. The insulating film 55 is located between the insulating film 45 and the field plate 50. In addition, the field plate 50 is electrically insulated from the gate electrode 40 via the insulating film 57.

[0025] The insulating film 45 is provided so that its upper end is in contact with the interlayer insulating film 47. The insulating film 55 and the insulating film 57 each have an upper end in contact with the gate electrode 40. The upper ends of the insulating film 55 and the insulating film 57 are arranged along the lower surface of the gate electrode 40.

[0026] like Figure 1 As shown, the semiconductor portion 10 includes an n-type drift layer 11 , a p-type diffusion layer 13 , an n-type source layer 15 , a p-type contact layer 17 , and an n-type drain layer 19 .

[0027] The p-type diffusion layer 13 is provided between the n-type drift layer 11 and the source electrode 30. The p-type diffusion layer 13 is provided to face the gate electrode 40 via the insulating film 45. That is, a part of the insulating film 45 between the p-type diffusion layer 13 and the gate electrode 40 functions as a gate insulating film.

[0028] The n-type source layer 15 is selectively provided between the p-type diffusion layer 13 and the source electrode 30. The n-type source layer 15 contains n-type impurities having a higher concentration than the n-type impurities of the n-type drift layer 11.

[0029] The p-type contact layer 17 is selectively provided in the p-type diffusion layer 13 , for example. The p-type contact layer 17 contains p-type impurities at a higher concentration than the p-type impurities in the p-type diffusion layer 13 . The p-type contact layer 17 is provided to electrically connect the p-type diffusion layer 13 and the source electrode 30 .

[0030] In this example, the source electrode 30 has a contact portion 30e extending from the upper surface of the interlayer insulating film 47 to the inside of the contact trench CT to the depth of the p-type diffusion layer 13. The contact portion 30e is provided to contact the n-type source layer 15 and the p-type contact layer 17. The source electrode 30 is electrically connected to the n-type source layer 15 and the p-type contact layer 17 via the contact portion 30e.

[0031] The n-type drain layer 19 is provided between the n-type drift layer 11 and the drain electrode 20. The n-type drain layer 19 contains n-type impurities at a higher concentration than the n-type impurities of the n-type drift layer 11. The drain electrode 20 is electrically connected to the n-type drain layer 19.

[0032] In the present embodiment, the field plate 50 is located in the n-type drift layer 11, and is electrically connected to the source electrode 30 through, for example, a portion not shown. The field plate 50 is electrically insulated from the n-type drift layer 11 by an insulating film having a stacked structure including an insulating film 45 and an insulating film 55. The insulating film 55 has a dielectric constant lower than that of the insulating film 45. Thus, the parasitic capacitance between the drain electrode 20 and the source electrode 30, that is, the drain-source capacitance, can be reduced.

[0033] The insulating film 45 is, for example, a silicon oxide film. The insulating film 55 is a porous silicon oxide film, a so-called porous silicon oxide film, having a lower atomic density than the silicon oxide of the insulating film 45. The insulating film 55 includes, for example, a low-k material such as SiOC.

[0034] The insulating film 55 is made of a material that exhibits a lower brightness than the insulating film 45 when measured using a transmission electron microscope (TEM), for example.

[0035] Reference Figure 2 (a)~ Figure 7 (b) of the drawings illustrates a method for manufacturing the semiconductor device 1. Figure 2 (a)~ Figure 7 (b) is a schematic cross-sectional view sequentially showing the manufacturing process of the semiconductor device 1 according to the embodiment.

[0036] like Figure 2As shown in (a), a gate trench GT is formed on the surface side of the silicon wafer 100. The gate trench GT is formed by selectively removing the silicon wafer 100 by RIE (Reactive Ion Etching) using an etching mask not shown. The silicon wafer 100 contains, for example, n-type impurities having the same concentration as the n-type impurities of the n-type drift layer 11.

[0037] like Figure 2 As shown in (b) of FIG. 1 , an insulating film 45 is formed to cover the inner surface of the gate trench GT. The insulating film 45 is, for example, a silicon oxide film, and is formed by thermally oxidizing the silicon wafer 100 .

[0038] like Figure 3 As shown in (a), a p-type diffusion layer 13, an n-type source layer 15, and a p-type contact layer 17 are formed on the surface side of the silicon wafer 100. For example, in a state where the inside of the gate trench GT is buried by a sacrificial film (not shown), a p-type impurity such as boron (B) is ion-implanted on the surface side of the silicon wafer 100. Next, the p-type impurity ion-implanted is diffused by heat treatment to form the p-type diffusion layer 13.

[0039] Then, n-type impurities such as phosphorus (P) are ion-implanted into a region to be the n-type source layer 15, and p-type impurities such as boron (B) are selectively ion-implanted into a region to be the p-type contact layer 17. Then, the n-type impurities and the p-type impurities are activated by heat treatment to form the n-type source layer 15 and the p-type contact layer 17. At this time, the heat treatment is performed for a short time so that the lower end of the p-type contact layer 17 is at a position shallower than the lower end of the p-type diffusion layer 13. In addition, the p-type contact layer 17 is formed at a position deeper than the n-type source layer 15 by ion implantation at a relatively high acceleration energy.

[0040] like Figure 3 As shown in (b), an insulating film 55 is formed inside the gate trench GT. The insulating film 55 is formed by, for example, selectively removing a sacrificial film (not shown) and then using CVD (Chemical Vapor Deposition). Inside the gate trench GT, the insulating film 55 is formed above the insulating film 45. In addition, the insulating film 55 is formed in a manner that a space remains inside the gate trench GT.

[0041] like Figure 4 As shown in (a) of FIG. 1 , a conductive film 50 f is formed so as to fill the space inside the gate trench GT. The conductive film 50 f is, for example, a polysilicon film formed by CVD.

[0042] like Figure 4As shown in (b), by etching back the conductive film 50f, a field plate 50 is formed at the lower part of the gate trench GT. The field plate 50 is formed, for example, so that its upper end is located at a level lower than the level of the lower end of the p-type diffusion layer 13 in the depth direction (Z direction). The gate trench GT includes a space formed above the field plate 50.

[0043] like Figure 5 As shown in FIG. 5( a ), an insulating film 57 is formed to fill the space inside the gate trench GT. The insulating film 57 is formed by, for example, CVD and includes the same material as that of the insulating film 55 .

[0044] like Figure 5 As shown in (b), the insulating film 55 and the insulating film 57 are etched back so that a part of the insulating film 55 and a part of the insulating film 57 remain under the gate trench GT. In addition, the etching back of the insulating films 55 and 57 is performed under the condition that the insulating film 45 is not etched.

[0045] The upper surface of the insulating film 55 and the upper surface of the insulating film 57 remaining in the gate trench GT are formed to be located at the same level as the lower end of the p-type diffusion layer 13 in the Z direction or at a level deeper than the lower end of the p-type diffusion layer 13. The insulating film 57 does not necessarily need to include the same material as the insulating film 55, but it is desirable to use a material having the same etching rate as the insulating film 55. For example, the upper surface of the insulating film 55 and the upper surface of the insulating film 57 are formed to have no step difference at the boundary thereof. The upper surface of the insulating film 55 and the upper surface of the insulating film 57 are formed as a continuous surface.

[0046] like Figure 6 As shown in (a) of FIG. 1 , a conductive film 40 f is formed so as to fill the space inside the gate trench GT. The conductive film 40 f is, for example, a conductive polysilicon film formed by CVD.

[0047] like Figure 6 As shown in (b) of FIG. 1 , a gate electrode 40 is formed on the upper portion of the gate trench GT. The gate electrode 40 is formed, for example, by etching back the conductive film 40 f. The gate electrode 40 is formed to face the p-type diffusion layer 13 via the insulating film 45 .

[0048] like Figure 7 As shown in (a), an interlayer insulating film 47 is formed to cover the gate electrode 40. The interlayer insulating film 47 is, for example, a silicon oxide film formed by CVD. Next, a contact trench CT having a depth from the upper surface of the interlayer insulating film 47 to the p-type contact layer 17 is formed.

[0049] like Figure 7As shown in (b), a source electrode 30 is formed on the interlayer insulating film 47. The source electrode 30 is formed, for example, by vacuum deposition or CVD. The source electrode 30 is formed to have a contact portion 30e extending into the inside of the contact trench CT and contacting the n-type source layer 15 and the p-type contact layer 17.

[0050] The source electrode 30 includes, for example, aluminum. Alternatively, the source electrode 30 may have a two-layer structure including tungsten that fills the inside of the contact trench CT and aluminum formed thereon.

[0051] Next, the back side of the silicon wafer 100 is etched or polished to be thinned to a predetermined thickness. In addition, n-type impurities are ion-implanted into the back side of the silicon wafer 100 to form an n-type drain layer 19 (see Figure 1 ). At this time, the n-type impurities ion-implanted into the back side of the silicon wafer 100 are activated by, for example, laser annealing. Thus, the n-type drain layer 19 can be formed without thermally denaturing the insulating film 55 provided on the surface side. Alternatively, an epitaxial wafer having a low-concentration n-type silicon layer formed on a high-concentration n-type silicon wafer may be used instead of the silicon wafer 100.

[0052] Next, the drain electrode 20 is formed on the n-type drain layer 19 (on the back surface of the silicon wafer 100), and the semiconductor device 1 is completed (see Figure 1 ). The drain electrode 20 is formed by vacuum evaporation, for example, and includes a gold-germanium (AuGe) alloy.

[0053] In the manufacturing method of this embodiment, for example, a process requiring high temperature treatment of 900° C. or higher, such as thermal oxidation and activation after ion implantation, is performed before forming the insulating film 55. The process after forming the insulating film 55 is performed by, for example, CVD that can be performed at a temperature of about 400° C. Thus, thermal denaturation of the insulating film 55 during the manufacturing process of the semiconductor device 1 can be avoided.

[0054] Figure 8 2 is a schematic cross-sectional view showing a semiconductor device 2 according to a modified example of the embodiment. In the semiconductor device 2, the insulating film 57 is provided to extend into the gate electrode 40. The upper end of the insulating film 57 is located at a level higher than the level of the lower surface of the gate electrode 40 in the Z direction. In addition, the upper end of the insulating film 57 is located at a level higher than the level of the lower surface of the p-type diffusion layer 13 in the Z direction.

[0055] In this example, the insulating film 57 includes a material having an etching rate slower than that of the insulating film 55. Figure 5In the process shown in (b), the insulating film 57 is left in a shape protruding upward from the upper surface of the insulating film 55. In addition, such a structure can also be formed by selectively etching back the insulating film 57 and then etching back the insulating film 55. The insulating film 57 can also include the same material as the insulating film 45.

[0056] In the semiconductor device 2 , by increasing the thickness of the insulating film 57 remaining in the gate trench GT in the Z direction, it is possible to reduce the parasitic capacitance between the gate and the source.

[0057] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device comprising: The semiconductor portion includes a first semiconductor layer of a first conductivity type; A first electrode disposed on the back side of the semiconductor portion; A second electrode is provided on the front side opposite to the back side of the semiconductor portion; a control electrode disposed between the second electrode and the semiconductor portion, disposed inside a trench provided on the front side of the semiconductor portion, and electrically insulated from the semiconductor portion via a first insulating film; and a field plate, provided inside the trench, located between the first electrode and the control electrode, electrically insulated from the semiconductor portion by the first insulating film and the second insulating film, and electrically insulated from the control electrode via a third insulating film, The above-mentioned Semiconductor Division also includes: a second semiconductor layer of the second conductivity type, disposed between the first semiconductor layer and the second electrode, and facing the control electrode via the first insulating film; and a third semiconductor layer of the first conductivity type, selectively disposed between the second semiconductor layer and the second electrode, The first insulating film includes a portion located between the first semiconductor layer and the second insulating film, the second insulating film is located between the first insulating film and the field plate, and has a dielectric constant lower than that of the first insulating film. An end portion of the control electrode located on the back side of the semiconductor portion is located at the same level as an end portion of the second semiconductor layer located on the back side of the semiconductor portion.

2. The semiconductor device according to claim 1, wherein: The second insulating film has an atomic density lower than that of the first insulating film.

3. The semiconductor device according to claim 1, wherein: The third insulating film includes the same material as that of the second insulating film.

4. The semiconductor device according to claim 1, wherein: The field plate is located in the first semiconductor layer and is electrically insulated from the first semiconductor layer by the first insulating film and the second insulating film.

5. The semiconductor device according to claim 1, wherein: The first insulating film includes silicon oxide, and the second insulating film includes SiOC.

6. The semiconductor device according to claim 5, wherein: The third insulating film includes SiOC.

7. The semiconductor device according to claim 1, wherein: The second insulating film has a first end in contact with the control electrode. The third insulating film has a second end in contact with the control electrode. The first end and the second end are arranged along the lower surface of the control electrode.

8. The semiconductor device according to claim 1, wherein: The third insulating film extends in the control electrode in a first direction from the first electrode toward the second electrode.

9. The semiconductor device according to claim 1, wherein: The third insulating film is located at a first level in a first direction from the first electrode toward the second electrode. The first level is higher than a second level at which the lower surface of the control electrode is located in the first direction.

10. The semiconductor device according to claim 9, wherein: The first level is higher than a third level at which the lower surface of the second semiconductor layer is located in the first direction.

11. The semiconductor device according to claim 8, wherein: The third insulating film includes the same material as that of the first insulating film.

12. The semiconductor device according to claim 8, wherein: The first insulating film and the third insulating film each include silicon oxide. The second insulating film includes SiOC.

13. A method for manufacturing a semiconductor device, comprising the following steps: A trench is formed on the front side of the semiconductor wafer including a portion to be the first semiconductor layer of the first conductivity type, forming a first insulating film covering the inner surface of the trench, forming a second semiconductor layer of a second conductivity type on the portion to be the first semiconductor layer, the second semiconductor layer containing the second conductivity type impurities introduced to the front side of the semiconductor wafer, forming a first conductivity type third semiconductor layer on the second semiconductor layer, the third semiconductor layer containing first conductivity type impurities introduced to the front side of the semiconductor wafer, forming a second insulating film on the first insulating film so that a first space remains in the groove, the second insulating film having a dielectric constant lower than that of the first insulating film, A field plate is formed in the first space in the trench so as to face the first semiconductor layer via the first insulating film and the second insulating film, wherein the field plate is formed so as to leave a second space above the field plate. forming a third insulating film on the field plate in the second space, In the trench, the second insulating film and the third insulating film are partially removed to form a third space. A control electrode is formed in the third space, the control electrode being electrically insulated from the field plate via the third insulating film and facing the second semiconductor layer via the first insulating film. An end portion of the control electrode located on the back side of the semiconductor wafer is located at the same level as an end portion of the second semiconductor layer located on the back side of the semiconductor wafer.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The first insulating film is an oxide film formed by thermally oxidizing the semiconductor wafer.

15. The method for manufacturing a semiconductor device according to claim 13 or 14, wherein: The second insulating film is formed after the first insulating film, the second semiconductor layer, and the third semiconductor layer are formed.

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