Switching regulator and electronic device including the same

Abstract

A switching regulator is provided, the switching regulator comprising a first conversion stage and a second conversion stage. The first conversion stage may include a first output capacitor connected between a first output node and ground, the first conversion stage being configured to receive a first input voltage and provide an output voltage by adjusting the level of the output voltage based on a first dynamic voltage scaling (DVS) rate related to a first load condition of a processing circuit. The second conversion stage may include a second output capacitor connected between a second output node and ground, the second conversion stage being configured to receive a second input voltage and provide the output voltage by adjusting the level of the output voltage based on a second DVS rate related to a second load condition of the processing circuit, the second load condition of the processing circuit being heavier than the first load condition of the processing circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2019-0032540 filed on March 21, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to generation of a power supply voltage, and more particularly, to a switching regulator and / or an electronic device including the switching regulator. Background Art

[0004] A power supply voltage may be generated to supply power to an electronic component, and the level of the power supply voltage supplied to the electronic component may be changed to reduce power consumption of the electronic component. For example, in the case of a processing circuit for processing a digital signal, a lower level of power supply voltage may be supplied when relatively lower performance is expected according to a workload, and a higher level of power supply voltage may be supplied when relatively higher performance is expected. Therefore, a switching regulator that generates various levels of power supply voltage and is capable of efficiently using power is being studied. Summary of the invention

[0005] The inventive concept provides a switching regulator and / or an electronic device including the switching regulator, which efficiently uses power by changing a dynamic voltage scaling (DVS) rate of a power supply voltage provided to an electronic component for each workload of the electronic component.

[0006] According to an example embodiment of the inventive concept, a switching regulator includes: a first conversion stage, including a first output capacitor connected between a first output node and ground, the first conversion stage being configured to receive a first input voltage and provide an output voltage by adjusting the level of the output voltage based on a first dynamic voltage scaling (DVS) rate related to a first load condition of a processing circuit; and a second conversion stage, including a second output capacitor connected between a second output node and ground, the second conversion stage being configured to receive a second input voltage and provide an output voltage by adjusting the level of the output voltage based on a second DVS rate related to a second load condition of the processing circuit, the load of the processing circuit under the second load condition being heavier than the load of the processing circuit under the first load condition.

[0007] According to an example embodiment of the inventive concept, a switching regulator includes: a first conversion stage, including a first output capacitor connected between a first output node and ground, the first conversion stage is configured to receive a first input voltage and provide an output voltage by adjusting the level of the output voltage based on a first dynamic voltage scaling (DVS) rate; a second conversion stage, including a second output capacitor connected between a second output node connected to an output terminal and ground, the second conversion stage is configured to receive a second input voltage and provide an output voltage by adjusting the level of the output voltage based on a second DVS rate; and a first switching element connected between the first output node and a second output node, the first switching element being configured to selectively connect the first conversion stage to the output terminal.

[0008] According to an example embodiment of the inventive concept, an electronic system includes: at least one processing circuit; and a switching regulator configured to generate an output voltage according to an input voltage and provide the output voltage to the processing circuit, the switching regulator including a plurality of conversion stages, each of the plurality of conversion stages including one or more output capacitors, the plurality of conversion stages being configured to adjust a level of the output voltage based on different dynamic voltage scaling (DVS) rates, and generating the output voltage by selecting at least one of the plurality of conversion stages based on a load condition of the processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating an electronic device including a switching regulator according to an example embodiment of the inventive concept;

[0011] Figure 2A and Figure 2B They are used to illustrate that there is no need to consider Figure 1 a loss when providing an output voltage generated by a conversion operation based on the same DVS rate to the processing circuit under a load condition of the processing circuit in the embodiment of the present invention;

[0012] Figure 3 is a flow chart of a conversion operation of a switching regulator according to an example embodiment of the inventive concept;

[0013] Figure 4 is a block diagram illustrating a switching regulator according to an example embodiment of the inventive concept;

[0014] Figure 5A and Figure 5B are schematic diagrams for explaining operations of switching regulators according to some example embodiments of the inventive concept;

[0015] FIG. 6A to FIG. 6Care block diagrams for explaining the operation in the transition mode of the switching regulator;

[0016] Figure 7 is a block diagram illustrating a switching regulator according to an example embodiment of the inventive concept;

[0017] Figure 8 is a block diagram illustrating a switching regulator according to an example embodiment of the inventive concept;

[0018] Fig. 9A and Fig. 9B are schematic diagrams for explaining operations of switching regulators according to some example embodiments of the inventive concept;

[0019] FIG. 10A to FIG. 10E are block diagrams for explaining the operation in the transition mode of the switching regulator; and

[0020] Fig.11 is a schematic diagram illustrating an electronic system according to an example embodiment of the inventive concept. DETAILED DESCRIPTION

[0021] In this specification, "on" of a switch may refer to a state in which both ends of the switch are electrically connected to each other, and "off" of a switch may refer to a state in which both ends of the switch are electrically disconnected from each other. In addition, two or more components electrically connected via a switch and / or a wire in an on state may be referred to as simply "connected", and two or more components electrically connected via a wire or the like at all times may be referred to as "coupled".

[0022] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0023] Figure 1 1 is a block diagram showing an electronic device 1 including a switching regulator 10 according to an exemplary embodiment of the inventive concept. The switching regulator 10 may receive a first input voltage V via a first input terminal 13 and a second input terminal 14. IN1 and the second input voltage V IN2 The output voltage V is output through the output terminal 15. O . Output voltage V O It can be used as a power supply voltage for other electronic components (or loads). In the following, the processing circuit 2 is described as providing the output voltage V of the switching regulator 10 to it. O The example embodiment is an example of an electronic component, but the example embodiment is only an example and the example embodiment is not limited thereto. The output voltage V may be provided to various electronic components (eg, a central processing unit (CPU), a graphics processing unit (GPU), and a camera). O .

[0024] like Figure 1As shown, the switching regulator 10 may include a first conversion stage 11, a second conversion stage 12, and a mode switch element SW_MODE. In some example embodiments, the components included in the switching regulator 10 may be included in one semiconductor package. In some example embodiments, the switching regulator 10 may include a printed circuit board (PCB), and at least two components of the switching regulator 10 may be mounted on the PCB as separate semiconductor packages. In addition, the mode switch element SW_MODE may include various semiconductor elements.

[0025] The switching regulator 10 may refer to a circuit that generates an output voltage V by switching on / off components. O As an example of the switching regulator 10, a DC-DC converter can be configured to provide a first input voltage V IN1 and the second input voltage V IN2 (both are DC voltages) to generate an output voltage V O (is a DC voltage). For example, a buck converter can generate a voltage lower than the first input voltage V IN1 Or the second input voltage V IN2 The output voltage V O , so it can be called a buck converter. The boost converter can generate a voltage higher than the first input voltage V IN1 Or the second input voltage V IN2 The output voltage V O , so it can be called a boost converter. A buck-boost (or buck / boost) converter can generate a voltage level lower or higher than the first input voltage V IN1 Or the second input voltage V IN2 The output voltage V O In the following, in this specification, reference is made to a device capable of generating an output voltage V in various modes. O The switching regulator 10 is described with reference to a buck-boost DC-DC converter, but it should be understood that the exemplary embodiments of the present inventive concept can be applied to other types of switching regulators 10, such as a first input voltage V IN1 Or the second input voltage V IN2 is an AC-DC converter for an AC voltage. In addition, according to an exemplary embodiment, the first input voltage V IN1 The level of the second input voltage V IN2 The levels of can be the same or different from each other. In addition, the second input voltage V IN2 The level can be greater than the first input voltage V IN1 level.

[0026] In some example embodiments, depending on the output voltage V OThe switching regulator 10 can be set to one of the buck mode, buck-boost mode and boost mode. Since the switching regulator 10 supports at least one of the buck mode, buck-boost mode and boost mode, the output voltage V O In addition, each of the first conversion stage 11 and the second conversion stage 12 may include a configuration of various switching circuits (not shown) to support at least one of the buck mode, the buck-boost mode, and the boost mode.

[0027] The first conversion stage 11 can receive a first input voltage V from a first input terminal 13 IN1 And according to the first input voltage V IN1 To generate the output voltage V O The first conversion stage 11 may be configured to include a first inductor L1, a first output capacitor C O1 and a switching circuit (not shown) to adjust the output voltage V based on the first DVS rate O The DVS rate can refer to the output voltage V O The speed at which the level changes can be called the DVS sensitivity. In other words, as the DVS rate increases, the output voltage V O The level can change faster. The inductance of the first inductor L1 and the first output capacitor C O1 The capacitance of the first output capacitor C may be determined to be a value capable of performing a conversion operation based on the first DVS rate. O1 The first output capacitor C may be connected between one end of the first inductor L1 and ground. O1 A node at which the first inductor L1 and the first output capacitor C1 contact each other may be referred to as a first output node N1. O2 The second output capacitor C may be connected between one end of the second inductor L2 and ground. O2 A node at which the second inductor L2 contacts each other may be referred to as a second output node N2 .

[0028] The second conversion stage 12 can receive a second input voltage V from the second input terminal 14 IN2 And according to the second input voltage V IN2 Generates output voltage V O The second conversion stage 12 may be configured to include a second inductor L2, a second output capacitor C O2 and a switching circuit (not shown) to adjust the output voltage V based on the second DVS rate O The inductance of the second inductor L2 and the second output capacitor C O2 The capacitance of may be determined to be a value capable of performing a conversion operation based on the second DVS rate.

[0029] In the exemplary embodiment, any one of the first conversion stage 11 and the second conversion stage 12 can be selected according to the working load condition of the processing circuit 2, and the output voltage V can be generated by the selected conversion stage. O The output voltage V is provided to the processing circuit 2 via the output terminal 15. O When the processing circuit 2 is in a light load condition, the first conversion stage 11 may be selected to generate the output voltage V O , and when the processing circuit 2 is under heavy load, the second conversion stage 12 may be selected to generate the output voltage V O The light load condition may be a condition where the operating load level of the processing circuit is less than or equal to the reference voltage level (or a condition where the processing circuit requires a voltage less than or equal to the reference voltage level), and the heavy load condition may be a condition where the operating load level of the processing circuit exceeds the reference voltage level (or a condition where the processing circuit requires a voltage exceeding the reference voltage level). However, the example embodiments are merely examples and the example embodiments are not limited thereto. The switching regulator 10 may select a conversion stage suitable for a wider variety of load conditions of the processing circuit and generate an output voltage V O .

[0030] In addition, despite the Figure 1 Only two conversion stages are shown in FIG. 1 , but the example embodiments are only examples and the example embodiments are not limited thereto. More conversion stages may be included to perform conversion operations based on more DVS rates, so that efficient power usage can be achieved under various load conditions of the processing circuit.

[0031] Figure 2A and Figure 2B It is used to illustrate that there is no need to consider Figure 1 In the case of the load condition of the processing circuit 2 in the embodiment of the present invention, the output voltage V generated by the conversion operation based on the same DVS rate is provided to the processing circuit 2. O time loss.

[0032] refer to Figure 2A , when the processing circuit 2 is in a light load condition, the desired demand voltage V in the processing circuit 2 需求 Therefore, even if the processing circuit 2 is provided with a voltage V 需求 The output voltage V is not sensitive to changes over time at a lower DVS rate O , a relatively small power loss Loss may also occur as a result.

[0033] refer to Figure 2B , when the processing circuit 2 is under heavy load, the desired demand voltage V in the processing circuit 2 需求 The level can be higher. Therefore, when the required voltage V 需求The output voltage V changes with the passage of time and directly provides the processing circuit 2 with a lower level of DVS rate that is insensitive to the change. O When Figure 2A Unlike the situation in FIG. 1 , a relatively large power loss Loss may occur. Such a power loss Loss may degrade the performance of the switching regulator and further degrade the performance of the electronic device 1.

[0034] Return to reference Figure 1 When the processing circuit 2 is in a light load condition, the first conversion stage 11 can adjust the output voltage V based on a relatively low first DVS rate. O After the level of the processing circuit 2 meets the first expected voltage of the processing circuit 2, the processing circuit 2 is provided with an output voltage V of the first level. O When the processing circuit 2 is under heavy load, the second conversion stage 12 can adjust the output voltage V based on the relatively low first DVS rate. O After the level of the processing circuit 2 meets the second expected voltage of the processing circuit 2, the processing circuit 2 is provided with an output voltage V of the second level. O For example, when the processing circuit 2 is in a light load condition, the switching regulator 10 may connect the first conversion stage 11 to the second output capacitor C O2 , and by using the first output capacitor C O1 and the second output capacitor C O2 To adjust the output voltage V O When the processing circuit 2 is in the second load condition, the switching regulator 10 can output the current to the output capacitor C by using the second output capacitor C included in the second conversion stage 12. O2 To adjust the output voltage V O level.

[0035] For example, the inductance of the first inductor L1 of the first conversion stage 11 may be greater than the inductance of the second inductor L2 of the second conversion stage 12, and the first output capacitor C of the first conversion stage 11 may be greater than the inductance of the second inductor L2 of the second conversion stage 12. O1 The capacitance may be greater than the second output capacitor C of the second conversion stage 12 O2 The capacitance of Figure 1 In the embodiment, the second conversion stage 12 includes a second inductor L2. However, the example embodiment is not limited thereto, and the following reference may be applied. Figure 7 Various configurations described.

[0036] In the exemplary embodiment, in order to generate the output voltage V by using a conversion stage selected from the first conversion stage 11 and the second conversion stage 12 O, the mode switch element SW_MODE may be connected between the first output node N1 of the first conversion stage 11 and the second output node N2 of the second conversion stage 12. The second output node N2 may be connected (or, coupled) to the output terminal 15, and the first output node N1 may be connected (or, coupled) to the output terminal 15 via the mode switch element SW_MODE. Because the first output capacitor C O1 The capacitance is greater than the second output capacitor C O2 capacitance, and therefore the first output capacitor C O1 Compared with the capacitance of the second output capacitor C, the influence of the second output capacitor C during the conversion operation of the first conversion stage 11 can be limited. O2 In the conversion operation of the first conversion stage 11, the first output capacitor C can be selectively switched to O1 The connection with the second conversion stage 12 is disconnected, so that the corresponding conversion operation can be performed smoothly.

[0037] In an example embodiment, under a light load condition of the processing circuit 2, the mode switch element SW_MODE may be turned on, the first output node N1 may be connected (or, coupled) to the output terminal 15, and the first conversion stage 11 may be switched on based on the first enable control signal EN1 ( Figure 7 ) and the reference voltage V REF ( Figure 7 ) performs a conversion operation to provide an output voltage V having a first DVS rate to the processing circuit 2 O In this case, the second conversion stage 12 may be in a disabled state. Hereinafter, the disabled state may refer to the first conversion stage 11 and / or the second conversion stage 12 being in a state with respect to the first input voltage V IN1 and / or the second input voltage V IN2 In other words, the disabled state may refer to a state in which the first conversion stage 11 and / or the second conversion stage 12 are disconnected from the first input terminal 13 and the second input terminal 14. The switching regulator 10 generates the output voltage V by using the first conversion stage 11. O The conversion mode can be called slow mode.

[0038] Under heavy load conditions of the processing circuit 2, the mode switch element SW_MODE may be turned off, and the second conversion stage 12 may be enabled based on the second enable control signal EN2 ( Figure 7 ) and the reference voltage V REF The conversion operation is performed to provide the processing circuit 2 with an output voltage V having a second DVS rate O In this case, the first conversion stage 11 may be in a disabled state. The switching regulator 10 generates an output voltage V by using the second conversion stage 12. OThe switching mode of the switching regulator 200 may be referred to as a fast mode. In other words, the first speed of the slow mode of the switching regulator 200 may be slower than the second speed of the fast mode of the switching regulator 200.

[0039] The signals (EN1, EN2, V REF , and mode control signal CS_MODE( Figure 7 )), or a controller (not shown) included in the switching regulator 10 may receive a specific signal from the processing circuit 2 and generate a signal (EN1, EN2, V REF and CS_MODE). Although not in Figure 1 However, there may be more control signals, which are expected to be used to control the conversion operation of the first conversion stage 11 and the second conversion stage 12. Such additional signals can be fully understood by those skilled in the art, so their detailed description is omitted. FIG. 6A to FIG. 6C etc. to describe in detail the operation of the switching regulator 10 according to each load condition.

[0040] In an exemplary embodiment, when the load condition of the processing circuit 2 is such that the switching regulator 10 provides the output voltage V to the processing circuit 2 O When the time changes, it is used to generate the output voltage V O The switching regulator 100 may transition from one level to another level within a transition period, wherein there is an intermediate transient level between the first level and the other level. In this case, the switching regulator 100 may enable both the first switching level and the second switching level, wherein the first switching level has generated an output voltage V having a first level for a certain period of time before the load condition begins to change. O , and the second conversion stage is configured to generate an output voltage V having a second level according to the changed load condition O , and during the transition period, the first conversion stage and the second conversion stage simultaneously generate an output voltage V having a first level O and an output voltage V having a second level O To perform complementary conversion operations. Figure 5B etc. to describe the details of the problem.

[0041] The switching regulator 10 according to some example embodiments may provide an output voltage V with different DVS rates according to a load condition or a desired voltage level of an electronic component such as the processing circuit 2. O To use power efficiently.

[0042] Figure 3 is a flowchart of a conversion operation of the switching regulator 10 according to an example embodiment of the inventive concepts.

[0043] refer to Figure 3 , the output voltage V of the switching regulator 10 can be analyzed. O The workload of the processing circuit 2 can be analyzed by the processing circuit 2 in real time, and the future workload can be estimated. The switching regulator 10 can select a conversion mode according to the analyzed workload (S20). The switching regulator 10 can receive information about the analyzed workload from the processing circuit 2 and select a conversion mode based on the information, or can directly receive a control signal related to the selection of the conversion mode from the processing circuit 2 and select the conversion mode in response to the control signal. The output voltage V of the switching regulator 10 can be determined according to the output voltage V O In some example embodiments, the switching regulator 10 may include a plurality of conversion stages, wherein each conversion stage generates an output voltage V having a different DVS rate. O , and each of the plurality of conversion stages may include at least one output capacitor. Thereafter, the switching regulator 10 may perform a conversion operation based on the selected conversion mode (S30). In other words, the switching regulator 10 may enable a conversion stage that satisfies the selected conversion mode and generates an output voltage V having a DVS rate suitable for the workload of the processing circuit 2. O And provide this to the processing circuit 2.

[0044] Figure 4 1 is a block diagram of a switching regulator 100 according to an exemplary embodiment of the inventive concept. Figure 4 In the description, the description has been given assuming that the conversion operation is controlled by the controller 103. However, the exemplary embodiment is only an example and the exemplary embodiment is not limited thereto, and various control examples may be applied.

[0045] refer to Figure 4 The switching regulator 100 may include a first switching circuit 101, a second switching circuit 102, a controller 103, a first inductor L1 and a second inductor L2, a first output capacitor C O1 and the second output capacitor C O2 , and a mode switch element SW_MODE. The first switch circuit 101, the first inductor L1 and the first output capacitor C O1 The configuration can correspond to Figure 1 The first conversion stage 11 in the embodiment of the present invention comprises a second switching circuit 102, a second inductor L2 and a second output capacitor C O2 The configuration can correspond to Figure 1 The second conversion stage 12 in FIG.

[0046] The controller 103 may receive a reference voltage V from a processing circuit (not shown).REF (not shown) and identifies the workload of the processing circuit 2, and thus may selectively control any one of the first switch circuit 101 and the second switch circuit 102, and control a conversion operation suitable for the workload of the processing circuit 2. In some example embodiments, the controller 103 may receive information about the workload from the processing circuit 2 as a separate signal and may control the conversion operation based on the separate signal.

[0047] The controller 103 can control the on / off of the mode switch element SW_MODE by providing the mode control signal CS_MODE to the mode switch element SW_MODE according to the conversion mode corresponding to the workload of the processing circuit 2, and can control the first switch circuit 101 or the second switch circuit 102 based on the feedback signal FB from the second output node N2 connected to the output terminal 115 and the reference voltage VREF. FIG. 6A to FIG. 6C A detailed description thereof is given.

[0048] The controller 103 in the present disclosure may include processing circuits, such as hardware including logic circuits or hardware-software combinations such as processors that execute software. For example, the processing circuits may more specifically include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0049] The software may include a computer program, a code segment, an instruction, or some combination thereof, to independently or collectively instruct and / or configure the controller 103 to operate as desired, thereby converting the controller into a special processor or a special computer. The software and data may be implemented permanently or temporarily in any type of machine, component, physical or virtual device and / or computer storage medium or device. The software may also be distributed on a network-coupled computer system so that the software is stored and executed in a distributed manner. The software and data may be stored by one or more computer-readable recording media.

[0050] Figure 5A and Figure 5B are example schematic diagrams for explaining the operation of the switching regulator 100 according to some example embodiments, and FIG. 6A to FIG. 6C They are block diagrams for explaining the operation of the switching regulator 100 in the conversion mode.

[0051] refer to Figure 5A, the switching regulator 100 can perform a switching operation based on the slow mode MODE_slow in the first period Period_1 corresponding to the light load condition of the processing circuit 2. In other words, the switching regulator 100 can generate a required voltage V having a slow tracking characteristic of the processing circuit 2. 需求 The relatively low DVS rate output signal V O And provide the output signal V to the processing circuit 2 O . refer to Fig. 6A To describe the switching operation of the switching regulator 100 in the slow mode MODE_slow, the controller 103 may turn on the mode switch element SW_MODE by providing the first mode control signal CS_MODEa to the mode switch element SW_MODE, may disable the second switch circuit 102 by providing the second control signal CS2a to the second switch circuit 102, and may generate a first transmission current I through the first inductor L1 and flow to the output terminal 115 by providing the first control signal CS1a to the first switch circuit 101. D1 The output voltage V is provided to the processing circuit 2 by using the switch control of the first switch circuit 101. O .

[0052] The switching regulator 100 may perform a conversion operation based on the fast mode MODE_fast in the second period Period_2 corresponding to the heavy load condition of the processing circuit 2. In other words, the switching regulator 100 may generate a required voltage V having a fast tracking characteristic of the processing circuit 2. 需求 The relatively high DVS rate output signal V O And provide output signal V to processing circuit 2 O . refer to Figure 6B To describe the switching operation of the switching regulator 100 in the fast mode MODE_fast, the controller 103 may disconnect the mode switch element SW_MODE by providing the second mode control signal CS_MODEb to the mode switch element SW_MODE, may disable the first switch circuit 101 by providing the first control signal CS1b to the first switch circuit 101, and may generate a second transmission current I through the second inductor L2 and flow to the output terminal 115 by providing the second control signal CS2b to the second switch circuit 102. D2 The output voltage V is provided to the processing circuit 2 by using the switch control of the second switch circuit 102. O .

[0053] Thereafter, the switching regulator 100 may perform a conversion operation based on the slow mode MODE_slow in a third period Period_3 corresponding to a light load condition of the processing circuit 2 .

[0054] Also refer to Figure 5B ,and Figure 5A Compared with the case in FIG. 1 , the switching regulator 100 can operate in the transition mode within a specific time interval (e.g., the fourth period Period_4 and the fifth period Period_5) when the conversion mode changes (or, alternatively, the load condition of the processing circuit 2 changes), and can generate the output voltage V by using a plurality of switching circuits (or, alternatively, by using a plurality of conversion stages). O . refer to Figure 6C To describe the switching operation of the switching regulator 100 in the transition mode TR, the controller 103 can turn on the mode switch element SW_MODE by providing the third mode control signal CS_MODEc to the mode switch element SW_MODE, and can generate a first transmission current I through the first inductor L1 and the second inductor L2 and flow to the output terminal 115 by providing the first control signal CS1c to the first switch circuit 101, providing the second control signal CS2c to the second switch circuit 102, and generating a first transmission current I D1 and the second transmission current I D2 The output voltage V is provided to the processing circuit 2 by using the switch control of the first switch control circuit 101 and the second switch control circuit 102 respectively. O The switching regulator 100 can be configured to generate an output voltage V corresponding to the first load condition before the transition period by performing the conversion operation of the first switching circuit 101 and the conversion operation of the second switching circuit 102 in parallel during the transition period (e.g., by performing the conversion operation of the first switching circuit 101 (which is already in operation to generate the output voltage V corresponding to the first load condition before the transition period) during the transition period. O ) until the second switch circuit 102 is enabled through the transition mode TR and stably generates an output voltage V corresponding to the second load condition after the transition period. O to generate a stable output voltage V O And provide a stable output voltage V to the processing circuit 2 O .

[0055] Figure 7 is a block diagram of a switching regulator 200 according to an example embodiment of the inventive concepts.

[0056] refer to Figure 7 , the switching regulator 200 may include a first conversion stage 210, a second conversion stage 220, and a mode switch element SW_MODE. The inductor connection configuration of the first conversion stage 210 may be different from the inductor connection configuration of the second conversion stage 220. The first conversion stage 210 may receive a first input voltage V from a first input terminal 213. IN1 And according to the first input voltage V IN1 To generate the output voltage V OThe first conversion stage 210 may include a first inductor L1, a first output capacitor C O1 and a switching circuit (not shown), and may be configured to adjust the output voltage V based on a first DVS rate O The configuration of the first conversion stage 210 may correspond to Figure 1 The configuration of the first conversion stage 11 in FIG. 1 is not shown, and thus a detailed description thereof is omitted.

[0057] The second conversion stage 220 can receive a second input voltage V from the second input terminal 214 IN2 And according to the second input voltage V IN2 To generate the output voltage V O The second conversion stage 220 may be configured to include a plurality of second inductors (L2_1 to L2_n), a second output capacitor C O2' and a plurality of switch circuits (not shown) to adjust the output voltage V based on the second DVS rate O The level of. One end of each of the plurality of second inductors (L2_1 to L2_n) may be commonly connected to the second output node N2. The second inductors (L2_1 to L2_n) may be connected in parallel to each other in the second conversion stage 220. In addition, the other end of each of the second inductors (L2_1 to L2_n) may be connected to a switching circuit (not shown). In an example embodiment, the inductance of the second inductors (L2_1 to L2_n) and the second output capacitor C O2’ The capacitance of may be determined as a value capable of performing a conversion operation based on the second DVS rate. In addition, the second inductors (L2_1 to L2_n) may have the same or different inductances, and the inductance of each of the second inductors (L2_1 to L2_n) may be less than Figure 1 All the switch circuits (not shown) included in the second conversion stage 220 can be controlled based on the same method, thereby providing an output voltage V to the processing circuit (not shown) by generating a transmission current through the second inductor (L2_1 to L2_n). O .

[0058] The magnitude of the total transmission current through the second output node N2 can be increased by using the connection configuration of the second inductor (L2_1 to L2_n) of the second conversion stage 220. Figure 1 Compared with the second inductor L2 in FIG. 1 , the connection configuration of the second inductors ( L2_1 to L2_n) occupies a relatively small area in the switching regulator 200 , so the utilization of the internal space of the switching regulator 200 is improved in the design stage.

[0059] When the output voltage V of the switching regulator 200 is provided to it OWhen a specific processing circuit (not shown) is in a light load condition, the first conversion stage 210 may be selected and may be based on the first enable signal EN1 and the reference voltage V REF Generates output voltage V O , and when a specific processing circuit (not shown) is in a heavy load condition, the second conversion stage 220 may be selected and may be based on the second enable signal EN2 'and the reference voltage V REF Generates output voltage V O .

[0060] Figure 8 is a block diagram of a switching regulator 300 according to an example embodiment of the inventive concepts.

[0061] refer to Figure 8 , the switching regulator 300 may include a first conversion stage 310, a second conversion stage 320, a third conversion stage 330, a first mode switch element SWa_MODE, and a second mode switch element SWb_MODE. Figure 1 Compared with the switching regulator 10 in FIG. 1 , the switching regulator 300 may further include a third conversion stage 302 and a second mode switch element SWb_MODE. Figure 1 The configurations of the switching regulator 10 are described in different configurations.

[0062] The third conversion stage 330 can receive a third input voltage V from the third input terminal 315 IN3 And according to the third input voltage V IN3 Generates output voltage V O The third conversion stage 330 may be configured to include a third inductor L3, a third output capacitor C O3 and a switch circuit (not shown) to adjust the output voltage V based on the third DVS rate O The inductance of the third inductor L3 and the third output capacitor C O3 The capacitance of the third output capacitor C may be determined to be a value capable of performing a conversion operation based on the third DVS rate. O3 The capacitance of the first output capacitor C O1 The capacitance is greater than the second output capacitor C O2的 In addition, the inductance of the third inductor L3 may be smaller than the inductance of the first inductor L1 and larger than the inductance of the second inductor L2.

[0063] The third output capacitor C O3 The third output capacitor C may be connected between one end of the third inductor L3 and ground. O3The node at which the third inductor L3 contacts each other may be referred to as a third output node N3. In addition, as described above, the first conversion stage 310 may adjust the output voltage V based on the first DVS rate. O The second conversion stage 320 can adjust the output voltage V based on the second DVS rate O level.

[0064] In an exemplary embodiment, the output voltage V of the switching regulator 300 is provided to the O Depending on the workload of the processing circuit (not shown), any one of the first conversion stage 310, the second conversion stage 320, and the third conversion stage 330 may be selected, and an output voltage V may be generated by the selected one or more conversion stages. O The output voltage V is provided to a processing circuit (not shown) via the output terminal 316. O When the processing circuit (not shown) is under light load condition, the first conversion stage 310 may be selected to generate the output voltage V O When the processing circuit (not shown) is under normal (or alternatively, intermediate) load conditions, the third conversion stage 330 may be selected and may generate an output voltage V O When the processing circuit (not shown) is under a heavy load condition, the second conversion stage 320 may be selected and may generate an output voltage V O .

[0065] In this case, a light load condition may refer to a state in which a workload level of the processing circuit (not shown) is less than or equal to a first reference level (or, a state in which the processing circuit (not shown) expects a voltage less than or equal to the first reference voltage level), a normal (or alternatively, an intermediate) load condition may refer to a state in which a workload level of the processing circuit (not shown) exceeds the first reference level and is less than or equal to a second reference level (or, a state in which the processing circuit (not shown) expects a voltage exceeding the first reference voltage level and less than or equal to the second reference voltage level), and a heavy load condition may refer to a state in which a workload level of the processing circuit (not shown) exceeds the second reference level (or, a state in which the processing circuit (not shown) expects a voltage exceeding the second reference voltage level).

[0066] In an example embodiment, under a normal load condition of a processing circuit (not shown), the third conversion stage 330 may be selected by the first mode control signal CSa_MODE and the second mode control signal CSb_MODE and may be based on the third enable control signal EN3 and the reference voltage V 晡 Generates an output voltage V with a third DVS rate O . Reference below FIG. 10A to FIG. 10C A detailed description thereof is given.

[0067] Fig. 9A and Fig. 9B are respectively used to illustrate some exemplary embodiments of the present invention. Figure 8 An example schematic diagram of the operation of the switching regulator 300 is shown in FIG. FIG. 10A to FIG. 10E is a block diagram for explaining the operation of the switching regulator 300 in each conversion mode.

[0068] refer to Fig. 9A , the switching regulator 300 can perform a switching operation based on the slow mode MODE_slow in a first period Period_1 corresponding to a light load condition of the processing circuit (not shown). In other words, the switching regulator 300 can generate a required voltage V having a slow tracking processing circuit (not shown). 需求 The relatively low first DVS rate output signal V O The output signal V is provided to a processing circuit (not shown). O . Referring to FIG. 1 for explaining the switching operation of the switching regulator 300 in the slow mode MODE_slow Fig. 10A In the slow mode MODE_slow, the first mode switch element SWa_MODE can be turned on by the first mode control signal CSa_MODEa, and the second mode switch element SWb_MODE can be turned off by the second mode control signal CSb_MODEa. In addition, the first conversion stage 310 can be enabled by the first enable control signal EN1a, the second conversion stage 320 can be disabled by the second enable control signal EN2a, and the third conversion stage 330 can be disabled by the third enable control signal EN3a. The first conversion stage 310 can be enabled by the first enable control signal EN1a based on the first enable control signal EN1a and the reference voltage V REF The conversion operation is performed to generate a first transmission current I through the first inductor L1 and flowing to the output terminal 316. D1 and can provide an output voltage V to a processing circuit (not shown) O .

[0069] The switching regulator 300 may perform a switching operation based on the normal mode MODE_normal in a second period Period_2 corresponding to a normal load condition of the processing circuit (not shown). In other words, the switching regulator 300 may generate a required voltage V having a speed tracking function of the processing circuit (not shown). 需求 The second DVS rate output signal V O The output signal V is provided to a processing circuit (not shown). O . Referring to FIG. 1 for explaining the switching operation of the switching regulator 300 in the normal mode MODE_normal Fig. 10BIn the normal mode MODE_normal, the first mode switch element SWa_MODE can be turned off by the first mode control signal CSa_MODEb, and the second mode switch element SWb_MODE can be turned on by the second mode control signal CSb_MODEb. In addition, the first conversion stage 310 can be disabled by the first enable control signal EN1b, the second conversion stage 320 can be disabled by the second enable control signal EN2b, and the third conversion stage 330 can be enabled by the third enable control signal EN3b. The third conversion stage 330 can be enabled by the third enable control signal EN3b based on the third enable control signal EN3b and the reference voltage V REF The conversion operation is performed to generate a second transmission current I through the third inductor L3 and flowing to the output terminal 316. D2 and can provide an output voltage V to a processing circuit (not shown) O .

[0070] The switching regulator 300 may perform a switching operation based on the fast mode MODE_fast in a third period Period_3 corresponding to a heavy load condition of the processing circuit (not shown). In other words, the switching regulator 300 may generate a required voltage V having a high speed to track the processing circuit (not shown). 需求 The relatively high third DVS rate output signal V O The output signal V is provided to a processing circuit (not shown). O . Referring to FIG. 1 for explaining the switching operation of the switching regulator 300 in the fast mode MODE_fast Fig. 10C In the fast mode MODE_fast, the first mode switch element SWa_MODE can be turned off by the first mode control signal CSa_MODEc, and the second mode switch element SWb_MODE can be turned off by the second mode control signal CSb_MODEc. In addition, the first conversion stage 310 can be disabled by the first enable control signal EN1c, the second conversion stage 320 can be enabled by the second enable control signal EN2c, and the third conversion stage 330 can be disabled by the third enable control signal EN3c. The second conversion stage 320 can be enabled by the second enable control signal EN2c and the reference voltage V REF The conversion operation is performed to generate a third transmission current I through the second inductor L2 and flowing to the output terminal 316. D3 and can provide an output voltage V to a processing circuit (not shown) O In an example embodiment, the magnitudes of the DVS rates may be the third DVS rate, the second DVS rate, and the first DVS rate in descending order.

[0071] Also refer to Fig. 9B ,and Fig. 9ACompared with the case of the switching regulator 300, the switching regulator 300 can be operated in the first transition mode TR1 and the second transition mode TR2 respectively within a specific time interval (for example, the fourth period Period_4 and the fifth period Period_5) including the moment when the conversion mode is changed (or the moment when the load condition of the processing circuit 2 is changed), and the output voltage V can be generated by using a plurality of conversion stages. O .

[0072] Referring to FIG. 1 for explaining the switching operation of the switching regulator 300 in the first transition mode TR1 Fig. 10D , in the first transition mode TR1, the first mode switch element SWa_MODE may be turned on by the first mode control signal CSa_MODEd, and the second mode switch element SWb_MODE may be turned on by the second mode control signal CSb_MODEd. In addition, the first conversion stage 310 may be enabled by the first enable control signal EN1d, the second conversion stage 320 may be disabled by the second enable control signal EN2d, and the third conversion stage 330 may be enabled by the third enable control signal EN3d. The first conversion stage 310 and the third conversion stage 330 may be enabled by the first enable control signal EN1d and the reference voltage V REF and the third enabling control signal EN3d and the reference voltage V REF The conversion operation is performed simultaneously to generate a first transmission current I through the first inductor L1 and the third inductor L3 and flow to the output terminal 316. D1 and the second transmission current I D2 and can provide an output voltage V to a processing circuit (not shown) O The switching regulator 300 can generate a stable output voltage V by performing the conversion operation using the first conversion stage 310 in parallel until the conversion operation by the third conversion stage 330 becomes stable during the first transition period in which the state of the switching regulator 300 changes from the slow mode MODE_slow to the normal mode MODE_normal. O .

[0073] Referring to FIG. 1 for explaining the switching operation of the switching regulator 300 in the second transition mode TR2 Fig. 10E, in the second transition mode TR2, the first mode switch element SWa_MODE may be turned off by the first mode control signal CSa_MODEe, and the second mode switch element SWb_MODE may be turned on by the second mode control signal CSb_MODEe. In addition, the first conversion stage 310 may be disabled by the first enable control signal EN1e, the second conversion stage 320 may be enabled by the second enable control signal EN2e, and the third conversion stage 330 may be enabled by the third enable control signal EN3e. The second conversion stage 320 and the third conversion stage 330 may be enabled by the second enable control signal EN2e and the reference voltage V, respectively. REF and the third enabling control signal EN3e and the reference voltage V REF The conversion operation is performed simultaneously to generate a third transmission current I passing through the second inductor L2 and the third inductor L3 and flowing to the output terminal 316. D3 and the second transmission current I D2 and can provide an output voltage V to a processing circuit (not shown) O The switching regulator 300 can generate a stable output voltage V by performing a conversion operation using the third conversion stage 330 in parallel until the conversion operation by the second conversion stage 320 becomes stable during a second transition period in which the state of the switching regulator 330 changes from the normal mode MODE_normal to the fast mode MODE_fast. O .

[0074] The switching regulator 300 may perform a complementary conversion operation by using a plurality of conversion stages during a transition period of a conversion mode change. Because the description given above should be sufficient as an explanation of this case, any further detailed description thereof is omitted.

[0075] Fig.11 is a schematic diagram showing an electronic system 400 according to an example embodiment of the inventive concept. In some example embodiments, the electronic system 400 may include a semiconductor integrated circuit such as a system on a chip (SoC), and in some other example embodiments, may include a printed circuit board and a package mounted thereon. Fig.11 As shown in FIG. 4 , the electronic system 400 may include first to fourth functional blocks 410 to 440 and a power management integrated circuit (PMIC) 450 .

[0076] The first to fourth functional blocks 410 to 440 may operate based on power provided by the first to fourth power supply voltages VDD1 to VDD4 output from the PMIC 450. For example, at least one of the first to fourth functional blocks 410 to 440 may include a digital circuit (e.g., an application processor (AP)) for processing digital signals, or may include an analog circuit for processing analog signals. In addition, at least one of the first to fourth functional blocks 410 to 440 may include a circuit (e.g., an analog-to-digital converter (ADC)) for processing mixed signals. Although the electronic system 400 is Fig.11 4 is shown as including four functional blocks, but in some example embodiments, the electronic system 400 may include less than four functional blocks or more than five functional blocks.

[0077] PMIC 450 can be configured to generate a voltage V IN A first power supply voltage VDD1 to a fourth power supply voltage VDD4 are generated, and the level of at least one of the first power supply voltage VDD1 to the fourth power supply voltage VDD4 is changed according to a voltage control signal C_V. At least one of the first functional block 410 to the fourth functional block 440 may receive a power supply voltage whose level dynamically changes depending on the desired performance and power consumption. For example, the first functional block 410 may include an image processor for processing image data, or the first functional block 410 may receive a high level of the first power supply voltage VDD1 when processing a video image including a series of images, or the first functional block 410 may receive a low level of the first power supply voltage VDD1 when processing a photo including a single image. The PMIC 450 may receive a voltage control signal C_V corresponding to the performance and power consumption desired by the first functional block 410 and may increase or decrease the level of the first power supply voltage VDD1 based on the voltage control signal C_V.

[0078] The PMIC 450 may include the switching regulator described above with reference to the accompanying drawings, and thus may provide the first to fourth functional blocks 410 to 440 with first to fourth power supply voltages VDD1 to VDD4 having DVS rates related to load conditions of the first to fourth functional blocks 410 to 440, respectively. In order to perform such an operation, the switching regulator of the PMIC 450 may include a plurality of conversion stages, and each of the plurality of conversion stages may include one or more output capacitors. For example, Figure 1 The switching regulator shown in FIG. 4 may be included in PMIC 450 .

[0079] While the inventive concept has been particularly shown and described with reference to the example embodiments disclosed herein, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A switching regulator, comprising: a first conversion stage including a first output capacitor connected between a first output node and ground, the first conversion stage configured to receive a first input voltage and to provide an output voltage by adjusting a level of the output voltage based on a first dynamic voltage scaling (DVS) rate related to a first load condition of the processing circuit; a second conversion stage including a second output capacitor connected between a second output node and the ground, the second conversion stage configured to receive a second input voltage and to provide the output voltage by adjusting the level of the output voltage based on a second DVS rate related to a second load condition of the processing circuit, the second load condition of the processing circuit being more heavily loaded than the first load condition of the processing circuit; an output terminal connected to the second output node of the second conversion stage, the output terminal being configured to provide the output voltage to the processing circuit; as well as A switching element is configured to selectively connect the first output node of the first conversion stage to the output terminal.

2. The switching regulator according to claim 1, wherein A first capacitance of the first output capacitor is greater than a second capacitance of the second output capacitor.

3. The switching regulator according to claim 1, wherein The first conversion stage further includes a first inductor connected to the first output capacitor via the first output node, The second conversion stage also includes a second inductor connected to the second output capacitor via the second output node, and A first inductance of the first inductor is greater than a second inductance of the second inductor.

4. The switching regulator according to claim 1, wherein When the processing circuit is under the first load condition, the switching regulator is configured to connect the first conversion stage to the second output capacitor and to adjust the level of the output voltage by using the first output capacitor and the second output capacitor, and When the processing circuit is under the second load condition, the switching regulator is configured to regulate the level of the output voltage by using the second output capacitor included in the second conversion stage. 5 . The switching regulator according to claim 1 , wherein the switching regulator is configured to switch on / off the switching element based on a specific load condition of the processing circuit.

6. The switching regulator according to claim 1, wherein When the processing circuit is under the first load condition, the switching regulator is configured to turn on the switching element, enable the first conversion stage, and disable the second conversion stage, and When the processing circuit is in the second load condition, the switching regulator is configured to control the switching element to be in an off state, disable the first conversion stage, and enable the second conversion stage.

7. The switching regulator of claim 6, wherein during a transition period when a load condition of the processing circuit changes from one of the first load condition and the second load condition to the other of the first load condition and the second load condition, the switching regulator is configured to turn on the switching element and enable both the first conversion stage and the second conversion stage to generate the output voltage.

8. The switching regulator according to claim 1, further comprising: a third conversion stage including a third output capacitor connected between a third output node and the ground, the third conversion stage being configured to adjust the level of the output voltage based on a third DVS rate related to a third load condition of the processing circuit, the third load condition being an intermediate load condition between the first load condition and the second load condition.

9. The switching regulator of claim 1, wherein the second conversion stage further comprises a plurality of inductors connected to the second output node. 10 . The switching regulator of claim 1 , wherein the first conversion stage and the second conversion stage are configured to operate in any one of a buck conversion operation, a buck-boost conversion operation, or a boost conversion operation.

11. A switching regulator, configured to generate an output voltage according to at least one of a first input voltage and a second input voltage, and output the output voltage through an output terminal, the switching regulator comprising: a first conversion stage including a first output capacitor connected between a first output node and ground, the first conversion stage being configured to receive the first input voltage and adjust a level of the output voltage based on a first dynamic voltage scaling (DVS) rate; a second conversion stage including a second output capacitor connected between a second output node connected to the output terminal and the ground, the second conversion stage being configured to receive the second input voltage and adjust the level of the output voltage based on a second DVS rate; as well as a first switching element connected between the first output node and the output terminal, the first switching element being configured to selectively connect the first conversion stage to the output terminal, The first DVS rate is slower than the second DVS rate.

12. The switching regulator of claim 11, wherein A first capacitance of the first output capacitor is greater than a second capacitance of the second output capacitor.

13. The switching regulator of claim 12, wherein When the switching regulator operates in a first mode, the switching regulator is configured to turn on the first switching element and connect the first output node to the output terminal, so that the level of the output voltage is controlled by the first conversion stage; and When the switching regulator operates in a second mode, the switching regulator is configured to turn off the first switching element so that the level of the output voltage is controlled by the second conversion stage, and a first speed of the first mode of the switching regulator is slower than a second speed of the second mode of the switching regulator.

14. The switching regulator of claim 13, wherein When the switching regulator operates in the first mode, the switching regulator is configured to enable the first conversion stage and disable the second conversion stage, and When the switching regulator operates in the second mode, the switching regulator is configured to disable the first switching stage and enable the second switching stage.

15. The switching regulator according to claim 13, wherein during a transition period in which the switching regulator changes from the first mode to the second mode or from the second mode to the first mode, the switching regulator is configured to turn on the first switching element and adjust the level of the output voltage by using the first conversion stage and the second conversion stage.

16. The switching regulator of claim 11, further comprising: a third conversion stage including a third output capacitor connected between a third output node and the ground, the third conversion stage being configured to adjust the level of the output voltage based on a third DVS rate; as well as A second switching element is connected between the second output node and the third output node, and the second switching element is configured to selectively connect the third conversion stage to the output terminal.

17. The switching regulator of claim 11, wherein the second conversion stage further comprises a plurality of inductors connected in parallel to the second output node.

18. The switching regulator of claim 11, further comprising: A controller is configured to control a conversion operation by selecting at least one of the first conversion stage and the second conversion stage according to a specific load condition of a processing circuit to which the output voltage is provided.

19. An electronic system comprising: at least one processing circuit; as well as a switching regulator configured to: generate an output voltage according to an input voltage and provide the output voltage to the processing circuit, the switching regulator comprising a plurality of conversion stages, each of the plurality of conversion stages comprising one or more output capacitors, the plurality of conversion stages being configured to adjust the level of the output voltage based on different dynamic voltage scaling (DVS) rates; and generating the output voltage by selecting at least one conversion stage of the plurality of conversion stages based on a load condition of the processing circuit, The switching regulator is configured to simultaneously select at least two conversion stages of the plurality of conversion stages and generate the output voltage during a transition period when the load condition of the processing circuit changes. 20 . The electronic system of claim 19 , wherein the switching regulator is configured to receive a control signal related to the load condition from the processing circuit and to generate the output voltage based on the control signal.

21. The electronic system of claim 19, wherein the plurality of conversion stages further include inductors having different inductances, respectively.

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