Display device

Abstract

A display device includes: a display panel including a plurality of pixels; a scan driver configured to supply a scan signal to the pixels through scan lines; and a timing controller configured to control a pulse width of the scan signal according to a display brightness of the display panel.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2019 - 0031301, filed on Mar. 19, 2019, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein. Technical field

[0003] Aspects of some example embodiments relate to an electronic device and, for example, to a display device. Background art

[0004] A display device may include pixels that emit light in response to data signals and a scan driver that outputs scan signals to write the data signals to the pixels. When the gray level (i.e., data voltage) changes suddenly between consecutive frames, some pixels may emit insufficient light or may not reach the desired gray level or brightness, and display failures such as screen dragging, afterimages, and image blurring may be visually recognized.

[0005] The above information disclosed in this background art section is only for enhancing the understanding of the background art and, therefore, may include information that does not constitute the prior art. Summary of the invention

[0006] Some example embodiments of the present invention may provide a display device in which the pulse width of a scan signal is controlled according to the display brightness of a display panel.

[0007] The features of the present invention are not limited to the features mentioned above. Various extensions or changes can be made to the features of the present invention without departing from the spirit and scope of the present invention.

[0008] According to some example embodiments of the present invention, a display device may include: a display panel including a plurality of pixels; a scan driver for supplying a scan signal to each of the plurality of pixels through scan lines; and a timing controller for controlling the pulse width of the scan signal according to the display brightness of the display panel.

[0009] According to some example embodiments, the scan driver may output a scan signal having a first pulse width corresponding to a first display brightness and output a scan signal having a second pulse width corresponding to a second display brightness lower than the first display brightness.

[0010] According to some example embodiments, the second pulse width may be shorter than the first pulse width.

[0011] According to some example embodiments, the pulse width of the scan signal may decrease as the display brightness decreases.

[0012] According to some example embodiments, when the display brightness is higher than a predetermined reference brightness, the scan driver may output a scan signal having a first pulse width.

[0013] According to some example embodiments, when the display brightness is equal to or lower than a predetermined reference brightness, the scan driver may output a scan signal having a second pulse width shorter than the first pulse width.

[0014] According to some example embodiments, when the display brightness is equal to or lower than a predetermined reference brightness, the pulse width of the scan signal may vary.

[0015] According to some example embodiments, when the display brightness is equal to or lower than a predetermined reference brightness, the pulse width of the scan signal may decrease as the display brightness decreases.

[0016] According to some example embodiments, the scan driver may determine the pulse width of the scan signal based on the width of the gate-on period of the clock signal supplied from the timing controller.

[0017] According to some example embodiments, the timing controller may output a clock signal having a gate-on period with a first pulse width corresponding to a first display brightness, and may output a clock signal having a gate-on period with a second pulse width corresponding to a second display brightness lower than the first display brightness.

[0018] According to some example embodiments, the second pulse width may be shorter than the first pulse width.

[0019] According to some example embodiments, the width of the gate-on period of the clock signal may decrease as the display brightness decreases.

[0020] According to some example embodiments, the timing controller may convert the display brightness into a brightness level of a digital value and output a clock signal having a gate-on period corresponding to the brightness level.

[0021] According to some example embodiments, the display device may further include: a data driver for supplying a data signal to each of a plurality of pixels through a data line; and an emission driver for supplying an emission control signal to each of the plurality of pixels through an emission control line.

[0022] According to some example embodiments, when the display brightness is equal to or lower than a predetermined reference brightness, the gate-off period of the emission control signal may vary according to the display brightness.

[0023] According to some example embodiments, when the display brightness is equal to or lower than a predetermined reference brightness, the display brightness may decrease as the width of the gate-off period of the emission control signal increases. Description of the Drawings

[0024] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate aspects of some example embodiments of the inventive concept and, together with the description, serve to explain some example features of the inventive concept.

[0025] Figure 1 is a block diagram illustrating a display device according to some example embodiments of the present invention.

[0026] Figure 2 is an illustration Figure 1 of an example of a pixel included in the display device.

[0027] Figure 3 is an illustration of Figure 2 an example of a signal supplied to the pixel.

[0028] Figure 4A , Figure 4B and Figure 4C is a graph illustrating an example of a pulse width of a scan signal determined according to display brightness.

[0029] Figure 5 is an illustration Figure 1 of an example of a scan driver included in the display device.

[0030] Figure 6A is an illustration Figure 5 of an example of a stage included in the scan driver.

[0031] Figure 6B is an illustration Figure 6A of an example of an output buffer unit included in the stage.

[0032] Figure 7 is an illustration Figure 5 of an example of an operation of the scan driver.

[0033] Figure 8 is an illustration of Figure 2 an example of a signal supplied to the pixel. DETAILED DESCRIPTION

[0034] Aspects of some example embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant explanations of the same components are omitted.

[0035] Figure 1 is a block diagram illustrating a display device according to some example embodiments of the present invention.

[0036] Referring to Figure 1, the display device 1000 may include a display panel 100, a scan driver 200, an emission driver 300, a data driver 400, and a timing controller 500.

[0037] The display panel 100 may display an image. The display panel 100 may include a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm, a plurality of emission control lines EL1 to ELn, and a plurality of pixels P connected to the plurality of scan lines SL1 to SLn, the plurality of data lines DL1 to DLm, and the plurality of emission control lines EL1 to ELn.

[0038] According to some example embodiments of the present invention, the number of scan lines SL1 to SLn and the number of emission control lines EL1 to ELn may each be n, where n may be a natural number. The number of data lines DL1 to DLm may be m, where m may be a natural number. Thus, the number of pixels P may be n×m. The display panel 100 may receive a first power supply voltage VDD and a second power supply voltage VSS from an external source (e.g., a power supply unit). According to some example embodiments, the display panel 100 may further receive a third power supply voltage (or initialization power supply voltage) VINT.

[0039] The timing controller 500 may receive an input control signal and input image data DATA1 from an image source such as an external graphics device. The timing controller 500 may generate image data DATA2 based on the input image data DATA1 according to the operating conditions of the display panel 100, and provide the image data DATA2 to the data driver 400. The timing controller 500 may generate a scan drive control signal for controlling the drive timing of the scan driver 200, an emission drive control signal for controlling the drive timing of the emission driver 300, and a data drive control signal DCS for controlling the drive timing of the data driver 400 based on the input control signal, and may provide the scan drive control signal, the emission drive control signal, and the data drive control signal DCS to the scan driver 200, the emission driver 300, and the data driver 400, respectively.

[0040] The scan drive control signal may include a scan start signal SSP and a clock signal CLK. The scan start signal SSP may control the first timing of the scan signal. The clock signal CLK may be used to shift the scan start signal SSP.

[0041] The emission drive control signal may include an emission control start signal ESP and a clock signal. The emission control start signal ESP may control the first timing of the emission control signal. The clock signal may be used to shift the emission control start signal ESP.

[0042] According to some example embodiments, the timing controller 500 may receive a brightness level DBV corresponding to the display brightness. The display brightness may be the brightness of an image displayed on the display panel 100. The display brightness may be determined by a user's setting or by a processor of the display device. The brightness level DBV may be a value obtained by converting the display brightness into a digital value. Alternatively, the timing controller 500 may receive a signal corresponding to the display brightness and convert the signal into a digital brightness level DBV. For example, a display brightness of up to about 650 nits may be divided into an 8-bit brightness level DBV. However, this is merely an example, and the maximum brightness of the display brightness and the brightness level DBV are not limited thereto.

[0043] The timing controller 500 may generate a clock signal CLK having a gate-on period corresponding to the brightness level DBV and provide the clock signal CLK to the scan driver 200. According to some example embodiments, the width of the gate-on period of the clock signal CLK may decrease as the brightness level DBV (e.g., the display brightness) decreases. Here, the gate-on period may be a period during which the clock signal CLK has a gate-on voltage level, and the gate-on voltage level may be a logic level that turns on a transistor receiving the clock signal CLK. For example, when the transistor is a p-type transistor, the gate-on voltage level may be a logic low level.

[0044] The scan driver 200 may receive scan drive control signals (including a scan start signal SSP and a clock signal CLK) from the timing controller 500. The scan driver 200 may supply scan signals to the scan lines SL1 to SLn in response to the scan drive control signals. The pulse width of the scan signal may be adjusted corresponding to the gate-on period of the clock signal CLK.

[0045] According to some example embodiments, the scan driver 200 may output a scan signal having a first pulse width corresponding to a first display brightness (or a first brightness level) and a scan signal having a second pulse width corresponding to a second display brightness (or a second brightness level) lower than the first display brightness. At this time, the second pulse width may be shorter than the first pulse width.

[0046] According to some example embodiments, the pulse width of the scan signal may decrease as the display brightness decreases. The pulse width of the scan signal may be the width of a period during which the scan signal has a gate-on level.

[0047] The emission driver 300 may receive emission drive control signals (including an emission control start signal ESP) from the timing controller 500. The emission driver 300 may supply emission control signals to the emission control lines EL1 to ELn in response to the emission drive control signals.

[0048] The data driver 400 may receive a data driving control signal DCS and image data DATA2 from the timing controller 500. The data driver 400 may supply data signals (data voltages) in an analog form to data lines DL1 to DLm in response to the data driving control signal DCS. The data signals supplied to the data lines DL1 to DLm may be supplied to the pixels P selected by the scan signal.

[0049] As described above, the display device 1000 according to some example embodiments of the present invention may adjust the pulse width of the scan signal according to the display brightness (e.g., brightness level DBV).

[0050] Figure 2 is a diagram Figure 1 of an example circuit diagram of a pixel included in the display device.

[0051] Reference Figure 1 and Figure 2 , the pixel P may include a first transistor T1 to a seventh transistor T7, a light emitting device LED, and a storage capacitor Cst. Here, the pixel P disposed in the j-th column (where j is a natural number) and the i-th row (where i is a natural number greater than 1) will be described as an example.

[0052] Although the first transistor T1 to the seventh transistor T7 are shown as p-type transistors (e.g., p-channel metal oxide semiconductor (PMOS) transistors) in Figure 2 , the first transistor T1 to the seventh transistor T7 are not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be an n-type transistor.

[0053] The first transistor T1 may be electrically coupled between the first power supply voltage VDD and the light emitting device LED. The first transistor T1 may include a gate electrode coupled to a first node N1. The first transistor T1 may determine the magnitude of the driving current flowing to the light emitting device LED according to the magnitude of the data voltage (data signal).

[0054] The second transistor T2 may be a scan transistor for transmitting the data voltage to the pixel P according to the scan signal supplied to the i-th scan line SLi. The second transistor T2 may be coupled between the j-th data line DLj and the first electrode (e.g., source electrode) of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the i-th scan line SLi.

[0055] The third transistor T3 can perform data voltage writing and threshold voltage compensation for the first transistor T1. The third transistor T3 can be coupled between the second electrode (e.g., drain electrode) of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the i-th scan line SLi. When the second transistor T2 and the third transistor T3 are turned on by a scan signal (the i-th scan signal), the first transistor T1 can be diode-connected, and the threshold voltage of the first transistor T1 can be compensated.

[0056] The fourth transistor T4 can be coupled between the first node N1 and the wire for transmitting the initialization power supply voltage VINT. The fourth transistor T4 can include a gate electrode connected to the (i - 1)-th scan line SLi-1. When the fourth transistor T4 is turned on, the initialization power supply voltage VINT can be supplied to the gate electrode of the first transistor T1. For example, the initialization power supply voltage VINT can be an initialization voltage for initializing the gate voltage of the first transistor T1.

[0057] The fifth transistor T5 can be coupled between the power supply line for transmitting the first power supply voltage VDD and the first electrode of the first transistor T1. The fifth transistor T5 can include a gate electrode connected to the i-th emission control line ELi.

[0058] The sixth transistor T6 can be coupled between the second electrode of the first transistor T1 and the first electrode (e.g., anode) of the light-emitting device LED. The sixth transistor T6 can include a gate electrode connected to the i-th emission control line ELi.

[0059] The fifth transistor T5 and the sixth transistor T6 can be turned on in response to an emission control signal. By turning on the fifth transistor T5 and the sixth transistor T6, a drive current can be supplied to the light-emitting device LED. The light-emitting device LED can emit light at a gray level corresponding to the drive current.

[0060] The seventh transistor T7 can be coupled between the first electrode of the light-emitting device LED and the wire for transmitting the initialization power supply voltage VINT. The seventh transistor T7 can include a gate electrode connected to the (i - 1)-th scan line SLi-1. When the seventh transistor T7 is turned on, the initialization power supply voltage VINT can be transmitted to the first electrode of the light-emitting device LED.

[0061] The light-emitting device LED can be connected between the second electrode of the sixth transistor T6 and the second power supply voltage VSS. According to some example embodiments, the first power supply voltage VDD can be greater than the second power supply voltage VSS. The light-emitting device LED can be an organic light-emitting diode including an organic light-emitting layer. According to some example embodiments, the light-emitting device LED can be an inorganic light-emitting device, a light-emitting device including a plurality of nano light-emitting diodes, or a light-emitting device using a quantum dot effect to emit light.

[0062] When the scan signal is supplied to the third transistor T3 for a sufficient time, a voltage corresponding to the difference between the data voltage and the threshold voltage (absolute value of the threshold voltage) of the first transistor T1 (e.g., the first gate voltage) can be supplied to the first node N1 through the diode-connected first transistor T1. However, when the pulse width of the scan signal becomes short, the threshold voltage compensation of the first transistor T1 is not fully performed, and for the same data voltage, a second gate voltage lower than the first gate voltage can be supplied to the first node N1. Accordingly, the drive current (or compensation current) flowing through the first transistor T1 can be increased.

[0063] On the other hand, when the change of the screen from an image of a black gray level (low gray image) to an image of a white gray level (high gray image) reaches a sudden gray level change, the step-up efficiency may be reduced due to the parasitic capacitance of the light-emitting device LED or the like, and the step-up efficiency is the ratio of the gray level immediately after the screen change (e.g., the actual gray level of the first frame immediately after the screen change) to the target gray level (e.g., ideal luminance) of the current image immediately after the screen change. For example, the lower the display luminance, the more image defects such as afterimages caused by the reduced step-up efficiency can be visually recognized.

[0064] The display device according to some example embodiments of the present invention can increase the drive current of the first transistor T1 by reducing the pulse width of the scan signal supplied to the second transistor T2 and the third transistor T3 as the luminance decreases. Accordingly, when the screen changes from a low gray level to a high gray level, the step-up efficiency can be improved.

[0065] Figure 3 is a timing diagram illustrating an example of signals supplied to Figure 2 the pixels.

[0066] Refer to Figure 1 、 Figure 2 and Figure 3 . The pulse widths of the scan signals Si-1 and Si of the first frame F1 and the pulse widths of the scan signals Si-1 and Si of the second frame F2 may be different from each other.

[0067] Figure 3 The timing diagram of

[0068] The display device 1000 can emit light with a first display brightness DB1 in the first frame F1, and the display device 1000 can emit light with a second display brightness DB2 lower than the first display brightness DB1 in the second frame F2. For example, the first display brightness DB1 can be approximately 50 nits, and the second display brightness DB2 can be approximately 4 nits.

[0069] At a first time point t1 of the first frame F1, the i-th emission control signal Ei can transition from a gate-on voltage to a gate-off voltage, and the fifth transistor T5 and the sixth transistor T6 can be turned off. The gate-off voltage of the i-th emission control signal Ei can be maintained until the sixth time point t6. The period from the first time point t1 to the sixth time point t6 can be defined as the non-emission period of the first frame F1. The remaining period of the first frame F1 except for the non-emission period can be the light-emitting period. The i-th emission control signal Ei can transition from the gate-off voltage to the gate-on voltage at the sixth time point t6.

[0070] After that, at a second time point t2, the (i - 1)-th scan signal Si-1 can transition from a gate-off voltage to a gate-on voltage, and the fourth transistor T4 and the seventh transistor T7 can be turned on. The gate-on voltage of the (i - 1)-th scan signal Si-1 can be maintained until the third time point t3. At this time, the gate voltage of the first transistor T1 and the anode voltage of the light-emitting device LED can be initialized. The (i - 1)-th scan signal Si-1 can transition from the gate-on voltage to the gate-off voltage at the third time point t3.

[0071] At a fourth time point t4, the i-th scan signal Si can transition from a gate-off voltage to a gate-on voltage, and the second transistor T2 and the third transistor T3 can be turned on. The gate-on voltage of the i-th scan signal Si can be maintained until the fifth time point t5. At this time, data can be written into the first transistor T1, and the threshold voltage of the first transistor T1 can be compensated. The i-th scan signal Si can transition from the gate-on voltage to the gate-off voltage at the fifth time point t5.

[0072] The scan signals Si-1 and Si in the first frame F1 can have a first pulse width PW1 corresponding to the first display brightness DB1.

[0073] Similar to the operation in the first frame F1, the i-1th scan signal Si-1 and the i-th scan signal Si may be sequentially supplied to the pixel P in the non-emission period of the second frame F2. In the second frame F2, the interval between the second time point t2 and the third time point t3′ and the interval between the fourth time point t4 and the fifth time point t5′ may each be smaller than the first pulse width PW1. That is, the second pulse width PW2 of the scan signals Si-1 and Si supplied in the second frame F2 may be smaller than the first pulse width PW1. In this case, the interval between the third time point t3′ and the fourth time point t4 of the second frame F2 may be larger than the interval between the third time point t3 and the fourth time point t4 of the first frame F1.

[0074] The threshold voltage compensation time of the first transistor T1 in the second frame F2 having relatively low display brightness may be shorter than the threshold voltage compensation time of the first transistor T1 in the first frame F1. Therefore, the gate voltage (or compensation point) of the first transistor T1 in the second frame F2 may be increased, and the stepping efficiency at low brightness may be improved.

[0075] Figure 4A , Figure 4B and Figure 4C is a graph illustrating an example of a pulse width of a scan signal determined according to display brightness.

[0076] refer to Figure 2 , Figure 3 , Figure 4A , Figure 4B and Figure 4C , the pulse width SPW of the scanning signal can be adjusted according to the display brightness DB and the brightness level DBV.

[0077] According to some example embodiments, when the display brightness DB is higher than a reference brightness (eg, a predetermined reference brightness) R_DB, the scan signal may have a first pulse width (eg, Figure 3 In other words, when the display brightness DB is higher than the reference brightness R_DB, the pulse width SPW of the scanning signal may not be changed. For example, the reference brightness R_DB may be set to about 100 nits. The reference brightness R_DB is not limited thereto. For example, the reference brightness R_DB may be determined to be a value less than or equal to about 10 nits corresponding to a relatively low brightness.

[0078] According to some example embodiments, Figure 4A As shown in FIG. 1 , when the display brightness DB is equal to or lower than the reference brightness R_DB, the scan signal may have a second pulse width (eg, Figure 3in PW2). The second pulse width PW2 may be shorter than the first pulse width PW1. However, the second pulse width PW2 may have a length of 50% or more of the first pulse width PW1. Thus, a required minimum threshold voltage compensation period can be ensured.

[0079] According to some example embodiments, when the display brightness DB is equal to or lower than a reference brightness R_DB, the pulse width SPW of the scan signal may decrease as the display brightness DB decreases. For example, as Figure 4B shown, the pulse width SPW of the scan signal may gradually decrease corresponding to a predetermined display brightness DB. In this case, as the display brightness DB is decreased, a period for changing the pulse width SPW of the scan signal may be shortened. In another embodiment, as Figure 4C shown, the pulse width SPW of the scan signal may linearly decrease as the display brightness DB decreases. Thus, the pulse width SPW of the scan signal may be determined according to the display brightness DB.

[0080] However, the pulse width SPW of the scan signal according to the display brightness DB is not limited thereto. The minimum pulse width of the scan signal may be set to not less than 40% to 50% of the maximum pulse width of the scan signal. For example, when the maximum pulse width of the scan signal is about 4.5 μm, the minimum pulse width of the scan signal may be about 2 μm.

[0081] As described above, the display device according to some example embodiments of the present invention may improve the stepping efficiency at low brightness by reducing the pulse width SPW of the scan signal corresponding to low brightness.

[0082] Figure 5 is a diagram Figure 1 of an example of a scan driver included in the display device.

[0083] Refer to Figure 5 , the scan driver 200 may include a plurality of stages ST1 to ST4. Each of the first stage ST1 to the fourth stage ST4 may be connected to each of the first scan line to the fourth scan line, and may be driven corresponding to clock signals CLK1 and CLK2. Such stages ST1 to ST4 may be configured with substantially the same circuit.

[0084] Each of the stages ST1 to ST4 may include a first input terminal 101, a second input terminal 102, a third input terminal 103, and an output terminal 104.

[0085] The first input terminal 101 may receive an output signal (e.g., a scan signal) from a previous stage or a scan start signal SSP. For example, the first input terminal 101 of the first stage ST1 may receive the scan start signal SSP, and the first input terminal 101 of the second stage ST2 may receive the scan signal S1 output from the first stage ST1.

[0086] According to some example embodiments, the second input terminal 102 of the k-th stage (k is a natural number less than n) may receive the first clock signal CLK1, and the third input terminal 103 may receive the second clock signal CLK2. On the other hand, the second input terminal 102 of the (k + 1)-th stage may receive the second clock signal CLK2, and the third input terminal 103 may receive the first clock signal CLK1.

[0087] The first clock signal CLK1 and the second clock signal CLK2 may have the same period and phase that do not overlap with each other. That is, the gate-on periods of the first clock signal CLK1 and the second clock signal CLK2 may not overlap with each other. For example, when the period during which a scan signal is supplied to a scan line is one horizontal period, each of the clock signals CLK1 and CLK2 may have a period of 2 horizontal periods and may be supplied in different horizontal periods.

[0088] Although Figure 5 it is shown that two clock signals are supplied to the scan driver 200, the number of clock signals supplied to the scan driver 200 is not limited thereto. For example, according to the configuration of the stages, three or more clock signals may be provided to the scan driver 200.

[0089] In addition, the stages ST1 to ST4 may be supplied with a first voltage VGL and a second voltage VGH. The first voltage VGL and the second voltage VGH may have DC voltage levels. The second voltage VGH may have a higher value than the first voltage VGL.

[0090] According to some example embodiments, the first voltage VGL may be set as a gate-on voltage, and the second voltage VGH may be set as a gate-off voltage. For example, when the pixel P and the scan driver 200 are composed of PMOS transistors, the first voltage VGL may correspond to a logic low level, and the second voltage VGH may correspond to a logic high level. The first voltage VGL and the second voltage VGH are not limited thereto. For example, the first voltage VGL and the second voltage VGH may be set according to the type of transistor, the usage environment of the display device, etc.

[0091] Figure 6A is a block diagram of an example of the stages included in the Figure 5 illustrated scan driver. Figure 6B is an illustration Figure 6ACircuit diagram of an example of an output buffer unit included in a stage.

[0092] Reference Figure 5 、 Figure 6A and Figure 6B and, the i-th stage STi may include a node control unit 120 and an output buffer unit 140, where i is a natural number less than or equal to n.

[0093] The node control unit 120 may include a plurality of transistors and at least one capacitor for controlling the voltages of the first node Q and the second node QB in response to an output signal of the previous stage (e.g., the (i - 1)-th scan signal Si - 1 or the (i - 1)-th carry signal). The node control unit 120 may supply a gate cut-off voltage to the first node Q and a gate-on voltage to the second node QB in response to the (i - 1)-th scan signal Si - 1 and the second clock signal CLK2.

[0094] The output buffer unit 140 may receive one of the first clock signal CLK1 and the second clock signal CLK2 provided from the timing controller 500.

[0095] When the voltage of the second node QB has a gate-on voltage, the output buffer unit 140 may apply the first clock signal CLK1 to the output terminal NO. When the voltage of the second node QB rises, the output buffer unit 140 may raise the voltage of the output terminal NO to a gate cut-off voltage. For example, as Figure 6B shown in, the output buffer unit 140 may include a pull-up transistor TU and a pull-down transistor TD.

[0096] The pull-up transistor TU may be turned on or off according to the voltage state of the first node Q, and may apply the second voltage VGH to the output terminal NO when the pull-up transistor TU is in an on state.

[0097] The pull-down transistor TD may be turned on or off according to the voltage state of the second node QB, and may apply the first clock signal CLK1 to the output terminal NO when the pull-down transistor TD is in an on state.

[0098] The gate-on period of the first clock signal CLK1 and the second clock signal CLK2 may be changed according to the brightness level DBV (or display brightness). For example, the gate-on periods of the first clock signal CLK1 and the second clock signal CLK2 may have a first pulse width corresponding to a first display brightness, and the gate-on periods of the first clock signal CLK1 and the second clock signal CLK2 may have a second pulse width corresponding to a second display brightness lower than the first display brightness. The second pulse width may be shorter than the first pulse width.

[0099] The scan driver 200 may determine the pulse widths of the scan signals S1 to S4 based on the widths of the gate-on periods of the first clock signal CLK1 and the second clock signal CLK2 supplied from the timing controller 500.

[0100] Accordingly, when the image suddenly changes from a low gray level to a high gray level, the gate voltage of the driving transistor is reduced by reducing the compensation time of the driving transistor ( Figure 2 the first transistor T1 in ) of the pixel P. That is, the driving current of the driving transistor is increased. Therefore, the step efficiency at the time of the transition from a low gray level image to a high gray level image can be improved.

[0101] Figure 7 is a timing diagram Figure 5 illustrating an example of the operation of the scan driver shown.

[0102] Except for showing the clock signals CLK1 and CLK2 and the scan start signal SSP, the timing diagram of this embodiment is substantially the same as Figure 3 the timing diagram of. Accordingly, the same reference numerals refer to the same or corresponding components, and redundant explanations are omitted.

[0103] Referring to Figure 1 , Figure 5 , Figure 6A , Figure 6B and Figure 7 , the pulse widths of the scan signals S1 and S2 of the first frame F1 and the second frame F2 may be different from each other. In addition, the pulse widths (gate-on periods GOP) of the first clock signal CLK1 and the second clock signal CLK2 in the first frame F1 and the second frame F2 may be different from each other.

[0104] The display device 1000 may emit light having a first display brightness DB1 in the first frame F1, and the display device 1000 may emit light having a second display brightness DB2 lower than the first display brightness DB1 in the second frame F2. The scan start signal SSP may be supplied to the scan driver 200 with a constant pulse width PW0 regardless of the display brightness.

[0105] The scan signals S1 and S2 may be output synchronously with the gate-on period GOP of the first clock signal CLK1 or the second clock signal CLK2.

[0106] The timing controller 500 may output the clock signals CLK1 and CLK2 having a gate-on period GOP with a first pulse width PW1 corresponding to the first display brightness DB1, and may output the clock signals CLK1 and CLK2 having a gate-on period GOP with a second pulse width PW2 corresponding to the second display brightness DB2. The second pulse width PW2 may be shorter than the first pulse width PW1.

[0107] During the first frame F1, the scan driver 200 may sequentially apply scan signals S1 and S2 having a first pulse width PW1 in synchronization with the gate-on period GOP of the first clock signal CLK1 or the second clock signal CLK2. During the second frame F2, the scan driver 200 may sequentially apply scan signals S1 and S2 having a second pulse width PW2 in synchronization with the gate-on period GOP of the first clock signal CLK1 or the second clock signal CLK2.

[0108] According to some example embodiments, the width of the gate-on period GOP of the clock signals CLK1 and CLK2 may decrease as the display brightness decreases.

[0109] In this way, the gate-on periods GOP of the clock signals CLK1 and CLK2 supplied to the scan driver 200 may be changed according to a change in the display brightness.

[0110] Figure 8 is a timing diagram illustrating an example of signals supplied to Figure 2 the pixels.

[0111] Except that the gate-off period (non-emission period) of the emission control signal varies according to the display brightness (brightness level DBV), the timing diagram of this embodiment is substantially the same as Figure 3 the timing diagram of. Accordingly, the same reference numerals refer to the same or corresponding components, and redundant explanations are omitted.

[0112] Refer to Figure 1 and Figure 8 . The pulse widths of the scan signals Si-1 and Si in the first frame F1 and the second frame F2 may be different from each other. The display device 1000 may emit light having a first display brightness DB1 in the first frame F1, and the display device 1000 may emit light having a second display brightness DB2 lower than the first display brightness DB1 in the second frame F2.

[0113] According to some example embodiments, when the display brightness (or brightness level DBV) is equal to or lower than a predetermined reference brightness, the gate-off period of the emission control signal Ei (i.e., the non-emission periods NEP1 and NEP2) may vary according to the display brightness. That is, when the display brightness is equal to or lower than the reference brightness, the display brightness may be determined according to the widths of the non-emission periods NEP1 and NEP2 of the emission control signal Ei.

[0114] For example, the first non-emission period NEP1 corresponding to the first display brightness DB1 may be shorter than the second non-emission period NEP2 corresponding to the second display brightness DB2. Additionally, the first pulse width PW1 of the scan signals Si-1 and Si corresponding to the first display brightness DB1 may be greater than the second pulse width PW2 of the scan signals Si-1 and Si corresponding to the second display brightness DB2.

[0115] As Figure 8 shown, the pulse width of the scan signals Si-1 and Si may decrease as the display brightness decreases, and the width of the non-emission period (gate cut-off period) of the emission control signal Ei may increase.

[0116] As described above, in a display device according to some exemplary embodiments of the present invention, the driving current of the pixel P can be increased by decreasing the pulse width of the scan signal supplied to the pixel P as the display brightness DB decreases. Therefore, the step efficiency and image quality when changing an image from a low gray level to a high gray level can be improved.

[0117] The foregoing description is intended to illustrate and describe aspects of some exemplary embodiments of the present invention. Additionally, the foregoing are only some illustrative and explanatory exemplary embodiments of the present invention, and as described above, the present invention can be used in various other combinations, modifications, and environments. Changes or modifications can be made within the scope of the inventive concept disclosed herein, within the scope equivalent to those described, and / or within the technical or knowledge scope of those skilled in the art. Therefore, the foregoing description of the present invention is not intended to limit the present invention to the disclosed embodiments. Additionally, the appended claims and their equivalents should be construed to include other embodiments.

Claims

1. A display device, comprising: a display panel including a plurality of pixels; a data driver configured to supply data signals to corresponding pixels through data lines; a scan driver configured to supply scan signals to corresponding pixels among the plurality of pixels through scan lines, wherein the scan signals are configured to write the data signals into the corresponding pixels; and a timing controller configured to control a pulse width of the scan signals supplied to the corresponding pixels according to an overall display brightness of the display panel.

2. The display device according to claim 1, wherein, The scan driver is configured to output the scan signals having a first pulse width corresponding to a first display brightness, and is configured to output the scan signals having a second pulse width corresponding to a second display brightness lower than the first display brightness.

3. The display device according to claim 2, wherein, The second pulse width is shorter than the first pulse width.

4. The display device according to claim 1, wherein, The pulse width of the scan signals decreases as the display brightness decreases.

5. The display device according to claim 1, wherein, The scan driver is configured to output the scan signals having a first pulse width in response to the display brightness being higher than a predetermined reference brightness, and wherein the scan driver is configured to output the scan signals having a second pulse width shorter than the first pulse width in response to the display brightness being equal to or lower than the predetermined reference brightness.

6. The display device according to claim 5, wherein, In response to the display brightness being equal to or lower than the predetermined reference brightness, the pulse width of the scan signals decreases as the display brightness decreases.

7. The display device according to claim 1, wherein, The scan driver is configured to determine the pulse width of the scan signals based on a width of a gate-on period of a clock signal supplied from the timing controller.

8. The display device according to claim 7, wherein, The timing controller is configured to output the clock signal having a first pulse width corresponding to a first display brightness, and is configured to output the clock signal having a second pulse width corresponding to a second display brightness lower than the first display brightness, and wherein the second pulse width is shorter than the first pulse width.

9. The display device according to claim 7, wherein, The width of the gate-on period of the clock signal decreases as the display brightness decreases, and wherein the timing controller is configured to convert the display brightness into a brightness level of a digital value, and is configured to output the clock signal having a gate-on period corresponding to the brightness level.

10. The display device according to claim 1, further comprising: a emission driver configured to supply emission control signals to the corresponding pixels through emission control lines, and wherein in response to the display brightness being equal to or lower than a predetermined reference brightness, the display brightness decreases as a width of a gate-off period of the emission control signals increases.

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