Thin film resistors and capacitors share a single layer

Abstract

An integrated circuit (IC) (295) includes a substrate (208) having a semiconductor surface layer (209) including a functional circuit (180) having interconnected transistors, a dielectric layer (230) thereon, and a metal stack including metal levels above the dielectric layer (230). A thin film resistor (TFR) layer (260a, 260b) including at least one metal is located within the metal stack. At least one capacitor (280, 285) is located in the metal stack, including a capacitor dielectric layer (245) above a metal bottom plate formed by one of the metal levels (240). A capacitor top plate (260a) is formed on the capacitor dielectric layer (245), and at least one resistor (290) formed by the same TFR layer is lateral to the capacitor (280, 285).

Description

Technical Field

[0001] The present application relates to the processing of integrated circuit (IC) devices having thin film resistors and capacitors both within a metal stack, and the resulting ICs of this type. Background Art

[0002] Some IC devices include thin film resistors (TFRs). Silicon chromium (SiCr) has been used for TFRs for many years due to its high resistance in thin film form, relatively low temperature coefficient of resistance (TCR), and ability to carry relatively high current density. TFRs are formed within a metal stack (e.g., between metal 1 (M1) and M2, or between M2 and M3) during back-end of line (BEOL) processing, and above functional circuits formed during front-end of line (FEOL) processing of the underlying semiconductor surface layer. Such IC devices may also include capacitors within the metal stack, also known as metal-insulator-metal (MIM) capacitors. Summary of the invention

[0003] Some aspects described include a method of manufacturing an IC device having thin film resistors and capacitors within a metal stack. At least one dielectric layer is deposited on a semiconductor surface layer on a substrate having a plurality of IC dies formed in the semiconductor surface layer, wherein each IC die includes a functional circuit including a plurality of interconnected transistors. A metal layer is formed over a dielectric layer for a bottom plate of a MIM capacitor as defined herein to have individual plates separated by a capacitor dielectric layer, each plate including at least one metal.

[0004] At least one capacitor dielectric layer is deposited on the metal layer. A TFR layer containing at least one metal is deposited on the capacitor dielectric layer. A pattern is formed on the TFR layer. The TFR layer is etched using the pattern, including defining a top plate containing the TFR layer on the capacitor dielectric layer, and defining a portion of the TFR layer in the lateral direction of the MIM capacitor to form a resistor containing the TFR layer (referred to herein as "TFR"). The pattern is formed on the capacitor dielectric layer, the capacitor dielectric layer is etched, and then the metal layer is etched to define the bottom plate, thereby completing the MIM capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a flow chart illustrating steps in an example method of manufacturing an IC including at least one TFR and at least one MIM capacitor, wherein according to one example aspect, the same TFR layer is used at a single mask level to form the TFR and also to form a top plate of the MIM capacitor.

[0006] Figure 2A-2Iis a cross-sectional diagram illustrating a process progression of an example method of forming an IC having at least one TFR and at least one MIM capacitor, wherein the same TFR layer is used to form the TFR and for a top plate of the MIM capacitor according to one example aspect. DETAILED DESCRIPTION

[0007] The drawings are not necessarily drawn to scale. In the drawings, similar reference numerals represent similar or equivalent elements. In the drawings and this specification, the order of the illustrated actions or events is not limiting, as some actions or events may occur in a different order and / or simultaneously with other actions or events. In addition, some illustrated actions or events may be optional to implement the methods described in accordance with this specification.

[0008] As used herein, without further qualification, the terms "coupled to" or "coupled with..." (and similar expressions) describe either an indirect or direct electrical connection. Thus, if a first device is "coupled" to a second device, the connection may be achieved through a direct electrical connection with only parasitic effects in the path, or through an indirect electrical connection via intervening objects including other devices and connectors. For indirect coupling, the intervening objects generally do not modify the information of the signal, but may adjust its current level, voltage level, and / or power level.

[0009] Figure 1 is a flow chart illustrating steps in an example method 100 of manufacturing an IC including at least one TFR and at least one MIM capacitor, wherein according to one example aspect, the same TFR layer is used at a single mask level to form the TFR and also to form a top plate of the MIM capacitor. Step 101 includes depositing at least one dielectric layer on a substrate (e.g., a wafer) including a semiconductor surface layer having a plurality of IC dies formed therein, wherein each IC die includes a functional circuit including a plurality of interconnected transistors. The substrate may include a bulk substrate material such as silicon or an epitaxial layer on a bulk substrate material (see substrate 208 having a semiconductor surface layer 209, wherein the substrate 208 includes a semiconductor surface layer 209, wherein the semiconductor surface layer 209 includes a plurality of IC dies formed therein. Figure 2A-2I The functional circuit 180 is formed in the semiconductor surface layer 209). Alternatively, the substrate may include silicon germanium, other Group IV materials, or other semiconductor materials including III-V and II-VI compound semiconductor materials.

[0010] As used herein, a functional circuit implements and performs a desired function, such as the function of a digital IC (e.g., a digital signal processor) or an analog IC (e.g., an amplifier or a power converter), and in one aspect, a BiCMOS (MOS and bipolar) IC. The capabilities of the functional circuits provided on the described ICs can vary, for example ranging from simple devices to complex devices. The specific functions contained in the functional circuits are not critical to the described ICs. The functional circuits (see the description below) are described in detail in the following sections. Figure 2A-2I The functional circuit 180 in FIG. 1 is typically formed in the substrate before forming the TFR described below.

[0011] Figure 2A The IC die in processing is shown after step 101, which shows a dielectric layer 230 on a semiconductor surface layer 209 on a substrate 208 having a plurality of IC dies formed in the semiconductor surface layer 209, wherein the IC dies include functional circuits 180 including a plurality of interconnected transistors. The dielectric layer 230 electrically isolates the FEOL components on the IC from its BEOL interconnects and components.

[0012] Figure 2A-2I The dielectric layer 230 shown is a pre-metal dielectric (PMD) layer, so the bottom plate of the MIM capacitor is Figure 2A-2I Described as Metal 1 (M1) in the MIM capacitor. However, the dielectric layer directly below the bottom plate of the MIM capacitor may also be an interlayer dielectric (ILD) layer so that the bottom plate of the MIM capacitor may also be M2, M3, or up to the top M layer-1M layer. Dielectric layer 230 may include a silicon oxide layer derived from tetraethoxysilane (TEOS). TEOS deposition for non-plasma deposition processes may include low pressure CVD (LPCVD) at a pressure of about 300 mTorr and a temperature of about 700°C. However, other dielectric layers including deposited silicon oxide may also be used, such as organic silicate glass (OSG), low-k dielectrics (i.e., a smaller dielectric constant relative to silicon dioxide), doped dielectric layers such as fluorine-doped quartz glass (FSG), or SiN layers or variants thereof (e.g., SiON). The thickness range of dielectric layer 230 is typically for a PMD layer of to For the ILD layer, it is usually 1.0μ to 1.4μm.

[0013] Step 102 includes forming a metal layer 240 over dielectric layer 230 , which will comprise a bottom plate for the capacitor. Figure 2BThe IC die in process is shown after step 102, showing a metal layer 240 over dielectric layer 230. Metal layer 240 may comprise AlCu, typically containing 0.5% to 4% copper by weight. Alternatively, metal layer 240 may comprise only copper, in which case a damascene process ( Figure 2A-2I The inlay process is not shown).

[0014] Step 103 includes depositing at least one capacitor dielectric layer 245 on the metal layer 240 . Figure 2C The IC die in processing is shown after step 103, showing at least one capacitor dielectric layer 245 on the metal layer 240. The thickness of the capacitor dielectric layer is typically to And can be a single layer or contain two or more layers. The dielectric stack may include at least one silicon nitride layer. In one embodiment, the capacitor dielectric layer 245 comprises a silicon oxide-silicon nitride (SiN)-silicon oxide (ONO) stack, wherein the ONO stack can act as an anti-reflective coating (ARC) for the bottom metal plate lithography and patterning described below.

[0015] Step 104 includes depositing a TFR layer including at least one metal on the capacitor dielectric layer 245. The TFR layer deposition process may include a direct current (DC) or radio frequency (RF) sputtering process. Figure 2D The IC die in processing after step 104 is shown, showing a TFR layer 260 on the capacitor dielectric layer 245. The TFR layer 260 may include SiCr or its alloys, such as carbon-containing materials, including SiCCr, SiCOCr (where C may be 1% to 50% by atomic percentage); or NiCr or its alloys, such as NiCrFe: 61% Ni, 15% Cr, 24% Fe (all in atomic percentage). The thickness of the TFR layer 260 is typically 10nm to 100nm, such as 25nm to 35nm thick, or about 30nm thick in one specific aspect.

[0016] Step 105 includes forming a first pattern on the TFR layer 260 . Figure 2E The IC die in processing is shown after forming a pattern, such as a photoresist (PR) pattern 270, on the TFR layer 260. Step 106 includes etching the TFR layer 260 using the PR pattern 270 to simultaneously define a top plate for a capacitor and a patterned resistor, wherein the top plate of the capacitor includes the TFR layer on the capacitor dielectric layer 245 (shown as TFR portion 260a), and the patterned resistor includes the TFR layer on the side of the capacitor (shown as TFR portion 260b). Figure 2FThe IC die in processing is shown after etching the TFR layer 260. The etching gas used for plasma etching the TFR layer 260 typically includes flowing O2, Cl2, and at least one carbon-halogen gas. For example, O2, Cl2, and CF4 and optionally Ar can be used to etch SiCr. In addition, other gases can also be used to etch the TFR layer 260, such as CHF3 or CH2F2, as an alternative or in addition to the CF4 and / or N2 also used.

[0017] Step 107 includes forming a second pattern on the capacitor dielectric layer 245, and then etching the capacitor dielectric layer 245 and the metal layer 240 to define the bottom plate, thereby completing the MIM capacitor. For this patterning, the capacitor dielectric layer 245 can be used as an anti-reflective coating (ARC), especially when it includes silicon nitride or silicon oxynitride. The metal wiring required for connecting to the functional circuit 180 is usually also defined in the step 107 of etching the metal layer 240.

[0018] Figure 2G The IC die is shown in processing after etching the capacitor dielectric layer 245 and the metal layer 240 therebelow to define the bottom plate to complete the MIM capacitor. The pattern used in step 107 provides a larger area of ​​the capacitor dielectric layer 245 and the metal layer 240 used to define the MIM capacitor than the area of ​​the TFR portion 260a used for the MIM capacitor (after step 106 of the TFR layer etching) to provide a location for placing vias (shown as via area 278 below) for contacting the bottom plate of the MIM capacitor including the metal layer 240.

[0019] Optionally, a hard mask / etch stop layer may be deposited on the TFR layer 260 before it is patterned (before step 105). The hard mask / etch stop layer may comprise an LPCVD process for TEOS-based deposition at a pressure of about 300 m Torr and a temperature of about 700° C. The thickness of the hard mask / etch stop layer may range from about 100 to about 1000 Å. to Such a hard mask / etch stop layer may not be needed if the TFR etch process does not substantially include over-etching of the TFR layer 260 . The top silicon oxide layer in the ONO stack for the capacitor dielectric layer 245 may serve as an etch stop for the TFR layer 260 .

[0020] Figure 2H The IC die is shown in processing after an ILD layer, such as shown as ILD layer 265, is deposited and then the wafer surface is planarized using, for example, chemical mechanical polishing (CMP). Fig.2I The IC die in processing is shown after a via is etched in the ILD layer 265 and then filled with a conductive material (eg, W) to form a via region 278. Fig.2IAs shown, on IC 295 are MIM capacitors 280, MIM capacitors 285, and TFR 290 including TFR portion 260b, and patterned metal layer 275 over via region 278. Although not shown, MIM capacitors 280, 285, and TFR 290 are connected to nodes within functional circuit 180. Since both TFR layer 260 and capacitor dielectric layer 245 are typically thin, a single contact process can be used to contact the bottom plates of MIM capacitors 280, 285 and TFR 290 including the TFR layer. This is because the height difference between the via etch in the capacitor area and standard metal 1 circuitry is small. This can also eliminate the need to have a hard mask layer over the TFR layer.

[0021] The wafer processing may then be completed by conventional BEOL processing, including forming one or more additional metal layers thereon (including a top metal layer). The top metal layer may include aluminum (or aluminum alloy) or copper. A passivation protective coating (PO) is then typically applied, and the PO is then patterned. The PO layer includes at least one dielectric layer, such as silicon oxide, silicon nitride, or SiON.

[0022] Advantages of the described process include:

[0023] 1. Allows contacts to be provided to the MIM capacitor and the resistor including the TFR layer in the same mask level.

[0024] 2. By using the TFR layer as the top plate of the MIM capacitor, the cost of 1 mask and increased cycle time are eliminated.

[0025] 3. Allows thinning of the TFR layer to provide higher sheet resistance for IC designers.

[0026] 4. Allows thinning or elimination of the via etch stop layer on top of the TFR layer.

[0027] 5. Improve the process window for metal (capacitor bottom plate and interconnect) patterning.

[0028] 6. Undesirable parasitic capacitors are eliminated or significantly reduced compared to MIM capacitors with TiN top plates created by post-etching TiN recesses.

[0029] 7. The isolation area design rules and spacing rules between metal lines are relaxed, which will benefit IC designers because the top plate of the MIM capacitor is thinner compared to the MIM capacitor with a thicker top plate material (such as TiN), and the etching selectivity of the top plate material relaxes the spacing rules between metal lines, for example, when the TFR layer is a chromium alloy (such as SiCr).

[0030] Example

[0031] For the current standard BEOL process of forming MIM capacitors using a TiN top plate, an 85% variation in top plate thickness across the wafer has been found. For the described process of forming the top plate of a MIM capacitor with a TFR layer, there is only a 12% variation in top plate thickness across the wafer. TiN and TFR resistor segments with different width and length (W / L) combinations have been tested, and the sheet resistance at each die location on the wafer has been extracted. The sheet resistance variation is evaluated as the 6-sigma of the sheet resistance divided by the mean. The sheet resistance is directly converted to thickness variation. Cross-sectional images of the capacitors were also collected to verify these measurements.

[0032] Some aspects described may be used to form semiconductor dies that may be integrated into various assembly processes to form a variety of different devices and related products. The semiconductor die may include various components therein and / or layers thereon, including barrier layers, dielectric layers, device structures, active components and passive components, including source regions, drain regions, bit lines, bases, emitters, collectors, wires, conductive vias, etc. In addition, the semiconductor die may be formed by various processes including bipolar, insulated gate bipolar transistors (IGBTs), CMOS, BiCMOS, and MEMS.

[0033] Modifications may be made in the described embodiments and other embodiments are possible within the scope of the claims.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: depositing a dielectric layer on a semiconductor surface layer having a plurality of IC dies formed therein, wherein each IC die comprises a functional circuit comprising a plurality of interconnected transistors; forming a metal layer over the dielectric layer, including a bottom plate for a capacitor; depositing at least one capacitor dielectric layer on the metal layer; Depositing a thin film resistor layer, i.e., a TFR layer, on the at least one capacitor dielectric layer, the TFR layer comprising silicon chromium SiCr; forming a first pattern on the TFR layer; etching the TFR layer using the first pattern, including defining a top plate for the capacitor, the top plate including the TFR layer, and defining the TFR layer laterally of the capacitor to form a resistor including the TFR layer; as well as A second pattern is formed on the at least one capacitor dielectric layer, the at least one capacitor dielectric layer is etched, and then the metal layer is etched to define the bottom plate for the capacitor. The method according to claim 1 , wherein the TFR layer further comprises nickel (Ni). The method according to claim 1 , wherein the TFR layer further comprises iron (Fe). The method of claim 1 , wherein the TFR layer further comprises carbon. The method according to claim 1 , wherein the TFR layer has a thickness of 10 nm to 100 nm. The method according to claim 5 , wherein the TFR layer has a thickness of 25 nm to 35 nm.

7. The method according to claim 1, further comprising: Before etching the TFR layer, a hard mask layer is deposited on the TFR layer. 8 . The method of claim 7 , wherein depositing the hard mask layer comprises using tetraethoxysilane (TEOS) as a precursor material.

9. The method of claim 1, wherein the capacitor dielectric layer has to and includes at least two dielectric layers.

10. The method of claim 9, wherein the at least two dielectric layers comprise silicon nitride or silicon oxynitride layers.

11. The method of claim 1, wherein etching the capacitor dielectric layer and etching the metal layer both utilize the second pattern on the at least one capacitor dielectric layer.

12. An integrated circuit IC, comprising: a substrate comprising a semiconductor surface layer, the semiconductor surface layer comprising a functional circuit, the functional circuit comprising a plurality of interconnected transistors; a dielectric layer on the semiconductor surface layer; a metal stack comprising a plurality of metal levels above the dielectric layer; A resistor in the metal stack, the resistor comprising a thin film resistor layer (TFR layer), the TFR layer comprising silicon chromium SiCr; a capacitor within the metal stack, the capacitor comprising a capacitor dielectric layer over a bottom plate formed by one of the plurality of metal levels; as well as A top plate for the capacitor, the top plate comprising the TFR layer on the capacitor dielectric layer, wherein the resistor is lateral to the capacitor. The IC of claim 12 , wherein the TFR layer further comprises nickel (Ni). The IC of claim 12 , wherein the TFR layer further comprises iron (Fe).

15. The IC of claim 12, wherein the TFR layer further comprises carbon. The IC of claim 12 , wherein the TFR layer has a thickness of 10 nm to 100 nm. The IC of claim 16 , wherein the thickness of the TFR layer is 25 nm to 35 nm.

18. The IC of claim 12, wherein the dielectric layer comprises a pre-metal dielectric (PMD) layer.

19. The IC of claim 12, further comprising: A hard mask layer is formed on the TFR layer.

20. The IC of claim 12, wherein the capacitor dielectric layer has to and includes at least two dielectric layers.

21. The IC of claim 20, wherein the at least two dielectric layers comprise silicon nitride or silicon oxynitride layers.

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