Non-volatile memory device

Abstract

A nonvolatile memory device is provided. The nonvolatile memory device includes a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of ground selection lines, a plurality of word lines, and a plurality of string selection lines; a block selection circuit connected with the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, and providing respective driving voltages to the plurality of ground selection lines, the plurality of word lines, and the plurality of string selection lines, respectively, in response to a block selection signal; and a block unselection circuit connected only with a specific string selection line among the plurality of string selection lines, and providing an off voltage to only the specific string selection line in response to a block unselection signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0034572, filed on March 26, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the inventive concept described herein relate to a semiconductor memory, and more specifically, to a non-volatile memory device. Background Technology

[0003] Semiconductor memory devices are classified into volatile memory devices (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) that lose the data stored therein when the power is turned off, and non-volatile memory devices (such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM) or ferroelectric RAM (FRAM)) that retain the data stored therein even when the power is turned off.

[0004] Flash memory devices are being widely used as high-capacity storage media. Currently, with the development of 3D flash memory devices, the integration level of flash memory devices is increasing, and various technologies are being developed to control flash memory devices with improved integration. Summary of the Invention

[0005] Embodiments of the inventive concept provide a non-volatile memory device that can reduce costs by reducing the area of ​​the peripheral circuitry (specifically, the row decoder) of the non-volatile memory device.

[0006] According to an exemplary embodiment, a non-volatile memory device includes: a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of ground select lines, a plurality of word lines, and a plurality of string select lines; a block select circuit connected to the plurality of ground select lines, the plurality of word lines, and the plurality of string select lines, and providing corresponding drive voltages to the plurality of ground select lines, the plurality of word lines, and the plurality of string select lines respectively in response to a block select signal corresponding to the first memory block; and a block unselected circuit connected only to a specific string select line among the plurality of string select lines, and providing a cutoff voltage to the specific string select line only in response to a block unselected signal not corresponding to the first memory block. The number of specific string select lines may be less than the number of the plurality of string select lines.

[0007] According to an exemplary embodiment, a non-volatile memory device includes: a first cell string including a plurality of first cell transistors connected in series between a common source line and a first cell line and stacked on top of each other in a direction perpendicular to a substrate; a second cell string including a plurality of second cell transistors connected in series between a common source line and a first cell line and stacked on top of each other in a direction perpendicular to a substrate; a block select circuit connected to the first cell string and the second cell string via a plurality of signal lines and providing a corresponding drive voltage to the plurality of signal lines in response to a block select signal; and a block unselect circuit connected only to a specific signal line among the plurality of signal lines and providing a cutoff voltage to the specific signal line in response to a block unselect signal. The remaining signal lines among the plurality of signal lines, excluding the specific signal line, include at least one first string select line connected to the first cell string and at least one second string select line connected to the second cell string.

[0008] According to an exemplary embodiment, a non-volatile memory device includes: a first memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate, the plurality of cell transistors being interconnected with a plurality of string select lines, a plurality of word lines, and a plurality of ground select lines; a block decoder activating a block select signal and a block unselect signal based on a first address corresponding to the first memory block and a second address not corresponding to the first memory block, the first address and the second address being received from an external device; a plurality of path transistors providing corresponding drive voltages to the plurality of string select lines, the plurality of word lines, and the plurality of ground select lines respectively in response to the activation of the block select signal; and a plurality of unselected path transistors providing a cutoff voltage to a specific string select line among the plurality of string select lines in response to the activation of the block unselect signal. The number of the plurality of unselected path transistors is less than the number of the plurality of string select lines. Attached Figure Description

[0009] The above and other objects and features of the inventive concept will become clear by describing in detail the exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram illustrating a non-volatile memory device according to an embodiment of the inventive concept.

[0011] Figure 2 It is shown that it includes Figure 1 A circuit diagram of the first memory block in a memory cell array of a non-volatile memory device.

[0012] Figure 3 This illustrates an example embodiment. Figure 1 A diagram of a line decoder for a non-volatile memory device.

[0013] Figure 4 This illustrates an example embodiment. Figure 1 A flowchart of the operation of a non-volatile memory device.

[0014] Figure 5 It is shown in detail according to the example embodiment. Figure 3 A diagram showing the configuration of the line decoder.

[0015] Figure 6 This illustrates an example embodiment. Figure 5 A graph of the programming bias of the line decoder.

[0016] Figure 7 It is used to describe according to the example embodiments Figure 1 A diagram illustrating the operation of a non-volatile memory device.

[0017] Figure 8 This illustrates an example embodiment. Figure 1 A diagram of a line decoder for a non-volatile memory device.

[0018] Figure 9A This illustrates an example embodiment. Figure 1 A diagram of a line decoder for a non-volatile memory device.

[0019] Figure 9B It is used to describe according to the example embodiments Figure 9A A diagram showing the configuration of the line decoder.

[0020] Figure 10 This is a circuit diagram illustrating a third memory block according to an embodiment of the inventive concept.

[0021] Figures 11A to 11D This is a diagram illustrating a line decoder according to an embodiment of the inventive concept.

[0022] Figure 12 This is a block diagram illustrating a storage system including a non-volatile memory device according to an embodiment of the inventive concept. Detailed Implementation

[0023] Hereinafter, embodiments of the inventive concept will be described in detail and clearly to the extent that those skilled in the art can easily implement the inventive concept.

[0024] Figure 1 This is a block diagram illustrating a non-volatile memory device according to an embodiment of the inventive concept.

[0025] Reference Figure 1The non-volatile memory device 100 may include a memory cell array 110 and peripheral circuitry 120. For ease of description, the following description will give the non-volatile memory device 100 as a NAND flash memory device, but the inventive concept is not limited thereto.

[0026] The memory cell array 110 may include multiple memory blocks (BLKs). Each memory block may include multiple cell strings. Each of the multiple cell strings may include multiple cell transistors connected in series, and the multiple cell transistors connected in series are connected to a string select line SSL, a word line WL, and a ground select line GSL.

[0027] In one exemplary embodiment, the cell transistors of the memory cell array 110 may be stacked in a direction perpendicular to the semiconductor substrate. For example, the memory cell array 110 may include a three-dimensional memory block.

[0028] The peripheral circuitry 120 may include a line decoder 121, a voltage generator 122, control logic circuitry 123, and input / output circuitry (I / O circuitry) 124. In one exemplary embodiment, the memory cell array 110 may be formed in a cell region of a semiconductor substrate, and the peripheral circuitry 120 may be formed in a peripheral region of the semiconductor substrate that is physically separated from the cell region. Optionally, the peripheral circuitry 120 may be formed on the semiconductor substrate, and the memory cell array 110 may be stacked on the peripheral circuitry 120. For example, the non-volatile memory device 100 may be formed in a cell-on-periphery (COP) configuration. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may be implemented in various shapes.

[0029] Row decoder 121 can be connected to memory cell array 110 via serial select line SSL, word line WL, and ground select line GSL. Row decoder 121 can receive address ADDR from an external device (e.g., a memory controller or host device). In one exemplary embodiment, address ADDR may include various address information, such as block address, row address, column address, etc. Row decoder 121 can decode the received address ADDR to control the voltage of serial select line SSL, word line WL, and ground select line GSL.

[0030] Voltage generator 122 can generate various voltages required for the operation of non-volatile memory device 100 (e.g., multiple programming voltages, multiple verification voltages, multiple pass voltages, multiple select read voltages, multiple non-select read voltages, and multiple block select voltages). The voltages generated from voltage generator 122 can be provided to line decoder 121.

[0031] The control logic circuit 123 can receive commands CMD or control signals CTRL from external devices (e.g., memory controllers or host devices) and can control the line decoder 121, voltage generator 122 and input / output circuit 124 based on the received commands CMD or control signals CTRL.

[0032] The input / output circuit 124 can be connected to the memory cell array 110 via multiple bit lines BL. The input / output circuit 124 can read data DATA stored in the memory cell array 110 via the multiple bit lines BL, and can output the read data DATA to an external device. Optionally, the input / output circuit 124 can receive data DATA from an external device, and can store the received data DATA in the memory cell array 110 via the multiple bit lines BL.

[0033] Despite Figure 1 Although not shown, the input / output circuitry 124 may include a column decoder connected to the memory cell array 110 via multiple bit lines BL. The column decoder may receive column addresses from external devices and decode the received column addresses to control the multiple bit lines BL. The input / output circuitry 124 may also include page buffers connected to the multiple bit lines BL for temporarily storing data received from external devices or data read from the memory cell array 110 via the multiple bit lines BL.

[0034] In one exemplary embodiment, the non-volatile memory device 100 may operate in specific units (e.g., block units, sub-block units, word line units, or page units). For example, when performing a page-based programming operation on the first word line of the non-volatile memory device 100, the row decoder 121 may select at least one memory block from a plurality of memory blocks included in the memory cell array 110 based on an address ADDR (specifically, a block address) received from an external device. The row decoder 121 may control the string select line SSL, word line WL, and ground select line GSL based on the address ADDR (specifically, a row address) received from an external device, such that a programming operation is performed on the first word line of the selected memory block.

[0035] In one exemplary embodiment, multiple memory blocks may share a bit line BL. For example, during a programming operation, a bit line voltage may be supplied to the remaining memory blocks (i.e., unselected memory blocks) of the multiple memory blocks, excluding the selected memory block. A specific cell transistor (e.g., a string select transistor) of an unselected memory block may be turned off, such that the bit line voltage is not applied to the unselected memory block. The line decoder 121 may supply a specific voltage to a control line (e.g., a portion of the string select lines SSL) connected to the specific string select transistor, causing the specific cell transistor to turn off. For example, when the number of string select lines SSL is Y, the number of a portion of the string select lines SSL (e.g., X) is equal to or greater than 1 and less than Y. Here, X may be a positive integer equal to or greater than 1, and Y may be a positive integer greater than X and equal to or greater than 2.

[0036] In one exemplary embodiment, the row decoder 121 according to an embodiment of the inventive concept may provide a specific voltage only to specific string select lines among the string select lines of unselected memory blocks. In this case, the size of the row decoder 121 can be reduced because it is not necessary to apply the specific voltage to all string select lines of the unselected memory blocks. The configuration of the row decoder 121 according to an embodiment of the inventive concept will be described more precisely with reference to the accompanying drawings.

[0037] Figure 2 It is shown that it includes Figure 1 A circuit diagram of the first memory block among multiple memory blocks in the memory cell array 110. In an exemplary embodiment, reference will be made to... Figure 2 The invention describes a first memory block BLK1 with a three-dimensional structure, but the inventive concept is not limited thereto. For example, the memory cell array 110 includes a plurality of memory blocks, each of which has a... Figure 2 The structure is similar to that of the first memory block BLK1. In one exemplary embodiment... Figure 2 The first memory block BLK1 shown may correspond to a physical erase unit of the non-volatile memory device 100, but the inventive concept is not limited thereto. For example, the physical erase unit may be changed to a page unit, a word line unit, a sub-block unit, etc.

[0038] Reference Figure 1 and Figure 2 The first memory block BLK1 may include multiple cell strings CS11, CS12, CS21, and CS22. Cell strings CS11, CS12, CS21, and CS22 may be arranged along both row and column directions. For simplicity, in... Figure 2 The diagram shows four unit strings CS11, CS12, CS21, and CS22, but the inventive concept is not limited thereto. For example, the number of unit strings may increase or decrease along the row or column direction.

[0039] Among multiple cell strings CS11, CS12, CS21, and CS22, cell strings located in the same column can be connected to the same bit line. For example, cell strings CS11 and CS21 can be connected to the first bit line BL1, and cell strings CS12 and CS22 can be connected to the second bit line BL2.

[0040] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors. Each of the multiple cell transistors may include a charge-trapped flash memory (CTF) cell. The multiple cell transistors may be stacked along a height direction that is perpendicular to a plane (e.g., a semiconductor substrate (not shown)) defined by row and column directions.

[0041] In each cell string, multiple cell transistors may be connected in series between a corresponding bit line (e.g., BL1 or BL2) and the common source line CSL. For example, the multiple cell transistors may include string select transistors SSTb and SSTa, dummy memory cells DMC1 and DMC2, memory cells MC1 through MC4, and ground select transistors GSTA and GSTb. The series-connected string select transistors SSTb and SSTa may be positioned between the series-connected memory cells MC1 through MC4 and the corresponding bit line (e.g., BL1 or BL2). The series-connected ground select transistors GSTA and GSTb may be positioned between the series-connected memory cells MC1 through MC4 and the common source line CSL.

[0042] In one exemplary embodiment, a second dummy memory cell DMC2 may also be provided between the series-connected string selection transistors SSTb and SSTa and the series-connected memory cells MC1 to MC4, and a first dummy memory cell DMC1 may also be provided between the series-connected memory cells MC1 to MC4 and the series-connected ground selection transistors GSTb and GSTa.

[0043] Here, the second dummy memory cell DMC2 is connected between the string select transistor SSTA and the memory cell MC4, and the first dummy memory cell DMC1 is connected between the ground select transistor GSTb and the memory cell MC1. For example, the first dummy memory cell DMC1 and the second dummy memory cell DMC2 may have a similar or identical structure to the memory cells MC1 to MC4, and may be formed using the same process. The first dummy memory cell DMC1 and the second dummy memory cell DMC2 may be activated via the first dummy word line DWL1 and the second dummy word line DWL2, respectively, but may not have any stored or read "data" from an external device. For example, unlike ordinary memory cells (e.g., memory cells MC1 to MC4), data stored in dummy memory cells electrically connected to the dummy word lines may not be sent to the outside of the memory cell array via any select signal provided by the column decoder.

[0044] In one exemplary embodiment, each of the plurality of cell strings CS11, CS12, CS21, and CS22 may not include one or both of the first dummy memory cell DMC1 and the second dummy memory cell DMC2. For example, in the absence of the first dummy memory cell DMC1 and the second dummy memory cell DMC2, the serially connected memory cells MC1 to MC4 may be directly connected to the serially connected string select transistors SSTb and SSTa and the serially connected ground select transistors GSTb and GSTa.

[0045] In multiple cell strings CS11, CS12, CS21, and CS22, memory cells MC1 through MC4 located at the same height can share the same word line. For example, the first memory cell MC1 in multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the base (not shown) and can share the first word line WL1. The second memory cell MC2 in multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the base (not shown) and can share the second word line WL2. Similarly, the third memory cell MC3 in multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the base (not shown) and can share the third word line WL3, and the fourth memory cell MC4 in multiple cell strings CS11, CS12, CS21, and CS22 can be located at the same height from the base (not shown) and can share the fourth word line WL4.

[0046] In multiple cell strings CS11, CS12, CS21, and CS22, dummy memory cells DMC1 and DMC2 located at the same height can share the same dummy word line. For example, the first dummy memory cell DMC1 in multiple cell strings CS11, CS12, CS21, and CS22 can share the first dummy word line DWL1, and the second dummy memory cell DMC2 in multiple cell strings CS11, CS12, CS21, and CS22 can share the second dummy word line DWL2.

[0047] In multiple cell strings CS11, CS12, CS21, and CS22, the string select transistors SSTb and SSTA located at the same height and in the same row can be connected to the same string select line. For example, the string select transistor SSTb of cell strings CS11 and CS12 can be connected to the string select line SSL1b, and the string select transistor SSTA of cell strings CS11 and CS12 can be connected to the string select line SSL1a. Similarly, the string select transistor SSTb of cell strings CS21 and CS22 can be connected to the string select line SSL2b, and the string select transistor SSTA of cell strings CS21 and CS22 can be connected to the string select line SSL2a.

[0048] Although not shown in the accompanying drawings, in multiple cell strings CS11, CS12, CS21, and CS22, the string select transistors SSTb and SSTa located in the same row can share the same string select line. For example, the string select transistors SSTb and SSTa in cell strings CS11 and CS12 can share a first string select line, while the string select transistors SSTb and SSTa in cell strings CS21 and CS22 can share a second string select line different from the first string select line.

[0049] In multiple cell strings CS11, CS12, CS21, and CS22, ground selection transistors GSTb and GSTA located at the same height and in the same row can be connected to the same ground selection line. For example, ground selection transistor GSTb in cell strings CS11 and CS12 can be connected to ground selection line GSL1b, and ground selection transistor GSTA in cell strings CS11 and CS12 can be connected to ground selection line GSL1a. Ground selection transistor GSTb in cell strings CS21 and CS22 can be connected to ground selection line GSL2b, and ground selection transistor GSTA in cell strings CS21 and CS22 can be connected to ground selection line GSL2a.

[0050] Although not shown in the accompanying drawings, in each of the multiple cell strings CS11, CS12, CS21, and CS22, the ground selection transistors GSTA and GSTb may share the same ground selection line. In the multiple cell strings CS11, CS12, CS21, and CS22, ground selection transistors GSTA and GSTb located at the same height may share the same ground selection line. Alternatively, in the multiple cell strings CS11, CS12, CS21, and CS22, ground selection transistors GSTA and GSTb located in the same row may share the same ground selection line.

[0051] In one exemplary embodiment, in Figure 2 The first memory block BLK1 shown is exemplary. For example, the number of cell strings can be increased or decreased, and the number of rows and columns of cell strings can be increased or decreased according to the number of cell strings. Furthermore, the number of cell transistors (GST, MC, DMC, SST, etc.) in the first memory block BLK1 can be increased or decreased, and the height of the first memory block BLK1 can be increased or decreased according to the number of cell transistors. Additionally, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors can be increased or decreased according to the number of cell transistors.

[0052] Figure 3 This illustrates an example embodiment. Figure 1 A diagram of the line decoder 121 is provided. For brevity, the configuration of the line decoder 121 will be described with reference to one of the multiple cell strings CS11, CS12, CS21, and CS22 of the first memory block BLK1, cell string CS11. Furthermore, components unnecessary for describing the line decoder 121 are omitted.

[0053] To clearly describe various embodiments of the inventive concept, examples of operations of the non-volatile memory device 100 performed based on memory block cells will be described below. That is, in the following embodiments, the operation of the non-volatile memory device 100 will be described with respect to selected and unselected memory blocks, but the inventive concept is not limited thereto. For example, operations of various lines (e.g., GSL, WL, DWL, SSL, etc.) connected to the selected memory block can be controlled based on the type of operation of the non-volatile memory device 100 (e.g., programming operation, read operation, or erase operation).

[0054] Reference Figures 1 to 3 The line decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block unselection circuit 121c, and a line driver 121d.

[0055] Block decoder 121a can decode block address ADDR_BLK (e.g., included in address ADDR) to output block selection signal SEL_BLK. For example, block decoder 121a can determine whether block address ADDR_BLK corresponds to a first memory block BLK1 including cell string CS11. When block address ADDR_BLK corresponds to the first memory block BLK1, the first memory block BLK1 can be a selected block; when block address ADDR_BLK does not correspond to the first memory block BLK1, the first memory block BLK1 can be an unselected block. That is, block decoder 121a can determine whether the first memory block BLK1 is a selected or unselected block based on block address ADDR_BLK.

[0056] When the first memory block BLK1 is selected, the block decoder 121a can output a "logic high" block selection signal SEL_BLK (e.g., activate the block selection signal SEL_BLK) and a "logic low" block unselected signal / SEL_BLK (e.g., deactivate the block unselected signal / SEL_BLK). When the first memory block BLK1 is not selected, the block decoder 121a can output a "logic low" block selection signal SEL_BLK (e.g., deactivate the block selection signal SEL_BLK) and a "logic high" block unselected signal / SEL_BLK (e.g., activate the block unselected signal / SEL_BLK). In an example embodiment, the block unselected signal / SEL_BLK can be generated by inverting the block selection signal SEL_BLK. However, the inventive concept is not limited to this. For example, the level of the block selection signal SEL_BLK can be changed or modified differently.

[0057] The block select circuit 121b can be connected between the signal lines SSL1a, SSL1b, DWL1, DWL2, WL1 to WL4, GSL1a and GSL1b (i.e., including the string select lines SSL1a and SSL1b, the dummy word lines DWL1 and DWL2, the word lines WL1 to WL4 and the ground select lines GSL1a and GSL1b) connected to the cell string CS11 of the first memory block BLK1 and the line driver 121d.

[0058] Block select circuit 121b can operate in response to block select signal SEL_BLK. For example, block select circuit 121b may include multiple path transistors respectively connected between multiple signal lines (e.g., SSL1a, SSL1b, DWL2, WL4…WL1, DWL1, GSL1b, and GSL1a) and line driver 121d. The multiple path transistors of block select circuit 121b can be turned on in response to the "logic high" block select signal SEL_BLK. In this case, drive voltages from line driver 121d (e.g., VSSL1a, VSSL1b, VDWL2, VWL4…VWL1, VDWL1, VGSL1b, and VGSL1a) can be provided to the corresponding signal lines (e.g., SSL1a, SSL1b, DWL2, WL4…WL1, DWL1, GSL1b, and GSL1a).

[0059] The multiple-path transistors of the block select circuit 121b can be turned off in response to the block select signal SEL_BLK, which is "logic low". In this case, the corresponding lines (e.g., SSL1a, SSL1b, DWL2, WL4...WL1, DWL1, GSL1b, GSL1a) can be floated.

[0060] For example, when the first memory block BLK1 is a selected block, the block selection circuit 121b can provide the corresponding drive voltage to the various lines connected to the first memory block BLK1; when the first memory block BLK1 is an unselected block, the block selection circuit 121b can make the various lines connected to the first memory block BLK1 float, or can prevent the corresponding drive voltage from being provided to the various lines.

[0061] In one exemplary embodiment, the drive voltage (e.g., VSSL1a, VSSL1b, VDWL2, VWL4…VWL1, VDWL1, VGSL1b, VGSL1a) from the line driver 121d can be varied or modified depending on the type of operation of the non-volatile memory device 100 (e.g., programming operation, verification operation, read operation, or erase operation), whether the cell string is selected or not, or whether the word line is selected or not.

[0062] In one exemplary embodiment, when the first memory block BLK1 is an unselected block, a portion of the string selection transistors SSTb and SSTA can be turned off, such that the voltage supplied to the bit line (e.g., BL1) is not applied to the first memory block BLK1.

[0063] For example, the block unselected circuit 121c may include an unselected path transistor connected between a cutoff voltage VOFF and a first string select line SSL1b of the string select lines SSL1a and SSL1b connected to the first memory block BLK1. The unselected path transistor may operate in response to a block unselected signal / SEL_BLK. In one exemplary embodiment, the cutoff voltage VOFF may be ground GND or a negative voltage.

[0064] For example, when the first memory block BLK1 is selected, the block unselected circuit 121c can be turned off, and when the first memory block BLK1 is unselected, the block unselected circuit 121c can be turned on. When the block unselected circuit 121c is on, the cutoff voltage VOFF can be applied to the first string select line SSL1b, therefore, the string select transistor SSTb connected to the first string select line SSL1b can be turned off. In this case, the voltage of the first bit line BL1 may not be applied to the first memory block BLK1.

[0065] In one exemplary embodiment, when a particular memory block is an unselected block, a conventional non-volatile memory device is configured to provide a cutoff voltage VOFF to all serial select lines associated with that particular memory block. In this case, the unselected block circuitry may include unselected path transistors connected to each of the serial select lines. This implies an increase in the size of the line decoder.

[0066] In contrast, according to an embodiment of the inventive concept, the block unselected circuit 121c can be connected to only some of the multiple string select lines connected to a memory block (i.e., the first memory block BLK1), thus reducing the size of the line decoder 121.

[0067] Figure 4 This illustrates an example embodiment. Figure 1 A flowchart of the operation of the non-volatile memory device 100 is provided. Hereinafter, the operation of the non-volatile memory device 100 according to an embodiment of the inventive concept will be described with reference to the first memory block BLK1. However, the inventive concept is not limited thereto. For example, the non-volatile memory device 100 may be based on… Figure 4 The flowchart executes operations on multiple memory blocks.

[0068] Reference Figures 1 to 4In operation S110, the non-volatile memory device 100 may determine whether the first memory block BLK1 is a selected block. For example, the non-volatile memory device 100 may receive an address ADDR from an external device (e.g., a memory controller or a host device) and may select at least one memory block from a plurality of memory blocks based on the received address ADDR. For example, the non-volatile memory device 100 may determine whether the first memory block BLK1 is a selected block based on the address ADDR received from the external device.

[0069] When the first memory block BLK1 is not a selected block (i.e., the first memory block BLK1 is an unselected block), in operation S120, the non-volatile memory device 100 can disconnect the block selection circuit 121b, causing the signal line connected to the first memory block BLK1 to be floated. For example, as shown in reference Figure 3 When the first memory block BLK1 is an unselected block, the block decoder 121a can output a logic low block select signal SEL_BLK. The block select circuit 121b can respond to the logic low block select signal SEL_BLK by floating the signal lines connected to the first memory block BLK1. For example, the block select circuit 121b can disconnect the signal lines connected to the first memory block BLK1 from the line driver 121d.

[0070] In operation S130, the non-volatile memory device 100 may provide a cutoff voltage VOFF to only some of the serial select lines in the serial select lines SSL. For example, as shown in reference Figure 3 When the first memory block BLK1 is an unselected block, the block unselection circuit 121c can be turned on in response to the block unselection signal / SEL_BLK (e.g., activating the block unselection signal / SEL_BLK), thus the cutoff voltage VOFF can be provided to only a portion of the serial select lines (e.g., SSL1b). In this case, because the block unselection circuit 121c is only connected to the serial select line SSL1b of the serial select lines SSL1b and SSL1a, the cutoff voltage VOFF can be provided only to the serial select line SSL1b. In this case, the remaining serial select lines (e.g., SSL1a) can be in a floating state.

[0071] When the first memory block BLK1 is selected, in operation S140, the non-volatile memory device 100 can turn on the block selection circuit 121b, so that a drive voltage is provided to the signal line connected to the first memory block BLK1. In operation S150, the non-volatile memory device 100 can control the drive voltage provided to the multiple lines connected to the first memory block BLK1.

[0072] For example, as referenced Figure 3When the first memory block BLK1 is selected, the block decoder 121a outputs a logic high block select signal SEL_BLK. The block select circuit 121b is activated in response to the logic high block select signal SEL_BLK. Various drive voltages from the line driver 121d can be supplied to the corresponding signal lines through the activated block select circuit 121b.

[0073] In one exemplary embodiment, the drive voltage can be varied depending on the type of operation of the non-volatile memory device 100, whether a cell string is selected, whether a word line is selected, or the operating conditions. In one exemplary embodiment, when the first memory block BLK1 is a selected block, the block unselected circuit 121c can be disconnected.

[0074] Figure 5 It is shown in detail according to the example embodiment. Figure 3 A block diagram of the configuration of the line decoder. Refer to the diagram showing only one unit string, CS11. Figure 3 A schematic configuration of the line decoder 121 is described, but reference will be made to the first memory block BLK1 shown therein. Figure 5 The configuration of line decoder 121 will be described more fully. For the sake of brevity and ease of description, unnecessary components of line decoder 121 will be omitted, and therefore additional descriptions will be omitted to avoid redundancy.

[0075] Reference Figures 1 to 5 The first memory block BLK1 may include multiple cell strings CS11, CS12, CS21, and CS22. Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include string selection transistors SSTb and SSTa. (See reference...) Figure 2 The remaining components of the first memory block BLK1 are described, so additional descriptions will be omitted to avoid redundancy.

[0076] The line decoder 121 may include a block decoder 121a, a block selection circuit 121b, a block unselection circuit 121c, and a line driver 121d. The block decoder 121a and the line driver 121d have been described above, so additional descriptions will be omitted to avoid redundancy.

[0077] The block select circuit 121b can be connected to various lines (e.g., SSL1a, SSL1b, SSL2a, and SSL2b) connected to the first memory block BLK1; in response to the block select signal SEL_BLK, the block select circuit 121b can provide a drive voltage from the line driver 121d to the corresponding signal line, or can block the drive voltage (or can make the corresponding signal line float).

[0078] In response to the block not selected signal / SEL_BLK, the block not selected circuit 121c can provide a cutoff voltage VOFF to some of the serial select lines SSL1a, SSL1b, SSL2a, and SSL2b connected to the first memory block BLK1 (e.g., SSL1b and SSL2b). For example, as Figure 5 As shown, in response to the block unselected signal / SEL_BLK, the block unselected circuit 121c can provide the cutoff voltage VOFF only to some of the serial select lines SSL1a, SSL1b, SSL2a and SSL2b connected to the first memory block BLK1.

[0079] In one exemplary embodiment, some string select lines SSL1b and SSL2b connected to the block unselected circuit 121c can be string select lines connected to string select transistors that are adjacent to the corresponding bit lines (e.g., without other intermediate cell transistors in between) and located in the same row within the string select transistors. For example, as Figure 5 As shown, the string select transistors SSTTa of cell strings CS11 and CS12 are in the same row and connected to the string select line SSL1a, respectively, while the string select transistors SSTb of cell strings CS11 and CS12 are in the same row and connected to the string select line SSL1b, respectively. In this case, the string select transistor SSTb may be physically closer to bit lines BL1 and BL2 than the string select transistor SSTTa. When the first memory block BLK1 is an unselected block, the cutoff voltage VOFF may be applied only to the string select lines (e.g., SSL1b and SSL2b) connected to the string select transistors (e.g., SSTb) immediately adjacent to bit lines BL1 and BL2.

[0080] In one exemplary embodiment, the block unselected circuit 121c may not be connected to the remaining serial select lines (e.g., SSL1a and SSL2a). For example, when the first memory block BLK1 is an unselected block, the cutoff voltage VOFF may not be applied to the remaining serial select lines SSL1a and SSL2a. This could mean that the remaining serial select lines SSL1a and SSL2a are floating.

[0081] In one exemplary embodiment, as described above, the block unselected circuit 121c may include unselected path transistors configured to provide a cutoff voltage VOFF to specific string select lines (e.g., SSL1b and SSL2b) in response to the block unselected signal / SEL_BLK. In this case, the number of unselected path transistors ( Figure 5 In the embodiment, "2" can be less than the number of multiple string select lines SSL1a, SSL1b, SSL2a, and SSL2b connected to the first memory block BLK1. Figure 5(4 in the embodiment).

[0082] As described above, according to embodiments of the inventive concept, the block unselection circuit 121c, configured to provide a cutoff voltage VOFF for turning off the string select transistors of unselected blocks, can be connected only to some of the multiple string select lines connected to the unselected block, and the block unselection circuit 121c can be omitted with respect to the remaining string select lines (i.e., the block unselection circuit 121c may not be connected to the remaining string select lines). Therefore, even if the number of string select transistors included in the memory block or the number of string select lines connected to the memory block increases, the number of unselected path transistors included in the block unselection circuit 121c will not increase, and thus the overall size of the line decoder 121 can be reduced.

[0083] Figure 6 This illustrates an example embodiment. Figure 5 A diagram of the programming (PGM) bias of the line decoder. To clearly describe embodiments of the inventive concept, the programming operation will be described with reference to selected and unselected blocks. Furthermore, to prevent the inventive concept from becoming obscure, only the bias string selection lines for selected and unselected blocks will be described, and detailed descriptions of the remaining signal lines (e.g., WL, DWL, GSL, and CSL) will be omitted.

[0084] Reference Figure 5 and Figure 6 The power supply voltage VCC or ground voltage VSS can be applied to the first bit line BL1 and the second bit line BL2. As described above, when the first memory block BLK1 is selected, the block selection circuit 121b can be turned on, and the block unselected circuit 121c can be turned off; therefore, the drive voltages VSSL1a, VSSL1b, VSSL2a, and VSSL2b can be provided to the corresponding string selection lines SSL1a, SSL1b, SSL2a, and SSL2b. In an exemplary embodiment, the drive voltages VSSL1a, VSSL1b, VSSL2a, and VSSL2b can be varied depending on whether the cell strings CS11, CS12, CS21, and CS22 are selected. For example, when cell strings CS11 and CS12 are selected strings and cell strings CS21 and CS22 are unselected strings, each of the drive voltages VSSL1a and VSSL1b can be a high voltage (e.g., VCC) for turning on the string selection transistors SSTA and SSTb of cell strings CS11 and CS12, and each of the drive voltages VSSL2a and VSSL2b can be a low voltage for turning off the string selection transistors SSTA and SSTb of cell strings CS21 and CS22. In one exemplary embodiment, the drive voltages VSSL2a and VSSL2b may have different levels than each other.

[0085] When the first memory block BLK1 is an unselected block, as described above, the block selection circuit 121b can be turned off and the unselected block circuit 121c can be turned on; therefore, the cutoff voltage VOFF can be applied only to some of the serial selection lines SSL1b and SSL2b, and the remaining serial selection lines SSL1a and SSL2a can be left floating.

[0086] Figure 7 It is used to describe according to the example embodiments Figure 1 A diagram illustrating the operation of a non-volatile memory device. (Refer to...) Figure 7 This describes the operation of the line decoder 121 associated with selected and unselected blocks. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy.

[0087] In one exemplary embodiment, Figure 7 Each of the first memory block BLK1 and the second memory block BLK2 shown may include multiple strings of cells arranged along three rows, and the strings of cells in the same row may be connected to the same string select line. However, the inventive concept is not limited thereto.

[0088] Reference Figure 7 The line decoder 121 may include a first selection circuit 121b-1, a second selection circuit 121b-2, a first unselected circuit 121c-1, and a second unselected circuit 121c-2. The first selection circuit 121b-1 may be connected to multiple serial selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the first memory block BLK1. The first unselected circuit 121c-1 may be connected only to some of the serial selection lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the first memory block BLK1 (e.g., SSL1b, SSL2b, and SSL3b).

[0089] The second select circuit 121b-2 can be connected to multiple serial select lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the second memory block BLK2. The second unselect circuit 121c-2 can be connected to only some of the serial select lines SSL1a, SSL1b, SSL2a, SSL2b, SSL3a, and SSL3b of the second memory block BLK2 (e.g., SSL1b, SSL2b, and SSL3b).

[0090] For brevity and ease of description, the serial select lines connected to the first memory block BLK1 and the second memory block BLK2 are labeled with the same reference numerals, but the inventive concept is not limited thereto. The serial select lines of the first memory block BLK1 may be physically separated from the serial select lines of the second memory block BLK2.

[0091] For the sake of brevity, only the serial select lines connected to the first memory block BLK1 and the second memory block BLK2 are shown, but the inventive concept is not limited thereto. For example, the first memory block BLK1 and the first block select circuit 121b-1, or the second memory block BLK2 and the second select circuit 121b-2, may also be connected to the various lines described above (e.g., DWL, WL, and GSL).

[0092] For ease of description, assume that the first memory block BLK1 is the selected block and the second memory block BLK2 is the unselected block. In this case, as described above, the first block selection circuit 121b-1 connected to the first memory block BLK1, which is the selected block, is activated. In this case, as... Figure 7 As shown, the corresponding voltages VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b and VSSL3a can be supplied to the serial select lines of the first memory block BLK1 (e.g. SSL1b, SSL1a, SSL2b, SSL2a, SSL3b and SSL3a) through the first select circuit 121b-1.

[0093] The second block selection circuit 121b-2, which is connected to the second memory block BLK2 (which is an unselected block), is disconnected. In this case, as... Figure 7 As shown, the serial select lines SSL1b, SSL1a, SSL2b, SSL2a, SSL3b and SSL3a of the second memory block BLK2 can be floated by the second block select circuit 121b-2, or the corresponding voltages (e.g. VSSL1b, VSSL1a, VSSL2b, VSSL2a, VSSL3b and VSSL3a) can be not provided or can be blocked by the second block select circuit 121b-2.

[0094] In this configuration, when the second unselected block circuit 121c-2, connected to some of the string select lines SSL1b, SSL2b, and SSL3b of the second memory block BLK2 (which is an unselected block), is turned on, the cutoff voltage VOFF can be supplied to some of the string select lines SSL1b, SSL2b, and SSL3b of the second memory block BLK2. Thus, even if the second memory block BLK2, which is an unselected block, shares bit lines with the first memory block BLK1, the voltage of the shared bit lines will not be applied to the second memory block BLK2.

[0095] Furthermore, even though the various voltages supplied to the first selection circuit 121b-1 and the second selection circuit 121b-2 are shared, no operation is performed in the second memory block BLK2 because the various voltages are blocked by the second selection circuit 121b-2.

[0096] As described above, according to embodiments of the inventive concept, a non-volatile memory device can apply a cutoff voltage VOFF only to some of the multiple serial select lines connected to the unselected memory block, thereby preventing abnormal operation of the unselected memory block. Because the block unselection circuit is only connected to some of the multiple serial select lines, the size of the line decoder can be reduced even if the number of serial select transistors or the number of serial select lines increases.

[0097] In one exemplary embodiment, the string select line among the multiple string select lines connected to a memory block that is subject to a cutoff voltage may be a string select line connected to a string select transistor adjacent to a bit line among the multiple string select lines. Alternatively, the string select line among the multiple string select lines connected to a memory block that is subject to a cutoff voltage may be a string select line connected to a string select transistor located at the topmost level from the substrate among the multiple string select lines.

[0098] Figure 8 This illustrates an example embodiment. Figure 1 A diagram illustrating an example of a line decoder. For brevity and ease of description, additional descriptions of the same components will be omitted to avoid redundancy.

[0099] Reference Figure 1 and Figure 8 The line decoder 121-3 may include a block decoder 121a-3, a block selection circuit 121b-3, a block unselection circuit 121c-3, and a line driver 121d-3. The block decoder 121a-3, the block selection circuit 121b-3, and the line driver 121d-3 have been described above, so additional descriptions will be omitted to avoid redundancy.

[0100] Unlike the above embodiments, in Figure 8 In one embodiment, the cell string CS11-1 may include a plurality of string selection transistors SST. The plurality of string selection transistors SST may be connected to string selection lines SSL1a to SSL1k respectively.

[0101] The block unselected circuit 121c-3 can be connected to some of the multiple string select lines SSL1a to SSL1i, where a is a positive integer and i is an integer greater than a and less than k. For example, when the memory block including the cell string CS11-1 is an unselected block, the block unselected circuit 121c-3 can be configured to provide a cutoff voltage VOFF to some of the multiple string select lines SSL1a to SSL1i.

[0102] In one exemplary embodiment, the number of some string selection lines SSL1a to SSL1i connected to the block unselected circuit 121c may be greater than the number of the remaining string selection lines SSL1i+1 to SSL1k.

[0103] exist Figure 8 The diagram illustrates an example of multiple string select transistors SST connected to multiple string select lines SSL1a to SSL1k in a 1:1 correspondence, but the inventive concept is not limited thereto. For example, the number of multiple string select transistors SST can be "m" (where m is a positive integer), and the number of multiple string select lines SSL1a to SSL1k can be "k" (where "k" is an integer less than "m"). For example, a string select line can be shared by at least two or more string select transistors.

[0104] Figure 9A This illustrates an example embodiment. Figure 1 A diagram of an example of a line decoder. Figure 9B It is used to describe according to the example embodiments Figure 9A A diagram showing the configuration of the line decoder. For brevity and ease of description, unnecessary components of line decoder 121-4 are omitted, and therefore additional descriptions will be omitted to avoid redundancy.

[0105] Reference Figure 1 , Figure 2 , Figure 9A and Figure 9B The line decoder 121-4 may include a block decoder 121a-4, a block selection circuit 121b-4, a block unselection circuit 121c-4, and a line driver 121d-4. The block decoder 121a-4, the block selection circuit 121b-4, and the line driver 121d-4 have been described above, so additional descriptions will be omitted to avoid redundancy.

[0106] The unselected block circuit 121c-4 can be connected to a specific string select line among multiple string select lines SSL1a, SSL1b, SSL2a, and SSL2b. For example, the unselected block circuit 121c-4 can be connected to specific string select lines SSL1a and SSL2b among multiple string select lines SSL1a, SSL1b, SSL2a, and SSL2b. In an exemplary embodiment, the specific string select lines SSL1a and SSL2b connected to the unselected block circuit 121c-4 can be determined based on the threshold voltages of the string select transistors SSTA and SSTb.

[0107] In detail, such as Figure 9B As shown, the string select transistor connected to the string select line SSL1b can form a first threshold voltage distribution Vth1, and the string select transistor connected to the string select line SSL1a can form a second threshold voltage distribution Vth2. In this case, the second threshold voltage distribution Vth2 can be higher in level than the first threshold voltage distribution Vth1. For example, the lower limit or upper limit of the second threshold voltage distribution Vth2 can be higher than the lower limit or upper limit of the first threshold voltage distribution Vth1.

[0108] Similarly, as Figure 9B As shown, the series select transistor connected to the series select line SSL2b can form a third threshold voltage distribution Vth3, and the series select transistor connected to the series select line SSL2a can form a fourth threshold voltage distribution Vth4. In this case, the third threshold voltage distribution Vth3 can be higher in level than the fourth threshold voltage distribution Vth4. For example, the lower limit or upper limit of the third threshold voltage distribution Vth3 can be higher than the lower limit or upper limit of the fourth threshold voltage distribution Vth4.

[0109] The string select line (e.g., SSL1b and SSL1a, or SSL2b and SSL2a) located in the same row and connected to the string select transistor with the highest threshold voltage distribution. Figure 9B In the embodiments, SSL1a or SSL2b can be connected to the unselected block circuit 121c-4.

[0110] In some examples, the threshold voltage of the series select transistor connected to the series select line connected to the same block unselected circuit 121c-4 may be greater than the threshold voltage of the series select transistor connected to the remaining series select lines not connected to the same block unselected circuit 121c-4.

[0111] In one exemplary embodiment, the series select transistor connected to the series select line connected to the same block of unselected circuit 121c-4 can be programmed to have a reference value or a higher threshold voltage.

[0112] Figure 10This is a circuit diagram illustrating a third memory block according to an embodiment of the inventive concept. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. In one exemplary embodiment, Figure 10 The third memory block BLK3 is an exemplary structure of a three-dimensional memory block, and embodiments of the inventive concept are not limited thereto. In one exemplary embodiment, each memory block included in the memory cell array may have Figure 2 The structure of the first memory block BLK1 or may have Figure 10 The structure of the third memory block BLK3.

[0113] Reference Figure 10 The third memory block BLK3 may include multiple cell strings CS11, CS12, CS21, and CS22. These cell strings can be arranged along both row and column directions. Cell strings belonging to the same column can be connected to the same bit line. For example, cell strings CS11 and CS21 can be connected to the first bit line BL1, and cell strings CS12 and CS22 can be connected to the second bit line BL2.

[0114] Each of the multiple cell strings CS11, CS12, CS21, and CS22 may include multiple cell transistors. Within each cell string, the multiple cell transistors may be connected in series between a corresponding bit line and a common-source line CSL. In one exemplary embodiment, within each cell string, the multiple cell transistors may include string select transistors SSTa and SSTb, memory cells MC1 to MC4, dummy memory cells DMC1 to DMC3, ground select transistors GSTA and GSTb, and erase control transistors ECT1 and ECT2. The cell transistors in each cell string may be connected to corresponding lines (e.g., SSL1a, SSL1b, SSL2a, SSL2b, DWL1 to DWL3, WL1 to WL4, GSL1a, GSL1b, GSL2a, GSL2b, ECL1, and ECL2). See also... Figure 2 The string selection transistors SSTa and SSTb, memory cells MC1 to MC4, dummy memory cells DMC1 and DMC2, and ground selection transistors GSTa and GSTb are described, so additional descriptions will be omitted to avoid redundancy.

[0115] and Figure 2 The first memory block BLK1 is different. Figure 10 The third memory block BLK3 may also include erase control transistors ECT1 and ECT2 and a third dummy memory cell DMC3.

[0116] The first erase control transistor ECT1 can be inserted between the series-connected ground select transistors GSTA and GSTb and the common-source line CSL, and can be connected to the first erase control line ECL1. The second erase control transistor ECT2 can be inserted between the series-connected string select transistors SSTa and SSTb and the bit line BL1 or BL2, and can be connected to the second erase control line ECL2. The first erase control transistor ECT1 and the second erase control transistor ECT2 can be controlled by the first erase control line ECL1 and the second erase control line ECL2, respectively. In an exemplary embodiment, the first erase control transistor ECT1 and the second erase control transistor ECT2 can be configured to control the gate-induced drain leakage (GIDL) current when the third memory block BLK3 is erased.

[0117] The third dummy memory cell DMC3 may be located between memory cells MC1 to MC4 stacked in a direction perpendicular to the substrate, and may be connected to the third dummy word line DWL3. For example, the third dummy memory cell DMC3 may be inserted between the second memory cell MC2 and the third memory cell MC3. In an exemplary embodiment, when the third memory block BLK3 has a multi-layer stacked structure, the third dummy memory cell DMC3 may be formed in the connection layer between the lower structure (e.g., a structure including ECT1, GST1, GST1, DMC1, MC1 and MC2) and the upper structure (e.g., a structure including ECT2, GST1, GST1, DMC2, MC4 and MC3).

[0118] In one exemplary embodiment, Figure 10 The third memory block BLK3 is exemplary, and the inventive concept is not limited thereto. For example, the third memory block BLK3 may not include... Figure 10 At least one of the components shown. Optionally, the third memory block BLK3 may also include additional components. For example, Figure 10 The third memory block BLK3 shown is exemplary, and it is understood that the structure of the memory block can be changed or modified in different ways.

[0119] Figures 11A to 11D This is a diagram illustrating a line decoder according to an embodiment of the inventive concept. For ease of description, reference will be made to... Figure 10 The third memory block BLK3 is used to describe the configuration of line decoders 221-1, 221-2, 221-3, and 221-4, and additional descriptions associated with the aforementioned components will be omitted to avoid redundancy. Figures 11A to 11D In order to make the accompanying drawings clear, solid lines are used to show the lines among the various lines connected to the third memory block BLK3 that are connected to the unselected block circuit.

[0120] like Figures 11A to 11DAs shown, row decoders 221-1, 221-2, 221-3, or 221-4 can be connected to the third memory block BLK3 via various lines. Row decoders 221-1, 221-2, 221-3, or 221-4 may include block decoders 221a-1, 221a-2, 221a-3, or 221a-4, block selection circuits 221b-1, 221b-2, 221b-3, or 221b-4, block unselected circuits 221c-1, 221c-2, 221c-3, or 221c-4, and line drivers 221d-1, 221d-2, 221d-3, or 221d-4. The block decoders 221a-1, 221a-2, 221a-3 and 221a-4, the block selection circuits 221b-1, 221b-2, 221b-3 and 221b-4, and the line drivers 221d-1, 221d-2, 221d-3 and 221d-4 are similar to the components described above, so additional descriptions will be omitted to avoid redundancy.

[0121] like Figure 11A As shown, the block unselected circuit 221c-1 can be connected to the second erase control line ECL2 and can be configured to provide a cutoff voltage VOFF to the second erase control line ECL2 when the third memory block BLK3 is an unselected block. For example, unlike the embodiments described above, Figure 11A The block unselected circuit 221c-1 can provide a cutoff voltage VOFF to the second erase control line ECL2 located above the string select line instead of the string select line. For example, the block unselected circuit 221c-1 may not be connected to any string select line of the third memory block BLK3. In one exemplary embodiment, the second erase control line ECL2 may indicate the line commonly connected to the cell transistor (i.e., the second erase control transistor ECT2) immediately adjacent to the bit lines BL1 and BL2.

[0122] like Figure 11B As shown, the block unselected circuit 221c-2 can be connected to the second dummy word line DWL2 and can be configured to provide a cutoff voltage VOFF to the second dummy word line DWL2 when the third memory block BLK3 is an unselected block. For example, unlike the embodiments described above, Figure 11B The unselected block circuit 221c-2 can provide the cutoff voltage VOFF to the second dummy word line DWL2, which is inserted between the serial select line and the word line, instead of the serial select line.

[0123] like Figure 11C As shown, the block unselected circuit 221c-3 can be connected to the third dummy word line DWL3 and can be configured to provide a cutoff voltage VOFF to the third dummy word line DWL3 when the third memory block BLK3 is an unselected block. For example, unlike the embodiments described above, Figure 11CThe unselected block circuit 221c-3 can provide the cutoff voltage VOFF to the third dummy word line DWL3 inserted between word lines instead of the serial select line.

[0124] like Figure 11D As shown, the block unselected circuit 221c-4 can be connected to the first erase control line ECL1 and can be configured to provide a cutoff voltage VOFF to the first erase control line ECL1 when the third memory block BLK3 is an unselected block. For example, unlike the embodiments described above, Figure 11D The unselected block circuit 221c-4 can provide a cutoff voltage VOFF to the first erase control line ECL1 located below the ground select line, instead of the series select line. In an exemplary embodiment, the first erase control line ECL1 can indicate the line commonly connected to the cell transistor (i.e., the first erase control transistor ECT1) adjacent to the common source line CSL.

[0125] As described above, the row decoder of the non-volatile memory device according to embodiments of the inventive concept can, depending on the various ways of implementing the memory cell array, provide a cutoff voltage VOFF only to a portion of the various signal lines connected to unselected blocks. In this case, the number of transistors included in the block unselection circuitry in the row decoder can be reduced, thereby reducing the size of the non-volatile memory device. This makes it possible to implement the non-volatile memory device with a reduced size and lower cost.

[0126] Figure 12 This is a block diagram illustrating a storage system including a non-volatile memory device according to an embodiment of the inventive concept. (Refer to...) Figure 12 The storage system 1000 may include a host 1100 and a storage device 1200.

[0127] Storage device 1200 exchanges signals SIG with host 1100 via signal connector 1201 and is powered by PWR via power connector 1202. Storage device 1200 includes a solid-state drive (SSD) controller 1210, a plurality of non-volatile memories (NVMs) 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240. In one exemplary embodiment, each of the NVMs 1221 to 122n may include a reference... Figures 1 to 8 , Figure 9A , Figure 9B , Figure 10 as well as Figures 11A to 11D Any of the non-volatile memory devices described.

[0128] SSD controller 1210 can control non-volatile memories 1221 to 122n in response to a SIG signal received from host 1100. Multiple non-volatile memories 1221 to 122n can operate under the control of SSD controller 1210. Auxiliary power supply 1230 is connected to host 1100 via power connector 1202. Auxiliary power supply 1230 can be charged by power PWR from host 1100. When power PWR is not stably supplied from host 1100, auxiliary power supply 1230 can power storage device 1200.

[0129] According to embodiments of the inventive concept, the size of a row decoder including block unselect circuitry can be reduced by connecting the block unselect circuitry only to some of the serial select lines of the memory block. Therefore, a non-volatile memory device with reduced cost is provided.

[0130] Furthermore, by connecting the block unselect circuit only to some of the various signal lines connected to the same memory block (e.g., erase control lines, dummy word lines, etc.), the size of the line decoder including the block unselect circuit can be reduced. Therefore, a non-volatile memory device with reduced cost is provided.

[0131] Although the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A non-volatile memory device, comprising: The first memory block includes a plurality of cell transistors stacked in a direction perpendicular to the substrate, the plurality of cell transistors being interconnected with a plurality of ground select lines, a plurality of word lines and a plurality of string select lines; A block select circuit, connected to the plurality of ground select lines, the plurality of word lines, and the plurality of string select lines, and configured to provide corresponding drive voltages to the plurality of ground select lines, the plurality of word lines, and the plurality of string select lines respectively in response to a block select signal; and The block-not-selected circuit is connected only to a specific string select line among the plurality of string select lines and is configured to provide a cutoff voltage only to the specific string select line in response to a block-not-selected signal. The number of specific string selection lines is less than the number of multiple string selection lines.

2. The non-volatile memory device according to claim 1, further comprising: The block decoder is configured to receive an address from an external device and output a block select signal and a block unselect signal based on the received address.

3. The non-volatile memory device according to claim 2, wherein, In response to the activation of the block not selected signal, the non-volatile memory device is configured such that the block not selected circuit provides a cutoff voltage to a specific serial select line, and In response to the deactivation of the block select signal, the block select circuit causes the remaining serial select lines, excluding the specific serial select line, to float.

4. The non-volatile memory device according to claim 1, wherein, The cutoff voltage can be either ground voltage or negative voltage.

5. The non-volatile memory device according to claim 1, wherein, The first memory block includes a first cell string and a second cell string, both inserted between the substrate and the first bit line. The first unit string includes: The first ground selection transistor among the plurality of unit transistors is stacked along a direction perpendicular to the substrate and connected to the first ground selection line among the plurality of ground selection lines; The first memory cell in the plurality of unit transistors is located above the first ground select transistor, stacked in a direction perpendicular to the substrate, and connected to the plurality of word lines respectively; and The first string select transistor among the plurality of unit transistors is located above the first memory cell, stacked in a direction perpendicular to the substrate, and connected to the first string select line among the plurality of string select lines. The second unit string includes: The second ground selection transistor among the plurality of unit transistors is stacked along a direction perpendicular to the substrate and connected to the second ground selection line among the plurality of ground selection lines; The second memory cell in the plurality of unit transistors is located above the second ground select transistor, stacked in a direction perpendicular to the substrate, and connected to the plurality of word lines respectively; and The second string select transistor among the plurality of unit transistors is located above the second memory cell, stacked in a direction perpendicular to the substrate, and connected to the second string select line among the plurality of string select lines.

6. The non-volatile memory device according to claim 5, wherein, A specific string selection line includes a first portion of the first string selection line and a second portion of the second string selection line.

7. The non-volatile memory device according to claim 6, wherein, The first portion of the first select line is connected to the first portion of the first select transistor, and the first portion of the first select transistor is arranged closer to the first bit line than the remaining first select transistors in the first select transistor group excluding the first portion of the first select transistor. The second portion of the second string select line is connected to the second portion of the second string select transistor, and the second portion of the second string select transistor is arranged closer to the first line than the remaining second string select transistors excluding the second portion of the second string select transistor.

8. The non-volatile memory device according to claim 6, wherein, The number of selection lines in the first sequence is M. The number of string selection transistors connected to the first part of the first string selection line in the first string selection transistor is N. Where M and N are both positive integers, and N is less than M. The second selection line has a quantity of M, and The number of string selection transistors connected to the second part of the second string selection line in the second string selection transistor is N.

9. The non-volatile memory device according to claim 6, wherein, The threshold voltage of the string select transistor connected to the first portion of the first string select line is greater than the threshold voltage of the string select transistor connected to the remaining string select lines of the first string select line excluding the first portion of the first string select line. Among them, the threshold voltage of the string selection transistor connected to the second part of the second string selection line is greater than the threshold voltage of the string selection transistor connected to the remaining string selection lines of the second string selection line excluding the second part of the second string selection line.

10. The non-volatile memory device according to claim 1, wherein, The block unselected circuit includes: a plurality of unselected path transistors configured to provide a cutoff voltage to a specific string select line in response to a block unselected signal; and The number of the plurality of unselected path transistors is less than the number of the plurality of string select lines.

11. A non-volatile memory device, comprising: The first unit string includes a plurality of first unit transistors, which are connected in series between the common source line and the first first line and are stacked on top of each other in a direction perpendicular to the substrate. The second unit string includes a plurality of second unit transistors, which are connected in series between the common source line and the first source line and stacked on top of each other in a direction perpendicular to the substrate. A block selection circuit, connected to a first unit string and a second unit string via multiple signal lines, is configured to provide a corresponding drive voltage to the multiple signal lines in response to a block selection signal; and The block is not selected circuitry, which is connected only to a specific signal line among the plurality of signal lines, and is configured to provide a cutoff voltage to the specific signal line in response to a block not selected signal. Among them, the remaining signal lines other than the specific signal lines include at least one first string select line connected to the first unit string and at least one second string select line connected to the second unit string.

12. The non-volatile memory device according to claim 11, wherein, Specific signal lines include: A first signal line is connected to the first unit transistor immediately adjacent to the first signal line among the plurality of first unit transistors; and The second signal line is connected to the second unit transistor that is adjacent to the first line among the plurality of second unit transistors.

13. The non-volatile memory device according to claim 12, wherein, The plurality of first unit transistors include a plurality of first string selection transistors. The plurality of second unit transistors include a plurality of second string selection transistors. Wherein, the first unit transistor is one of the plurality of first string selection transistors, and The second unit transistor is one of the plurality of second string selection transistors.

14. The non-volatile memory device according to claim 12, wherein, The plurality of first unit transistors include a first erase control transistor. The plurality of second unit transistors include a second erase control transistor. The first unit transistor is the first erase control transistor, and The second unit transistor is the second erase control transistor.

15. The non-volatile memory device according to claim 14, wherein, The first signal line and the second signal line are erase control lines that are connected together with the first erase control transistor and the second erase control transistor.

16. The non-volatile memory device according to claim 11, wherein, The first unit string and the second unit string are included in the first memory block. Wherein, when the first memory block is selected, the non-volatile memory device is configured such that: the block selection circuit provides a corresponding drive voltage to the plurality of signal lines, and the block unselection circuit is turned off, and When the first memory block is an unselected block, the non-volatile memory device is configured such that: the block selection circuit floats the plurality of signal lines, and the block unselection circuit provides a cutoff voltage to a specific signal line.

17. The non-volatile memory device according to claim 11, wherein, The cutoff voltage is the ground voltage or a negative voltage.

18. A non-volatile memory device, comprising: The first memory block includes a plurality of cell transistors stacked in a direction perpendicular to the substrate, the plurality of cell transistors being interconnected with a plurality of string select lines, a plurality of word lines and a plurality of ground select lines; The block decoder is configured to activate a block select signal and a block unselect signal based on a first address corresponding to a first memory block and a second address not corresponding to the first memory block, respectively, with the first address and the second address being received from an external device. Multiple path transistors are configured to provide corresponding drive voltages to the multiple serial select lines, the multiple word lines, and the multiple ground select lines respectively in response to activation of a block select signal; as well as Multiple unselected path transistors are configured to provide a cutoff voltage to a specific string select line among the multiple string select lines in response to activation of a block unselected signal. The number of the plurality of unselected path transistors is less than the number of the plurality of string select lines.

19. The non-volatile memory device according to claim 18, wherein, The first memory block includes: The first unit string is connected to the first bit line and includes a plurality of first unit transistors connected in series; The second unit string is connected to the first unit line and includes multiple second unit transistors connected in series; The third unit string is connected to the second bit line and includes a plurality of third unit transistors connected in series; and The fourth unit string, connected to the second bit line, includes multiple fourth unit transistors connected in series. Among them, the first string selection line of the multiple string selection lines is connected to the first unit string and the third unit string; Among them, the second string selection line of the plurality of string selection lines is connected to the second unit string and the fourth unit string, and The specific string selection line includes the first part of the first string selection line and the second part of the second string selection line.

20. The non-volatile memory device according to claim 19, wherein, The first portion of the first selection line is connected to the unit transistor among the plurality of first unit transistors that is physically closest to the first bit line and the unit transistor among the plurality of third unit transistors that is physically closest to the second bit line, and The second part of the second selection line is connected to the unit transistor that is physically closest to the first bit line among the plurality of second unit transistors and the unit transistor that is physically closest to the second bit line among the plurality of fourth unit transistors.

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