Semiconductor device packaging method and semiconductor device

Abstract

The present disclosure relates to a semiconductor device packaging method, comprising: providing at least one wafer, the wafer having an active surface and a wafer back surface; arranging at least one of the wafers on a panel to form a panel assembly; forming a conductive layer and / or a dielectric layer on one side of the active surface of at least one of the wafers. This packaging method helps to improve the production efficiency of packaging, reduce the packaging price; increase the effective use area of wafer packaging; improve the parameter stability of packaged products and increase the yield. The present disclosure also relates to a semiconductor device, comprising: at least one die, the die having a die active surface and a die back surface; a plastic encapsulation layer formed on the back surface of at least one of the dies; a composite layer formed on the active surface of at least one of the dies. This semiconductor device can avoid warping.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a packaging method for a semiconductor device and a semiconductor device. Background Art

[0002] In recent years, with the miniaturization and light weight of electronic devices and the increasing demand for information processing volume, chips that are small, light, and have a high operating speed have become the mainstream market demand. Chip Scale Package (CSP) has become the most advanced integrated circuit packaging form due to its small size, thin thickness, high reliability for long-term chip operation, small line impedance, and high chip operating speed. The heat generated by the chip can be conducted to the outside through a very short channel, and CSP-packaged chips have been rapidly applied in electronic devices.

[0003] In wafer level CSP, a conductive layer is formed on the active surface of a single wafer through processes such as spin coating photoresist, lithography, development, sputtering, electroplating, and stripping; an insulating layer is formed on the conductive layer, and the wafer on which the conductive layer and the insulating layer are formed is divided into single chips to complete the packaging.

[0004] (1) Since each process step is carried out on a single wafer, the packaging production efficiency of the chip is low and the packaging cost is high.

[0005] (2) On the other hand, as Figure 8 shown, it is a schematic diagram of a conductive fixture of a conductive layer forming device commonly used in wafer level CSP in the prior art. During the formation of the conductive layer in wafer level CSP, the periphery of the wafer needs to be clamped by the conductive fixture of the conductive layer forming device, and then the wafer is immersed in the processing liquid in the processing tank of the conductive layer forming device to form a conductive layer. However, this process requires leaving a region for clamping by the conductive fixture at the periphery of the wafer: including the electrical connection region corresponding to the electrical connection contact point and the sealing region corresponding to the seal. Therefore, at least 3 mm of the periphery of the wafer is an invalid region, that is, the bare die in the peripheral region cannot be used for packaging to produce chips. Due to the high price of the wafer, the existence of this invalid region greatly increases the packaging price.

[0006] (3) On the other hand, due to the uneven distribution of the current density on the surface of the wafer during the formation of the conductive layer, the conductive layer formed in the peripheral region of the wafer is thicker, and the conductive layer formed in the inner region is thinner, resulting in unstable parameters of the same batch of packaged products.

[0007] The above three defects of wafer level CSP limit the application of CSP. Summary of the Invention

[0008] The present disclosure provides a packaging method for semiconductor devices to improve the production efficiency of packaging and reduce the packaging cost. This packaging method uses panel-level packaging to replace the single-wafer packaging in wafer-level chip-scale packaging.

[0009] (1) Use a panel component to connect the wafers to be packaged into a whole, enabling the packaging of multiple wafers at the same time, improving the production efficiency of packaging, and reducing the packaging cost;

[0010] (2) The blank area of the panel component can provide an area for contacting the electrical connection points of the conductive layer forming device; and the blank area can provide an area for mating with the seal of the conductive layer forming device, thereby increasing the effective use area of the wafer for packaging;

[0011] (3) The blank area of the panel component can provide an area for forming a metal simulation pattern, thereby improving the parameter stability of the packaged product and increasing the yield.

[0012] The present disclosure also provides a semiconductor device, the back surface of which has a plastic encapsulation layer, which can avoid warping.

[0013] A packaging method for semiconductor devices includes:

[0014] Providing at least one wafer, the wafer having an active surface and a wafer back surface;

[0015] Arranging at least one of the wafers on a panel to form a panel component;

[0016] Forming a conductive layer on the active surface of the wafer on the panel component;

[0017] Forming a dielectric layer on the active surface of the wafer and the conductive layer.

[0018] In some embodiments, the active surface of the wafer includes bonding pads and an insulating protective layer, the conductive layer is formed on the bonding pads and the insulating protective layer, and the conductive layer is electrically connected to the bonding pads for leading out the bonding pads.

[0019] In some embodiments, the back surface of the wafer faces the panel component, and the active surface of the wafer faces away from the panel component, exposing the active surface.

[0020] In some embodiments, the panel component has a front surface of the panel component, and the front surface of the panel component is a flat surface.

[0021] In some embodiments, the panel component includes a blank area, and the blank area includes an electrical connection point contact area for providing a position for contacting the electrical connection points.

[0022] In some embodiments, the panel assembly includes a blank area, and the blank area includes a sealing area for providing a position where a seal is fitted.

[0023] In some embodiments, the panel assembly includes a blank area, and the blank area includes a metal simulation pattern formation area.

[0024] In some embodiments, it further includes the step of forming a metal simulation pattern in the metal simulation pattern formation area.

[0025] In some embodiments, the panel assembly includes at least one conductive member, and at least a part of at least one of the conductive members corresponds to the position of at least one electrical connection point.

[0026] In some embodiments, the panel assembly is formed by plastic material molding to connect at least one of the wafers into one body.

[0027] In some embodiments, the plastic material molding includes arranging at least one of the wafers on a carrier plate or arranging them on a lower template;

[0028] The active surface of the wafer faces the front of the carrier plate or the front of the lower template;

[0029] A plastic encapsulation layer is formed on the front of the carrier plate or the front of the lower template and on the wafer to construct the panel assembly.

[0030] In some embodiments, the panel assembly is formed by plastic material molding to connect at least one of the wafers and at least one of the conductive members into one body.

[0031] In some embodiments, the plastic material molding includes:

[0032] Arranging at least one of the wafers and at least one conductive member on a carrier plate or arranging them on a lower template;

[0033] The active surface of the wafer faces the front of the carrier plate or the front of the lower template;

[0034] A plastic encapsulation layer is formed on the front of the carrier plate or the front of the lower template, on the wafer, and on the conductive member to construct the panel assembly.

[0035] In some embodiments, the plastic material molding includes:

[0036] Providing at least one mold frame having through holes;

[0037] Arranging at least one of the wafers and at least one of the mold frames on a carrier plate or arranging them on a lower template, and arranging the wafers in the through holes;

[0038] The active surface of the wafer faces the front of the carrier plate or the front of the lower template;

[0039] Form a molding compound layer on the front side of the carrier board or the front side of the lower template, on the wafer, and on the mold frame to construct a panel assembly.

[0040] In some embodiments, the step of forming the conductive layer includes forming a seed layer that integrally covers at least a part of at least one of the conductive members on the panel assembly and at least one of the wafers on the panel assembly.

[0041] In some embodiments, it further includes the step of using an image positioning device to perform image positioning on the wafers on the panel assembly to determine the arrangement positions of the wafers on the panel assembly.

[0042] A semiconductor device packaging method includes:

[0043] Provide at least one wafer having an active surface and a back side of the wafer;

[0044] Arrange at least one of the wafers on a panel to form a panel assembly;

[0045] Form a conductive layer and / or a dielectric layer on the active surface side of at least one of the wafers.

[0046] In some embodiments, the step of forming the panel assembly includes the step of forming a passivation layer on the active surface of the wafer.

[0047] In some embodiments, the front side of the panel assembly includes a blank area configured to provide at least one electrical connection point contact area for providing a position for contacting an electrical connection point.

[0048] In some embodiments, the blank area includes a sealing area for providing a position for the sealing member to fit.

[0049] In some embodiments, the front side of the panel assembly includes a blank area that includes a metal simulation pattern formation area.

[0050] In some embodiments, the panel assembly is formed by molding a plastic material to connect at least one of the wafers into one body.

[0051] A semiconductor device includes:

[0052] A wafer having an active surface and a back side of the wafer;

[0053] A molding compound layer encapsulating the wafer;

[0054] A conductive layer formed on the active surface of the wafer;

[0055] A dielectric layer formed on the active surface of the wafer and the conductive layer.

[0056] In some embodiments, the active surface of the wafer includes bonding pads and an insulating protective layer, the conductive layer is formed on the bonding pads and the insulating protective layer, and the conductive layer is electrically connected to the bonding pads for leading out the bonding pads.

[0057] In some embodiments, the encapsulation layer encapsulates the side surface and the back surface of the wafer.

[0058] In some embodiments, the material and / or thickness of the encapsulation layer are designed to match the material and / or thickness of the dielectric layer to mitigate or eliminate warping.

[0059] In some embodiments, the encapsulation layer encapsulates the side surface of the wafer, exposing the back surface of the wafer.

[0060] In some embodiments, the encapsulation layer has a front surface on which a metal simulation pattern is formed.

[0061] In some embodiments, the surface of the dielectric layer has grooves.

[0062] A semiconductor device, comprising:

[0063] At least one wafer having an active surface and a back surface;

[0064] An encapsulation layer encapsulating at least one of the wafers;

[0065] A composite layer is formed on the active surface of at least one of the wafers.

[0066] In some embodiments, the composite layer includes a conductive layer and / or a passivation layer and / or a dielectric layer.

[0067] In some embodiments, the composite layer includes a conductive layer and a dielectric layer.

[0068] In some embodiments, the composite layer includes a conductive layer, a dielectric layer, and a passivation layer.

[0069] In some embodiments, at least one of the wafers includes a side surface, and the encapsulation layer encapsulates the side surface and the back surface of the wafer.

[0070] In some embodiments, the material and thickness of the encapsulation layer are designed to match the material and thickness of the dielectric layer to mitigate or eliminate warping.

[0071] A semiconductor device, comprising:

[0072] A die having a die active surface and a die back surface;

[0073] A plastic encapsulation layer formed on the back surface of the die;

[0074] A conductive layer formed on the active surface of the die;

[0075] A dielectric layer formed on the active surface of the die and the conductive layer.

[0076] In some embodiments, the active surface of the die includes bonding pads and an insulating protective layer, the conductive layer is formed on the bonding pads and the insulating protective layer, and the conductive layer is electrically connected to the bonding pads for leading out the bonding pads.

[0077] In some embodiments, the edge of the plastic encapsulation layer is flush with the edge of the semiconductor die.

[0078] In some embodiments, the edge of the dielectric layer is flush with the edge of the semiconductor die.

[0079] In some embodiments, the material and / or thickness of the plastic encapsulation layer is designed to match the material and / or thickness of the dielectric layer to slow down or eliminate warping.

[0080] In some embodiments, the surface of the dielectric layer has grooves.

[0081] A semiconductor device, comprising:

[0082] At least one die having an active surface and a back surface;

[0083] A plastic encapsulation layer formed on the back surface of at least one of the dies;

[0084] A composite layer formed on the active surface of at least one of the dies.

[0085] In some embodiments, the composite layer includes a conductive layer and / or a passivation layer and / or a dielectric layer.

[0086] In some embodiments, the composite layer includes a conductive layer and a dielectric layer.

[0087] In some embodiments, the composite layer includes a conductive layer, a dielectric layer and a passivation layer.

[0088] In some embodiments, the edge of the plastic encapsulation layer is flush with the edge of the semiconductor die.

[0089] In some embodiments, the material and / or thickness of the plastic encapsulation layer is designed to match the material and / or thickness of the dielectric layer to slow down or eliminate warping. Description of the Drawings

[0090] Figures 1a to 1jis a flowchart of a packaging method according to an exemplary embodiment of the present disclosure.

[0091] Figures 2a to 2d is a flowchart of a packaging method according to another exemplary embodiment of the present disclosure.

[0092] Figures 3a to 3e is a flowchart of a packaging method according to still another exemplary embodiment of the present disclosure.

[0093] Figures 4a to 4h is a flowchart of a packaging method according to yet another exemplary embodiment of the present disclosure.

[0094] Figures 5a to 5d is a schematic structural diagram of a wafer packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure.

[0095] Figures 6a to 6d is a schematic structural diagram of a chip packaging structure obtained by using the above packaging method according to an exemplary embodiment of the present disclosure.

[0096] Figure 7 is a cross-sectional view of a packaging structure welded to a circuit board formed according to an exemplary embodiment of the present disclosure.

[0097] Figure 8 In (a) and (b) are respectively the front view and the top view of a schematic diagram of a conductive fixture of a wafer-level chip size packaging and a conductive layer forming device. Detailed implementation manners

[0098] To make the technical solutions, advantages, and objectives of the present disclosure clearer and more understandable, the following further elaborates on the present disclosure in detail in combination with specific embodiments and with reference to the accompanying drawings.

[0099] Figures 1a to 1j is a flowchart of a chip packaging method according to an exemplary embodiment of the present disclosure.

[0100] As Figure 1a shown, at least one semiconductor wafer 100 is provided. The semiconductor wafer 100 has an active surface 101 and a wafer back surface 107. The wafer 100 includes a plurality of dies. The active surface of each die constitutes the active surface 101 of the wafer 100. A series of active components and passive components are formed on the active surface of each die through a series of processes such as doping, deposition, and etching. The active components include diodes, triodes, etc., and the passive components include voltage transformers, capacitors, resistors, inductors, etc. These active components and passive components are connected using connection lines to form a functional circuit, thereby realizing various functions of the chip. The active surface 101 further includes bonding pads 103 for leading out the functional circuit and an insulating protective layer 105 for protecting the bonding pads 103.

[0101] As shown in Figure 1b , a carrier 111 is provided, and at least one wafer 100 is arranged on the front surface 113 of the carrier. The active surface 101 of the wafer 100 faces the carrier 111 and is arranged thereon. In one embodiment, the wafer 100 is bonded and fixed to the carrier 111 by an adhesive layer 109.

[0102] The shape of the carrier 111 is circular, triangular, quadrilateral or any other shape. The size of the carrier 111 can be a small-sized wafer substrate or various sizes, especially large-sized rectangular carriers. The material of the carrier can be metal, non-metal, plastic, resin, glass, stainless steel, etc. The present disclosure does not make any limitations on the shape, size, and material of the carrier. Preferably, the carrier 111 is a quadrilateral plate made of stainless steel.

[0103] The carrier 111 has a front surface 113 and a back surface 115 of the carrier. The front surface 113 of the carrier is preferably a flat surface, and the front surface 113 of the carrier can also be set to have a concave-convex surface according to specific needs.

[0104] The adhesive layer 109 can be formed on the front surface 113 of the carrier by means of lamination, printing, spraying, coating, etc. In order to facilitate the separation of the carrier 111 and the encapsulated wafer 100 in the subsequent process, the adhesive layer 109 preferably uses an easily separable material. In one embodiment, a thermal separation material is used as the adhesive layer 109, and the thermal separation material can lose its viscosity under heating conditions. In another embodiment, the adhesive layer 109 adopts a double-layer structure: a thermal separation material structure layer and a wafer adhesion layer. The thermal separation material structure layer is pasted on the carrier 111, and the wafer adhesion layer is used to adhere to the wafer 100. When separating the wafer 100 and the carrier 111, heating is used to make the thermal separation material structure layer lose its viscosity, the carrier 111 is removed, and then the adhesive layer 109 is removed from the surface of the wafer 100 by mechanical force peeling. At the same time, the wafer adhesion layer can be removed by chemical cleaning. After removing the adhesive layer 109, the residues remaining on the chip surface can be removed by chemical cleaning.

[0105] Preferably, the arrangement position of the wafer 100 can be pre-identified on the carrier 111. The identification can be formed on the carrier 111 by means of laser, mechanical engraving, etc. At the same time, alignment marks are also provided on the wafer 100 to aim and align with the pasting position on the carrier 111 during pasting.

[0106] Preferably, while arranging the wafers 100 on the carrier plate 111, conductive members are also arranged. The material of the conductive members can be selected from metals, graphite, copper, gold, silver, iron, aluminum, etc. The position where the conductive members are arranged is at least partially corresponding to the position of the electrical connection contact points of the equipment used in the subsequent conductive layer formation process. Generally, the position of the electrical connection contact points corresponds to the periphery of the carrier plate 111. Therefore, the conductive members are arranged around the periphery of the carrier plate 111. For example, when the shape of the carrier plate 111 is rectangular, the position of the electrical connection contact points can be the inner sides of the edges corresponding to the four sides of the rectangular carrier plate 111, and extend parallel to the four sides of the rectangular carrier plate 111. At this time, the conductive members are arranged on the inner sides of the edges of the four sides of the rectangular carrier plate 111 and extend parallel to the four sides of the rectangular carrier plate 111. At this time, the conductive members can also be arranged on the inner sides of the edges of the two opposite sides of the rectangular carrier plate 111 and extend parallel to the inner sides of the edges of the two opposite sides of the rectangular carrier plate 111; the position of the electrical connection contact points can also be the inner sides of the edges corresponding to the two opposite sides of the rectangular carrier plate 111 and extend parallel to the two opposite sides of the rectangular carrier plate 111. At this time, the conductive members are arranged on the inner sides of the edges of the two opposite sides of the rectangular carrier plate 111 and extend parallel to the inner sides of the edges of the two opposite sides of the rectangular carrier plate 111. The area and / or width of the conductive members are preferably larger than the area of the electrical connection contact point region in the conductive layer forming device. The height of the conductive members can be the same as the height of the wafers 100, can be lower than the height of the wafers 100, or can be higher than the height of the wafers 100. The present disclosure does not make any limitation on the shape of the conductive members. The conductive members are preferably metal foils, such as copper foils.

[0107] Figure 1c FIG. is a top view of the arrangement of the wafers 100 on the carrier plate 111 according to an embodiment.

[0108] In another embodiment, the number of wafers 100 on the carrier plate 111 is determined by the sizes of the carrier plate 111 and the wafers 100. For example: when the size of the carrier plate 111 is 600×580 mm, it can accommodate two (02) 12-inch wafers 100, five (05) 8-inch wafers 100, and nine (09) 6-inch wafers 100; when the size of the carrier plate 111 is 670x670 mm, it can accommodate four (04) 12-inch wafers 100, nine (09) 8-inch wafers 100, and sixteen (16) 6-inch wafers.

[0109] Preferably, when arranging the wafers 100 on the carrier plate 111, a blank area is left on the carrier plate 111. The blank area is a sealing area and / or an electrical connection point contact area. The sealing area corresponds to the corresponding area where the seal is located in the conductive layer formation process, and the electrical connection point contact area is used to provide a position for contacting the electrical connection points. In one embodiment, the sealing area is located inside the electrical connection point contact area.

[0110] Preferably, the wafers 100 are arranged on the carrier 111 with blank areas left between the wafers 100. The blank areas include the areas for forming metal simulation patterns in the subsequent processes and the dicing areas for dicing the wafers 100 on the panel assembly into individual single wafers 100 in the subsequent processes.

[0111] Figure 1d It shows that a molding compound layer 117 is formed around the wafers 100 on the carrier 111. The molding compound layer 117 is formed on the back surface 107 of the wafer, the exposed carrier 111 and / or the exposed adhesive layer 109. The molding compound layer 117 is used to completely encapsulate the carrier 111 and the wafers 100 to construct a panel structure. When there are conductive components on the carrier 111, the molding compound layer 117 completely encapsulates the carrier 111, the wafers 100 and the conductive components to construct a panel structure.

[0112] Optionally, before forming the molding compound layer 117, some pretreatment steps can be performed, such as chemical cleaning, plasma cleaning, etc., to remove impurities on the surface so that the molding compound layer 117 can be more closely bonded to the wafers 100 and the carrier 111.

[0113] The molding compound layer 117 can be formed by methods such as paste printing, injection molding, thermoforming, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods.

[0114] The molding compound layer 117 can be made of organic composite materials, resin composite materials, polymer composite materials, polymer composites, such as epoxy resins with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers.

[0115] The molding compound layer 117 includes a back surface 119 of the molding compound layer opposite to the carrier 111. In one embodiment, the back surface 119 of the molding compound layer is substantially parallel to the front surface 113 of the carrier. Optionally, the thickness of the molding compound layer 117 can be reduced by grinding or polishing the back surface 119 of the molding compound layer. In one embodiment, the thickness of the molding compound layer 117 can be reduced to the back surface of the wafers 100.

[0116] Figure 1e It shows the removal of the carrier 111, exposing the active surface 101 of the wafer, the front surface 121 of the molding compound layer, and one surface of the conductive components when there are conductive components.

[0117] The first carrier 111 can be removed by direct mechanical force peeling; when a thermal release film is used as the adhesive layer 109, the first carrier 111 can also be peeled off by heating to reduce the viscosity of the thermal release film when heated.

[0118] Optionally, before peeling off the carrier substrate 111, a support plate is connected to the back surface 803 of the panel assembly to support the panel assembly 800, making it easier to transfer the panel assembly 800 and perform operations in the subsequent processes.

[0119] After peeling off the carrier substrate 111, the active surface 101 of the wafer 100, the front surface 121 of the encapsulation layer, and one surface of the conductive member (when present) are exposed. The encapsulation layer 117 connects the wafer 111 and the conductive member (when present) into one body, and the subsequent encapsulation steps are performed on this reconfigured panel structure.

[0120] The panel structure composed of the wafer 100, the encapsulation layer 117, and the conductive member (when present) is referred to as the panel assembly 800.

[0121] The front surface 801 of the panel assembly is composed of the active surface 101 of the wafer 100, one surface of the conductive member (when present), and the front surface 121 of the encapsulation layer.

[0122] The front surface 801 of the panel assembly is preferably a flat surface, that is, the active surface 101 of the wafer 100, one surface of the conductive member (when present), and the front surface 121 of the encapsulation layer are at the same height and in a plane.

[0123] The front surface 801 of the panel assembly may also not be a flat surface. When the front surface 113 of the carrier substrate is set to have a concave-convex surface, the front surface 801 of the panel assembly is the corresponding concave-convex surface, or after peeling off the carrier substrate 111, the required pattern is formed on the front surface 121 of the encapsulation layer by laser or mechanical engraving.

[0124] The back surface 803 of the panel assembly is preferably a horizontal structure that is substantially parallel to the front surface 801 of the panel assembly.

[0125] Corresponding to the arrangement of the wafers 100 on the carrier substrate 111, in one embodiment, the panel assembly 800 includes a blank area, and the blank area includes an electrical connection point contact area for providing a position for contacting the electrical connection point.

[0126] In one embodiment, the panel assembly 800 includes a blank area, and the blank area includes a sealing area for providing a position for the sealing member to be sealed.

[0127] In one embodiment, the panel assembly 800 includes a blank area, and the blank area includes a metal simulation pattern formation area.

[0128] In one embodiment, the panel assembly 800 includes at least one conductive member 207, and at least a part of at least one of the conductive members 207 corresponds to the position of at least one electrical connection point.

[0129] Preferably, after the encapsulation process is completed, the panel is transferred to an image positioning device to perform image positioning on the wafer 100 on the panel assembly 800 to determine the arrangement position of the wafer 100 on the panel assembly 800.

[0130] During the encapsulation process, the molding material shrinks during curing, causing the relative position of the wafer 100 on the panel assembly 800 to be different from its arrangement position on the original carrier 111. By using the image positioning device to reposition the wafer 100, the alignment during the formation process of the conductive layer can be made precise. Moreover, the wafer 100 is different from the molding material. The wafer 100 itself does not expand or contract, and its surface area does not change during the molding process. In addition, due to the large surface area of the wafer 100, it is easily recognizable during image positioning. Therefore, the image positioning device can accurately locate the relative position of the wafer 100 on the panel assembly 800, and thus the relative positions between the die chips within the wafer are also easily locatable, ensuring the position accuracy of the subsequent conductive layer formation process.

[0131] Figures 1f - 1g An embodiment of the process of forming a patterned conductive layer on the active surface 101 of the wafer 100 arranged on the panel assembly 800 is shown.

[0132] Figure 1f It shows that a conductive trace 123 is formed on the active surface of the wafer 100 arranged on the panel assembly 800 and / or a metal simulation pattern a is formed in the metal simulation pattern formation area of the panel assembly 800; the conductive trace 123 is formed on the solder pad 103 and the insulating protective layer 105 on the active surface 101 of the wafer 100 and is electrically connected to the solder pad 103; the conductive trace 123 can be made of one or more layers of materials such as gold, silver, copper, tin, aluminum, or other suitable conductive materials.

[0133] Figure 1g It shows that a conductive bump 127 is formed on the solder pad or connection point of the conductive trace 123 and / or a metal simulation pattern b is formed in the metal simulation pattern formation area of the panel assembly 800; the shape of the conductive bump 127 can be circular or other shapes such as oval, square, linear, etc. The conductive bump 127 can be made of one or more layers of materials such as gold, silver, copper, tin, aluminum, or other suitable conductive materials.

[0134] The conductive layer is composed of the conductive trace and / or the conductive bump 127, and the conductive layer can be one layer or multiple layers. In one embodiment, repeat Figure 1f and / or Figure 1g the steps to form a multi-layer conductive layer on the active surface 101 of the wafer 100.

[0135] In one embodiment, the steps of forming the conductive layer include spin coating photoresist, photolithography, development, sputtering and / or electroless plating, electroplating, stripping, etc.

[0136] Compared with wafer-level chip scale packaging, forming a conductive layer on the active surface of a single wafer results in low production efficiency and high production costs.

[0137] In the embodiments of the present disclosure, the panel assembly 800 is used to complete the fabrication of the conductive layers of multiple wafers at one time, improving the packaging efficiency and reducing the packaging price.

[0138] In a preferred embodiment, the panel assembly 800 has an edge blank area, which includes a sealing area and an electrical connection point contact area. The sealing area is used to provide a region where the sealant fits during the conductive layer formation process, and the electrical connection point contact area is used to provide a region for electrical connection point contact with the conductive layer forming equipment. Thus, each wafer 100 on the panel assembly 800 has no invalid area, and the entire wafer is an effective area, increasing the utilization rate of the wafer and further reducing the packaging price.

[0139] In another preferred embodiment, there is also a certain blank area left between the wafers 100 arranged on the panel assembly 800. This blank area can be provided as a region for forming a metal simulation pattern 125, which is called a metal simulation pattern formation area. The metal simulation pattern 125 is a metal layer formed outside the active surface range of the wafer during the conductive layer formation process. The metal layer can be any pattern. Preferably, the metal layer pattern is a pattern that is continuous and consistent with the pattern on the wafer. During the conductive layer formation process, the metal simulation pattern 125 is formed on the front surface 121 of the encapsulation layer. During the formation of the metal simulation pattern 125, the current flowing into the wafer 100 is dispersed, reducing the current density in the peripheral area of the wafer 100 and making the current evenly distributed across the entire wafer 100, so that the thickness of the conductive layer on the entire surface of the wafer 100 is uniform. Preferably, the metal simulation pattern formation area is the periphery of the wafer 100. Further preferably, the metal simulation pattern formation area is formed to extend at least 5 mm from the edge of the wafer 100 towards the encapsulation layer.

[0140] In yet another preferred embodiment, the panel assembly 800 includes at least one conductive member 207, and at least a part of at least one of the conductive members 207 corresponds to the position of at least one electrical connection point. During the formation of the conductive layer, the electrical connection point is connected to the conductive member. In the conductive layer formation process, it is necessary to first deposit a seed metal layer on the front surface 801 of the panel assembly including the front surface 121 of the encapsulation layer and the active surface 101 of the wafer 100 by sputtering or electroless plating. The seed metal layer is usually a copper layer. The seed layer is very thin, usually in the range of 100 nm. The seed layer is used as a conductive plane for the formation of the patterned conductive layer. During the formation of the patterned conductive layer circuit, the electrical connection point is connected to the front surface 801 of the panel assembly in the form of physical connection contact and physically contacts the seed layer to form a conductive path. Generally, the conductive layer forming device also includes an anode. During the formation of the conductive layer, the panel assembly 800 is used as the cathode and immersed in the processing solution. The current flows through the electrical connection point, the seed layer, the processing solution and the anode, and metal is deposited on the front surface 801 of the panel assembly to form a conductive layer circuit pattern. During this process, the physical contact condition between the electrical connection point of the conductive layer forming device and the seed layer is crucial for the stability of the conductive layer formation process and the quality of the circuit pattern of the conductive layer. However, due to the thin thickness of the seed layer, the contact force with the electrical connection point may cause wear of the conductive seed layer at the contact position, resulting in poor conductive contact between the panel assembly 800 and the electrical connection point and affecting the quality of the conductive layer circuit pattern. The presence of the conductive member enables the seed layer of the electrical connection point to still have good contact between the panel assembly 800 and the electrical connection point due to the conductive ability of the conductive member even in the case of wear. At the same time, the conductive member enhances the conductive performance of the panel assembly 800 and has a good conduction effect on the current. The conductive member enables the current at the electrical connection point to flow uniformly across the entire front surface 801 of the panel assembly. Preferably, the seed layer covers at least a part of at least one of the conductive members 207 on the panel assembly 800 and at least one of the wafers 100 on the panel assembly 800 as a whole.

[0141] As Figure 1h shown, the wafer 100 is separated from the panel assembly 800, and cutting is performed along the periphery of the wafer 100 using mechanical or laser means. The panel assembly 800 can be divided into circular, polygonal, and any irregular shapes; cutting can be performed along the outer edge of the wafer 100; preferably, cutting is performed at a certain distance from the outer edge of the wafer. In the cutting step, the metal simulation pattern 125 can be retained around the divided wafer, or the metal simulation pattern 125 can be removed during the division process.

[0142] As Figure 1i shown, in one embodiment, cutting is performed along the edge of the metal simulation pattern 125 around the periphery of the wafer 100. For example, cutting is performed along the dividing line 131.

[0143] AsFigure 1j As shown, a dielectric layer 133 is formed on the active surface 101 and the conductive layer of the wafer 100; and the packaged wafer is diced to form individual chips.

[0144] One or more dielectric layers 133 are formed on the surface of the conductive layer using lamination, coating, spraying, printing, molding, and other suitable methods.

[0145] The dielectric layer 133 can be BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, a polymer matrix dielectric film, an organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymer composite, such as an epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulating and structural properties.

[0146] The dielectric layer 133 serves to protect the conductive layer and provide insulation.

[0147] The structure of the packaged wafer is as Figure 5a shown.

[0148] Optionally, the step of applying the dielectric layer 133 can also be performed after the formation of the conductive layer and before the panel assembly 800 is diced to separate individual wafers.

[0149] Optionally, after the step of separating individual wafers from the panel assembly 800 and / or after the step of applying the dielectric layer 133, the back surface 119 of the encapsulation layer is ground or polished to thin the thickness of the encapsulation layer 117. In one embodiment, the thickness of the encapsulation layer 117 can be thinned to the back surface of the wafer 100. The structure of the packaged wafer is as Figure 5b shown.

[0150] In a preferred embodiment, after the step of applying the dielectric layer 133, the outermost conductive layer is etched to thin its thickness to form a groove 137 on the outer surface of the dielectric layer 133. The structure of the packaged wafer is as Figure 5c shown.

[0151] The packaged wafer 100 is diced using mechanical or laser cutting to form multiple packaged chips 135. The packaged structure of the formed chips 135 is as Figure 6a , Figure 6b and Figure 6c shown.

[0152] Return to Figures 1f to 1j the step of

[0153] In one embodiment, the step of forming the conductive layer can be:

[0154] Form a conductive trace 123 on the active surface 101 of the wafer 100;

[0155] Use lamination, coating, spraying, printing, molding, and other suitable methods to form one or more dielectric layers 133 on the surface of the conductive trace 123. The height of the dielectric layer 133 is higher than that of the conductive trace 123, and the conductive trace 123 is completely encapsulated in the dielectric layer 133;

[0156] Form an opening at a position on the dielectric layer 133 corresponding to the pad or connection point of the conductive trace 123, and form a conductive bump in the opening.

[0157] In another embodiment, a conductive bump may not be formed in the opening, so that the pad or connection point of the conductive trace 123 of the completed package is exposed from the opening.

[0158] Advantages of forming the panel assembly by encapsulation:

[0159] (1) The panel assembly is firmly combined;

[0160] (2) It is easy to form a panel assembly with a horizontal front surface;

[0161] (3) The encapsulation layer 117 firmly wraps the back and side surfaces of the wafer. During the formation of the conductive layer, the processing liquid is not easily infiltrated into the back and side surfaces of the wafer.

[0162] Figures 2a to 2d The process flow embodiment of an exemplary panel packaging method is shown.

[0163] As Figure 2a shown, provide a plastic material processing and forming device, and the plastic material processing and forming device can be an injection molding device, a hot pressing device, a slurry printing device, a compression molding device, a transfer molding device, a liquid sealant molding device, a vacuum lamination device, or other suitable molding devices.

[0164] The plastic material processing and forming device has a lower template 201. The lower template 201 has a lower template front surface 203 and a lower template back surface 205. The lower template front surface 203 is preferably a flat surface, and the lower template front surface 203 can also be set to have a concave-convex surface according to specific needs.

[0165] At least one semiconductor wafer 100 is directly arranged on the lower template 201, and the active surface 101 of the wafer 100 faces the lower template 201. The plastic material processing equipment further includes a vacuum pumping device, wherein the lower template 201 is provided with air holes for vacuum pumping, and the lower template fixes the wafer 100 on the lower template 201 by using the vacuum degree formed during vacuum pumping. Preferably, before arranging the wafer 100 on the lower template 201, an isolation layer 209 is placed on the front surface 203 of the lower template to isolate the wafer 100 from the lower template 201. The isolation layer 209 also has the function of protecting the active surface 101 of the wafer 100, and after the plastic encapsulation layer is formed, it makes it easy for the panel assembly to be separated from the lower template. The isolation layer 209 can be a polymer film, a rubber film, a polymer film, etc. In one embodiment, the isolation layer 209 can be placed on the front surface 203 of the lower template by means of a reel 211, and the isolation layer 209 is automatically replaced by the reel 211 after each molding.

[0166] Preferably, while arranging the wafer 100 on the lower template 201, a conductive member 207 is also arranged. The material of the conductive member 207 can be selected from metals, graphite, copper, gold, silver, iron, aluminum, etc. The setting position of the conductive member 207 is such that at least a part of the conductive member corresponds to the position of the electrical connection contact point during the subsequent formation process of the conductive layer. Generally, the position of the electrical connection contact point corresponds to the periphery of the lower template 201. Therefore, the conductive member is arranged around the periphery of the lower template 201. Usually, the shape of the lower template 201 is quadrilateral, and the position of the electrical connection contact point can be corresponding to the inner sides of the edges of the four sides of the lower template 201, and extends parallel to the four sides of the lower template 201. At this time, the conductive member is arranged on the inner sides of the edges of the four sides of the lower template 201 and extends parallel to the four sides of the lower template 201. At this time, the conductive member can also be arranged on the inner sides of the edges of the two opposite sides of the lower template 201 and extends parallel to the inner sides of the edges of the two opposite sides of the lower template 201; the position of the electrical connection contact point can also be corresponding to the inner sides of the edges of the two opposite sides of the lower template 201 and extends parallel to the two opposite sides of the lower template 201. At this time, the conductive member is arranged on the inner sides of the edges of the two opposite sides of the lower template 201 and extends parallel to the inner sides of the edges of the two opposite sides of the lower template 201. The width of the conductive member is preferably greater than the area of the electrical connection contact point region; the length of the conductive member is preferably to pass through the entire lower template 201 and extend from one end of the lower template 201 to the other end; the height of the conductive member can be any height, can be the same as the height of the die, can be lower than the height of the die, or can be higher than the height of the die. The conductive member is preferably a metal foil, such as a copper foil.

[0167] Figure 2b As shown in a top view of the arrangement of the wafer 100 on the lower template 201 according to an embodiment.

[0168] In another embodiment, the number of wafers 100 on the lower template 201 is determined by the sizes of the lower template 201 and the wafers 100. For example, when the size of the lower template 201 is 600×580 mm, it can accommodate two (02) 12-inch wafers 100; five (05) 8-inch wafers 100, or nine (09) 6-inch wafers 100. In another embodiment, when the size of the lower template 201 is 670x670 mm, it can accommodate four (04) 12-inch wafers 100, nine (09) 8-inch wafers 100 or sixteen (16) 6-inch wafers.

[0169] Preferably, the arrangement of the wafers 100 on the lower template 201 is such that a blank area is left around the outer peripheral edge of the lower template 201. The blank area is divided into a sealing area 215 and an electrical connection point contact area 217, and conductive members 207 are arranged in the electrical connection point contact area 217. During the formation of the conductive layer, the area where the sealant is located is inside the area where the conductive members 207 are located, so the sealing area 215 is located between the wafer arrangement area and the area where the conductive members 207 are located. The arrangement of the wafers 100 on the lower template 201 is such that there is also a certain blank area between the wafers 100. This blank area is a metal simulation pattern formation area 213 for forming the metal simulation pattern 125 in the subsequent process, and a dicing area for dicing the wafers 100 on the panel assembly into independent single wafers 100 in the subsequent process.

[0170] Figure 2c As shown in, a molding compound layer 117 is formed around the wafers 100 on the lower template 201. The molding compound layer 117 is formed on the back surface 107 of the wafer, the exposed lower template 201, and / or the exposed isolation layer 209. The molding compound layer 117 is used to completely encapsulate the lower template 201 and the wafers 100 to construct a panel structure. When the conductive members 207 are provided on the lower template 201, the molding compound layer 117 completely encapsulates the lower template 201, the wafers 100, and the conductive members 207 to construct a panel structure.

[0171] Optionally, before forming the molding compound layer 117, some pretreatment steps can be performed, such as chemical cleaning, plasma cleaning, etc., to remove impurities on the surface so that the molding compound layer 117 can be more closely bonded to the wafers 100 and the lower template 201.

[0172] The molding compound layer 117 can be formed by methods such as paste printing, injection molding, thermocompression molding, compression molding, transfer molding, liquid sealant molding, vacuum lamination, or other suitable molding methods.

[0173] The molding compound layer 117 can be made of organic composite materials, resin composite materials, polymer composite materials, polymer composites, such as epoxy resins with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers.

[0174] The encapsulation layer 117 includes a back surface 119 of the encapsulation layer opposite to the lower template 201, and the back surface 119 of the encapsulation layer is substantially parallel to the lower template 201. Optionally, the thickness of the encapsulation layer 117 can be reduced by grinding or polishing the back surface 119 of the encapsulation layer. In one embodiment, the thickness of the encapsulation layer 117 can be reduced to the back surface of the wafer 100.

[0175] Figure 2d It shows the separation of the panel assembly 800 from the lower template 201 and the formation of a conductive layer on the surface of the wafer 100 using the panel assembly 800.

[0176] After the molding process is completed, the panel structure composed of the wafer 100, the encapsulation layer 117, and the conductive member 207 when the conductive member 207 exists is called the panel assembly 800. The subsequent conductive layer formation process is carried out on the panel assembly 800.

[0177] The front surface 801 of the panel assembly is composed of the active surface 101 of the wafer 100, one surface of the conductive member 207 when the conductive member 207 exists, and the front surface 121 of the encapsulation layer.

[0178] The front surface 801 of the panel assembly is preferably a flat surface, that is, the active surface 101 of the wafer 100, one surface of the conductive member when the conductive member exists, and the front surface 121 of the encapsulation layer are at the same height and in a plane.

[0179] The front surface 801 of the panel assembly can also be any surface. When the lower template 201 is set to have a concave-convex surface, the front surface 801 of the panel assembly is the corresponding concave-convex surface, or after the assembly is separated from the lower template 201, the desired pattern is formed on the front surface 121 of the encapsulation layer by laser or mechanical engraving.

[0180] The back surface 803 of the panel assembly is preferably a horizontal structure substantially parallel to the front surface 801 of the panel assembly, but the present disclosure does not impose any restrictions on the shape and state of the back surface of the panel assembly.

[0181] Optionally, after the panel assembly 800 is separated from the lower template 201, a support plate is connected to the back surface 803 of the panel assembly to support the panel assembly 800 and make it easier to transfer and operate in the subsequent processes.

[0182] A patterned conductive layer is formed on the active surface 101 of the wafer 100 using the formed panel assembly 800. Details such as the formation method and materials of the conductive layer are specifically described in the description of the conductive layer formation step in Figures 1a to 1j and will not be elaborated here.

[0183] In one embodiment, while arranging the wafers 100 on the carrier plate 111, conductive members 207 are also arranged. At this time, the positions of the conductive members 207 correspond to those of the electrical connection points. During the formation process of the conductive layer, the electrical connection points are connected to the conductive members 207. The existence of the conductive members 207 enables the seed layer of the electrical connection points to maintain good contact with the electrical connection points of the panel assembly 800 and the conductive layer forming equipment due to the conductive ability of the conductive members even under worn conditions. At the same time, the conductive members enhance the conductive performance of the panel assembly 800, have a good conduction effect on the current, and enable the current at the electrical connection points to flow uniformly on the entire front surface 801 of the panel assembly.

[0184] The specific details of the steps of separating the wafers 100 from the panel assembly 800, forming the dielectric layer 133 on the active surface 101 of the wafers 100 and the conductive layer, and cutting the packaged wafers to form individual chips can be found in Figures 1a to 1j the descriptions of the corresponding steps therein, which will not be elaborated here.

[0185] Figures 3a to 3e The process flow embodiments of an exemplary panel packaging method are shown.

[0186] As Figure 3a shown, a mold frame 300 is provided. The shape of the mold frame 300 can be: circular, triangular, quadrilateral or any other shape. The material of the mold frame 300 is preferably metal or any material coated with metal (both the metal and the metal-coated mold frame 300 will be hereinafter referred to as the metal mold frame). The metal mold frame 300 can be used as a conductive structure during the conductive layer formation process to improve conductivity and make the current density distribution uniform. The metal mold frame 300 can optionally be copper, iron, aluminum, stainless steel, etc. Preferably, the mold frame 300 is a quadrilateral frame made of stainless steel. The height of the mold frame is not less than the height of the wafers 100. The mold frame 300 has at least one mold through-hole 301, and the size of the mold through-hole 301 is not less than the size of the wafers 100. Preferably, blank areas are distributed around the mold frame 300, and the blank areas are the sealing areas 303 and / or the electrical connection point contact areas 305. The sealing area 302 corresponds to the corresponding area where the seal is located during the conductive layer formation process, and the electrical connection point contact area 305 corresponds to the position of the electrical connection contact points. The area where the seal is located is inside the electrical connection contact point area, so the sealing area 302 is located inside the electrical connection point contact area 305.

[0187] Figure 3b As shown, the wafers 100 and the mold frame 300 are arranged at predetermined positions on the carrier plate 111 or the lower template 201 of the plastic material processing and forming equipment.

[0188] Provide a carrier 111, arrange a die frame 300 and at least one wafer 100 on the front side 113 of the carrier. The wafer 100 is placed in the die through-hole 301 of the die frame 300, and the active surface 101 of the wafer 100 faces the arrangement direction of the carrier 111. In one embodiment, the wafer 100 is bonded and fixed to the carrier 111 by an adhesive layer 109.

[0189] The shape of the carrier 111 is: circular, triangular, quadrilateral or any other shape. The size of the carrier 111 can be a small-sized wafer substrate or various sizes, especially large-sized rectangular carriers. The material of the carrier can be metal, non-metal, plastic, resin, glass, stainless steel, etc. The present disclosure does not make any limitations on the shape, size, and material of the carrier. Preferably, the carrier 111 is a quadrilateral plate made of stainless steel.

[0190] The adhesive layer 109 can be formed on the front side 113 of the carrier by means of lamination, printing, spraying, coating, etc. In order to facilitate the separation of the carrier 111 and the encapsulated wafer 100 in the subsequent process, the adhesive layer 109 preferably uses a material that is easily separable.

[0191] Transfer the carrier 111 to a plastic material forming device for encapsulation molding.

[0192] Optionally, directly arrange the wafer 100 on the lower template 201 of the plastic material processing and forming device. The plastic material processing and forming device can be an injection molding device, a transfer molding device, a liquid sealant molding device, or other suitable molding devices. The plastic material processing and forming device has a lower template 201. Arrange at least one wafer 100 directly on the lower template 201, and the active surface 101 of the wafer 100 faces the arrangement direction of the lower template 201. The plastic material processing device further includes a vacuum pumping device, where the lower template 201 has air holes for vacuum pumping, and the lower template fixes the wafer 100 on the lower template 201 by the vacuum degree formed during vacuum pumping. Preferably, before arranging the wafer 100 on the lower template 201, place an isolation layer 209 on the front side 203 of the lower template to isolate the wafer 100 and the lower template 201. The isolation layer 209 also has the function of protecting the active surface 101 of the wafer 100 and making it easy for the panel assembly to separate from the lower template after the encapsulation layer is formed. The isolation layer 209 can be a polymer film, a rubber film, a polymer film, etc. In one embodiment, the isolation layer 209 can be placed on the front side 203 of the lower template by means of a reel 211, and the isolation layer 209 is automatically replaced by the reel 211 after each molding. The plastic material processing and forming device further includes a gate 307, and the molten molding material is poured into the die through-hole 301 on the die frame 300 through the gate.

[0193] Figure 3cIt shows the separation of the encapsulated component from the lower template 201, exposing the active surface 101 of the wafer 100, the front surface 121 of the encapsulation layer, and the front surface 309 of the mold frame. The encapsulation layer 117 connects the wafer 110 and the mold frame 300 into an integrated panel-like structure, and the subsequent processes are carried out on this reconstructed panel structure.

[0194] The panel structure composed of the wafer 100, the encapsulation layer 117, and the mold frame 300 is called the panel component 800.

[0195] The front surface 801 of the panel component is composed of the active surface 101 of the wafer 100, the front surface 309 of the mold frame, and the front surface 121 of the encapsulation layer.

[0196] The front surface 801 of the panel component is preferably a flat surface, that is, the active surface 101 of the wafer 100, the front surface 309 of the mold frame, and the front surface 121 of the encapsulation layer are at the same height and in a plane.

[0197] The front surface 801 of the panel component can also be any surface. When the lower template 201 / carrier 111 is set to have a concave-convex surface, the front surface 801 of the panel component is the corresponding concave-convex surface, or after separating the component from the lower template 201 / carrier 111, the required pattern is formed on the front surface 121 of the encapsulation layer by laser or mechanical engraving.

[0198] The back surface 803 of the panel component is preferably a horizontal structure substantially parallel to the front surface 801 of the panel component, but the present disclosure does not impose any restrictions on the shape of the back surface of the panel component 800.

[0199] The advantage of using the mold frame 300 for encapsulation is that it can effectively reduce the warping of the panel component 800. During the encapsulation process, the encapsulation layer material needs to undergo a curing process to fully cure the material so that it firmly binds to the wafer 100 to form the encapsulation layer. The curing process is accompanied by the shrinkage of the encapsulation layer material, which causes the warping of the entire panel component 100. In the embodiment of the present disclosure, the mold frame 300 is used to divide the encapsulation process into multiple zones, and the encapsulation material is cured in each zone. This method of zoned curing reduces the shrinkage area of the encapsulation material from the entire large area to the small areas in each mold frame through hole 301. Therefore, the stress caused by the curing shrinkage of the encapsulation material will be reduced by a corresponding multiple due to the reduction of the shrinkage area, thereby reducing the warping degree.

[0200] Optionally, after separating the panel component 800 from the lower template 201, a support plate is connected to the back surface 803 of the panel component to support the panel component 800, making it easier to transfer the panel component 800 and perform the operations of the subsequent processes.

[0201] Figure 3dShown is the formation of a patterned conductive layer on the active surface 101 of the wafer 100 using the panel assembly 800 and the separation of the wafer 100 from the panel assembly 800.

[0202] Details such as the formation method and material of the conductive layer are specifically described in the Figures 1a to 1j description of the conductive layer formation step in, which will not be elaborated here.

[0203] There are blank areas distributed around the mold frame 300. The blank areas are the sealing area 303 and / or the electrical connection point contact area 305. The sealing area 303 is used to provide an area where the sealant fits during the formation of the conductive layer. The electrical connection point contact area 305 is used to provide an area for electrical connection point contact with the conductive layer formation device. At the same time, the front surface 121 of the encapsulant layer around the wafer 100 and / or the front surface 309 of the mold frame in the mold through hole 301 provide blank areas, and the blank areas can be provided as metal simulation pattern formation areas for forming the metal simulation pattern 125.

[0204] The advantage of introducing the metal mold frame 300 into the panel assembly is that the metal mold frame 300 has good current conduction. In the conductive layer formation process, the electrical connection point contact area 305 of the metal mold frame 300 is connected to the electrical connection point of the device. The presence of the metal mold frame 300 enables the seed layer at the electrical connection point to still have good electrical connection between the panel assembly 800 and the electrical connection point of the device due to the conductive ability of the metal mold frame 300 even under the condition of wear. At the same time, the metal mold frame 300 enhances the conductive performance of the panel assembly 800 and has good current conduction. The conductive member makes the current at the electrical connection point flow evenly across the entire front surface 801 of the panel assembly.

[0205] Separate the wafer 100 from the panel assembly 800, and separate the encapsulation unit containing the wafer 100 in the mold through hole 301 from the mold frame 300.

[0206] Details of the steps of forming the dielectric layer 133 on the active surface 101 of the wafer 100 and the conductive layer and cutting and encapsulating the wafer to form individual chips are specifically described in Figures 1a to 1j the descriptions of the corresponding steps in, which will not be elaborated here.

[0207] In addition to constructing the panel assembly 800 by the method of molding with plastic materials, in one embodiment, the method of constructing the panel assembly 800 is: providing a plate member having at least one cavity. Preferably, the plate member is a quadrilateral made of stainless steel.

[0208] The size of the cavity is not less than the size of the wafer. Preferably, the shape and size of the cavity are substantially the same as the shape and size of the wafer, and the wafer can be exactly embedded in the cavity with the edges of the wafer and the cavity seamlessly connected.

[0209] The height of the plate member and the cavity is preferably the same as the height of the wafer 100 installed in the cavity, that is, the active surface 101 of the wafer 100 and the front surface of the plate member are kept horizontal.

[0210] Preferably, blank areas are distributed around the cavity on the plate member, and the blank areas can be provided as sealing areas and / or electrical connection point contact areas and / or metal simulation pattern areas.

[0211] Provide at least one wafer 100, the wafer 100 has an active surface 101 and a back surface 107 of the wafer. Orient the active surface 101 of the wafer 100 towards the outside of the cavity and the back surface 107 of the wafer towards the inside of the cavity, and place it in the cavity of the plate member, exposing the active surface 101 of the wafer 100.

[0212] Preferably, the active surface 101 of the wafer 100 and the front surface of the plate member are in the same plane.

[0213] The panel assembly 800 is composed of at least one wafer 100 and a plate member.

[0214] The front surface 801 of the panel assembly is composed of the active surface 101 of the wafer 100 and the front surface of the plate member. Preferably, the front surface 801 of the panel assembly is a plane, that is, the active surface 101 of the wafer 100 and the front surface of the plate member have the same height and are in a plane. The back surface of the panel assembly is preferably a horizontal structure substantially parallel to the front surface 801 of the panel assembly.

[0215] The principle followed by the embodiments of the present disclosure is to use a method capable of connecting at least one wafer 100 into an integrated body, so that the wafer 100 and the carrier form a panel assembly 800. For example, it can be a method of plastic material molding, a method of plate member connection, or a method of spraying and curing with an adhesive substance, etc. Under the guidance of this principle, those skilled in the art can conceive other construction methods of the panel assembly 800 without departing from the protection scope of the present disclosure.

[0216] Figures 4a to 4h is the flow of the packaging method proposed according to another exemplary embodiment of the present disclosure. The solution of this embodiment is compared with Figures 1a to 1j the embodiment shown in Figures 2a to 2d the embodiment shown in Figures 3a to 3e the embodiment shown in

[0217] As Figure 4a shown, provide at least one semiconductor wafer 100, the semiconductor wafer 100 has a wafer active surface 101 and a back surface 107 of the wafer, and apply a passivation layer 150 on the wafer active surface 101.

[0218] In one embodiment, the passivation layer 150 is applied to the active surface 1001 of the wafer by lamination.

[0219] The passivation layer 150 can be BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, a polymer matrix dielectric film, an organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymer composite, such as an epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulating and structural properties;

[0220] As Figure 4b shown, a passivation layer opening 152 is formed at a position corresponding to the electrical connection point 103 on the active surface 101 of the wafer, exposing the pad 103 on the active surface 101 of the wafer.

[0221] As Figure 4c shown, a carrier plate 111 is provided, and at least one wafer 100 is arranged on the front surface 113 of the carrier plate. The active surface 101 of the wafer 100 faces the carrier plate 111, and the wafer 100 is bonded and fixed to the carrier plate 111 by an adhesive layer 109.

[0222] Preferably, the arrangement of the wafers 100 on the carrier plate 111 leaves a blank area on the carrier plate 111. The blank area is a sealing area and / or an electrical connection point contact area and / or a metal simulation pattern formation area and / or a dividing area for dividing the wafers 100 on the panel assembly into independent single wafers 100 in the subsequent process.

[0223] Further preferably, conductive members are also arranged on the carrier plate 111, and the setting positions of the conductive members are at least partially corresponding to the electrical connection contact points of the equipment used in the subsequent conductive layer formation process.

[0224] As Figure 4d shown, a molding compound layer 117 is formed on the carrier plate 111 to construct the panel assembly 800.

[0225] Figure 4e shows the peeling of the carrier plate 111, exposing the passivation layer 150 on the active surface 101 of the wafer 100, the front surface 121 of the molding compound layer, and one surface of the conductive member when there is a conductive member. The panel structure composed of the wafer 100, the passivation layer 150, the molding compound layer 117, and the conductive member when there is a conductive member is called the panel assembly 800.

[0226] Optionally, the passivation layer opening 152 can also be formed after peeling the carrier plate 111.

[0227] Preferably, corresponding to the arrangement of the wafer 100 on the carrier 111, the panel assembly 800 includes a blank area, and the blank area includes a sealing area and / or a metal simulation pattern forming area and / or an electrical connection point contact area and / or a dividing area.

[0228] Figure 4f Another alternative step for forming the passivation layer 150 is shown. The wafer 100 is directly arranged on the carrier 111 to form a plastic encapsulation layer 117. The carrier 111 is removed, and the passivation layer 150 is formed on the active surface 101 of the wafer 100 and the front surface 121 of the plastic encapsulation layer. The panel structure composed of the wafer 100, the passivation layer 150, the plastic encapsulation layer 117, and the conductive parts when there are conductive parts is called the panel assembly 800.

[0229] A passivation layer opening 152 is formed on the passivation layer 150.

[0230] Another process for forming the passivation layer can be to form a first passivation layer on the active surface of the wafer 100 and then arrange it on the carrier 111. After applying the plastic encapsulation layer 117 on the carrier 111, the carrier 111 is removed, and then a second passivation layer is formed on the front surface 121 of the plastic encapsulation layer.

[0231] Figure 4g An embodiment of the process for forming a patterned conductive layer on the active surface 101 of the wafer 100 arranged on the panel assembly 800 is shown. A conductive medium is filled in the passivation layer opening 152 so that the passivation layer opening 152 becomes a filled passivation layer opening 154, and a conductive trace 123 is further formed. The filled passivation layer opening 154 is electrically connected to the pad 103 on the wafer active surface 1001. During this process, preferably, a metal simulation pattern a is formed simultaneously. A conductive bump 127 is formed on the pad or connection point of the conductive trace 123. During this process, preferably, a metal simulation pattern b is formed in the metal simulation pattern forming area of the panel assembly 800;

[0232] The conductive layer is composed of a conductive trace and / or a conductive bump 127, and the conductive layer can be one layer or multiple layers.

[0233] Such as Figure 4h As shown, a dielectric layer 133 is formed on the front surface 121 of the plastic encapsulation layer, the passivation layer 150, and the conductive layer. The wafer 100 is cut and separated from the panel assembly, and the packaged wafer is cut to form individual chips.

[0234] The separation process and the dielectric layer 133 application process can also be: separating the wafer 100 from the panel assembly 800 and cutting along the periphery of the wafer 100 using mechanical or laser means. A dielectric layer 133 is formed on the passivation layer 150 and the conductive layer; and the packaged wafer is cut to form individual chips.

[0235] The packaged and formed wafer structure is asFigure 5d As shown. The formed chip 135 structure is as Figure 6d shown.

[0236] Figures 4a to 4h In the encapsulation embodiments shown, the encapsulation layer structure formed during encapsulation is shown to include forming a passivation layer 150, a conductive layer, and a dielectric layer 133. However, this is merely exemplary, and according to the specific types of encapsulation products, for example, a passivation layer 150 and a conductive layer can be formed, or for another example, only a conductive layer can be formed.

[0237] Figures 5a to 5d is a schematic diagram of a wafer encapsulation structure obtained by using the above encapsulation method according to some exemplary embodiments of the present disclosure. The wafer encapsulation structure includes: at least one wafer 100, the wafer having an active surface 101 and a wafer back surface 107; a molding compound layer 117 encapsulating at least one of the wafers; a composite layer formed on the active surface 101 of at least one of the wafers;

[0238] In some embodiments, the composite layer includes a conductive layer and / or a passivation layer 150 and / or a dielectric layer 133;

[0239] In some embodiments, at least one of the wafers 100 includes a wafer side surface 129, and the molding compound layer 117 encapsulates the wafer side surface 129 and the wafer back surface 107;

[0240] In some embodiments, at least one of the wafers 100 includes a wafer side surface 129, and the molding compound layer 117 encapsulates the wafer side surface 129;

[0241] In some embodiments, the material and thickness of the molding compound layer 117 are designed to match the material and thickness of the dielectric layer 133 to reduce or eliminate warping;

[0242] Optionally, the molding compound layer 117 can be made of an organic composite material, a resin composite material, a polymer composite material, a polymeric composite material, such as an epoxy resin with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers;

[0243] Optionally, the conductive layer is one or more layers of materials such as gold, silver, copper, tin, aluminum, or other suitable conductive materials;

[0244] Optionally, the dielectric layer 133 is BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, a polymer matrix dielectric film, an organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymer composite, such as an epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulating and structural properties.

[0245] Figure 5a FIG.

[0245] is a schematic diagram of a wafer package structure obtained by using the above packaging method according to some exemplary embodiments of the present disclosure. The wafer package structure includes:

[0246] A semiconductor wafer 100, the semiconductor wafer 100 having an active surface 101 and a wafer back surface 107. The wafer 100 includes a plurality of dies, and the active surface of each die constitutes the active surface 101 of the wafer 100. The active surface 101 includes pads 103 for leading out functional circuits and an insulating protective layer 105 for protecting the pads 103;

[0247] A plastic encapsulation layer 117 encapsulating the semiconductor wafer 100;

[0248] A conductive layer formed on the active surface of the semiconductor wafer 100. Optionally, the conductive layer is composed of conductive traces 123 and / or conductive studs 127. The optional conductive layer can be one layer or multiple layers;

[0249] A dielectric layer 133 formed on the conductive layer and the active surface of the semiconductor wafer 100. The dielectric layer 133 functions to protect the conductive layer and provide insulation;

[0250] In some embodiments, the conductive layer is electrically connected to the pads 103 on the active surface of the semiconductor wafer 100 for leading out the pads 103;

[0251] In some embodiments, the plastic encapsulation layer 117 has a front surface of the plastic encapsulation layer, and the front surface of the plastic encapsulation layer may further include a metal simulation pattern 125;

[0252] In a preferred embodiment, through the simulation design of the chip package structure, the material and / or thickness of the plastic encapsulation layer is designed to match the material and / or thickness of the dielectric layer to slow down or eliminate warping;

[0253] In some embodiments, the plastic encapsulation layer encapsulates the side surface 129 and the back surface 107 of the wafer 100;

[0254] In other embodiments, as Figure 5bAs shown, the encapsulation layer 117 encapsulates the side surface 129 of the chip 100, exposing the back surface 107 of the chip.

[0255] In some preferred examples, as Figure 5c described, the surface of the dielectric layer 133 has grooves 137.

[0256] Figure 5d is a schematic diagram of a chip packaging structure obtained by using the above packaging method according to some exemplary embodiments of the present disclosure. The chip packaging structure includes: at least one chip 100 having an active surface 101 and a back surface 107 of the chip; an encapsulation layer 117 encapsulating at least one of the chips 100; a composite layer formed on the active surface 101 of at least one of the chips 100; the composite layer includes a conductive layer, a dielectric layer 133, and a passivation layer 150;

[0257] In some embodiments, at least one of the chips 100 includes a side surface 129 of the chip, and the encapsulation layer 117 encapsulates the side surface 129 and the back surface 107 of the chip;

[0258] In some embodiments, the encapsulation layer 117 encapsulates the side surface 129 of the chip 100, exposing the back surface 107 of the chip;

[0259] In some embodiments, the conductive layer is composed of conductive traces 123 and / or conductive studs 127, and the conductive layer can be one layer or multiple layers;

[0260] In some embodiments, the material and thickness of the encapsulation layer 117 are designed to match the material and thickness of the dielectric layer 133 to slow down or eliminate warping;

[0261] In some embodiments, the surface of the dielectric layer 133 has grooves 137.

[0262] Figures 6a to 6d is a schematic diagram of a chip 135 packaging structure obtained by using the above packaging method according to some exemplary embodiments of the present disclosure. The chip 135 packaging structure includes: at least one die 140 having a die active surface 141 and a die back surface 143; an encapsulation layer 117 formed on the back surface 143 of at least one of the dies; a composite layer formed on the active surface 141 of at least one of the dies.

[0263] In some embodiments, the composite layer includes a conductive layer and / or a passivation layer and / or a dielectric layer 133.

[0264] In some embodiments, the edge of the encapsulation layer 117 is flush with the edge of the die 140.

[0265] In some embodiments, the material and / or thickness of the encapsulation layer 117 is designed to match the material and / or thickness of the dielectric layer 133 to mitigate or eliminate warping;

[0266] Optionally, the encapsulation layer 117 may be made of an organic composite material, a resin composite material, a polymer composite material, a polymeric composite material, such as epoxy resin with fillers, ABF (Ajinomoto buildup film), or other polymers with suitable fillers;

[0267] Optionally, the conductive layer is one or more layers of materials such as gold, silver, copper, tin, aluminum, or other suitable conductive materials;

[0268] Optionally, the dielectric layer 133 is BCB (benzocyclobutene), PI (polyimide), PBO (polyphenylene benzoxazole), ABF, silicon dioxide, silicon nitride, silicon oxynitride, tantalum pentoxide, aluminum oxide, a polymer matrix dielectric film, an organic polymer film; it can also be an organic composite material, a resin composite material, a polymer composite material, a polymeric composite material, such as epoxy resin with fillers, ABF, or other polymers with suitable fillers; it can also be other materials with similar insulating and structural properties.

[0269] Figure 6a It is a schematic diagram of a chip 135 packaging structure obtained by using the above packaging method according to some exemplary embodiments of the present disclosure. The chip 135 packaging structure includes:

[0270] A die 140 having a die active surface 141 and a die back surface 143. The die active surface 141 further includes pads 103 for leading out functional circuits and an insulating protection layer 105 for protecting the pads;

[0271] An encapsulation layer 117 formed on the die back surface 143;

[0272] A conductive layer formed on the die active surface 143, which is composed of conductive traces 123 and / or conductive studs 127, and the conductive layer can be one layer or multiple layers;

[0273] A dielectric layer 133 formed on the conductive layer, and the dielectric layer 133 serves to protect the conductive layer and provide insulation;

[0274] In some embodiments, the conductive layer is electrically connected to the pads 103 on the die active surface 141 for leading out the pads 103;

[0275] In some embodiments, the edge of the dielectric layer 133 is flush with the edge of the die 140;

[0276] In a preferred embodiment, through the simulation design of the chip packaging structure, the material and / or thickness of the plastic encapsulation layer 117 is designed to match the material and / or thickness of the dielectric layer 133 to slow down or eliminate warping.

[0277] In some embodiments, the edge of the plastic encapsulation layer 117 is flush with the edge of the die 140;

[0278] In other embodiments, as Figure 6b shown, there is no plastic encapsulation layer 117 covering the back surface 143 of the die, and the back surface 143 of the die is exposed.

[0279] In still other embodiments, as Figure 6c shown, the surface of the dielectric layer 133 has grooves 137.

[0280] Figure 6d FIG. is a schematic diagram of a chip 135 packaging structure obtained by using the above packaging method according to some exemplary embodiments of the present disclosure. The chip 135 packaging structure includes: at least one die 140 having a die active surface 141 and a die back surface 143; a plastic encapsulation layer 117 formed on at least one of the die back surfaces 143; a composite layer formed on at least one of the die active surfaces 141; the composite layer includes a conductive layer, a dielectric layer 133, and a passivation layer;

[0281] In some embodiments, the edge of the plastic encapsulation layer 117 is flush with the edge of the die 140;

[0282] In some embodiments, the edge of the dielectric layer 133 is flush with the edge of the die 140;

[0283] In some embodiments, the conductive layer is composed of conductive traces 123 and / or conductive studs 127, and the conductive layer can be one layer or multiple layers;

[0284] In some embodiments, there is no plastic encapsulation layer 117 covering the back surface 143 of the die, and the back surface 143 of the die is exposed.

[0285] In still other embodiments, the surface of the dielectric layer 133 has grooves 137;

[0286] In a preferred embodiment, through the simulation design of the chip packaging structure, the material and / or thickness of the plastic encapsulation layer 117 is designed to match the material and / or thickness of the dielectric layer 133 to slow down or eliminate warping.

[0287] Figure 7 FIG. shows a schematic diagram of the packaged chip during use. During use, the packaged chip is connected to a circuit board or a substrate 603 through solder 601, and then connected to other circuit components.

[0288] When there are grooves 137 on the surface of the dielectric layer 133 of the encapsulated chip, the solder 601 can be stably connected and is not easily movable.

[0289] When connecting the chip 135 to the circuit board or substrate 502 through the solder 601, a reflow process is required, and the solder 601 needs to be heated above its melting point. During this process, due to the difference in material properties between the material of the dielectric layer 133 on the active surface side of the die and the material of the die, local thermal stress is likely to be generated in the chip package structure during heating, causing the chip package structure to warp. When there is a plastic encapsulation layer 117 on the back side of the die, due to this "balanced" package structure, that is, organic layer material properties / inorganic layer material properties / organic layer material properties, the warping of the chip package structure can be alleviated or eliminated.

[0290] Furthermore, through the simulation design of the chip package structure, the material properties and / or thickness of the plastic encapsulation layer 117 can be designed to match the material and / or thickness of the dielectric layer 133. Thus, the warping of the chip package structure can be better reduced or eliminated.

[0291] The specific embodiments described above are intended to further elaborate on the technical solutions and technical effects of the present disclosure. However, those skilled in the art will understand that the above specific embodiments are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the inventive concept of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A semiconductor device packaging method, characterized in that, Comprising: Providing at least one wafer having an active surface and a back surface of the wafer; Arranging at least one of the wafers on a panel to form a panel assembly; Forming a conductive layer on the active surface of the wafer on the panel assembly; Forming a dielectric layer on the active surface of the wafer and the conductive layer; Wherein, the panel assembly includes a blank area, and the blank area includes one or any combination of an electrical connection point contact area, a sealing area, and a metal simulation pattern forming area. The electrical connection point contact area is used to provide a position for contacting the electrical connection point, the sealing area is used to provide a position for the seal to fit, and the metal simulation pattern forming area is used to form a metal simulation pattern.

2. The method according to claim 1, wherein The active surface of the wafer includes bonding pads and an insulating protective layer. The conductive layer is formed on the bonding pads and the insulating protective layer, and the conductive layer is electrically connected to the bonding pads for leading out the bonding pads.

3. The method according to claim 2, wherein The back surface of the wafer faces the panel assembly, and the active surface of the wafer faces away from the panel assembly, exposing the active surface.

4. The method according to claim 3, characterized in that The panel assembly has a front surface of the panel assembly, and the front surface of the panel assembly is a flat surface.

5. The method according to claim 1, wherein It further includes the step of forming a metal simulation pattern in the metal simulation pattern forming area.

6. The method according to any one of claims 1-5, characterized in that The panel assembly includes at least one conductive member, and at least a part of at least one of the conductive members corresponds to the position of at least one electrical connection point.

7. The method according to any one of claims 1-5, characterized in that, The panel assembly is formed by plastic material molding to connect at least one of the wafers into one body.

8. The method according to claim 7, wherein The plastic material molding includes: arranging at least one of the wafers on a carrier plate or arranging on a lower template; The active surface of the wafer faces the front surface of the carrier plate or faces the front surface of the lower template; Forming a plastic encapsulation layer on the front surface of the carrier plate or the front surface of the lower template and on the wafer to construct the panel assembly.

9. The method according to claim 6, wherein The panel assembly is formed by plastic material molding to connect at least one of the wafers and at least one of the conductive members into one body.

10. The method according to claim 9, wherein The plastic material molding includes: Arranging at least one of the wafers and at least one conductive member on a carrier plate or arranging on a lower template; The active surface of the wafer faces the front surface of the carrier plate or faces the front surface of the lower template; Forming a plastic encapsulation layer on the front surface of the carrier plate or the front surface of the lower template, on the wafer, and on the conductive member to construct the panel assembly.

11. The method according to claim 7, characterized in that, The plastic material molding includes: Providing at least one mold frame having through holes; Arranging at least one of the wafers and at least one of the mold frames on a carrier plate or arranging on a lower template, and arranging the wafer in the through holes; The active surface of the wafer faces the front surface of the carrier plate or faces the front surface of the lower template; Forming a plastic encapsulation layer on the front surface of the carrier plate or the front surface of the lower template, on the wafer, and on the mold frame to construct the panel assembly.

12. A semiconductor device packaging method, characterized in that, Comprising: Providing at least one wafer having an active surface and a back surface of the wafer; Arranging at least one of the wafers on a panel to form a panel assembly; Forming a conductive layer and / or a dielectric layer on one side of the active surface of at least one of the wafers; Among them, the panel assembly includes a blank area, and the blank area includes one or any combination of an electrical connection point contact area, a sealing area, and a metal simulation pattern forming area. The electrical connection point contact area is used to provide a position for contacting the electrical connection point, the sealing area is used to provide a position for the seal to fit, and the metal simulation pattern forming area is used to form a metal simulation pattern.

13. The semiconductor device packaging method according to claim 12, wherein, The step of forming the panel assembly includes the step of forming a passivation layer on the active surface of the wafer.

14. The semiconductor device packaging method according to claim 12 or 13, characterized in that, The panel assembly is formed by molding a plastic material to connect at least one of the wafers into one body.

15. A semiconductor device, characterized in that, Including: A wafer having an active surface and a back side of the wafer; A plastic encapsulation layer encapsulating the wafer; A conductive layer formed on the active surface of the wafer; A dielectric layer formed on the active surface of the wafer and the conductive layer; Among them, the plastic encapsulation layer is used to construct the panel assembly, and the panel assembly includes a blank area, and the blank area includes one or any combination of an electrical connection point contact area, a sealing area, and a metal simulation pattern forming area. The electrical connection point contact area is used to provide a position for contacting the electrical connection point, the sealing area is used to provide a position for the seal to fit, and the metal simulation pattern forming area is used to form a metal simulation pattern.

16. The semiconductor device according to claim 15, wherein, The active surface of the wafer includes bonding pads and an insulating protective layer, and the conductive layer is formed on the bonding pads and the insulating protective layer, and the conductive layer is electrically connected to the bonding pads for leading out the bonding pads.

17. The semiconductor device according to claim 16, wherein, The plastic encapsulation layer encapsulates the side surface and the back side of the wafer of the wafer.

18. The semiconductor device according to claim 17, wherein The material and / or thickness of the plastic encapsulation layer are designed to match the material and / or thickness of the dielectric layer to slow down or eliminate warping.

19. The semiconductor device according to claim 16, wherein, The plastic encapsulation layer encapsulates the side surface of the wafer of the wafer, and exposes the back side of the wafer of the wafer.

20. The semiconductor device according to any one of claims 15-19, characterized in that, The plastic encapsulation layer has a front surface of the plastic encapsulation layer, and a metal simulation pattern is formed on the front surface of the plastic encapsulation layer.

21. The semiconductor device according to any one of claims 15-19, characterized in that, The surface of the dielectric layer has grooves.

22. A semiconductor device, characterized in that, Including: At least one wafer having an active surface and a back side of the wafer; A plastic encapsulation layer encapsulating at least one of the wafers; A composite layer is formed on the active surface of at least one of the wafers; Among them, the plastic encapsulation layer is used to construct the panel assembly, and the panel assembly includes a blank area, and the blank area includes one or any combination of an electrical connection point contact area, a sealing area, and a metal simulation pattern forming area. The electrical connection point contact area is used to provide a position for contacting the electrical connection point, the sealing area is used to provide a position for the seal to fit, and the metal simulation pattern forming area is used to form a metal simulation pattern.

23. The semiconductor device according to claim 22, characterized in that, The composite layer includes a conductive layer and / or a passivation layer and / or a dielectric layer.

24. The semiconductor device according to claim 22, wherein, The composite layer includes a conductive layer and a dielectric layer.

25. The semiconductor device according to claim 22, characterized in that, The composite layer includes a conductive layer, a dielectric layer, and a passivation layer.

26. The semiconductor device according to any one of claims 22-25, characterized in that, At least one of the wafers includes a side surface of the wafer, and the plastic encapsulation layer encapsulates the side surface of the wafer and the back side of the wafer.

27. The semiconductor device according to any one of claims 23 to 25, characterized in that The material and thickness of the plastic encapsulation layer are designed to match the material and thickness of the dielectric layer to slow down or eliminate warping.

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