A transistor device having a source region section and a body region section

Abstract

The invention is titled "Transistor Device with Source Region Segments and Body Region Segments". In at least one general aspect, the device may include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The device may include a mesa region disposed between the first trench and the second trench, and a source region of a first conduction type disposed in a top portion of the mesa region. The device includes a plurality of body region segments of a second conduction type disposed in a side of the mesa region. The plurality of body region segments define a pattern alternating with a plurality of source region segments along the side of the mesa region.

Description

[0001] Related Applications

[0002] This application claims the priority and benefit of U.S. Non - Provisional Application No. 16 / 512,854, filed on Jul. 16, 2019, which claims the priority and benefit of U.S. Provisional Application No. 62 / 826,736, filed on Mar. 29, 2019. The entire disclosures of both of these applications are incorporated herein by reference. Technical Field

[0003] This specification relates to transistor devices having source region segments and body region segments. Background Art

[0004] Some transistor devices can be affected by, for example, parasitic bipolar transistors, which can be triggered and can prevent the transistor device from turning off. The parasitic bipolar transistor can be triggered by self - biasing in the base of the parasitic bipolar transistor due to substrate current. Accordingly, there is a need for systems, methods, and devices to address the deficiencies of the prior art and to provide other novel and innovative features. Summary of the Invention

[0005] In at least one general aspect, a device can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The device can include a mesa region disposed between the first trench and the second trench and a source region of a first conductivity type disposed in a top portion of the mesa region. The device includes a plurality of body region segments of a second conductivity type disposed in a side of the mesa region. The plurality of body region segments define an alternating pattern with a plurality of source region segments along the side of the mesa region.

[0006] Details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. Brief Description of the Drawings

[0007] Figure 1 is a schematic cross - sectional view showing a transistor according to one embodiment.

[0008] Figure 2 Shows that Figure 1 is a perspective view of a transistor that is a variation of the transistor shown.

[0009] Figure 3 is a schematic view showing at least Figure 1 and Figure 2 embodiments of the transistor shown.

[0010] Figure 4 Shows that Figure 1 and Figure 2Perspective view of another transistor of a variant of the transistor shown.

[0011] Figure 5A and Figure 5B are schematic diagrams showing the transistor embodiments of at least Figure 1 and Figure 4 the transistors shown.

[0012] Figure 6 Shows that it is Figure 1 Perspective view of another transistor of a variant of the transistor shown.

[0013] Figure 7A and Figure 7B are schematic diagrams showing the transistor embodiments of at least Figure 1 and Figure 6 the transistors shown.

[0014] Figures 7C to 7E Is a schematic diagram showing other examples of the checkerboard patterned body region section and source region section.

[0015] Figures 8A to 8H Shows various cross-sections of the upper region of the mesa region, which can be combined along the longitudinal axis according to at least Figure 1 the variants of the transistors shown.

[0016] Figure 9 Is an exemplary plan view of a transistor that can include various combinations of the transistors and cross-sections in Figures 1 to 8H .

[0017] Figures 10A to 10H Is a schematic diagram showing the process of manufacturing one or more transistors as described herein.

[0018] Figure 11 Is a flowchart showing a method of forming a transistor.

[0019] Figure 12 Is a graph showing the latch scenario of the transistor.

[0020] Figure 13 Is a graph showing the operation of the transistor according to the embodiments described herein.

[0021] Figure 14 and Figure 15 Is a graph showing the characteristics of the transistor with sections as described herein compared to other transistors. Detailed Description

[0022] The transistors described herein may have a body region section and a source region section that are defined such that parasitic bipolar devices (e.g., NPN bipolar transistor devices) included within the transistor are prevented from being activated in an undesirable manner. Specifically, the transistor structures as described herein may be configured to prevent turn - on of parasitic bipolar devices included within the transistor structure when the transistor structure is being turned off. Activation of the parasitic bipolar device may be referred to as latch - up and may be triggered in response to substrate current and in response to self - biasing of the base in the parasitic bipolar device. The transistor devices described herein may be configured to have a structure that reduces the base resistance while maintaining a desired on - resistance. Thus, when the transistor structure is being turned off, undesirable latch - up conditions associated with the parasitic bipolar device are reduced or eliminated.

[0023] For example, as described herein, at least one side of the mesa region of the transistor may have source region sections of a first conductivity type alternating with body region sections of a second conductivity type. As a specific example, in a trench metal - oxide - semiconductor field - effect transistor (MOSFET) device, the sides and the upper surface (the mesa top and the mesa sidewalls) of the silicon mesa may have N - type conducting source region sections alternating with P - type conducting body region sections. The N - type conducting source region sections and the P - type conducting body region sections may be disposed above a P - type channel region. The P - type channel region may be in contact with the P - type conducting body region section. Such a structure within the transistor may be used, for example, to reduce the base resistance while maintaining the desired on - resistance of the transistor. Thus, when the transistor is being changed to an off state, undesirable latch - up conditions associated with potential parasitic bipolar devices are reduced or eliminated.

[0024] The channel and the mesa top of a conventional structure may be connected by a P - type highly doped body layer that does not operate as a channel in a desired manner. Thus, when attempting to reduce the body, in order to reduce the base resistance, the effective channel area is reduced. In contrast, a transistor having the body region section and the source region section as described herein may have a discontinuous body region section without adversely affecting the performance in the channel region. The transistors described herein are configured to prevent the parasitic bipolar device from turning on, for example, by reducing the base resistance of the parasitic device without having a loss of channel area (e.g., a reduced channel area). The transistor configuration described herein may solve the latch - up condition while having a desired on - resistance (Ron), which may be problematic in other transistor designs. The transistor configuration described herein may minimize (e.g., reduce) the mesa width and may minimize (e.g., reduce) the potential Ron * area loss.

[0025] Figure 1 is a schematic diagram showing a cross - sectional view of a transistor 100 (e.g., a vertical transistor device, a MOSFET device) according to one embodiment.Figure 1 The transistor 100 shown has a mesa region 120 (also referred to as a mesa) disposed between a pair of trenches 114A, 114B formed in a semiconductor region 102 (e.g., defined within the semiconductor region). The mesa 120 (or its sidewalls) can be at least partially defined by the pair of trenches 114A, 114B. Each of the trenches 114A, 114B includes electrodes 110A, 110B (e.g., gate electrodes) insulated by dielectric layers 112A, 112B, respectively.

[0026] The mesa 120 includes an upper region 122 (of the mesa region 120), a body region 160, and at least a portion of an epitaxial layer 170. At least a portion of the upper region 122 can include Figure 1 one or more source region segments not shown. The upper region 122 can also include one or more body region segments coupled to the body region 160, the one or more body region segments not shown in Figure 1 the figure.

[0027] One or more source region segments in the upper region 122 and the epitaxial layer 170 can each be of a first conductivity type. The body region 160 disposed between (e.g., vertically disposed between and around) one or more source region segments in the upper region 122 and the epitaxial layer 170 is of a second conductivity type. The first conductivity type is opposite to the second conductivity type. In some embodiments, the transistor 100 (and other transistors disclosed herein) can be associated with only a few cells. In some embodiments, the first conductivity type can be N-type conductivity (e.g., N-type dopants (e.g., phosphorus (P), arsenic (As), antimony (Sb))), and the second conductivity type can be P-type conductivity (e.g., P-type dopants (e.g., boron (B), aluminum (Al), gallium (Ga))). In some embodiments, the first conductivity type can be P-type conductivity, and the second conductivity type can be N-type conductivity. Although the examples described herein and the associated conductivity types are discussed as being associated with specific types of dopants, they can be reversed to form different devices (e.g., P-channel devices, N-channel devices).

[0028] When the transistor 100 is in an on state (based on the applied voltage to the electrodes 110A, 110B), a channel (or channels) can be defined within the body region 160. When the transistor 100 is in an on state, current can flow between a source conductor 180 and a drain conductor 190.

[0029] The source conductor 180 is in contact with one or more source region segments included in the upper region 122. The source conductor 180 is insulated from the electrodes 110A, 110B by corresponding dielectric layers 112A, 112B. The epitaxial layer 170 may be disposed on the substrate 185, and the drain conductor 190 may be in contact with the substrate 185. The vertical direction (which is the depth direction or the height direction) in this embodiment is aligned along the y-axis. The horizontal direction (which is the width direction or the lateral direction) in this embodiment is aligned along the x-axis. The length direction in this embodiment is aligned along the z-axis. The mesa region 120 may be longitudinally aligned along the z-axis. As Figure 1 oriented, the top of the transistor 100 may face the source portion (e.g., the source conductor 180 and one or more source region segments in the upper region 122), and the bottom of the transistor 100 may face the drain portion (e.g., the drain conductor 190).

[0030] As described above, the upper region 122 of the mesa region 120 may include one or more source region segments, and the upper region 122 may further include one or more body region segments. One or more body region segments may be connected (e.g., adjacent to, in contact with) the body region 160 (and / or its channel region). One or more body region segments (although one or more body region segments of the opposite conductivity type) may be in contact with one or more source regions (and may define a PN junction with the one or more source regions). In some embodiments, the body region segments may be interleaved with the source region segments (e.g., may be disposed between them). Such embodiments are shown in Figure 2 FIG.

[0031] In some embodiments, the surface area (or volume) of the body region 160 (and the body region segments) may be smaller than the surface area (or volume) of the source region segments within the mesa region 120. In some embodiments, the surface area (or volume) of the body region 160 (and the body region segments) may be smaller than the surface area (or volume) of the source region segments within the mesa region 120 over the longitudinal length of the mesa region 120 including an equal number of body region segments and source region segments.

[0032] In this embodiment, the mesa region 120 is aligned along the vertical axis A1 (or plane). The vertical axis A1 intersects the upper region 122, the body region 160 (which is located below the upper region 122), and the epitaxial layer 170 (in the order from top to bottom). As Figure 1As shown, the horizontal axis A2 (or plane) intersects the electrodes 110A, 110B (and dielectric layers 112A, 112B) and the upper region 122. The horizontal axis A2 is orthogonal to the vertical axis A1 and is aligned parallel to the x-axis and the top surface of the mesa region 120. The vertical axis A1 and the horizontal axis A2 are orthogonal to the longitudinal axis aligned along the z-direction. In some embodiments, the top surface of the mesa region 120 is also disposed above (e.g., vertically above) the top surface of each of the electrodes 110A, 110B and the dielectric layers 112A, 112B.

[0033] Figure 2 A perspective view of a transistor 200, which is a variant of the transistor 100, is shown. The trench 114B (including the electrode 110B and the dielectric 112B) is omitted from this view so that the mesa region 120 can be seen more clearly.

[0034] As Figure 2 shown, the semiconductor region 102 of the transistor 100 has source region segments 131A, 131B, 131C (which may be collectively referred to as source region segments 131) that are interleaved with body region segments 161A, 161B (which may be collectively referred to as body region segments 161). Specifically, the source region segments 131 and the body region segments 161 are included in the upper region 122 of the transistor 200.

[0035] As Figure 2 shown, the body region segment 161 is in contact with the channel region 163. The body region segment 161 and the channel region 163 may have the same conductivity type. The body region segment 161 and the channel region 163 may have the same conductivity type as the body region 160. In this embodiment, the source region segment 131 has a conductivity type opposite to that of the body region segment 161.

[0036] As Figure 2 shown, the upper region 122 of the mesa region 120 may be longitudinally aligned along the z-axis. Thus, the source region segments 131 and the body region segments 161 may also be longitudinally aligned along the z-axis.

[0037] The source region section 131 and the body region section 161 are disposed on one side of the upper region 122 of the mesa region 120. In this embodiment, the source region section 131 and the body region section 161 define approximately half (e.g., about half) of the cross-sectional surface area of the upper region 122 of the mesa region 120 (e.g., the cross-sectional surface area perpendicular to the longitudinal direction along the z-axis). In other words, the cross-sectional width (along the x-axis) of the source region section 131 is half of the width of the upper region 122 of the mesa region 120. In some embodiments, the cross-sectional surface area of the source region section 131 and / or the body region section 161 may be less than or greater than half of the upper region 122 of the mesa region 120. In other words, the cross-sectional width of the source region section 131 and / or the body region section 161 is less than or greater than half of the width of the upper region 122 of the mesa region 120.

[0038] As Figure 2 shown, the source region section 131 has a length B1, and the body region section 161 has a length C1. In some embodiments, the length B1 of the source region section 131 may be the same as the length C1 of the body region section 161. In some embodiments, the length B1 of the source region section 131 may be longer than or shorter than the length C1 of the body region section 161. In some embodiments, the length of B1 may be between 0.2 μm and 0.9 μm (e.g., 0.3 μm). In some embodiments, the length of C1 may be between 0.2 μm and 0.9 μm (e.g., 0.3 μm). In some embodiments, the mesa width W1 may be between, for example, 80 nm and 180 nm. In some embodiments, the mesa width W1 may be between 0.09 μm and 0.13 μm (e.g., 0.11 μm). Accordingly, the ratio of W1 / B1 and / or W1 / C1 may be between approximately 0.1 and 0.6. In some embodiments, the cell pitch between the mesa regions 120 may be about 0.3 μm to 0.5 μm (e.g., 0.38 μm). In some embodiments, the source width may be approximately half of the mesa width W1.

[0039] Since the mesa region 160, the channel region 163, and the upper region 122 of the mesa region 120 all have the same conductivity type, the source region section 131 can be implanted into the upper region 122 of the mesa region 120 to define the body region section 161. The process of forming the source region section 131 and the body region section 161 is discussed in more detail below.

[0040] To prevent the parasitic NPN from turning on, the body region section 161 is formed discontinuously, and the base resistance of the NPN is controlled by alternately arranging the body region section 161 and the source region section 131 along the mesa region 120. Figure 2The configuration shown can be focused on enhancing the on-resistance characteristics, and the alternating source region segments 131 and body region segments 161 are aligned on only one side along the mesa region 120.

[0041] Figure 3 is a schematic diagram showing an embodiment of at least Figure 1 and Figure 2 the transistor 200 shown. As Figure 3 shown, the transistor 200 includes source region segments 131 and body region segments 161.

[0042] Figure 4 shows a perspective view of another transistor 400 that is a variant of the transistor shown in Figure 1 and Figure 2 The variant of this transistor 400 can be referred to as a single-sided body transistor. In some embodiments, the continuous source region 133 is connected to (e.g., coupled to, electrically coupled to, adjacent to) each of the source region segments 131 in the source region segments. The continuous source region 133 has the same conductivity type as the source region segments 131. In some embodiments, the continuous source region 133 is aligned along the channel region 163. In some embodiments, the continuous source region 133 is aligned along the longitudinal z-axis. In some embodiments, the continuous source region 133 is disposed below the body region segments 161. In some embodiments, the continuous source region 133 is disposed between the channel region 163 and the body region segments 161.

[0043] In some embodiments, the length of the continuous source region 133 is greater than the length of one or more of the source region segments 131 in the source region segments. In some embodiments, the continuous source region 133 (along the longitudinal direction) spans more than two source region segments in the source region segments 131. In some embodiments, the continuous source region 133 spans more than three source region segments in the source region segments 131.

[0044] Figure 5A and Figure 5B is a schematic diagram showing an embodiment of at least Figure 1 and Figure 4 the transistor shown. As Figure 5A and Figure 5B shown, the transistor 500 includes a continuous source region 133 coupled to the source region segments 131.

[0045] Figure 6 shows a perspective view of a transistor 500 that is a variant of the transistor shown in Figure 1Perspective view of another transistor 600 of a variant of the transistor shown. This variant of the transistor 600 may be referred to as a double-sided body transistor. Trench 114B (including electrode 110B and dielectric 112B) is omitted from this view so that mesa region 120 can be more clearly seen.

[0046] As Figure 6 shown, the semiconductor region 102 of transistor 100 has source region segments 131A, 131B, 131C, 132A, 132B (which may be collectively referred to as source region segments 131, 132) that are interleaved with body region segments 161A, 161B, 162A, 162B (which may be collectively referred to as body region segments 161, 162). The top surfaces of the source region segments 131, 132 are shown with a hash surface so that these source region segments can be more easily distinguished from the body region segments 161, 162.

[0047] As Figure 6 shown, source region segment 131 is interleaved with body region segment 161 on the first side of mesa region 120, and source region segment 132 is interleaved with body region segment 162 on the second side of mesa region 120. Source region segment 131 is offset from source region segment 132 along the longitudinal z-axis. Similarly, body region segment 161 is offset from body region segment 162 along the longitudinal z-axis. In this embodiment, the source region segments 131, 132 and the body region segments 161, 162 define a checkerboard (e.g., periodic, periodically alternating) pattern when viewed from above (along the y-direction).

[0048] To at least prevent parasitic NPN turn-on, the p-type body region segments 161, 162 are formed discontinuously, and the base resistance of the NPN is controlled by alternately arranging these body region segments and the source region segments 131, 132 in a checkerboard pattern along mesa region 120.

[0049] Figure 7A and Figure 7B are schematic diagrams showing an embodiment of transistor 700 of at least Figure 1 and Figure 6 shown. As shown in FIG. 7, source region segment 131 is interleaved with body region segment 161 on the first side of mesa region 120, and source region segment 132 is interleaved with body region segment 162 on the second side of mesa region 120. Source region segment 131 is offset from source region segment 132 along the longitudinal z-axis. Similarly, body region segment 161 is offset from body region segment 162 along the longitudinal z-axis. In this embodiment, the source region segments 131, 132 and the body region segments 161, 162 define a checkerboard pattern when viewed from above (along the y-direction).

[0050] In Figure 7B the transistor 700 shown, source region segments 131, 132 are separated by a separation region of the source region segments 131, 132. The separation region has a conductivity type opposite to that of the source region segments 131, 132 and the same as that of the body region segments 161, 162. The separation region is aligned between the source region segments 131B, 132B along line D1. In some embodiments, the separation region may have a width (width orthogonal to line D1) of less than one micron (e.g., a fraction of one micron, less than 0.1 micron). As previously described, the source width (e.g., the width of 131B, 132B) may be approximately half of the mesa width W1.

[0051] Figures 7C to 7E is a schematic diagram showing other examples of the checkerboard patterned body region segments 161, 162 and source region segments 131, 132.

[0052] may include more than Figures 1 to 7B the source region segments 131 and / or body region segments 161 shown. More variations of the cross-section that can be included along the longitudinal axis are shown and described at least in the following Figures 8A to 8H below.

[0053] Figures 8A to 8H shows various cross-sections of the upper region 122 of the mesa region 120, which can be combined along the longitudinal axis (z-axis) according to variations of the transistor 100 shown at least in Figure 1 the following. Figures 8A to 8G shows source region segments 8A to 8G respectively associated with Figures 8A to 8G having a hash region. The cross-section can be identified based on the cross-section label. For example, Figure 8A the cross-section in (and specifically, the source region area) can be referred to as cross-section 8A. In this embodiment, the source region segments 8A to 8H will be assumed to have a first conductivity type, and the body region 160 (and associated body region segments) will be assumed to have a second conductivity type. The characteristics of the cross-section are described below.

[0054] Figure 8A shows a cross-section of the upper region 122 that includes the source segment 8A on side F1 (e.g., the left side of line A1) of the upper region 122. Figure 8B shows a cross-section of the upper region 122 that includes the source segment 8A on side F2 (e.g., the right side of line A1) of the upper region 122.

[0055] Figure 8CA cross-section of the upper region 122 is shown, where the source region segment 8C is located on side F1 of the upper region 122 (e.g., to the left of line A1). The source region segment 8C does not extend to the top surface of the mesa region 120, such that a portion 160A of the body region 160 of the second conductivity type is disposed between the top surface of the source region segment 8C and the top surface of the mesa region 122. The portion 160A of the body region 160 disposed between the top surface of the source region segment 8C and the top surface of the mesa region 122 can be used as an enhanced body contact region. Figure 8D A cross-section of the upper region 122 including a source region segment 8D is shown, which is a pattern of the source region segment 8C mirrored onto side F2 of the upper region 122 (e.g., to the left of line A1). Figure 8C and Figure 8D The cross-section shown can be used as (e.g., referred to as) an enhanced body contact cross-section.

[0056] Figure 8E A cross-section of the upper region 122 including a source region segment 8E is shown, which has a first portion extending vertically along line A1 on side F1 and a second portion extending horizontally across (e.g., across the entire) top surface of the mesa region 120. Figure 8F A cross-section of the upper region 122 including a source region segment 8F is shown, which is a pattern of the Figure 8E source region segment 8E mirrored within the mesa region 122.

[0057] Figure 8G A cross-section of the upper region 122 including a source region segment 8G is shown, which extends across the entire upper region 122. Figure 8H A cross-section of the upper region 122 that does not include a source region segment is shown. Specifically, the upper region 122 only includes dopants of the body region 160 of the second conductivity type.

[0058] As described above, Figures 8A to 8H the cross-sections shown can be combined along the longitudinal axis (z-axis) according to at least Figure 1 the variations of the transistor 100 shown. For example, Figure 2 and Figure 3 the embodiments shown can be a combination (e.g., an alternating combination) of source region segments based on the Figure 8A source region segments shown and the Figure 8H cross-sections shown. Another example, Figures 4 to 5B the embodiments shown can be a combination of alternating source region segments based on the Figure 8B source region segment 8B shown and the Figure 8D source region segment 8D shown. Another example, Figure 6The illustrated embodiments may be based on Figure 8A and Figure 8B a combination of alternating source region segments of source region segments 8A and 8B shown respectively. For example, Figure 7A and Figure 7B the illustrated embodiments may be based on source region segments 8A ( Figure 8A ) and 8B ( Figure 8A ) and Figure 8H a combination of cross-sections between any of source region segments 8A and 8B.

[0059] Figures 8A to 8H The cross-sections shown may be combined (e.g., sorted along the longitudinal axis) along the longitudinal axis (z-axis) according to the variations of the transistors described herein. These combinations may include various combinations of Figure 8G and Figure 8H mixed with Figures 8A to 8E . The combinations of 8G and 8H include: 8G; 8H; 8G and 8H; or 8H and 8G. The combinations of 8G and 8H will be represented below as X in at least the following combinations of 8A to 8E, where the combinations may be repeated combinations: 8A+X; 8A+8B; 8A+X+8B; 8C+8D; 8C+X+8D; 8C+X; 8E+8F; 8E+X+8F; 8E+X; 8A+8D; 8A+X+8D; 8A+8F; and / or 8A+X+8F.

[0060] may include Figures 1 to 8H An exemplary plan view of transistor 900 including various combinations of transistors and cross-sections in Figure 9 is shown. As Figure 9 shown, transistor 900 may have a device region 901 (e.g., a channel region or an active region) and body contact regions 902-1, 902-2 along a mesa 920A (extending in the direction Z). Figure 9 Parallel trenches 910A, 910B (also extending in the direction Z) are also shown in Figures 8A to 8H . The cross-sections shown in, for example, Figures 8A to 8H may be included in various combinations (in various orders) along the length of mesa 920A. As a specific example, device region 901 may have the cross-sections shown in Figure 8A and Figure 8B .

[0061] Figure 9 Body pitch G is also shown in . In some embodiments, a relatively narrow body pitch G may be achieved to reduce the base resistance of parasitic NPN bipolar devices. In some embodiments, body contacts (e.g., body contact regions 902-1, 902-2) may include doped regions that serve as body contacts for transistor 900. In some embodiments, the body contact regions may be at the same potential as the source regions.

[0062] Figures 10A to 10F is a schematic diagram showing a process for fabricating one or more transistors as described herein. The processing steps may be performed in an epitaxial layer 1070 formed on, for example, a substrate (not shown). These steps will generally be discussed in terms of an N-type epitaxial layer, but the conduction type may be reversed to form in a P-type epitaxial layer.

[0063] Combined with Figures 10A to 10H The process shown in involves the formation of an embodiment of a single-sided body implementation, such as, for example, Figures 4 to 5B shown. Combined with Figures 10A to 10C , Figure 10E and Figure 10F The process shown in involves the formation of an embodiment of a double-sided body implementation, such as, for example, Figures 6 to 7B shown. The single-sided body implementation and / or the double-sided body implementation may be modified based on the body implantation options, as combined with at least Figure 10G and Figure 10H shown and described. These implementations will be described in more detail below.

[0064] As Figure 10A shown, trenches 1014A, 1014B are formed in a semiconductor region 1002 of a semiconductor (e.g., the epitaxial layer 1070 of the semiconductor region). A mesa 1020 is defined together with the formation of the trenches 1014A, 1014B. The sidewalls of the trenches 1014A, 1014B and the top of the mesa 1020 are lined with a dielectric layer 1004 (e.g., a silicon dioxide layer, a sacrificial oxide, a gate oxide, etc.). Electrodes 1010A, 1010B are formed in the respective trenches 1014A, 1014B using, for example, a polysilicon material (e.g., polysilicon deposition). The electrodes 1010A, 1010B may be recessed (e.g., have a lower height) relative to the top surface of the mesa 120.

[0065] After the dielectric layer 1004 is formed, a P-type implantation process (e.g., a two-sided boron implantation at 30 degrees) (shown by arrows P1 and P2) may be performed, as Figure 10B shown, to form a P-type region that can at least partially form the body region 1060 and the channel region 1063. In some embodiments, the implantation process may include a three-step implantation process. In some embodiments, the three-step implantation process may include one or more two-sided implantation processes. In some embodiments, two or more of the implantation processes in the two-sided implantation process may be performed at different energies and / or angles (e.g., 20 degrees, 55 degrees). Such a three-step implantation process may increase the yield and may result in the elimination of at least some subsequent processing steps.

[0066] A single-sided N-type implantation process (e.g., as part of a first-stage nano-layer deposition (NLD) (e.g., NLD-1) process) can be performed as Figure 10C along direction S1 to form at least a portion of a continuous source region (e.g., Figures 4 to 5B the continuous source region 133 as shown). In some embodiments, the single-sided N-type implantation process can include more than one N-type implantation process (e.g., 1-sided arsenic implantation at 15 degrees and 1-sided arsenic implantation at 40 degrees). During the single-sided N-type implantation process, a resist 1005 is applied to block the region where the source region segment 1031 (e.g., Figures 4 to 5B the source region segment 131 as shown) will be formed. Figure 10D Shown).

[0067] A single-sided P-type implantation process (e.g., as part of a first-stage nano-layer deposition (NLD) (e.g., NLD-1) process) can be performed as Figure 10C along direction S2 (on the opposite side of the mesa region 1020 related to S1) to at least partially form the body region segment 1061 (e.g., Figures 4 to 5B the source region segment 161 as shown). In some embodiments, the single-sided P-type implantation process can include one P-type implantation process (e.g., 1-sided boron implantation at 40 degrees). During the single-sided P-type implantation process, a resist 1005 is applied to block the region where the source region segment 1031 will be formed. Figure 10D Shown). After performing the NLD-1 process, the resist 1005 can be removed (e.g., stripped).

[0068] In some embodiments, the NLD-1 process can be performed along direction S2 without the single-sided P-type implantation process. Such embodiments can be referred to as body lithography addition processes.

[0069] As Figure 10D shown, a double-sided N-type implantation process (e.g., as part of a second-stage nano-layer deposition (NLD) (e.g., NLD-2) process) can be performed along directions P1 and P2 (which are on opposite sides of the mesa region 1020). The N-type implantation process along direction P1 forms another portion of the continuous source region (e.g., Figures 4 to 5B the continuous source region 133 as shown), and the N-type implantation process along direction P2 forms the source region segment 1031. One or more of the double-sided N-type implantation processes can include, for example, arsenic implantation at 15 degrees, arsenic implantation at 40 degrees, etc. During the double-sided N-type implantation process, a resist 1006 is applied to the block region of the body region segment 1061 (e.g., Figures 4 to 5B the body region segment 161 as shown), as Figure 10CAs shown. After performing the NLD-2 process, the resist 1006 can be removed (e.g., stripped).

[0070] In some embodiments, the surface area of the mesa region 120 covered by the resist 1005 can be different from the surface area of the mesa region 120 covered by the resist 1005. In some embodiments, the surface area of the mesa region 120 covered by the resist 1005 can be mutually exclusive with the surface area of the mesa region 120 covered by the resist 1005. In some embodiments, the surface area of the mesa region 120 covered by the resist 1005 can overlap with the surface area of the mesa region 120 covered by the resist 1005. In some embodiments, each section of the resist 1005 can be the same length (e.g., equal length) (along the Z direction) as each section of the resist 1006. In some embodiments, the length of each section of the resist 1005 can be less than or greater than the length of each section of the resist 1006 (along the Z direction).

[0071] As Figure 10E shown, after the resist 1006 has been removed, a dielectric layer 1017 is formed on the transistor. The dielectric layer 1017 can include interlayer dielectric, high-temperature oxide deposition, borophosphosilicate glass (BPSG) deposition, BPSG reflow, etc. In some embodiments, the dielectric layer 1017 can be recessed (e.g., etched (contact etch)) to expose the top surface of the mesa region 1020 for source and / or body contacts (not shown) coupled to, for example, source region sections 1031 and / or body region sections 1061. As described above, Figures 10A to 10E the process shown in

[0072] can be used to form a single-sided body embodiment of a transistor. Figures 10A to 10C As described above, Figure 10E and Figure 10F shown, the process can be used to form a double-sided body embodiment of a transistor (e.g., Figures 6 to 7B the double-sided transistor embodiment shown). Specifically, the process shown and described in conjunction with Figure 10F can replace the process shown and described in conjunction with Figure 10D to form a double-sided body embodiment of a transistor.

[0073] As Figure 10FAs shown, a single-sided N-type implantation process (e.g., as part of a second-level nano-layer deposition (NLD) (e.g., NLD-2) process) can be performed along the direction T2 (which is on opposite sides of the mesa region 1020 relative to T1). The N-type implantation process along the direction T2 forms the source region segment 1031. One or more of the single-sided N-type implantation processes can include, for example, arsenic implantation at 15 degrees, arsenic implantation at 40 degrees, etc. During the single-sided N-type implantation process, the resist 1006 is applied to a block region of the body region segment 1061 (e.g., Figures 6 to 7B the body region segment 161 shown), as Figure 10F shown.

[0074] In addition, as Figure 10F shown, a single-sided P-type implantation process can be performed along the direction T1 (as part of the second-level NLD-2 process) to at least partially form the body region segment 1062 (e.g., Figures 6 to 7B the body region segment 162 shown). Thus, Figure 10C the N-type implantation process shown forms the source region segment (e.g., Figures 6 to 7B the source region segment 132 shown). After performing the NLD-2 process, the resist 1006 can be removed (e.g., stripped). In addition, the process described in conjunction with Figure 10E can be performed after the process described in conjunction with Figure 10F described.

[0075] Figure 10G And Figure 10H are schematic diagrams showing body implantation options that can be combined with any of the embodiments described herein. Specifically, as shown, the size (e.g., volume) of the body region 1060 (or body segment region) is increased in size by one or more body implantations, which can include, for example, body implantation, body mask, etc. In this embodiment, the defined portion 1060A (e.g., Figure 8C the portion 160A shown) is defined. In some embodiments, the portion 1060A can be referred to as a body contact enhancer.

[0076] For single-sided transistors, the body implantation options can include a body lithography / mask step and a single-sided body implantation (e.g., P-type implantation) at 40 degrees. The body implantation can be performed to increase the size (e.g., volume) of one or more body region segments.

[0077] For a double-sided transistor, the body implant options may include a first body lithography / masking step, a first single-sided body (e.g., P-type) implant at 40 degrees on a first side of the mesa region 1020 associated with a first set of body region segments, a second body lithography / masking step, and a second single-sided body (e.g., P-type) implant at 40 degrees on a second side of the mesa region 1020 associated with a second set of body region segments.

[0078] In some embodiments, when implementing the body implant options for a double-sided body transistor embodiment, the single-sided P-type implant process associated with NLD-2 along direction T1 ( Figure 10F as shown) may be omitted.

[0079] Figure 11 is a flowchart showing a method of forming a transistor according to one embodiment. Figure 11 The flowchart shown in

[0080]

[0081]

[0082]

[0083] Figures 10A to 10H

[0084] Figure 12 Figure 12 ​​​​​As shown, as the gate voltage 1201 (in V / div) and the transistor current 1202 (in A / div) decrease over time, the source voltage 1203 increases. However, at approximately time N1, when the transistor turns off, the source voltage 1203 (in V / div) does not continue to the desired source voltage 1203A (shown by the dashed line), and when the transistor turns off, the transistor current 1202 does not continue to the desired transistor current of 0 (also shown by the dashed line). When the transistor turns off, the latching condition prevents the source voltage 1203 from reaching the desired source voltage 1203A and prevents the transistor current 1202 from continuing to the desired transistor current of 0.

[0085] Figure 13 is a graph showing the operation of a transistor according to an embodiment described herein. As Figure 13 shown, as the gate voltage 1302 decreases, the drain voltage 1303 rises as expected, and the drain current 1301 decreases to zero.

[0086] Figure 14 and Figure 15 are graphs showing the characteristics of a transistor having segments (e.g., source region segments and body region segments) as described herein compared to other transistors (e.g., transistors U1 to U3). Figure 14 and Figure 15 show the on-resistance (Rsp) versus the mesa width (along the x-axis) and the V-latch robustness versus the mesa width (along the x-axis), respectively. As Figure 14 shown, for a transistor having segments, the on-resistance is relatively low at a relatively small mesa width. As Figure 15 shown, even in the case of a relatively small mesa width (e.g., in the target operating region between 80 nm and 140 nm mesa width), a transistor having segments is relatively robust against V-latch. Specifically, the V-latch performance of the embodiments described herein including source region segments and / or body region segments can be at least 10% greater than the V-latch performance of embodiments not including source region segments and / or body region segments.

[0087] In at least one embodiment, the device may include a first trench disposed in a semiconductor region and including a gate electrode, a second trench disposed in the semiconductor region, and a mesa region disposed between the first trench and the second trench. The device may include a plurality of source region segments of a first conductivity type disposed on a side of the mesa region and a plurality of body region segments of a second conductivity type disposed on a side of the mesa region, wherein the plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.

[0088] In some embodiments, the plurality of body region segments are a first plurality of body region segments, the plurality of source region segments are a first plurality of source region segments, and the side of the mesa region is a first side of the mesa region. The device may include a second plurality of body region segments disposed on a second side of the mesa region opposite the first side of the mesa region.

[0089] In some embodiments, the mesa is aligned along a vertical axis, and the vertical axis is aligned along the depth directions of the first trench and the second trench. In some embodiments, the device may include a source conductor that contacts the source region segment and defines an ohmic contact. In some embodiments, the mesa region has a length aligned along a longitudinal axis that is orthogonal to the vertical axis and orthogonal to the width of the mesa region along the height of the mesa region, and the side is on one side of the vertical axis. In some embodiments, the device is configured to have a plurality of source region segments and a plurality of body region segments to minimize the width of the mesa region and Ron * area loss.

[0090] In another embodiment, the device may include a first trench disposed in a semiconductor region and including a gate electrode, a second trench disposed in the semiconductor region, a mesa region disposed between the first trench and the second trench, and a channel region disposed in the mesa region. The device may include a plurality of source region segments of a first conductivity type on a first side of the mesa region, a plurality of body region segments of a second conductivity type alternating with the plurality of source region segments on the first side of the mesa region, and a continuous source region disposed on a second side of the mesa region, wherein the continuous source region is disposed above the channel region and the length of the continuous source region is greater than the length of the source region segments of the plurality of source region segments.

[0091] In some embodiments, each source region segment of the plurality of source region segments is connected to the continuous source region on a second side of the mesa region. In some embodiments, the device may include a drain conductor, a source conductor that contacts the source region segment, and a substrate that contacts the epitaxial layer. In some embodiments, the mesa region has a top surface disposed above the top surface of the electrode disposed in the first trench.

[0092] It should be understood that in the foregoing description, when an element such as a layer, region, substrate, or component is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element can be directly on the other element, connected to or coupled to the other element, or there can be one or more intermediate elements. In contrast, when an element is referred to as being directly on another element or layer, directly connected to another element or layer, or directly coupled to another element or layer, there are no intermediate elements or layers. Although the terms directly on..., directly connected to..., or directly coupled to... may not be used throughout the detailed description, elements shown as being directly on an element, directly connected, or directly coupled can be referred to in such a manner. The claims of the present application (if any) can be amended to recite the exemplary relationships described in the specification or shown in the drawings.

[0093] As used in this specification, unless specifically indicated otherwise by context, the singular forms may include the plural forms. Except for the orientations shown in the drawings, the spatial relative terms (e.g., above, on top of, over, below, under, beneath, below, etc.) are intended to cover different orientations of the device during use or operation. In some embodiments, the relative terms above and below may respectively include vertically above and vertically below. In some embodiments, the term adjacent can include laterally adjacent or horizontally adjacent.

[0094] Some embodiments can be implemented using various semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, which includes but is not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0095] Although certain features of the described embodiments have been illustrated as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Accordingly, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the specific embodiments. It should be understood that these modifications and variations are presented by way of example only and not by way of limitation, and various changes in form and detail can be made. Except for mutually exclusive combinations, any part of the devices and / or methods described herein can be combined in any combination. The embodiments described herein can include various combinations and / or sub - combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A device, comprising: A first trench, the first trench being disposed in a semiconductor region and including a gate electrode; A second trench, the second trench being disposed in the semiconductor region; A mesa region, the mesa region being disposed between the first trench and the second trench, the mesa region having a length aligned along a longitudinal axis orthogonal to a vertical axis, the vertical axis being aligned along a height of the mesa region; A plurality of source region segments of a first conductivity type, the plurality of source region segments of the first conductivity type being disposed on one side of the mesa region; And A plurality of body region segments of a second conductivity type, the plurality of body region segments of the second conductivity type being disposed on the side of the mesa region, the plurality of body region segments defining an alternating pattern with the plurality of source region segments along the side of the mesa region, the alternating pattern being aligned along the longitudinal axis, wherein at least one of the plurality of source region segments and the plurality of body region segments has a cross-sectional width smaller than a width of the mesa region.

2. The device according to claim 1, wherein each source region segment of the plurality of source region segments is separated from another source region segment of the plurality of source region segments by a body region segment of the plurality of body region segments.

3. The device according to claim 1, wherein each body region segment of the plurality of body region segments is connected to a channel region disposed between the first trench and the second trench, the channel region being disposed below the plurality of body region segments.

4. The device according to claim 1, wherein the plurality of source region segments are a first plurality of source region segments, the side of the mesa region is a first side of the mesa region, The device further comprises: A second plurality of source region segments, the second plurality of source region segments being disposed on a second side of the mesa region opposite to the first side of the mesa region.

5. The device according to claim 1, wherein the plurality of body region segments are a first plurality of body region segments, the plurality of source region segments are a first plurality of source region segments, the side of the mesa region is a first side of the mesa region, The device further comprises: A second plurality of body region segments, the second plurality of body region segments being disposed on a second side of the mesa region opposite to the first side of the mesa region.

6. The device according to claim 1, wherein the plurality of body region segments are a first plurality of body region segments, the plurality of source region segments are a first plurality of source region segments, the side of the mesa region is a first side of the mesa region, The device further comprises: A second plurality of body region segments, the second plurality of body region segments being disposed on a second side of the mesa region opposite to the first side of the mesa region, the second plurality of body region segments alternating with a second plurality of source region segments along the second side of the mesa region.

7. The apparatus of claim 1 , wherein the plurality of body region segments is a first plurality of body region segments, the side of the mesa region is a first side of the mesa region, The device also includes: a second plurality of body region segments disposed on a second side of the mesa region opposite the first side of the mesa region, the second plurality of body region segments alternating with the second plurality of source region segments along the second side of the mesa region such that a checkerboard pattern is defined on a top surface of the mesa by the first plurality of body region segments, the second plurality of body region segments, the first plurality of source region segments, and the second plurality of source region segments.

8. A device comprising: a first trench disposed in the semiconductor region and including a gate electrode; a second trench disposed in the semiconductor region; a mesa region disposed between the first groove and the second groove, the mesa region having a length aligned along a longitudinal axis orthogonal to a vertical axis aligned along a height of the mesa region; a channel region, the channel region being disposed in the mesa region; a plurality of source region segments of a first conductivity type, the plurality of source region segments of the first conductivity type being located on a first side of the mesa region; a plurality of body region segments of a second conductivity type alternating with the plurality of source region segments along the longitudinal axis on the first side of the mesa region; and A continuous source region is disposed on the second side of the mesa region, the continuous source region is disposed above the channel region and has a length greater than a length of the source region segments of the plurality of source region segments. 9 . The device of claim 8 , wherein each of the plurality of body region segments contacts the continuous source region on the second side of the mesa region.

10. A device comprising: a first trench disposed in the semiconductor region and including a gate electrode; a second trench disposed in the semiconductor region; a mesa region disposed between the first groove and the second groove, the mesa region having a length aligned along a longitudinal axis orthogonal to a vertical axis aligned along a height of the mesa region; a source region segment of a first conductivity type disposed in a first side of the mesa region, the source region segment being included in a plurality of source region segments, the plurality of source region segments being aligned along the longitudinal axis; as well as A main region segment of a second conductive type is arranged in a second side of the mesa region opposite to the first side of the mesa region and has a portion arranged above the source region segment, and the main region segment is included in a plurality of main region segments, and the plurality of main region segments are aligned along the longitudinal axis.

11. A device comprising: a first trench disposed in the semiconductor region and including a gate electrode; a second trench disposed in the semiconductor region; a mesa region disposed between the first groove and the second groove, the mesa region having a length aligned along a longitudinal axis orthogonal to a vertical axis aligned along a height of the mesa region; a source region segment of a first conductivity type, disposed in one side of the mesa region, the source region segment being included in a plurality of source region segments; a body region segment of a second conductivity type disposed in the mesa region and having a portion of its width extending across the mesa region, the body region segment being included in a plurality of body region segments aligned along the longitudinal axis, The source region segment has a cross-sectional width that is smaller than a width of the mesa region.

12. A device comprising: a first trench disposed in the semiconductor region and including a gate electrode; a second trench disposed in the semiconductor region; a mesa region disposed between the first groove and the second groove, the mesa region having a length aligned along a longitudinal axis orthogonal to a vertical axis aligned along a height of the mesa region; a first source region segment of a first conductivity type disposed in a first side of the mesa region, the first source region segment being included in a plurality of source region segments; a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region, the body region segment being included in a plurality of body region segments aligned along the longitudinal axis; as well as a second source region segment disposed in the mesa region and having a portion of its width extending through the mesa region, The first source region segment has a cross-sectional width that is smaller than a width of the mesa region.

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