A Bidirectional Symmetric TVS Diode and Its Manufacturing Method

Abstract

The present invention relates to a bidirectional symmetric TVS diode and a manufacturing method thereof. By using the method of low-pressure chemical vapor deposition, the thermal process is reduced, realizing a lateral bidirectional TVS with stable performance and consistent bidirectional symmetry. By using the etching method of dry humidification method, it not only ensures that the silicon in the window is not over-etched, but also ensures that the window has a good morphology, which is beneficial to metal coverage, improves the reliability of the device. The surface dielectric layer is replaced by TEOS silica produced by low-pressure chemical vapor deposition instead of silica produced by thermal oxidation, greatly reducing the thermal process in the process, reducing the production cost, and improving the stability of the device. One end of the TVS of the present invention is connected to the back of the chip through the through region, saving the area of the chip.

Description

Technical Field

[0001] The present invention relates to a TVS diode, and particularly to a bidirectional symmetric TVS diode and a manufacturing method thereof. Background Art

[0002] Transient interference of voltage and current is the main cause of damage to electronic circuits and devices, often bringing incalculable losses to people. These interferences usually come from the start and stop operations of power equipment, the instability of the AC power grid, lightning interference, and electrostatic discharge, etc. Transient interference is almost everywhere and at all times, making people feel impossible to guard against. Fortunately, the emergence of a high-performance circuit protection device, TVS, effectively controls transient interference. When a high-energy impact is applied instantaneously across the two ends of a TVS tube, it can reduce its impedance suddenly at an extremely high speed, while absorbing a large current, clamping the voltage across its two ends at a predetermined value, thereby ensuring that the subsequent circuit components are not damaged by the transient high-energy impact. TVS can be divided into unidirectional and bidirectional TVS according to polarity. Unidirectional TVS is generally applicable to DC circuits, while in AC circuits, a bidirectional protection TVS diode is required. If a TVS is made into a lateral bidirectional diode, since it is a surface device, its performance is greatly affected by the heating process. Therefore, traditional bidirectional TVS is generally made into a vertical bidirectional diode, and the process generally uses a mesa process to make a bidirectional TVS diode, or a heterojunction epitaxial substrate, and by doping the same type of impurities as the substrate on the epitaxy to form an NPN or PNP structure. Traditional bipolar TVS has great limitations, and it is very difficult to control the consistency of the bidirectional voltage, and the process fluctuations have a very large impact on the voltages in both directions. There are also some bidirectional TVS protection circuits composed of multiple packaged discrete TVSs combined. The combination of these independent chips results in low integration, large size, and waste of chip area. Summary of the Invention

[0003] In view of this, the object of the present invention is to provide a bidirectional symmetric TVS diode and a manufacturing method thereof to solve the deficiencies in the prior art.

[0004] To achieve the above object, the object of the present invention is realized through the following technical solutions:

[0005] On the one hand, a bidirectional symmetric TVS diode is provided, which includes:

[0006] A P-type substrate;

[0007] An N-type epitaxial layer formed on the P-type substrate;

[0008] A P+ doping region formed on the surface of the N-type epitaxial layer;

[0009] A P+ punch-through region penetrates through the N-type epitaxial layer, and the bottom of the P+ punch-through region is connected to the P-type substrate;

[0010] An oxide layer is formed on the N-type epitaxial layer, and the surface of the P+ punch-through region is connected to the P+ doped region through the oxide layer;

[0011] Metal vias are formed above the P+ punch-through region and the P+ doped region and between the oxide layers;

[0012] A passivation layer is formed on the metal layer; and

[0013] A backside metal layer is formed on the backside of the P-type substrate.

[0014] In the above bidirectional symmetric TVS diode, the passivation layer includes an oxide layer and silicon nitride, the oxide layer is in contact with the metal, and the silicon nitride is formed on the oxide layer.

[0015] In the above bidirectional symmetric TVS diode, the backside metal layer sequentially includes a titanium layer, a nickel layer, and a silver layer.

[0016] On the other hand, a method for manufacturing a bidirectional symmetric TVS diode is provided, which includes:

[0017] S1. Provide a P-type substrate and grow N-type epitaxy on the P-type substrate;

[0018] S2. Grow a 800 Å thick silicon dioxide layer on the N-type epitaxy by dry thermal oxidation, then grow a 8000 Å thick TEOS silicon dioxide layer by low-pressure chemical vapor deposition under low-temperature conditions of 650 °C to 750 °C, and then densify the TEOS silicon dioxide at 850 °C for 40 minutes;

[0019] S3. Form a window for the P+ punch-through region on the surface silicon dioxide by photolithography and wet etching, and then dope the P+ punch-through region by boron implantation, with a doping dose of 2.5E16 KEV and an energy of 120 kev; after doping, grow a 6000 Å thick TEOS silicon dioxide layer by low-pressure chemical vapor deposition under low-temperature conditions of 650 °C to 750 °C, and then push it at 1250 °C under N 2 conditions for 1 hour;

[0020] S4. Open a window for the P+ active region by photolithography, first dry-etch 10000 Å of silicon dioxide, then cure with glue, and then wet-etch the remaining oxide layer. After etching, perform boron implantation with an implantation dose of 5E15 and an implantation energy of 90 KEV. After the implantation is completed, grow a 6000 Å thick TEOS silicon dioxide layer by LPCVD method, and then perform a push under 1000 °C N 2 conditions;

[0021] S5. By a method combining dry and wet processes, first dry-etch the 4500A oxide layer. After curing with glue at 90°C for 1 hour, then wet-etch the remaining oxide layer. At the same time, open holes on the 12000A TEOS oxide layer in the P+ punch-through region and the 6000A TEOS oxide layer in the P+ active region;

[0022] S6. Deposit metal ALSiCu on the surface with a thickness of 3um;

[0023] S7. Grow a passivation layer on the metal layer. The passivation layer has a two-layer structure. One layer is a PSG oxide layer, and the second layer is silicon nitride. Open holes on the passivation layer through photolithography and etching to expose the metal lead holes;

[0024] S8. Grind the back of the P-type substrate to 150um, and then deposit three layers of metal on the back of the P-type substrate, namely 2000A titanium, 3000A nickel, and 8000A silver.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] The present invention uses the method of low-pressure chemical vapor deposition to reduce the thermal process, realizes the lateral two-way TVS, has stable performance, and consistent two-way symmetry; uses the etching method of dry plus wet method, which not only ensures that the silicon in the window is not over-etched, but also ensures that the window has a good morphology, is beneficial to metal coverage, and improves the reliability of the device; one end of the TVS of the present invention is connected to the back of the chip through the punch-through region, saving the area of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0028] Figure 1 Shows the structural schematic diagram of the present invention;

[0029] Figure 2 Shows the flow schematic diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

[0031] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0032] As shown in the reference Figure 1 figures, the bidirectional symmetric TVS diode of the present invention includes a P-type substrate 1, an N-type epitaxial layer 2, a P+ doping region 3, a P+ punch-through region 4, an oxide layer 5, a metal hole 6, a passivation layer 7, and a back metal layer 8. The N-type epitaxial layer 2 is formed on the P-type substrate 1. The P+ doping region 3 is formed on the surface of the N-type epitaxial layer 2. The P+ punch-through region 4 penetrates through the N-type epitaxial layer 2. The bottom of the P+ punch-through region 4 is connected to the P-type substrate 1. The oxide layer 5 is formed on the N-type epitaxial layer 2. The surface of the P+ punch-through region 4 is connected to the P+ doping region 3 through the oxide layer 5. The metal hole 6 is formed above the P+ punch-through region 4 and the P+ doping region 3 and between the oxide layers 5. The passivation layer 7 is formed on the metal layer 6. The back metal layer 8 is formed on the back of the P-type substrate 1. In this technical solution, the passivation layer 7 includes an oxide layer and a silicon nitride layer. The oxide layer is in contact with the metal, and the silicon nitride layer is formed on the oxide layer. The back metal layer 8 successively includes a titanium layer, a nickel layer, and a silver layer.

[0033] As shown in the reference Figure 2 figures, the method for manufacturing this diode is as follows:

[0034] S1. Provide a P-type substrate and grow an N-type epitaxy on the P-type substrate;

[0035] S2. Thermally oxidize the surface dryly to grow a 800A thick silicon dioxide layer, and then grow a 8000A thick TEOS silicon dioxide layer by low-pressure chemical vapor deposition under the low-temperature condition of 650°C - 750°C. After that, densify the TEOS silicon dioxide at 850°C for 40 minutes;

[0036] S3. Form a window for the P+ punch-through region on the surface silicon dioxide through photolithography and wet etching, and then dope the P+ punch-through region by boron implantation. The doping dose is 2.5E16 KEV, and the energy is 120 kev. After doping, grow a 6000A thick TEOS silicon dioxide layer by low-pressure chemical vapor deposition under the low-temperature condition of 650°C - 750°C, and then drive it at 1250°C for 1 hour under the N 2 condition;

[0037] S4. At this time, the thickness of the oxide layer in the area other than the P+ punch-through region on the surface is 14,800 Å. The oxide layer is very thick. If wet etching is used for such a thick oxide layer, the edge morphology etched out will be very oblique, which will affect the reliability of the device. If dry etching is used, because the oxide layer is relatively thick, the dry etching time will be very long, greatly reducing the utilization rate of the equipment, and the cost of the dry process is relatively high. The present invention uses a method combining dry and wet processes. First, 10,000 Å of silicon dioxide is etched off by dry etching, and then the remaining oxide layer is wet-etched. After dry etching, the photoresist is cured at 90 °C for one hour, which is beneficial to enhancing the adhesion of the photoresist. After etching the window, boron implantation is carried out with an implantation dose of 5E15 and an implantation energy of 90 keV. After implantation, a 6,000 Å TEOS silicon dioxide layer is grown by the LPCVD method, and then N at 1000 °C is carried out. 2 Advancement of conditions;

[0038] S5. At this time, the thickness of the oxide layer on the surface is different in each area. The thickness of the oxide layer above the P+ punch-through region is 12,000 Å, the thickness of the oxide layer above the P+ active region is 6,000 Å, and the thickness of the oxide layer in the area that needs to be isolated on the surface is 20,800 Å (the oxide layer is thick and has a very good isolation effect). At this time, openings need to be made simultaneously on the 12,000 Å TEOS oxide layer in the P+ punch-through region and the 6,000 Å TEOS oxide layer in the P+ active region. If dry etching is used, to etch clean the 12,000 Å oxide layer, over-etching is bound to occur in the 6,000 Å area. Usually, when dry etching equipment etches silicon dioxide, it will also etch some Si, unless a dry etching equipment with a high selectivity is selected. The present invention uses a method combining dry and wet processes. First, 4,500 Å of the oxide layer is dry-etched, and then the photoresist is cured at 100 °C and wet-etched. Through the etching method combining dry and wet processes, a very good step morphology is formed in the P+ punch-through region and the P+ active region, and there is no over-etching phenomenon in the P+ active region;

[0039] S6. Metal AlSiCu is deposited on the surface with a thickness of 3 μm. Due to the step morphology of the holes, the step coverage morphology of the metal is particularly good, enhancing the reliability of the device;

[0040] S7. A passivation layer is grown on the metal layer. The passivation layer has a two-layer structure. The first layer structure is a PSG oxide layer, and the second layer structure is a silicon nitride layer. Openings are made on the passivation layer by photolithography and etching to expose the metal lead holes;

[0041] S8. The back of the P-type substrate is ground to 150 μm, and then three layers of metal are deposited on the back of the P-type substrate, namely 2,000 Å of titanium, 3,000 Å of nickel, and 8,000 Å of silver. The function of titanium is an adhesion layer.

[0042] In the present invention, the surface dielectric layer is made of TEOS silicon dioxide produced by low-pressure chemical vapor deposition instead of silicon dioxide produced by thermal oxidation, which greatly reduces the thermal process in the process, lowers the production cost, and improves the stability of the device. By combining dry etching and wet etching to etch the window, a window morphology with very good step characteristics is obtained. The subsequent metal has good step coverage performance, improving the reliability of the device. After dry etching, a step of photoresist curing is added, enabling the photoresist to have a good protective effect during the subsequent wet process.

[0043] As can be seen from the above embodiments, the advantages of the present invention are as follows:

[0044] The present invention uses the method of low-pressure chemical vapor deposition to reduce the thermal process, realizes lateral bidirectional TVS with stable performance and consistent bidirectional symmetry; uses the etching method of dry etching combined with wet etching to ensure that the silicon in the window is not over-etched and the window has a good morphology, which is beneficial to metal coverage and improves the reliability of the device; one end of the TVS of the present invention is connected to the back of the chip through a punch-through region, saving the area of the chip.

[0045] The specific embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific embodiments described above, which are only examples. For those skilled in the art, any equivalent modifications and substitutions are also within the scope of the present invention. Therefore, equivalent transformations and modifications made without departing from the spirit and scope of the present invention should be covered within the scope of the present invention.

Claims

1. A manufacturing method of a bidirectional symmetric TVS diode, characterized in that, it includes: S1. Provide a P-type substrate, and grow an N-type epitaxy on the P-type substrate; S2. Grow a 800 Å silicon dioxide layer on the surface of the N-type epitaxy by dry thermal oxidation, then grow an 8000 Å TEOS silicon dioxide by low-pressure chemical vapor deposition under low-temperature conditions of 650 °C to 750 °C, and then densify the TEOS silicon dioxide at 850 °C for 40 minutes; S3. On the surface silica, form a window for the P+ punch-through region through photolithography and wet etching, and then dope the P+ punch-through region by boron implantation with a doping dose of 2.5E16 ions / cm² and an energy of 120 KeV. After doping, grow a layer of 6000 Å TEOS silica by low-pressure chemical vapor deposition under low-temperature conditions of 650 °C to 750 °C, and then drive it for 1 hour under the condition of 1250 °C N 2 condition; S4. Lithographically pattern the window for the P+ active region. First, dry-etch 10000 Å of silicon dioxide, then cure with photoresist at 90 °C for 1 hour, and then wet-etch the remaining silicon dioxide. After etching, perform boron implantation with an implantation dose of 5E15 ions / cm² and an implantation energy of 90 keV. After implantation, grow a 6000 Å layer of TEOS silicon dioxide by LPCVD, and then perform annealing at 1000 °C in N 2 condition promotion; S5. By a method combining dry and wet etching, first dry-etch 4500 Å of silicon dioxide, then cure with glue at 90 °C for 1 hour, and then wet-etch the remaining silicon dioxide, and at the same time open holes on the 12000 Å TEOS silicon dioxide in the P+ punch-through region and the 6000 Å TEOS silicon dioxide in the P+ active region; S6. Deposit metal AlSiCu on the surface, with a thickness of 3 μm; S7. Grow a passivation layer on the metal layer. The passivation layer has a two-layer structure. The first layer structure is phosphosilicate glass PSG, and the second layer structure is silicon nitride. Open holes on the passivation layer by photolithography and etching to expose the metal lead holes; S8. Grind the back of the P-type substrate to 150 μm, and then deposit three layers of metal on the back of the P-type substrate, namely 2000 Å titanium, 3000 Å nickel, and 8000 Å silver.

2. A bidirectional symmetric TVS diode, implemented based on the manufacturing method of a bidirectional symmetric TVS diode described in claim 1, characterized in that, it includes: A P-type substrate; An N-type epitaxial layer, formed on the P-type substrate; A P+ active region, formed in the N-type epitaxial layer; A P+ punch-through region, passing through the N-type epitaxial layer, and the bottom of the P+ punch-through region is connected to the P-type substrate; An oxide layer, formed on the N-type epitaxial layer, and the surface of the P+ punch-through region is connected to the P+ active region through the oxide layer; A metal layer, formed above the P+ punch-through region and the P+ active region and between the oxide layers; A passivation layer, formed above the metal layer; and A back metal layer, formed on the back of the P-type substrate.

3. The bidirectional symmetric TVS diode according to claim 2, characterized in that, the passivation layer includes phosphosilicate glass PSG and silicon nitride, the phosphosilicate glass PSG is in contact with the metal layer, and the silicon nitride is formed above the phosphosilicate glass PSG.

4. The bidirectional symmetric TVS diode according to claim 2, characterized in that, the back metal layer sequentially includes a titanium layer, a nickel layer, and a silver layer.

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