Capacitive sampling circuit

Abstract

A capacitive sampling circuit includes: a first differential input terminal configured to receive a first of a pair of differential input signals; a second differential input terminal configured to receive the other of the pair of differential input signals; a capacitive circuit output terminal configured to provide a sampled output signal; a plurality of first sampling capacitors each having a first plate and a second plate; a plurality of reference voltage terminals each configured to receive a respective reference voltage; and a first capacitor first plate switch block configured to selectively connect the first plate of each of the plurality of first sampling capacitors to either (i) the first differential input terminal; or (ii) a respective one of the plurality of reference voltage terminals; and a first capacitor second plate switch configured to selectively connect the second plate of each of the plurality of first sampling capacitors to or disconnect it from the second differential input terminal.

Description

Technical Field

[0001] The present disclosure relates to a capacitive sampling circuit, and more particularly (but not exclusively) to a successive approximation register (SAR) analog-to-digital converter (ADC) including a capacitive sampling circuit. Background Art

[0002] A successive approximation analog-to-digital converter circuit (ADC) is a type of analog-to-digital converter circuit that uses a successive approximation register (SAR) to convert an analog waveform into a digital output signal. Sampling on a SAR ADC can occur on either the bottom plate or the top plate of a sampling capacitor present in the digital-to-analog converter (DAC) of the overall SAR ADC circuit. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a circuit including a capacitive sampling circuit, wherein the capacitive sampling circuit includes:

[0004] A first differential input terminal configured to receive a first of a pair of differential input signals;

[0005] A second differential input terminal configured to receive the other of the pair of differential input signals;

[0006] A capacitive circuit output terminal configured to provide a sampled output signal;

[0007] A plurality of first sampling capacitors, each having a first plate and a second plate;

[0008] A plurality of reference voltage terminals, each configured to receive a respective reference voltage;

[0009] A first capacitor first plate switch block configured to selectively connect the first plate of each of the plurality of first sampling capacitors to either (i) the first differential input terminal; or (ii) a respective one of the plurality of reference voltage terminals; and

[0010] A first capacitor second plate switch configured to selectively connect the second plate of the plurality of first sampling capacitors to the second differential input terminal, or disconnect from the second differential input terminal.

[0011] This capacitive sampling circuit can perform fully differential capacitive sampling, which can advantageously reduce any common-mode noise sampled across the first sampling capacitors.

[0012] In one or more embodiments, the circuit further includes a controller configured to control the first capacitor first plate switch block and the first capacitor second plate switch to alternate between:

[0013] (a) A sampling operation state, wherein:

[0014] The first capacitor first plate switch block connects the first plate of each of the plurality of first sampling capacitors to a first differential input terminal; and

[0015] The first capacitor second plate switch connects the second plate of each of the plurality of first sampling capacitors to a second differential input terminal; and

[0016] (b) A conversion operation state, wherein:

[0017] The first capacitor first plate switch block connects the first plate of each of the plurality of first sampling capacitors to a respective one of the plurality of reference voltage terminals; and

[0018] The first capacitor second plate switch disconnects the second plate of each of the plurality of first sampling capacitors from the second differential input terminal.

[0019] In one or more embodiments, the circuit is a digital - to - analog converter circuit. The circuit can be an analog - to - digital converter circuit.

[0020] In one or more embodiments, the circuit is a SAR ADC circuit. The SAR ADC may further include one or more of the following:

[0021] A first capacitive sampling circuit, which includes any capacitive sampling circuit disclosed herein;

[0022] A comparator, which includes a comparator first input terminal and a comparator output terminal; and

[0023] A SAR logic block, which includes:

[0024] A SAR logic input terminal, which is configured to receive a comparator output signal;

[0025] A SAR logic feedback terminal, which is configured to provide a SAR logic feedback signal, the SAR logic feedback signal representing a digital word used as a reference for the first capacitive sampling circuit. The digital word may include a plurality of bits. The SAR logic block may be configured to process the comparator output signal to determine the SAR logic feedback signal; and

[0026] A SAR logic output terminal, which is configured to provide an ADC output signal representing the digital word at the end of the conversion;

[0027] The capacitor circuit output terminal of the first capacitor sampling circuit can be connected to the first input terminal of the comparator. The output terminal of the comparator can be connected to the SAR logic input terminal. The SAR logic feedback terminal can be connected to the plurality of reference voltage terminals of the first capacitor sampling circuit. Each of the plurality of reference voltage terminals can be configured to receive a corresponding reference voltage representing the value of one of the bits in a digital word.

[0028] In one or more embodiments, the circuit further includes: a plurality of buffers connected in series between the SAR logic feedback terminal and the plurality of reference voltage terminals of the first capacitor sampling circuit.

[0029] In one or more embodiments, the circuit may further include:

[0030] One or more first dummy capacitors, each having a first plate and a second plate of the first dummy capacitor, wherein the second plate of the first dummy capacitor is connected to the first input terminal of the comparator; and

[0031] A first dummy capacitor switch block configured to selectively connect the first plate of each of the one or more first dummy capacitors to any one of the following: (i) a first differential input terminal; or (ii) a ground terminal.

[0032] In one or more embodiments, when the circuit is in a conversion operation state, the first dummy capacitor switch block connects the first plate of each of the one or more first dummy capacitors to the ground terminal; and

[0033] When the circuit is in a sampling operation state, the first dummy capacitor switch block connects the first plate of each of the one or more first dummy capacitors to the first differential input terminal.

[0034] In one or more embodiments, the circuit further includes: a second capacitor sampling circuit including any capacitor sampling circuit disclosed herein. The first differential input terminal of the first capacitor sampling circuit can be configured to receive a first differential input signal. The second differential input terminal of the first capacitor sampling circuit can be configured to receive a second differential input signal. The first differential input terminal of the second capacitor sampling circuit can be configured to receive the second differential input signal. The second differential input terminal of the second capacitor sampling circuit can be configured to receive the first differential input signal. The comparator may further include a second input terminal of the comparator. The capacitor circuit output terminal of the second capacitor sampling circuit can be connected to the second input terminal of the comparator. The SAR logic feedback terminal can be connected to the plurality of reference voltage terminals of the second capacitor sampling circuit. Each of the plurality of reference voltage terminals can be configured to receive a corresponding reference voltage representing the value of one of the bits in a digital word.

[0035] In one or more embodiments, the circuit further includes: a plurality of buffers connected in series between the SAR logic feedback terminal and the plurality of reference voltage terminals of the second capacitive sampling circuit.

[0036] In one or more embodiments, the circuit further includes: one or more second dummy capacitors, each having a first plate of the second dummy capacitor and a second plate of the second dummy capacitor. The second plate of the second dummy capacitor can be connected to the second input terminal of the comparator. The second dummy capacitor switch block can be configured to selectively connect the first plate of the second dummy capacitor of each of the one or more second dummy capacitors to any one of the following: (i) the second differential input terminal; or (ii) the ground terminal.

[0037] In one or more embodiments, when the SAR ADC is in the conversion operation state, the second dummy capacitor switch block connects the first plate of the second dummy capacitor of each of the one or more second dummy capacitors to the ground terminal; and when the SAR ADC is in the sampling operation state, the second dummy capacitor switch block connects the first plate of the second dummy capacitor of each of the one or more second dummy capacitors to the second differential input terminal.

[0038] In one or more embodiments, the first differential input signal is a positive differential input signal; and the second differential input signal is a negative differential input signal.

[0039] In one or more embodiments, the first differential input signal is a negative differential input signal; and the second differential input signal is a positive differential input signal.

[0040] Although the present disclosure admits of various modifications and alternative forms, specific details thereof have been shown by way of example in the drawings and will be described in detail. However, it should be understood that other embodiments beyond the specific embodiments described are also possible. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0041] The foregoing discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The drawings and the following detailed description also illustrate various example embodiments. The various example embodiments can be more fully understood by considering the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0043] Figure 1 An SAR ADC that performs top plate sampling of the received differential signaling is shown;

[0044] Figure 2 A SAR ADC that performs bottom plate sampling of received differential signaling is shown;

[0045] Figure 3A and 3B A SAR ADC that includes a capacitive sampling circuit according to an example embodiment of the present disclosure is shown;

[0046] Figure 4 Another example embodiment of a SAR ADC that includes two capacitive sampling circuits is shown; and

[0047] Figure 5 Yet another example embodiment of a SAR ADC that includes one or more dummy capacitors is shown. DETAILED DESCRIPTION

[0048] Figure 1 A SAR ADC 100 that performs top plate sampling of received differential signaling is shown.

[0049] The SAR ADC 100 includes a first DAC 110, a second DAC 112, a comparator 114, and a SAR logic block 116. As will be discussed in detail below, each of the first DAC 110 and the second DAC 112 includes a capacitive sampling circuit. The SAR ADC 100 has a first differential input terminal 102 that receives a first differential input signal (in_p) that is a positive differential input signal in this example. The SAR ADC 100 also includes a second differential input terminal 104 that receives a second differential input signal (in_n) that is a negative differential input signal in this example.

[0050] The first differential input terminal 102 is connected to the positive input terminal of the comparator 114 through a first sampling switch 106. In this way, the first sampling switch 106 can selectively connect the first differential input terminal 102 to the comparator 114 (and also to a plurality of first sampling capacitors 120, as will be discussed below) or disconnect it therefrom. When the first sampling switch 106 is closed, the circuit samples the first differential input signal (in_p). When the first sampling switch 106 is open, the circuit converts the sampled value of the first differential input signal (in_p). The first DAC 110 is also connected to the positive input terminal of the comparator 114. More specifically, the analog output signal from the first DAC 110 is provided to the positive input terminal of the comparator 114.

[0051] In a similar manner, a second differential input terminal 104 is connected to a negative input terminal of a comparator 114 via a second sampling switch 108. In this way, the second sampling switch 108 can selectively connect the second differential input terminal 104 to the comparator 114 (and also to a plurality of second sampling capacitors 124, as will be discussed below) or disconnect it therefrom. When the second sampling switch 108 is closed, the circuit samples the second differential input signal (in_n). When the second sampling switch 108 is open, the circuit converts the sampled value of the second differential input signal (in_n). A second DAC 112 is also connected to the negative input terminal of the comparator 114. More specifically, an analog output signal from the second DAC 112 is provided to the negative input terminal of the comparator 114.

[0052] The comparator 114 has a comparator output terminal that is connected to a SAR logic input terminal 154 of a SAR logic block 116. The SAR logic input terminal 154 receives a comparator output signal from the comparator 114. The SAR logic block 116 also includes a SAR logic feedback terminal 156 (shown as two separate terminals for clarity in Figure 1 and a SAR logic output terminal 158. The SAR logic feedback terminal 156 is configured to provide a SAR logic feedback signal that represents a digital word used as a reference for the first DAC 110 and the second DAC 112. The digital word includes a plurality of bits. The SAR logic block 116 processes the comparator output signal to determine the SAR logic feedback signal, as is known in the art. The SAR logic output terminal 158 provides an ADC output signal (out-digital) representing a digital code at the end of the analog-to-digital conversion, again as is known in the art of SAR ADCs.

[0053] The first DAC 110 includes a plurality of first sampling capacitors 120 and a corresponding plurality of first buffers 118, which may also be referred to as inverters. Each corresponding pair of the first sampling capacitors 120 and the first buffers 118 is connected (in series with each other) between (i) the SAR logic feedback terminal 156 and (ii) the positive input terminal of the comparator 114. More specifically, each corresponding pair of the first sampling capacitors 120 and the first buffers 118 is connected to the SAR logic feedback terminal 156 such that it receives a corresponding reference voltage that represents the bit value of the digital word provided as the SAR logic feedback signal by the SAR logic block 116.

[0054] Similarly, the second DAC 112 includes a plurality of second sampling capacitors 124 and a corresponding plurality of second buffers 122. Each corresponding pair of second sampling capacitors 124 and second buffers 122 are connected (in series with each other) between (i) the SAR logic feedback terminal 156 and (ii) the negative input terminal of the comparator 114. As with the first DAC 110, each corresponding pair of second sampling capacitors 124 and second buffers 122 receive a corresponding reference voltage, the corresponding reference voltage representing the bit value of the digital word provided as the SAR logic feedback signal.

[0055] Figure 1 The SAR ADC 100 of performs top plate sampling of the received differential signaling because the first differential input signal (in_p) and the second differential input signal (in_n) are connected to the top plates of the sampling capacitors 120, 124. The differential input signaling (in_n and in_p) is sampled in a pseudo-differential manner on the DAC.

[0056] Figure 2 Fig. shows a SAR ADC 200 that performs bottom plate sampling of the received differential signaling. Figure 2 that has been referenced Figure 1 The features described will be given corresponding features in the 200 series and will not be described again here.

[0057] Figure 2 The circuit of Figure 2 includes a plurality of first reference voltage terminals 232 and a plurality of second reference voltage terminals 262, each of which receives a corresponding reference voltage. Each of the corresponding reference voltages represents the value of one of the bits in the digital word provided as the SAR logic feedback signal by the SAR logic block 216. In this way, the SAR logic block applies the digital word across both the plurality of first reference voltage terminals 232 and the plurality of second reference voltage terminals 262.

[0058] Figure 2 The circuit of Figure 2 also includes a first capacitor first plate switch block 226 that selectively connects the first plate 234 of each of the plurality of first sampling capacitors 220 to either (i) the first differential input terminal 202; or (ii) a corresponding one of the plurality of first reference voltage terminals 232. Similarly, the circuit includes a second capacitor first plate switch block 228 that selectively connects the first plate 235 of each of the plurality of second sampling capacitors 224 to either (i) the second differential input terminal 204; or (ii) a corresponding one of the plurality of second reference voltage terminals 262.

[0059] The positive input terminal of the comparator 214 is connected to ground through the first sampling switch 206. In this way, the first sampling switch 206 can selectively connect the comparator 214 (and the plurality of first sampling capacitors 220) to ground or disconnect it from ground. Similarly, the negative input terminal of the comparator 214 is connected to ground through the second sampling switch 208. In this way, the second sampling switch 208 can selectively connect the comparator 214 (and the plurality of second sampling capacitors 224) to ground or disconnect it from ground.

[0060] The SAR ADC 200 is in the conversion operation state when the following occurs (as Figure 2 shown):

[0061] · The first capacitor first plate switch block 226 connects the first plate 234 of each of the plurality of first sampling capacitors 220 to a corresponding one of the plurality of first reference voltage terminals 232;

[0062] · The second capacitor first plate switch block 228 connects the first plate 235 of each of the plurality of second sampling capacitors 224 to a corresponding one of the plurality of second reference voltage terminals 262;

[0063] · The first sampling switch 206 disconnects the positive input terminal of the comparator 214 from ground; and

[0064] · The second sampling switch 208 disconnects the negative input terminal of the comparator 214 from ground.

[0065] The SAR ADC 200 is in the sampling operation state when the following occurs ( Figure 2 not shown):

[0066] · The first capacitor first plate switch block 226 connects the first plate 234 of each of the plurality of first sampling capacitors 220 to the first differential input terminal 202;

[0067] · The second capacitor first plate switch block 228 connects the first plate 235 of each of the plurality of second sampling capacitors 224 to the second differential input terminal 204;

[0068] · The first sampling switch 206 connects the positive input terminal of the comparator 214 to ground; and

[0069] · The second sampling switch 208 connects the negative input terminal of the comparator 214 to ground.

[0070] Figure 2The SAR ADC 200 performs bottom plate sampling of the received differential signaling because the first differential input signal (in_p) and the second differential input signal (in_n) are connected to the bottom plates (first plates 234, 235) of the sampling capacitors 220, 224. The differential input signaling (in_n and in_p) is again sampled in a pseudo-differential manner on the DAC, but on the other side of the sampling capacitor compared to the Figure 1 circuit.

[0071] As discussed above, for both the Figure 1 top plate sampling and Figure 2 bottom plate sampling of the

[0072] the differential input signaling is sampled in a pseudo-differential manner on the DAC. In a pseudo-differential setting, the even-order distortion components will be common-mode. The common-mode distortion components can be suppressed using downstream processing, for example, in a manner similar to a fully differential setting. Therefore, such pseudo-differential circuits just shift the problem to the next stage. In contrast, a fully differential setting will cancel (or at least reduce) the common-mode signal, regardless of the source (crosstalk, distortion components, bias shift, etc.). Figure 1 For the

[0073] SAR ADC, the stage after the DAC is a comparator. Although the comparator can be fully differential and thus reject the common-mode signal, there are still reasons to want a fully differential DAC (which includes the sampling capacitors in the SAR ADC). These reasons include:

[0074] 1. The comparator has a limited common-mode rejection ratio (CMRR). This means that unwanted common-mode signals may propagate to the output of the ADC, thereby limiting performance. Therefore, additional CMRR may be useful, especially since increasing the CMRR of a dynamic comparator can increase the power consumption of the circuit.

[0075] 2. The comparator may have a limited common-mode range. A comparator with an NMOS input stage may be limited at its low end by its threshold voltage (which can easily be half of the supply voltage in modern CMOS). And, at its high end, overvoltage may occur during conversion. Therefore, performance may degrade rapidly as the common-mode voltage increases.

[0076] Figure 3A and 3B show a SAR ADC 300 including a capacitive sampling circuit 330 according to an example embodiment of the present disclosure. Figure 3A shows the SAR ADC 300 in a conversion operation state. Figure 3B shows the SAR ADC 300 in a sampling operation state. Figure 3A and3B already referenced Figure 1 or Figure 2 The features described will be given corresponding features in the 300 series and need not be described again here.

[0077] The capacitive sampling circuit 330 receives a pair of differential input signals. The first of the pair will be referred to as the first differential input signal. The other of the pair will be referred to as the second differential input signal.

[0078] The capacitive sampling circuit 330 includes a first differential input terminal 304 that receives the first differential input signal. The capacitive sampling circuit 330 also includes a second differential input terminal 302 that receives the second differential input signal. In this example, the first differential input signal is the negative differential input signal (in_n), and the second differential input signal is the positive differential input signal (in_p). In other examples, the polarities of the input signals may be reversed.

[0079] The capacitive sampling circuit 330 also includes a capacitive circuit output terminal 305 that provides a sampled output signal. In Figure 3A and 3B the capacitive sampling circuit 330 is part of the SAR ADC 300 such that the sampled output signal is provided to the input of the comparator.

[0080] The capacitive sampling circuit 330 further includes a plurality of reference voltage terminals 332, each of which is configured to receive a corresponding reference voltage. As discussed above, for a SAR ADC, the reference voltage represents the value of one of the bits in the digital word provided as the SAR logic feedback signal.

[0081] As Figure 3A and 3B shown in

[0082] The first capacitor first plate switch block 326 can selectively connect the first plate 334 of each of the plurality of first sampling capacitors 320 to either: (i) the first differential input terminal 304; or (ii) a corresponding one of the plurality of reference voltage terminals 332. The first capacitor second plate switch 327 can selectively connect the second plate 336 of each of the plurality of first sampling capacitors 320 to the second differential input terminal 302 or disconnect it therefrom.

[0083] In this manner, one of the two differential input signals (in_n and in_p) is sampled on the first plate (bottom plate) 334 of the first sampling capacitor 320, and the other of the two differential input signals (in_n and in_p) is sampled on the second plate (top plate) 336 of the first sampling capacitor 320. Thus, both sides of the sampling capacitor 320 can be sampled simultaneously. This can mean that only the differential signal (and no common-mode signal) is sampled via the first sampling capacitor 320. Therefore, Figure 3A and 3B the capacitive sampling circuit 330 of can perform fully differential capacitive sampling, which can advantageously reduce any common-mode noise sampled across the first sampling capacitor 320.

[0084] Figure 3A shows the capacitive sampling circuit 330 in a conversion operation state, where:

[0085] · The first capacitor first plate switch block 326 connects the first plate 334 of each of the plurality of first sampling capacitors 320 to a corresponding one of the plurality of reference voltage terminals 332; and

[0086] · The first capacitor second plate switch 327 disconnects the second plate 336 of each of the plurality of first sampling capacitors 320 from the second differential input terminal 302.

[0087] Figure 3B shows the capacitive sampling circuit 330 in a sampling operation state, where:

[0088] · The first capacitor first plate switch block 326 connects the first plate 334 of each of the plurality of first sampling capacitors 320 to the first differential input terminal 304; and

[0089] · The first capacitor second plate switch 327 connects the second plate 336 of each of the plurality of first sampling capacitors 320 to the second differential input terminal 302.

[0090] Figure 3A and 3B 's circuit may also include a controller (not shown) that controls the first capacitor first plate switch block 326 and the first capacitor second plate switch 327 such that the SAR ADC alternates between the conversion operation state and the sampling operation state.

[0091] Figure 3A and 3B The SAR ADC circuit 300 of also includes a comparator 314, a SAR logic block 316, and a plurality of buffers / inverters 318.

[0092] Comparator 314 includes a comparator first input terminal and a comparator output terminal. In this example, comparator 314 is used as a single-ended comparator by connecting the first input terminal of comparator 314 to the capacitive sampling circuit 330 and connecting the other input terminal of comparator 314 to a fixed reference voltage.

[0093] The SAR logic block 316 includes a SAR logic input terminal 354 that can receive the comparator output signal; and a SAR logic feedback terminal 356 that can provide a SAR logic feedback signal. In the same manner as described above, the SAR logic feedback signal represents a digital word used as a reference for the first capacitive sampling circuit 330. The SAR logic block 316 is configured to process the comparator output signal to determine the SAR logic feedback signal, as is known in the art. The capacitive sampling circuit 330 can operate in the manner described herein, regardless of any particular switching scheme employed by the SAR logic block 316.

[0094] The SAR logic block 316 further includes a SAR logic output terminal 358, which is configured to provide an ADC output signal (out_digital) representing a digital word at the end of the conversion, again as is known in the art.

[0095] As Figure 3A and 3B shown, the capacitive circuit output terminal 305 of the first capacitive sampling circuit 330 is connected to the comparator first input terminal of comparator 314. The comparator output terminal of comparator 314 is connected to the SAR logic input terminal 354. The SAR logic feedback terminal 356 is connected to the plurality of reference voltage terminals 332 of the first capacitive sampling circuit 330. As discussed above, each of the plurality of reference voltage terminals 332 is configured to receive a corresponding reference voltage representing a bit value of a digital word.

[0096] The plurality of buffers 318 are connected in series between the SAR logic feedback terminal 356 and the plurality of reference voltage terminals 332 of the first capacitive sampling circuit 330. It should be understood from the above description that the capacitive sampling circuit 330 and the plurality of buffers 318 can be regarded together as a DAC, which is part of the overall SAR ADC circuit 300.

[0097] It should be understood that Figure 3A and 3B the capacitive sampling circuit 330 shown can be used in other applications. For example, as part of a DAC, a capacitive charge redistribution SAR ADC, any other suitable type of ADC, or any circuit that performs capacitive sampling.

[0098] Figure 4Shows another exemplary embodiment of the SAR ADC 400. In this example, the SAR ADC includes two capacitive sampling circuits 430, 438. Also, a fully differential comparator 414 is used. As will be discussed below, compared to the circuits for Figure 3A and 3B , the loads on the two differential input signals (in_n and in_p) can be more closely matched, which further improves the common-mode rejection (CMRR) of the circuit.

[0099] The SAR ADC 400 includes a first capacitive sampling circuit 430 and a second capacitive sampling circuit 438. The first capacitive sampling circuit 430 includes: a plurality of first sampling capacitors 420; a plurality of reference voltage terminals 432; a first capacitor first plate switch block 426; and a first capacitor second plate switch 427. These components are connected in the same manner as described above with reference to Figure 3A and 3B .

[0100] The second capacitive sampling circuit 438 includes: a plurality of second sampling capacitors 442; a plurality of reference voltage terminals 462; a second capacitor first plate switch block 440; and a second capacitor second plate switch 446. These components are also connected in the same manner as described above with reference to Figure 3A and 3B .

[0101] The first capacitive sampling circuit 430 includes: (i) a first differential input terminal 404 that receives the first differential input signal (in_n); and (ii) a second differential input terminal 402 that receives the second differential input signal (in_p). The second capacitive sampling circuit 438 includes; (i) a first differential input terminal 476 that receives the second differential input signal (in_p); and (ii) a second differential input terminal 478 that receives the first differential input signal (in_n). In this way, the first of a pair of differential input signals is connected to the top plate of the first sampling capacitor 420 and the bottom plate of the second sampling capacitor 442. The other of the pair of differential input signals is connected to the bottom plate of the first sampling capacitor 420 and the top plate of the second sampling capacitor 442. Thus, the first capacitive sampling circuit 430 (which can be regarded as part of the positive half of the SAR ADC 400) samples the positive input signal on its top plate and samples the negative input signal on its bottom plate. For the second capacitive sampling circuit 438 (which can be regarded as part of the negative half of the SAR ADC 400), this is switched. Advantageously, in this way, the imbalance in the top and bottom plate connections of the sampling capacitors 420, 442 for the differential input signals (in_n, in_p) can be cancelled (or at least reduced).

[0102] At Figure 4In this case, the first differential input signal is the negative differential input signal (in_n), and the second differential input signal is the positive differential input signal (in_p). It should be understood that in other examples, these signals may be reversed.

[0103] Comparator 414 includes a comparator first input terminal (which is the comparator positive input terminal in this example) and a comparator second input terminal (which is the comparator negative input terminal in this example). The comparator first input terminal is connected to the capacitive circuit output terminal 405 of the first capacitive sampling circuit 430. The comparator second input terminal is connected to the capacitive circuit output terminal 460 of the second capacitive sampling circuit 438.

[0104] The SAR logic feedback terminal 456 is connected to the plurality of reference voltage terminals 432, 462 of both the first and second capacitive sampling circuits 430, 438. As discussed above, each of the plurality of reference voltage terminals 432, 462 is configured to receive a corresponding reference voltage representing the bit value of a digital word.

[0105] In this example, the SAR ADC 400 further includes a plurality of buffers / inverters 444, which are connected in series between the SAR logic feedback terminal 456 of the second capacitive sampling circuit 438 and the plurality of reference voltage terminals 462.

[0106] In practice, there may be parasitic capacitances associated with the top plates of the sampling capacitors 420, 442. For example, this can be attributed to the input capacitance of the comparator 414. And in some examples, dummy capacitors may be placed around the sampling capacitors 420, 442 for matching purposes.

[0107] Figure 5 Another exemplary embodiment of the SAR ADC 500 is shown, which includes dummy capacitors 550, 568. Figure 5 The features that have been Figure 4 described with reference to Figure 5 will be given corresponding features in the 500 series and will not be described again here. In Figure 4 this case, compared with

[0108] the first differential input terminal 504 receives the positive differential input signal (in_p), and the second differential input terminal 502 receives the negative differential input signal (in_n). Figure 5The first dummy capacitor first plate 566 of each of the one or more first dummy capacitors 550 can be selectively connected to any one of the following: (i) the first differential input terminal 504; or (ii) the ground terminal (simply a single switch in

[0109] When the SAR ADC 500 is in the conversion operation state (as Figure 5 shown), the first dummy capacitor switch block 552 connects the first dummy capacitor first plate 566 of each of the one or more first dummy capacitors 550 to the ground terminal.

[0110] When the SAR ADC 500 is in the sampling operation state ( Figure 5 not shown in the figure), the first dummy capacitor switch block 552 connects the first dummy capacitor first plate 566 of each of the one or more first dummy capacitors 550 to the first differential input terminal 504.

[0111] Similarly, the SAR ADC 500 includes one or more second dummy capacitors 568, each having a second dummy capacitor first plate 570 and a second dummy capacitor second plate 572. The second dummy capacitor second plate 572 is connected to the second input terminal of the comparator. The second dummy capacitor switch block 574 (which is simply a single switch in Figure 5 can selectively connect the second dummy capacitor first plate 570 of each of the one or more second dummy capacitors 568 to any one of the following: (i) the second differential input terminal 502; or (ii) the ground terminal.

[0112] When the SAR ADC 500 is in the conversion operation state (as Figure 5 shown), the first dummy capacitor switch block 552 connects the first dummy capacitor first plate 566 of each of the one or more first dummy capacitors 550 to the ground terminal.

[0113] When the SAR ADC 500 is in the sampling operation state ( Figure 5 not shown in the figure), the first dummy capacitor switch block 552 connects the first dummy capacitor first plate 566 of each of the one or more first dummy capacitors 550 to the second differential input terminal 502.

[0114] Therefore, the dummy capacitors 550, 568 can also use the same sampling scheme as the sampling capacitors. In this way, the parasitic capacitance on the top plates of the shown dummy capacitors 552, 568 will not significantly reduce the common-mode rejection.

[0115] For example, other capacitances such as the comparator input capacitance can limit the CMRR of the circuit. Such capacitances can be 10% of the main capacitance, and for some embodiments, this can limit the achievable CMRR to approximately 20 dB. However, 20 dB can be considered an improvement over, for example, Figure 1 and 2 pseudo-differential settings.

[0116] One or more of the capacitive sampling circuits described herein can advantageously allow for fully differential sampling on the sampling capacitors of a DAC / SAR ADC to increase common-mode rejection.

[0117] The capacitive sampling circuits described herein that sample on both sides of the sampling capacitor can be better than circuits using an op-amp-based input buffer. This is because an op-amp-based input buffer can be power-hungry, add distortion / noise, and can be slow.

[0118] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the figures above can be executed in any order. And, those skilled in the art will recognize that although one example instruction set / method has been discussed, the materials in this specification can be combined in many ways to also produce other examples, and should be understood within the context provided herein.

[0119] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied in an executable instruction set that is implemented on a computer or a machine programmed and controlled by the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or multiple components.

[0120] In other examples, the instruction set / method shown herein, as well as the data and instructions associated therewith, are stored in corresponding storage devices that are implemented as one or more non-transitory machine or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any manufactured single component or multiple components. As defined herein, a non-transitory machine or computer-usable medium does not include a signal, but such media may be capable of receiving and processing signals from a signal and / or other transitory media.

[0121] Example embodiments of the materials discussed in this specification may be implemented, in whole or in part, via a network, computer, or data-based device and / or service. These may include the cloud, the Internet, an intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0122] In one example, one or more of the instructions or steps discussed herein are automated. The term automatic or automatically (and its like variations) means the use of a computer and / or mechanical / electrical device to control the operation of a device, system, and / or process without human intervention, observation, effort, and / or decision-making.

[0123] It should be understood that any components referred to as coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be positioned between the two components referred to as coupled.

[0124] In this specification, example embodiments have been presented in accordance with a selected set of details. However, those of ordinary skill in the art will understand that many other example embodiments may be practiced that include different selected sets of these details. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A SAR ADC circuit, characterized in that, Comprising a first capacitive sampling circuit, wherein the first capacitive sampling circuit comprises: A first differential input terminal configured to receive a first of a pair of differential input signals; A second differential input terminal configured to receive the other of the pair of differential input signals; A capacitive circuit output terminal configured to provide a sampled output signal; A plurality of first sampling capacitors, each having a first plate and a second plate; A plurality of reference voltage terminals, each configured to receive a respective reference voltage; A first capacitor first plate switch block configured to selectively connect the first plate of each of the plurality of first sampling capacitors to either (i) the first differential input terminal; or (ii) a respective one of the plurality of reference voltage terminals; and A first capacitor second plate switch configured to selectively connect the second plate of each of the plurality of first sampling capacitors to the second differential input terminal or disconnect it from the second differential input terminal; A comparator comprising a comparator first input terminal and a comparator output terminal; and A SAR logic block comprising: A SAR logic input terminal configured to receive the comparator output signal; A SAR logic feedback terminal configured to provide a SAR logic feedback signal representing a digital word used as a reference for the first capacitive sampling circuit, wherein the digital word comprises a plurality of bits, and wherein the SAR logic block is configured to process the comparator output signal to determine the SAR logic feedback signal; and A SAR logic output terminal configured to provide an ADC output signal representing the digital word at the end of a conversion; Wherein: The capacitive circuit output terminal of the first capacitive sampling circuit is connected to the comparator first input terminal of the comparator; The comparator output terminal of the comparator is connected to the SAR logic input terminal; and The SAR logic feedback terminal is connected to the plurality of reference voltage terminals of the first capacitive sampling circuit, wherein each of the plurality of reference voltage terminals is configured to receive a respective reference voltage representing a value of one of the bits in the digital word.

2. The SAR ADC circuit according to claim 1, wherein Further comprising a controller configured to control the first capacitor first plate switch block and the first capacitor second plate switch to alternate between: (a) A sampling operation state, wherein: The first capacitor first plate switch block connects the first plate of each of the plurality of first sampling capacitors to the first differential input terminal; and The first capacitor second plate switch connects the second plate of each of the plurality of first sampling capacitors to the second differential input terminal; and (b) A conversion operation state, wherein: The first capacitor first plate switch block connects the first plate of each of the plurality of first sampling capacitors to a respective one of the plurality of reference voltage terminals; and The first capacitor second plate switch disconnects the second plate of each of the plurality of first sampling capacitors from the second differential input terminal.

3. The SAR ADC circuit according to claim 1 or claim 2, characterized in that, The first capacitor sampling circuit is a digital-to-analog converter circuit.

4. The circuit according to claim 1 or claim 2, characterized in that, The first capacitor sampling circuit is an analog-to-digital converter circuit.

5. The SAR ADC circuit according to claim 1, wherein Further comprising: A plurality of buffers connected in series between the SAR logic feedback terminal and the plurality of reference voltage terminals of the first capacitor sampling circuit.

6. The SAR ADC circuit according to claim 1, wherein Further comprising: One or more first dummy capacitors, each having a first plate of the first dummy capacitor and a second plate of the first dummy capacitor, wherein the second plate of the first dummy capacitor is connected to the first input terminal of the comparator; And A first dummy capacitor switch block configured to selectively connect the first plate of each of the one or more first dummy capacitors to any one of the following: (i) the first differential input terminal; or (ii) the ground terminal.

7. The SAR ADC circuit according to claim 6, wherein: When the circuit is in the conversion operation state, the first dummy capacitor switch block connects the first plate of each of the one or more first dummy capacitors to the ground terminal; and When the circuit is in the sampling operation state, the first dummy capacitor switch block connects the first plate of each of the one or more first dummy capacitors to the first differential input terminal.

8. The SAR ADC circuit according to claim 1, wherein Further comprising: A second capacitor sampling circuit, which includes the capacitor sampling circuit according to claim 1 or claim 2; Wherein: The first differential input terminal of the first capacitor sampling circuit is configured to receive a first differential input signal; The second differential input terminal of the first capacitor sampling circuit is configured to receive a second differential input signal; The first differential input terminal of the second capacitor sampling circuit is configured to receive the second differential input signal; The second differential input terminal of the second capacitor sampling circuit is configured to receive the first differential input signal; The comparator further includes a second input terminal of the comparator; The capacitor circuit output terminal of the second capacitor sampling circuit is connected to the second input terminal of the comparator; and The SAR logic feedback terminal is connected to the plurality of reference voltage terminals of the second capacitor sampling circuit, wherein each of the plurality of reference voltage terminals is configured to receive a corresponding reference voltage representing a value of one of the bits in the digital word.

9. The SAR ADC circuit according to claim 8, wherein Further comprising: A plurality of buffers connected in series between the SAR logic feedback terminal and the plurality of reference voltage terminals of the second capacitor sampling circuit.

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