Power distribution for active area die stacking on active area with reduced resistance

Abstract

An active-area-on-active-area microelectronic device (200A, 200B, 400A, 400B) is described. For example, respectively, a first die (211, 411) is located on a second die (212, 211) with a lower surface of a first substrate (213, 414) facing an upper surface of the second substrate (214, 213) to provide a die stack (210A, 210B, 410A, 410B). The first and second dies (212, 211) each have a metal layer (M1-M11, M1-M13) in an ILD layer (ILD1-ILD11, ILD1-ILD13) to provide a first stack structure (217, 417) and a second stack structure (227, 217), respectively. The first stacked structure (217, 417) is interconnected to the upper end of the TSV (222, 422) of the first tube core (211, 411). The metal layer (M11, M13) of the second stacked structure (227, 217) near the lower surface of the first substrate (213, 414) is interconnected to the lower end of the TSV (222, 422). The power distribution network layer (M5) of the second stacked structure (227, 217) is located between the lower layer and the upper layer of its metal layer (M1-M11, M1-M13). The transistor (223, 224) at least partially located in the second substrate (214, 213) is interconnected to the power distribution network layer (M5) to receive a power supply voltage or ground.

Description

Field of the Invention

[0001] The following description relates to integrated circuit (IC) devices. More specifically, the following description relates to power distribution for active-on-active die stacks with reduced resistance to reduce current resistance (IR) losses in microelectronic devices. Background Art

[0002] Over time, integrated circuits have become increasingly "dense," i.e., more logic functions are implemented in an IC of a given size. However, to further increase circuit density, integrated circuit dies are stacked on top of each other to form a die stack, e.g., for "3D" ICs. However, there are limitations due to voltage drops in such die stacks. For example, one possible limitation may be the voltage drop along the power rails (i.e., power and / or ground conductive paths) of the chip stack. Summary of the invention

[0003] The apparatus generally relates to an active-area-on-active-area microelectronic device. In such an apparatus, a first die has a first substrate having a through-hole extending between an upper surface and a lower surface of the first substrate and extending through the substrate. A second die has a second substrate having an upper surface and a lower surface. The first die is on the second die, and the lower surface of the first substrate faces the upper surface of the second substrate to provide a die stack. The first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stack structure and a second stack structure for conducting electricity, respectively. The first stack structure is interconnected to the upper end of the through-hole extending through the substrate to achieve conduction. The metal layer of the second stack structure near the lower surface of the first substrate is interconnected to the lower end of the through-hole extending through the substrate for conducting electricity. The power distribution network layer of the second stack structure is located between the lower and upper layers of its plurality of metal layers. The first transistor and the second transistor are at least partially located in the first substrate and the second substrate, respectively. The second transistor is interconnected to the power distribution network layer to receive at least one of a power supply voltage or ground.

[0004] A method generally relates to forming an active-area-on-active-area microelectronic device. In the method, a first die is obtained. The first die has a first substrate having a through-hole extending between an upper surface and a lower surface of the first substrate. A second die having a second substrate having an upper surface and a lower surface is obtained. The first die is interconnected on the second die, with the lower surface of the first substrate facing the upper surface of the second substrate to provide a die stack. The first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stack structure and a second stack structure for conducting electricity, respectively. The first stack structure is interconnected to an upper end of the through-hole through the substrate to achieve conduction. As part of the interconnection of the first die and the second die, a metal layer of the second stack structure near the lower surface of the first substrate is connected to a lower end of the through-hole through the substrate for conducting electricity. A power distribution network layer of the second stack structure is located between a lower layer and an upper layer of its plurality of metal layers. The first transistor and the second transistor are at least partially located in the first substrate and the second substrate, respectively. The second transistor is interconnected to the power distribution network layer to receive at least one of a power supply voltage or a ground.

[0005] In another example, a semiconductor die is disclosed that includes a first plurality of metals and a first standard cell. The first standard cell and the first plurality of metal layers are disposed within the first die body. The first plurality of metal layers form a portion of a first BEOL stack. The first plurality of metal layers include a first metal layer disposed closest to the first standard cell and a last metal layer disposed farthest from the first standard cell. The first plurality of metal layers include a first power distribution network layer disposed above the first standard cell and below a last metal layer of the first plurality of metal layers. The first power distribution network layer is configured to provide at least one of a supply voltage or a ground to the first standard cell.

[0006] In yet another example, an active area on active area microelectronic device is provided. The active area on active area microelectronic device includes a first die, a second die having a standard cell formed therein, and a power distribution network layer. The first die is stacked on the second die to provide a die stack. The first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stacked structure and a second stacked structure. The power distribution network layer of the second stacked structure is located between a first metal layer of the plurality of metal layers closest to the standard cell and a last metal layer of the plurality of metal layers farthest from the standard cell. The power distribution network layer is configured to provide a power supply voltage or ground to the standard cell.

[0007] Other features will be appreciated by consideration of the following detailed description and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings illustrate exemplary devices and / or methods. However, the accompanying drawings should not be used to limit the scope of the claims, but are only for explanation and understanding.

[0009] Figure 1 are perspective views depicting top and side views of a wafer stack in an exemplary process for wafer level processing (WLP).

[0010] Figure 2-1 is a block diagram depicting a side view of an exemplary portion of a microelectronic device having die stacking.

[0011] Figure 2-2 is a block diagram depicting a side view of an exemplary portion of another microelectronic device having another die stack.

[0012] Figure 3-1 is a block diagram depicting a cross-sectional view of an exemplary portion of a semiconductor die at a lower metallization level.

[0013] Figure 3-2 is a block diagram depicting a cross-sectional view of an exemplary portion of a semiconductor die at an upper metallization level.

[0014] Figure 3-3 is a block diagram depicting a cross-sectional view of an exemplary portion of a semiconductor die at an intermediate power distribution network level.

[0015] Figure 4-1 is described as Figure 2-1 A block diagram of a side view of an exemplary portion of yet another microelectronic device having a die stack.

[0016] Figure 4-2 is a block diagram depicting a side view of an exemplary portion of yet another microelectronic device having yet another die stack.

[0017] Figure 5 is a flow chart depicting an exemplary microelectronic device formation process.

[0018] Figure 6 is a simplified block diagram depicting an exemplary columnar field programmable gate array (FPGA) architecture. DETAILED DESCRIPTION

[0019] In the following description, numerous specific details are set forth to provide a more thorough description of the specific examples described herein. However, it will be apparent to those skilled in the art that one or more other examples and / or variations of these examples may be practiced without all of the following specific details. In other cases, well-known features are not described in detail to avoid obscuring the description of the examples herein. For ease of illustration, the same numerical designations are used in different figures to represent the same items; however, in alternative examples, these items may be different.

[0020] Exemplary devices and / or methods are described herein. It should be understood that the word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any example or feature described herein as "exemplary" is not necessarily to be construed as being preferred or advantageous over other examples or features.

[0021] Before describing the examples illustratively depicted in several figures, a general introduction is provided for further understanding. As traditional "2D" scaling becomes increasingly challenging at smaller and smaller semiconductor process nodes, stacking individual dies (e.g., semiconductor substrate dies or semiconductor dies) on top of each other using through-substrate vias (TSVs) becomes an increasingly attractive approach to increase circuit density. Along these lines, active area-on-active area die stacking can be used as a die stack or as part of a die stack.

[0022] Due to the structure of the die stack, it does not make sense to continue to be constrained by the configuration of 2D dies. In other words, the die stack does not have to consist of a stack of traditional 2D dies.

[0023] With each semiconductor processing node, the voltage or current resistance (IR) drop increases, in some cases doubling. In semiconductor process nodes below 20 nanometers, a dramatic increase in IR drop on voltage and ground power rails has been observed. This means that stacking using conventional 2D dies (e.g., providing active area on active area die stacking) may result in significant IR drop. The accumulation of IR drop reduces the available voltage across components (e.g., such as transistors). If the supply voltage or supply power is increased to account for such an accumulation of IR drop, power consumption may increase.

[0024] However, in order to reduce the power consumption of microelectronic devices, down-scaling of supply voltages has been used. The reduction in supply voltage combined with the additional IR drop makes it more difficult to achieve performance goals.

[0025] TSVs, and the corresponding chimney-like stacking structures (referred to as "chimneys" or "chimney stacks") used to carry power and ground currents in such die stacks, have a cumulative IR drop that is much greater than the IR drop in conventional non-stacked 2D die. In conventional non-stacked 2D die configurations, power and ground distribution originates from the topmost conductive layer and propagates down the metallization levels to the substrate. In die stacking of conventional 2D dies, power and ground distribution may start from the backside of the substrate, go up through the TSV and chimney metallization levels to the topmost metallization levels, and then back down through such metallization levels to the substrate.

[0026] Conventional placement and routing (PnR) cells or blocks for chimney construction reduce IR drop by having more conductive vias between metal layers. Additionally, by having more chimneys, the effects of IR drop or loss can be reduced. However, these configurations use more area, which increases the cost per die.

[0027] In contrast to the power and ground distribution in such conventional die stacking, a lower resistance path for power and ground distribution will be described in more detail below. As described below, a chimney temporary buss path is provided to bypass the chimney metallization level to reduce IR drop. Such a chimney temporary buss path can be provided with a power and ground distribution network (PDN) metallization layer. The "early off-ramp" bussing out of the chimney for conducting current for the power or ground path reduces the IR drop. Such an "early off-ramp" has an intermediate metallization level that is formed to be thicker than the conventional intermediate metallization level. By providing a thicker intermediate metallization level for power and ground distribution, that is, providing thick traces for power and ground bussing, the IR drop can be reduced compared to the power and ground routing in the conventional die stacking. The IR drop can be reduced by at least 20% without increasing the area and increasing the cost of each die.

[0028] With the general description above in mind, various configurations of die stacks are generally described below.

[0029] Figure 1 1 is a perspective view depicting a top view and a side view of a wafer stack 100 in an exemplary process for wafer level processing (WLP). Top wafer 101 and bottom wafer 102 can be coupled to each other. For example, Cu / Sn microbump transient liquid phase (TLP) bonding technology can be used to bond one die to another die at a die-to-die level, a wafer-to-wafer level, or a die-to-wafer level, or to interconnect one die to another die differently for conductivity and mechanical coupling. However, other types of interconnections from one die to another die can be used.

[0030] The interconnect layer can be on the upper side, or the lower side, or both of a die in a 3D die stack. The lower surface 101b and upper surface 102a of each of wafers 101 and 102 can face each other after such coupling with a die-to-die interconnect that interconnects the corresponding dies in the die stack to achieve electrical conduction. Along those lines, the semiconductor die ("active die") 104 of the top wafer 101 can be coupled to the corresponding active die 105 of the bottom wafer 102 to form a stacked wafer 103 having a stacked die or die stack.

[0031] Each semiconductor die 104 and 105 may include a semiconductor material such as silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), germanium (Ge), Si 1-x Ge x In addition, any microelectronic component having a die stack with a substrate including one or more through-hole structures extending through the substrate and two or more active dies may be used. An active die may be distinguished from a passive die because an active die includes transistors, while a passive die does not have transistors. A die stack with an active region on an active region is described below.

[0032] As used herein with respect to wafers, dies and substrates and other structures, terms such as "upper surface" and "lower surface" are used to refer to features that extend generally in a "horizontal" or other lateral direction and are generally parallel to each other in thickness. Terms such as "horizontal", "upper", "lower" or other directional terms are used relative to the reference frame of the drawings and / or orientation during processing, and they are not meant to limit potential possible orientations (e.g., orientations used in subsequent assembly or in various systems).

[0033] Along these lines, when processing the wafer 101 or 102, the respective upper surface 101a or 102a is generally associated with the so-called "front side" of the wafer being processed, and the respective lower surface 101b or 102b can be generally associated with the so-called "back side" of the wafer being processed. Along these lines, the front side of the wafer being processed can be used to form so-called front-end of line (FEOL) structures, and the back side of the wafer being processed can be used to form back-end of line (BEOL) structures. Generally, the FEOL structures can include shallow trench isolation (STI), transistor gates, transistor source / drain regions, transistor gate dielectrics, contact etch stop layers (CESL), pre-metallization dielectrics or pre-metal dielectrics (PMD), and contact plugs, among other FEOL structures. The PMD can be composed of one or more layers. Generally, the BEOL structures can include one or more interlayer dielectrics (ILDs) and one or more metallization levels (M). In the following examples, multiple ILDs are described exemplarily; however, in other configurations, there may be fewer or more ILDs than described exemplarily. In addition, each ILD can be composed of one or more dielectric layers. In the following examples, multiple metallization levels or metal layers are exemplarily depicted; however, in other configurations, the number of metallization levels may be less or more than the exemplarily depicted metallization levels. In addition, metal from a metallization level may extend through one or more ILDs in the form of known conductive vias. Furthermore, each metallization level may be composed of one or more metal layers.

[0034] The passivation level may be formed on the last or topmost metallization layer or level. Such a passivation level may include one or more dielectric layers and may also include an anti-reflective coating (ARC). The passivation layer may be formed by one or more dielectric layers (e.g., polymer layers). For example, the passivation layer may be a benzocyclobutene (BCB) layer, or a combination of a silicon nitride layer and a BCB layer. In some die stacking applications, the passivation layer may be referred to as an inter-die layer.

[0035] A metal layer such as copper, copper alloy or other metal can be formed on the passivation layer and on the lower contact surface of the uppermost through-hole conductor. The metal layer can be an RDL metal layer. Balls or bumps can be formed on the bonding pads, respectively, wherein these pads can be formed on such a metal layer or these pads can be formed as part of such a metal layer. The ball can be formed by a bonding material such as solder or other eutectic bonding materials. The ball can be a microbump, a C4 bump, a ball grid array (BGA) ball, or some other die interconnect structure. In some applications, the uppermost metal layer can be referred to as a landing pad layer or landing pad.

[0036] In addition, a redistribution layer (RDL) may be formed on such a passivation layer. Conventionally, an RDL may include: a dielectric layer, such as a polyimide layer; another metal layer on the dielectric layer and connected to the bonding pad of the metal layer of the last metallization level; and another dielectric layer on the RDL metal layer, such as another polyimide layer, while the other dielectric layer exposes a portion of the RDL metal layer to provide another bonding pad. The end opening may expose such another bonding pad of such an RDL metal layer. Thereafter, a solder bump or wire bond may be conventionally coupled to such a bonding pad.

[0037] As part of the formation of the FEOL or BEOL structures, a plurality of via structures may extend within openings formed in a substrate that extend into the substrate. The via structures may generally be in the form of any solid of any shape formed by filling or plating an opening or hole formed in the substrate. Examples of such solid shapes generally include cylinders, cones, truncated cones, rectangular prisms, cubes, etc.

[0038] Conventionally, through-substrate via structures, or TSVs, can extend from the upper surface of the substrate downward to or toward the lower surface of the substrate, i.e., by first forming a front-side TSV by etching from the front side of the substrate and then plating or otherwise depositing material in the etched hole of the substrate. Along those lines, after the back-side is exposed to expose the bottom of such TSV, the TSV can extend between the upper and lower surfaces of the substrate, because the thickness of the substrate can be effectively thinned to expose the lower end face of the TSV. However, the TSV can have a back-side via structure. The manufacture of back-side TSVs is generally referred to as a "via last approach", and correspondingly, the manufacture of front-side TSVs is generally referred to as a "via first approach". In addition, a "via middle approach" can be used. The "middle via approach" is also a front-side method of via formation, but is called "middle" because the via is made after the FEOL operation but generally before the BEOL operation. The following description generally applies equally to front-side or back-side TSVs formed by any or all of the via-first, via-last, or via-in-the-middle approaches.

[0039] The TSVs may each include an upper contact surface that may be flush with the upper surface of the substrate and a lower contact surface that may be flush with the lower surface of such substrate, such as after backside exposure. The end surfaces may be used to interconnect the TSVs with other internal or external components, as described in more detail below.

[0040] For example, the upper end contact surface of the through-hole conductor can be interconnected to the first metallization level (M1) through corresponding contact pads. The contact pads can be formed in each opening formed in the PMD to which M1 extends. However, in other configurations, one or more through-hole conductors can extend to one or more other higher metallization levels through one or more ILDs.

[0041] More recently, TSVs have been used to provide so-called three-dimensional (3D) ICs, or "3D ICs." Typically, the process of attaching one chip to another using TSVs as conductive pathways through a substrate can be performed at the bonding pad level or at the on-chip electrical routing level; however, wafer-to-wafer bonding can also be used. Semiconductor dies such as semiconductor dies 104 and 105 can be cut into individual dies from wafers 101 and 102, respectively. Such individual dies can be bonded to each other or to a circuit platform. Interposers, package substrates, and printed circuit boards are examples of circuit platforms.

[0042] 3D wafer-level packaging (3D-WLP) can be used to interconnect two or more dies, one or more dies to an interposer, or any combination thereof, wherein their interconnection can use TSVs. Alternatively, the dies can be interconnected die-to-die (D2D) or chip-to-chip (C2C), wherein their interconnection can use TSVs. Furthermore, optionally, the dies can be interconnected die-to-wafer (D2W) or chip-to-wafer (C2W), wherein their interconnection can use TSVs. Thus, any of a variety of die stacking or chip stacking methods can be used to provide a 3D stacked IC (3D-SIC or 3D-IC).

[0043] For clarity, by way of example and not limitation, it will be assumed that a die-level package with D2D die stacking is used, with at least two active dies in the die stack. Since WLP for die-to-die stacking is not currently a common practice for commercial production of 3D die stacking, cut die-to-die stacking will be described in more detail below. However, other configurations may be used, including but not limited to WLP, as described herein. In addition, for the purpose of brevity and not limitation, many of the details described above regarding the formation of the semiconductor die will not be repeated below.

[0044] Figure 2-1 2 is a block diagram showing a side view of an exemplary portion of a microelectronic device 200A having a die stack 210A. The die stack 210A includes an upper semiconductor die 211 and a lower semiconductor die 212 coupled to each other. The upper semiconductor dies 211 and 212 each have a consistent body. Figure 2-1 The same reference numerals may be used to refer to the identical body. The back surface 201 of the upper semiconductor die 211 is connected to the front surface 202 of the lower semiconductor die 212, ie, the lower surface 201 and the upper surface 202 are opposite to each other.

[0045] The upper semiconductor die 211 includes a substrate 213 having TSVs 222. Although only one TSV 222 is illustrated for clarity, the substrate 213 may include more than one TSV. The TSV 222 extends between the upper surface 208 of the substrate 213 and the back side 201 of the substrate 213. In this example, for clarity and not limitation, the back side 201 is the surface of the substrate 213 of the upper semiconductor die 211. In another example, the back side of the semiconductor die may be a back side RDL or a surface of one or more other layers formed on the back side 201 of the substrate 213. In addition, in this example, the TSV 222 extends above the upper surface 208, such as by using a PMD layer that is used to provide a form for a portion of the TSV 222. This is merely for convenience in showing the metal layer M1 of the plurality of metallization layers interconnected to the TSV 222, such as by forming M1-M13 in the upper semiconductor die 211 in an exemplary manner. However, as described in more detail below, metal layer M1 may be used to form conductive vias, which may be interconnects to TSVs 222 .

[0046] The upper semiconductor die 211 may include circuit components forming a circuit, wherein such circuit components may include one or more transistors 224 and other circuit components, as generally depicted for purposes of clarity and not limitation. In an example, a gate and a gate dielectric (not specifically shown for purposes of clarity and not limitation) may be located above the upper surface 208 of the substrate 213.

[0047] The upper semiconductor die 211 includes a "chimney" or "chimney stack" 217. Although only one "chimney" or "chimney stack" is illustrated for clarity, the upper semiconductor die 211 or another semiconductor die described herein may include more than one "chimney". The chimney 217 is formed by multiple metallization and ILD levels. In this example, the non-chimney portion of the lower metallization and ILD level 218 of the semiconductor die 211 is typically used for interconnection between components, such as circuit components that may include one or more transistors 224. In this example, the non-chimney portion of the upper metallization and ILD level 219 of the semiconductor die 211 is typically used for interconnection between the semiconductor die 211 and the circuit platform 215 and "global" on-die wiring, such as clocks and other signals.

[0048] In this example, there are 13 metallization levels M1 to M13, and corresponding 13 ILD layers ILD1 to ILD13. In this example, the power distribution network (PDN) metal layer (shown as M5 in this example) is thicker or taller than adjacent metal layers, and can be thicker or taller than all other metallization levels of metallization levels M1 to M13. In one or more examples, the thickness of the PDN layer is at least twice the thickness of the first (M1) or last (M13) metallization layer. Such a PDN layer is between the upper and lower metallization levels, and can typically be the first, second, third, or fourth metallization level above the last wiring metallization level, used for direct interconnect wiring of repeating cells of the circuit, sometimes referred to as the first metallization level above the last "standard cell" metal wiring layer. In this way, the metallization layer and the "standard cell" are all within the tube core 211. In other words, the PDN layer can reside on the first metal layer, the second metal layer, the third metal layer, or the fourth metal layer of multiple metal layers immediately and sequentially located above the standard cell. A "standard cell" is a set of transistors and interconnect structures that provide a Boolean logic function (e.g., AND, OR, XOR, XNOR, inverter, buffer, etc.) or a storage function (flip-flop or latch). The simplest cells are direct representations of the basic NAND, NOR, and XOR Boolean functions, although cells of higher complexity (e.g., 2-bit full adders or multiplexed D-input flip-flops) are often used. The PDN layer is also not located in the last two (e.g., highest) metal layers. The PDN layer is also located on a metal layer that is closer to the standard cell than the last metal layer of the multiple metal layers. In one example, the PDN layer is at least 2 or more metal layers below the last metal layer (M13) of the upper metallization level, such as at least 5, 7, or even 8 or more metal layers below the last metal layer. In this example, the height of the PDN layer M5 is at least twice the height of the immediately adjacent upper metal layer relative to the thickness of its respective horizontal traces. In this example, the height H1 of the horizontal trace 245 of the PDN layer M5 is at least twice the height H2 of the horizontal trace 247 of the chimney stack portion of the metallization layer M1 or M13. More generally, in one example, the PDN layer M5 is configured to have a lower resistivity, wherein in this example, the resistivity of its horizontal traces (e.g., horizontal trace 245) is observed to be less than 30 ohms for a length of at least 30 microns. A horizontal trace generally refers to a conductive line formed in a trench defined in an ILD, wherein such a conductive line follows the trench, and generally the trench may have a horizontal extent relative to the plane of its ILD. Without the above enhancements, in a complex FPGA, the total resistance from the topmost metal layer in the BEOL stack down to the transistor area in the substrate in a "2D" IC may be 120 ohms. Although this number may be much smaller relative to a traditional placement and routing ASIC, it is still a burden relative to the voltage drop on one or more power rails.

[0049] Although a 13-level BEOL chimney is illustratively depicted, fewer or more metallization and corresponding ILD levels may be used in other examples according to the description herein. The uppermost metal layer or metallization level M13 (which may include one or more layers of material) associated with the upper surface 203 of the semiconductor die 211 may be interconnected to conductive contacts (not shown for purposes of clarity and non-limiting purposes) along the surface 204 of the circuit platform 215 for electrical conduction, and thus such metallization layer M13 in this example may be partly a power and ground distribution layer.

[0050] In the region of chimney 217, portions of lower metallization and ILD level 218 and upper metallization and ILD level 219 are used to provide low resistivity paths by increasing the density of conductive vias in such chimney regions to achieve metallization level to metallization level conductivity. Between lower metallization and ILD level 218 and upper metallization and ILD level 219 is a PDN metal layer M5 and a corresponding ILD level ILD5. Alternative locations of the PDN metal layer (i.e., locations other than M5) may be determined as described above. Likewise, portions of the PDN metal layer M5 where the ILD layer is ILD5 in the region of chimney 217 are used to provide more localized power and ground routing to one or more circuit components, where such circuit components may include one or more transistors of transistors 223 and 224, respectively. For metallization level to metallization level conductivity, such localized power and ground routing from the PDN metal layer M5 may be used to achieve a path with reduced resistivity by increasing the density of conductive vias in the chimney region associated with such a PDN metal layer M5 as compared to the upper metal layer relative thereto. Such routing is more localized than the power and ground routing from the topmost metal layer of the IC to one or more of its transistors. Additionally, intermediate metallization levels for providing a PDN metal layer (e.g., PDN metal layer M5) may include, including but not limited to, intra-die power and ground routing bussing relative to such metallization layers.

[0051] Since the front surface generally has more electrical interconnect opportunities than the back surface, the front surface 203 (i.e., upper surface 203) can be coupled to a lower surface 204 of a printed circuit board, an interposer substrate, an RDL stack, a package substrate, or other circuit platform 215 to couple the die stack 210A to such a circuit platform 215. The circuit platform 215 can be used to provide off-die power and ground routing busses, generally indicated by arrows 230.

[0052] The lower semiconductor die 212 includes a substrate 214 having TSVs 221. Although only one TSV 221 is illustrated for clarity, the substrate 214 may include multiple TSVs. The TSVs 221 extend between an upper surface 209 and a lower surface 205 of the substrate 214. In this example, for purposes of clarity and not limitation, the lower surface 205 of the substrate 214 is the back surface 205 of the lower semiconductor die 212. However, in other examples, the back surface of the semiconductor die may be a surface of a back RDL, or other one or more surfaces formed on the back surface 205 of the substrate 214.

[0053] Lower semiconductor die 212 may include circuit components, such as may include one or more transistors 223 , and other circuit components, as generally depicted for purposes of clarity and not limitation. In one example, a gate and gate dielectric may be located above upper surface 209 of substrate 214 .

[0054] For clarity, by way of example and not limitation, an enlarged view of a portion of a MOSFET transistor 260 of transistor 223 or transistor 224 is shown. The transistor 260 of transistor 223 and the transistor 260 of transistor 224 may be formed at least partially in substrates 214 and 213, respectively. In another example, another type of transistor may be formed. Each transistor 260 may include a source region 261 and a drain region 262 formed in substrate 214. A gate dielectric 263 may be formed on substrate 214, and a gate electrode 264 may be formed on gate dielectric 263. A conductive layer (e.g., M1) may be used to form a conductive via 266 that provides electrical conduction to source region 261, gate electrode 264, and / or drain region 262. Conductive via 266 may be formed in dielectric layer 265. Another or the same metal layer used to form the conductive via 266 can be used to form horizontal conductive lines, such as conductive lines 267, which can be interconnected to one or more conductive vias 266 for conduction. Another dielectric layer 268 can be formed above the conductive line 267 for another conductive layer metal layer to provide a conductive via 269. One or more conductive vias 269 can be interconnected to one or more conductive lines, such as conductive line 267, for conduction. Moreover, one or more conductive vias 266 can be directly or indirectly interconnected to the power distribution network (PDN) metal layer M5, as described in further detail below. Along those lines, one of the conductive vias 266 can be used to provide a power supply voltage or a ground voltage to the source region 261, the drain region 262, and / or the gate electrode 264 of the transistor 260 to operate it. Similarly, another of the conductive vias 266 can be used to provide a power supply voltage or a ground voltage to another of the source region 261, the drain region 262, and / or the gate electrode 264 of the transistor 260 to operate it. Although only a single transistor 260 of transistors 223 and 224 is shown for clarity, more than one transistor 260 of transistors 223 and 224 may be similarly provided with power and / or ground.

[0055] The lower semiconductor die 212 includes a "chimney" or "chimney stack" 227. Although only one "chimney" is illustrated for clarity, the lower semiconductor die 212 may include multiple "chimneys." The chimney 227 is formed to have multiple metallization and ILD levels. The uppermost metallization level (e.g., M11) of the semiconductor die 212 can be interconnected to the lower end or lower end surface 251 of the TSV 222 for conduction. The lowermost metallization layer (e.g., M1) of the semiconductor die 211 can be interconnected to the upper end or upper end surface 252 of the TSV 222 for conduction. Using the metallization layer M1 as the lowermost metallization layer of the lower semiconductor die 212 means that the metal layer for the TSV 221, which may include, for example, a PMD layer, is not included as part of the BEOL stack.

[0056] In this example, the lower metallization of semiconductor die 212 and the non-chimney portion of ILD level 228 are generally used for interconnection or routing between components (e.g., transistor 223). In this example, the upper metallization of semiconductor die 212 and the non-chimney portion of ILD level 229 are generally used for interconnection or routing between semiconductor die 212 and semiconductor die 211, as well as "global" on-die routing, such as clock and other signals. For this example, there are 11 metallization levels M1 to M11, and corresponding 11 ILD levels ILD1 to ILD11. As described with reference to PDN layer M5, power distribution network (PDN) metal layer M5 can be thicker or taller than all other metallization levels of metallization levels M1 to M11. Alternative locations (i.e., in addition to M5) and thicknesses of PDN metal layers can be determined as described above. In this example, the height H1 of horizontal traces 245 of PDN layer M5 is at least twice the height H3 of horizontal traces 246 of the chimney stack portion of metallization layer M7. Again, the PDN metal layer M5 is configured to have a reduced resistivity. In one example, it has been observed that the PDN metal layer M5 has a resistivity of less than 30 Ohms for a length of at least 30 microns.

[0057] Although an 11-stage BEOL chimney structure is illustratively shown, fewer or more metallization and corresponding ILD stages may be used in other examples according to the description herein. In addition, even though in this example, different semiconductor dies 211 and 212 are used with respect to the number of stages of the BEOL structure, in another example, semiconductor dies 211 and 212 may also have the same number of stages of the BEOL structure.

[0058] The uppermost metal layer of semiconductor die 212, such as metallization level M11 in this example, can include one or more layers of conductor material and one or more layers of barrier layer. Again, such uppermost metal layer can be interconnected to a conductive contact for conducting electricity so as to interconnect with the lower side or lower end surface 251 of TSV 222 along surface 201 of upper semiconductor die 211.

[0059] In the region of the chimney 227, for metallization level to metallization level conductivity, the lower metallization and ILD level 228 and the upper metallization and ILD level 229 are used to provide a low resistivity path by increasing the density of conductive vias in such chimney regions. Between the lower metallization and ILD level 228 and the upper metallization and ILD level 229 is the PDN metal layer M5 and the corresponding ILD level ILD5. Similarly, in the region of the chimney 227, the PDN metal layer M5 together with the ILD level ILD5 is used to provide a low vertical resistivity path by increasing the density of conductive vias in such chimney regions to achieve metallization level to metallization level conductivity. Again, the topmost metal layer (in this example, such as metal level M11), which may include one or more layers of material, can be interconnected to the lower end of the TSV 222 for conduction.

[0060] Alternatively or additionally, the back surface 205, i.e., the lower surface, of the substrate 214 can be coupled to another semiconductor die. Along those routes, the TSVs and chimneys of the semiconductor dies of the die stack can be vertically aligned with each other, respectively, to provide low resistance paths for conducting current in an upward or downward direction within such a die stack when applicable. Such low resistance conductive paths can be used to provide a supply voltage to the chip stack 210A or to provide a path to ground from the chip stack 210A, generally as shown by arrow 230. In-die power or ground wiring can be provided by using lower metallization levels 218 and 228 from its metallization level M5, respectively, as generally indicated by arrows 231 and 232, respectively. Such in-die power and ground wiring can be used for the operation of transistors 224 and 223.

[0061] In this example, chimney 217, TSV 222, chimney 227, and TSV 221 are all vertically aligned with each other to provide a low vertical resistance path to the next semiconductor die in die stack 210A. However, if only semiconductor dies 211 and 212 are used for through-die low resistance routing in die stack 210A, then the last (for Figure 2-1 The lowest semiconductor die 233 may omit a portion of the chimney 227 and all corresponding TSVs, as shown in FIG. Figure 2-2The BEOL lower layer 238 of the semiconductor die 233 of the semiconductor die stack 210B is shown. Similar to the die body 211, the metallization layers and "standard cells" are also within the die body 212.

[0062] Figure 2-2 2 is a block diagram depicting a side view of an exemplary portion of a microelectronic device 200B having a die stack 210B. The die stack 210B includes semiconductor dies 211 and 212 as previously described, and a third lower semiconductor die 233. For clarity, the previous description of semiconductor dies 211 and 212 will not be repeated for the description of the microelectronic device 200B, as most of the microelectronic device 200B is similar to the microelectronic device 200B. Figure 2-1 Therefore, for the sake of clarity, only the differences will generally be described.

[0063] The lowermost semiconductor die 233 of the die stack 210B includes a partial chimney 237. The partial chimney 237 includes an upper metallization and ILD level 239 and a PDN metallization level M5 and a corresponding ILD level ILD5. However, although a lower metallization and ILD level 238 exists below the PDN metallization level M5 and the corresponding ILD level ILD5, such a lower level 238 is not used to provide a partial chimney in the semiconductor die 233. However, such a lower level 238 can be used to provide conventional power and ground routing to the substrate 234 of the semiconductor die 233, such as its transistors 235 as generally indicated. Despite providing additional routing area, the current carrying capacity of the power and ground of the conventional routing in the lower level 238 is less than that in the chimney, resulting in a higher resistance than in the chimney.

[0064] Also refer to Figure 2-1 and 2-2 , further describing microelectronic devices 200A and 200B. As previously described, a PDN level or layer (such as metal layer M5 in the above example) located between an upper level and a lower level of a plurality of metal layers (such as a BEOL metallization upper level and a lower level) can be coupled to a TSV through a corresponding portion of a chimney structure. These portions of the chimney structure can be interconnected to one or more TSVs for electrical conduction.

[0065] For example, current may flow through the TSVs 221 of the semiconductor die 212 through the lower metallization level 238, to a portion of the chimney 239, and to the substrate 234, generally as indicated by arrows 240. In the semiconductor die 233, the PDN layer M5 of such a semiconductor die 233 interconnected to the substrate 234 through the lower metallization and ILD level 238 may be coupled to such TSVs 221 through portions of the upper metallization and ILD level 239. The upper metallization and ILD level 239 may be used to form chimneys and other conductive routing of the semiconductor die 233. Figure 2-2 An example of an inflow current or power into microelectronic device 200B of the present invention can receive power to a portion of chimney 237 via TSV 221. Chimney 227, which is interconnected to TSV 221 of semiconductor die 212, can be coupled to circuit platform 215 for electrical conduction to receive such supplied power. In this example, chimney 217 and TSV 222 (the latter interconnected to chimney 227) can be used to power semiconductor die 212 and semiconductor die 233 through semiconductor die 211. Along these lines, PDN layer M5 of semiconductor die 211 and 212 can be used to provide power downward to substrates 213 and 214, respectively, through lower metallization levels 218 and 228, respectively, as generally indicated by arrows 231 and 232, respectively.

[0066] However, in semiconductor die 233, current for ground interconnection can flow from substrate 234 to portions of chimney 237, for example, via lower metallization level 238, generally as indicated by arrow 240, which lower metallization level 238 is in semiconductor die 233. In semiconductor die 233, PDN layer M5 of such semiconductor die 233 interconnected to substrate 234 via lower metallization and ILD level 238 can be coupled to TSV 221 via portions of upper metallization and ILD level 239, as these upper metallization and ILD levels 239 can also be used to form portions of chimney 237, as well as other conductive routing of semiconductor die 233. Continuing with reference to Figure 2-2 An example of providing a ground for the microelectronic device 200B may receive an outflow current to the TSV 221 of the semiconductor die 212 via the portion of the chimney 237 .

[0067] Chimney 227 interconnecting TSV 221 of semiconductor die 212 may be coupled to TSV 222 of semiconductor die 211 for electrical conduction. Chimney 217 interconnecting TSV 222 and circuit platform 215 for electrical conduction may be used to pass outgoing current to such circuit platform. In this example, a chain of interconnected chimney 217, TSV 222, chimney 227, TSV 221, and partial chimney 237 may be used to pass current from semiconductor die 233 to and through semiconductor die 212 and 211 through lower metallization level 238 for grounding of circuit platform 215. Along these lines, PDN layer M5 of semiconductor die 211 and 212 may be used to pass current from substrates 213 and 214 through lower metallization levels 218 and 228, respectively, to corresponding chimney structures (generally shown as arrows 231 and 232, respectively), as previously described, for outgoing ground connections to circuit platform 215.

[0068] In order to pass current up or down through the die stack, the resistance (R) is reduced compared to the resistance used in conventional wiring. For clarity, for purposes of example and not limitation, assuming that the semiconductor die has 13 metallization levels with a PDN layer M5, it has been observed that the resistance through the chimney stack from metallization level M13 to M5 ("stack resistance") can be in the range of greater than 2 to less than 10 ohms, such as 3.5 ohms, and the resistance through the chimney stack from metallization level M5 to M1 can be equal to or less than 1 ohm. In other words, it has been observed that the stacked portion of the lower metallization layer can be configured to have a stack resistance of equal to or less than 1 ohm overall from the lowest metal layer of the semiconductor die to the PDN layer.

[0069] For the purpose of chimney stacking, the wiring crowding between metallization levels M5 and M1 may be less than the wiring crowding between metallization levels M13 and M5. This allows the chimney stack to have more conductive vias formed for interconnection of metallization levels from the substrate to M1 and up to the PDN layer (M5 in this example). The higher conductive via density in the lower metallization level in the chimney stack allows it to have a lower stack resistance than the higher metallization levels in the chimney stack.

[0070] Along these lines, the chimney stack may have fewer conductive vias formed for interconnecting the metallization levels from the PDN layer (M5 in this example) up to the highest metallization level due to the increased amount of routing congestion in the metallization levels above the PDN layer. For example, the horizontal interconnects of the upper metallization levels may pass through the area where the TSV area intersects the chimney stack area. Additionally, the horizontal interconnects of the upper metallization levels may be narrow to provide areas for feedthroughs. By distributing power and grounding by bypassing the upper metallization levels that are not part of the chimney stack, the higher resistance associated with such upper metallization levels can be avoided.

[0071] For the sake of clarity, for the purpose of example and not limitation, the portion of the upper metallization layer associated with the chimney stack can be configured to have a lower stack resistance together. In one example, it is observed that the upper metallization layer in the chimney stack has a resistivity in the range of greater than 2 and less than 10 ohms from the uppermost metal layer to the PDN layer. In addition, for the sake of clarity, for the purpose of example and not limitation, the PDN layer can be configured to have a reduced resistivity. In one example, for a horizontal trace length of at least 30 microns, it is observed that the PDN layer has a resistivity of less than 30 ohms. Compared with a conventional 13-metallization-level semiconductor die, the use of an intermediate metallization level for the PDN layer of a semiconductor die with 13 metallization levels may result in at least a 20% reduction in IR drop. Although such a configuration does not cause an area loss, a thicker intermediate metallization level is used to provide a PDN layer, which may result in a slightly higher semiconductor die overall. Along those lines, for the sake of clarity, for the purpose of example and not limitation, the height H1 of the intermediate PDN layer in the BEOL stack described herein is at least about twice as long or high relative to other horizontal traces in such a stack. Furthermore, as described herein, the height H1 of the middle PDN layer in the BEOL stack can be at least about twice as long or tall as the same metallization level in a conventional chimney stack.

[0072] Figure 3-1 is a block diagram depicting a top cross-sectional view of an exemplary portion of semiconductor die 300 at a lower metallization level. Figure 3-2 is a block diagram depicting a top cross-sectional view of an exemplary portion of a semiconductor die 300 at an upper metallization level. Figures 2-1 to 3-2 , further describing the semiconductor die 300 .

[0073] Semiconductor die 300 may be semiconductor die 211 or 212 . Figure 3-1 The cross-sectional view shown is an example portion of the metallization level M1 and the ILD level ILD1 , although other levels below the PDN level of the BEOL stack may be used. Figure 3-2 The cross-sectional view shown is an example portion of metallization level M7 and ILD level ILD7, although other levels above the PDN level of the BEOL stack may be used.

[0074] Metallization level M1 and ILD level ILD1 may be used to form a plurality of conductive vias 303 within chimney region 302. Chimney region 302 may be used for chimney 217 or 227, as previously described. Chimney region 302 may completely overlap with corresponding TSV region 301. TSV region 301 may be one or both of the semiconductor die having conductive vias 303, or a chimney interconnected to such semiconductor die having conductive vias 303.

[0075] Metallization level M7 and ILD level ILD7 may be used to form a plurality of conductive vias 304 within chimney region 302. Although conductive vias 304 may have a larger cross-sectional area than conductive vias 303, the number of conductive vias 304 within chimney region 302 may be substantially less. The presence of feedthroughs (such as horizontal feedthroughs 305) passing through chimney region 302 limits the amount of area available in that region for conductive vias 304. As previously discussed, routing congestion at metallization levels above intermediate PDN levels may be greater than routing congestion at metallization levels below such intermediate PDN levels.

[0076] Even though the cross-sectional area of ​​the conductive vias above the intermediate PDN level may be larger than the cross-sectional area of ​​the conductive vias below such intermediate PDN level, the number of conductive vias 303 below such intermediate PDN layer within the chimney region 302 may be at least 2 times, and in some cases at least 4 times, larger than the number of conductive vias 305 above the intermediate PDN level within the chimney region 302. Therefore, the chimney stack resistance of the lower metallization level may be 1 / 3 or less of the chimney stack resistance of the upper metallization level.

[0077] Figure 3-3 is a block diagram showing a cross-sectional view of an exemplary portion of a semiconductor die 300 at an intermediate PDN level. Figure 2-1 to Figure 3-3 , further describing the semiconductor die 300 .

[0078] Semiconductor die 300 may be semiconductor die 211 or 212 . Figure 3-3 The cross section shown is an example portion of the metallization level M5 and the ILD level ILD5, although another intermediate metal layer may be used as a PDN layer of the BEOL stack. For clarity, by way of non-limiting example, although it is assumed that the BEOL stack includes a single intermediate level for providing a PDN level, in other examples, more than one intermediate PDN level may be used in the BEOL stack.

[0079] The metallization level M5 and the ILD level ILD5 may be used to form a plurality of conductive vias 303 within the chimney region 302, as previously described with reference to Figure 3-1As described. Conductive vias 303 may be formed in ILD5. Grooves may be formed in ILD5, including such conductive vias 303 as above, such as metallization layer M5. For metallization or metal layer M5, the grooves formed by such ILD5 may be plated or otherwise deposited with one or more layers, which may include one or more layers of conductive material for metal layer M5, typically a metal or a mixture of metals. Such metal layer M5 interconnected to such grooves of conductive vias 303 may be used to provide conductive traces, such as conductive power traces 311 and conductive ground traces 312 of PDN layer 310. Such intra-die power and ground wiring bussing provided with traces 311 and 312 of PDN layer 310 may be thicker than conventional power and ground wiring to reduce resistivity, such as at least twice as thick as the directly adjacent upper metal horizontal traces. Along these routes, the PDN layer (e.g., metal layer M5) may be configured to have a lower resistivity. In one example, the PDN metal layer M5 is observed to have a resistivity of less than 30 Ohms for a horizontal trace length 355 extending at least 30 microns from the chimney stack structure or region.

[0080] Figure 4-1 4 is a block diagram depicting a side view of an exemplary portion of a microelectronic device 400A having a die stack 410A. As previously described, the die stack 410A includes at least the same semiconductor die 211 and 212 as in the die stack 210A, and for the purpose of clarity and not limitation, this description will not be repeated. However, in this example, the circuit platform 215 is not directly interconnected to the front or upper surface of the semiconductor die 211. Instead, the circuit platform 215 in the microelectronic device 400A is interconnected to the back or lower surface 205 of the substrate 214 of the lowermost semiconductor die 212 of the die stack 410A. Along these lines, the lower end surface of the TSV 221 can be interconnected to one or more contacts of the circuit platform 215 (not shown for clarity and not for limitation) to achieve electrical conduction. The upper end surface of the TSV 221 can be interconnected to the metallization level M1 of the lower metallization level 228 of the semiconductor die 212.

[0081] For the corresponding chimneys 227 and 217, because the lower metallization levels 228 and 218 have less chimney stack resistance than the upper metallization levels 229 and 219, the current may encounter less resistance in the reverse die stacking direction for power and / or ground routing busses, such as in the die stack 410A, generally as shown by arrows 230, 231, and 232. For example, the resistance through TSV 221 and the lower metallization layer 228 to the PDN layer M5 may be less than the resistance through TSV 222 and the upper metallization layer 229 to the PDN layer M5. Although the topmost semiconductor die (e.g., semiconductor die 211 in the reverse die stack 410A) may be exposed to any additional resistance difference between the group of upper metallization layers 219 and 229 compared to the group of lower metallization layers 228 and 218 and metallization layer M5, as well as the additional resistance of TSVs 221 and 222, such additional resistance is comparable to the difference between the group of upper metallization layers 219 and 229 and the group of lower metallization layers 228 and 218 and metallization layer M5. Figure 2-1 The resistance of the conductive path to metallization level M5 to semiconductor die 212 in die stack 210A is smaller than that of metallization level M5.

[0082] Figure 4-2 4 is a block diagram depicting a side view of an exemplary portion of a microelectronic device 400B having a die stack 410B. Microelectronic device 400B is identical to microelectronic device 400A, except that the uppermost semiconductor die 411 on semiconductor die 211 of die stack 410B is a conventional semiconductor die 411. Along these lines, a conventional BEOL stack 418 may be used, with a conventional chimney 417 above upper surface 408 of substrate 414, and corresponding TSVs 422 extending between upper surface 408 and lower surface 401 of substrate 414. Upper ends 452 of TSVs 422 may be interconnected to the lowest metal layer of chimney 417 to enable electrical conduction. In addition, power and ground are distributed from the uppermost metallization layer (e.g., M13 metal layer of BEOL stack 418) downward to substrate 414 of semiconductor die 411, generally as indicated by arrows 230 and 431. The lower end 451 of the TSV 422 may be interconnected to the uppermost metal layer (eg, metal layer M13 ) of the chimney 217 to achieve electrical conduction.

[0083] Semiconductor die 211, 212, and / or 414 may be from the same series of integrated circuits. For example, the same series of system-on-chip (SoC) die. An example of an SoC die may be a field programmable gate array or an FPGA die. One or more of semiconductor die 211, 212, and / or 414 may be from different series of integrated circuit dies, such as different series of system-on-chip (SoC) dies. One or more of semiconductor die 211, 212, and / or 414 may be different types of integrated circuit dies from each other. For example, one of semiconductor die 211, 212, or 414 may be a storage die, another of semiconductor die 211, 212, or 414 may be a SoC die, and another of semiconductor die 211, 212, or 414 may be a focal plane array or other sensor die.

[0084] Figure 5 is a flow chart depicting an exemplary microelectronic device formation process 500. Process 500 can be used to form a microelectronic device, as previously described with reference to Figure 1 to Figure 4-2 Therefore, while referring to Figures 1 to 5 The process 500 is further described.

[0085] At 501, a first integrated circuit die may be obtained, the first integrated circuit die having a through-substrate via extending between a first upper surface and a first lower surface of a first substrate thereof. Such a first integrated circuit die may be in a wafer (such as with reference to Figure 1 ), or may be a single semiconductor die (eg, semiconductor die 212 with TSVs 221 ).

[0086] At 502, a second integrated circuit die having a second substrate may be obtained, the second substrate having a second upper surface and a second lower surface. Such a second integrated circuit die may be in a wafer (such as reference Figure 1 ), or may be a single semiconductor die (eg, semiconductor die 211 with TSVs 222 ).

[0087] At 503, such a first integrated circuit die and a second integrated circuit die may be interconnected to each other in such a manner that such a first upper surface and such a second lower surface face each other. The interconnection may be used for die-to-die conductivity. In addition, the interconnection may include a mechanical interconnection, which may include an interconnection for die-to-die conductivity, and a dielectric adhesive, polyimide, or other bonding dielectric layer for die-to-die bonding, for example, bonding semiconductor die 211 and 212 together.

[0088] Acquiring such a first integrated circuit die at operation 501 may include operations 504 and 505. At operation 504, a plurality of metal layers and a plurality of interlevel dielectric layers (e.g., M1-M11 and ILD1-ILD11) of such a first integrated circuit die may be formed or have been formed above such a first upper surface, respectively, while a lowermost layer (e.g., M1) of the plurality of metal layers is interconnected to the first through-substrate via for conduction, and an uppermost layer (e.g., M11) of the plurality of metal layers is interconnected to the second through-substrate via for conduction.

[0089] At operation 505, a power distribution network layer (e.g., M5) of such multiple metal layers may be located or has been located between a lower layer and an upper layer of such multiple metal layers and coupled to the upper end of the first through-substrate via through a stacked structure (e.g., a lower portion of a chimney 227 formed with a lower metallization and an ILD level or including a lower portion of a chimney 227, i.e., a partial chimney), as previously described. Such a stacked structure may include a portion of such a lower layer, including a portion of such a lowermost layer interconnected to such an upper end of such a first through-substrate via.

[0090] Again, portions of such lower layers of such stacked structures can be configured to have a reduced stack resistance together. In one example, it was observed that the stack resistance from the lowest layer to the power distribution network layer was equal to or less than 1 ohm. Such a power distribution network layer can be configured to have a reduced resistivity. In one example, it was observed that the resistivity of the power distribution network layer was less than 30 ohms for horizontal traces of at least 30 microns in length. Relative to their respective horizontal traces, the height of such a power distribution network layer can be at least twice the height of such an upper adjacent metal layer of such multiple metal layers.

[0091] Because one or more of the examples described herein may be implemented in an FPGA, a detailed description of such an IC is provided. However, it should be understood that other types of ICs may benefit from the techniques described herein.

[0092] A programmable logic device (PLD) is a well-known integrated circuit that can be programmed to perform a specified logic function. One type of PLD, a field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles may include, for example, input / output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAMs), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay locked loops (DLLs), etc. As used herein, "include" and "comprising" mean including but not limited to this.

[0093] Each programmable cell block generally includes programmable interconnect and programmable logic. Programmable interconnect generally includes a large number of interconnect lines of different lengths interconnected by programmable interconnect points (PIPs). Programmable logic uses programmable elements to implement user-designed logic, which may include, for example, function generators, registers, arithmetic logic, etc.

[0094] Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. Configuration data can be read from memory (e.g., from an external PROM) or written to the FPGA by an external device. The collective state of the individual memory cells then determines the functionality of the FPGA.

[0095] Another type of PLD is the complex programmable logic device (CPLD). A CPLD consists of two or more "functional blocks" that are connected together and to input / output (I / O) resources through an interconnecting switch matrix. Each functional block of a CPLD consists of a two-level AND / OR structure similar to that used in programmable logic array (PLA) and programmable array logic (PAL) devices. In a CPLD, configuration data is typically stored on-chip in nonvolatile memory. In some CPLDs, configuration data is stored on-chip in nonvolatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

[0096] For all of these programmable logic devices (PLDs), the function of the device is controlled by the data bits provided to the device for this purpose. The data bits can be stored in volatile memory (e.g., static memory cells in FPGAs and some CPLDs), non-volatile memory (e.g., FLASH memory in some CPLDs), or any other type of memory cell.

[0097] Other PLDs are programmed by applying a processing layer (e.g., a metal layer) that programmably interconnects the various cells on the device. These PLDs are called mask programmable devices. PLDs may also be implemented in other ways, for example, using fuse or anti-fuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, and include devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch structure that programmably interconnects the hard-coded transistor logic.

[0098] As mentioned above, advanced FPGAs can include several different types of programmable logic blocks in an array. For example, Figure 6An FPGA architecture 600 is shown, which includes a large number of different programmable unit blocks, including multi-gigabit transceivers (MGTs) 601, configurable logic blocks (CLBs) 602, random access memory blocks (BRAMs) 603, input / output blocks (IOBs) 604, configuration and clock logic (CONFIG / CLOCKS) 605, digital signal processing blocks (DSPs) 606, dedicated input / output blocks (I / Os) 607 (e.g., configuration ports and clock ports), and other programmable logic 608, such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. Some FPGAs also include dedicated processor blocks (PROCs) 610.

[0099] In some FPGAs, each programmable cell block includes a programmable interconnect element (INT) 611 that has standardized connections to and from corresponding interconnect elements in each adjacent cell block. Thus, the programmable interconnect elements together implement the programmable interconnect structure for the FPGA shown. Programmable interconnect element 611 also includes connections to and from programmable logic elements within the same cell block, such as Figure 6 The example included at the top is shown.

[0100] For example, CLB 602 may include a configurable logic element (CLE) 612 that can be programmed to implement user logic and a single programmable interconnect element (INT) 611. In addition to one or more programmable interconnect elements, BRAM 603 may also include a BRAM logic element (BRL) 613. Typically, the number of interconnect elements included in a cell block depends on the height of the cell block. In the illustrated embodiment, the BRAM block has the same height as five CLBs, but other numbers (e.g., four) may also be used. In addition to an appropriate number of programmable interconnect elements, DSP cell block 606 may also include a DSP logic element (DSPL) 614. In addition to one instance of programmable interconnect element 611, IOB 604 may also include, for example, two instances of input / output logic element (IOL) 615. Those skilled in the art will appreciate that the actual I / O pads connected to the I / O logic element 615 are typically not limited to the area of ​​the input / output logic element 615.

[0101] In the illustrated embodiment, the horizontal area near the center of the die (eg Figure 6 609 are used to distribute clock and configuration signals across the width of the FPGA.

[0102] Some use Figure 6The FPGA of the illustrated architecture includes additional logic blocks that disrupt the regular columnar structure that makes up a large portion of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic. For example, processor block 610 spans several columns of CLBs and BRAMs.

[0103] It should be pointed out that Figure 6 The present invention is intended only to illustrate an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative widths of the rows, the number and order of the rows, the types of logic blocks contained in the rows, the relative sizes of the logic blocks, and the number of logic blocks contained in the rows. Figure 6 The interconnect / logic implementation scheme shown at the top is exemplary only. For example, in a real FPGA, wherever a CLB appears, it is usually accompanied by more than one adjacent CLB row to facilitate efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA.

[0104] An apparatus related to an active-area-on-active-area microelectronic device may be provided. The active-area-on-active-area microelectronic device may include: a first die having a first substrate having a through-substrate via extending between an upper surface and a lower surface of the first substrate; a second die having a second substrate having an upper surface and a lower surface; the first die is on the second die, the lower surface of the first substrate faces the upper surface of the second substrate to provide a die stack; the first die and the second die respectively have a plurality of metal layers formed in a plurality of interlayer dielectric layers to respectively provide a first stack structure and a second stack structure for conduction; the first stack structure is interconnected to an upper end of the through-substrate via for conduction. The metal layer of the second stacked structure near the lower surface of the first substrate is interconnected to the lower end of the through hole penetrating the substrate for conduction; the power distribution network layer of the second stacked structure is located between the lower and upper layers of its multiple metal layers; the first transistor and the second transistor are at least partially located in the first substrate and the second substrate, respectively; the second transistor is interconnected to the power distribution network layer to receive at least one of a power supply voltage or a ground.

[0105] In some such active-area-on-active-area microelectronic devices, the through-substrate via can be a first through-substrate via, and wherein the second die has a second through-substrate via extending between the upper and lower surfaces of the second substrate.

[0106] Some such active-area-on-active-area microelectronic devices may also include: a third die having a third substrate having an upper surface and a lower surface; the third die having a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a third stacking structure for conduction; and a second die on the third die, with the lower surface of the second substrate facing the upper surface of the third substrate to provide a die stack.

[0107] Some such active-area-on-active-area microelectronic devices may also include: a second stacked structure interconnected to the upper end of the second through-substrate via for conduction; and a metal layer of a third stacked structure near the lower surface of the second substrate, which is interconnected to the lower end of the second through-substrate via for conduction.

[0108] In some such active-area-on-active-area microelectronic devices, the power distribution layer may be a first power distribution network layer; the first stacked structure has a second power distribution network layer, which is located between the lower and upper layers of its multiple metal layers; and the third stacked structure has a third power distribution network layer, which is located between the lower and upper layers of its multiple metal layers.

[0109] In some such active-area-on-active-area microelectronic devices, a first transistor of a first die may be interconnected to a second power distribution network layer to receive at least one of a power supply voltage or a ground; a third transistor of a third die at least partially formed in a third substrate may be interconnected to a third power distribution network layer to receive at least one of a power supply voltage or a ground.

[0110] In some such active-area-on-active-area microelectronic devices, each of the first, second, and third stacked structures can be configured to have a higher via density in a lower layer of its multiple metal layers than in an upper layer of its multiple metal layers, respectively, thereby providing, for each of the first, second, and third stacked structures, a lower resistivity path through the lower layer than through the upper layer.

[0111] In some such active-area-on-active-area microelectronic devices, the upper layer of each of the first, second, and third stacked structures can be configured to have a stacking resistance greater than 2 but less than 10 ohms; the lower layer of each of the first, second, and third stacked structures can be configured to have a stacking resistance equal to or less than 1 ohm.

[0112] In some such active-area-on-active-area microelectronic devices, each of the first, second, and third power distribution network layers can provide local power and ground routing to the second, first, and third transistors, respectively.

[0113] In some such active-area-on-active-area microelectronic devices, each of the first, second, and third power distribution network layers can be configured to provide intra-die power and ground bussing for the second, first, and third dies, respectively.

[0114] Some of such active-area-on-active-area microelectronic devices may further include a circuit platform interconnected to the first die for conducting electricity, external input power and ground busing for the die stack.

[0115] In some such active-area-on-active-area microelectronic devices, the third stacked structure may be a partial stacked structure extending from the metal layer of the third stacked structure to the third power distribution network layer.

[0116] In some such active-area-on-active-area microelectronic devices, the power distribution layer may be a first power distribution network layer; a third stacked structure having a second power distribution network layer between lower and upper layers of its multiple metal layers; and a third die having a third through-substrate via extending between the upper and lower surfaces of the third substrate and interconnected to the third stacked structure for conduction.

[0117] Some such active-area-on-active-area microelectronic devices may further include a third transistor of a third die at least partially formed in a third substrate interconnected with the second power distribution network layer to receive at least one of a supply voltage or ground.

[0118] Some such active-area-on-active-area microelectronic devices may also include a circuit platform interconnected to a third die for electrical conduction, external input power to the die stack, and ground busing.

[0119] In some such active-area-on-active-area microelectronic devices, the first stacked structure can be configured to distribute at least one of a power supply voltage or a ground from an uppermost metal layer of the first stacked structure downward to the first transistor.

[0120] In another example, a method involving forming an active-area-on-active-area microelectronic device may be provided. The method for forming an active-area-on-active-area microelectronic device may include: obtaining a first die having a first substrate, the first substrate having a through hole extending through the substrate between an upper surface and a lower surface of the first substrate; obtaining a second die having a second substrate, the second substrate having an upper surface and a lower surface; interconnecting the second die to the first die so that the lower surface of the first substrate faces the upper surface of the second substrate to provide a die stack; wherein the first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stack structure and a second stack structure for electrical conduction, respectively. Two stacked structures; wherein the first stacked structure can be interconnected to the upper end of the through-hole through the substrate for conduction; the interconnection includes connecting the metal layer of the second stacked structure near the lower surface of the first substrate to the lower end of the through-hole through the substrate for conduction; wherein the power distribution network layer of the second stacked structure can be located between the lower and upper layers of its multiple metal layers; wherein the first transistor and the second transistor can be at least partially located in the first substrate and the second substrate, respectively; and wherein the second transistor can be interconnected to the power distribution network layer to receive at least one of a power supply voltage or a ground.

[0121] Such a method may also include: wherein the through-substrate via may be a first through-substrate via; wherein the second die has a second through-substrate via extending between an upper surface and a lower surface of the second substrate; wherein the third die has a third substrate having an upper surface and a lower surface; wherein the third die has a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a third stacked structure for conduction; and interconnecting the second die on the third die so that the lower surface of the second substrate faces the upper surface of the third substrate to provide a die stack.

[0122] In some such methods, the second stacked structure can be interconnected to the upper end of the second through-substrate via for conduction, for conduction; the interconnection of the second tube core on the third tube core includes connecting the metal layer of the third stacked structure, close to the lower surface of the second substrate, to the lower end of the second through-substrate via for conduction.

[0123] In some such methods, the power distribution layer can be a first power distribution network layer; the first stacked structure has a second power distribution network layer, which is located between the lower and upper layers of its multiple metal layers; the third stacked structure has a third power distribution network layer, which is located between the lower and upper layers of its multiple metal layers; the first transistor of the first tube core can be interconnected to the second power distribution network layer to receive at least one of the power supply voltage or ground; and the third transistor of the third tube core can be interconnected to the third power distribution network layer to receive at least one of the power supply voltage or ground.

[0124] Examples of semiconductor dies, active-area-on-active-area microelectronic devices, and methods for manufacturing active-area-on-active-area microelectronic devices are also disclosed. In one example, the semiconductor die includes a first standard cell disposed within a first die body and a first plurality of metal layers disposed within the first die body above the first standard cell. The first plurality of metal layers form a portion of a first BEOL stack. The first plurality of metal layers includes a first metal layer closest to the first standard cell and a last metal layer farthest from the first standard cell. The first plurality of metal layers includes a first power distribution network layer disposed above the first standard cell and below a last metal layer of the first plurality of metal layers. The first power distribution network layer is configured to provide at least one of a supply voltage or ground to the first standard cell.

[0125] In another example, the semiconductor die may further include a first plurality of vias extending between the upper surface and the lower surface of the first die body. The vias are electrically coupled to the first power distribution network layer.

[0126] In another example, the first power distribution network layer of the semiconductor die may optionally be at least twice as thick as the first and last metal layers. The first power distribution network layer may optionally have a lower resistivity relative to the first plurality of metal layers disposed above and below the first power distribution network layer.

[0127] In another example, a first plurality of metal layers disposed above the first power distribution network layer of the semiconductor die may be optionally configured to have a stacking resistance greater than 2 but less than 10 ohms, wherein a plurality of first metal layers disposed below the power distribution network layer are configured to have a stacking resistance equal to or less than 1 ohm.

[0128] In another example, an active-area-on-active-area microelectronic device is provided, comprising a first die; a second die having a standard cell formed therein; the first die is stacked on the second die to provide a die stack; the first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stacking structure and a second stacking structure; and a power distribution network layer of the second stacking structure, located between a first metal layer among the plurality of metal layers closest to the standard cell and a last metal layer among the plurality of metal layers farthest from the standard cell, the power distribution network layer being configured to provide a power supply voltage or ground to the standard cell.

[0129] In another example, the active-area-on-active-area microelectronic device further includes a first through-substrate via extending from an upper surface to a lower surface of the first die, and a second through-substrate via extending between an upper surface and a lower surface of the second substrate. The first through-substrate via is coupled to the second through-substrate via by a bonding material disposed between the first die and the second die.

[0130] In another example, the above-mentioned active-area-on-active-area microelectronic device also includes a third tube core having a third substrate, the third substrate having an upper surface and a lower surface, the third tube core having multiple metal layers formed in multiple interlayer dielectrics to provide a third stacking structure for conduction, and the second tube core is on the third tube core, so that the lower surface of the second substrate faces the upper surface of the third substrate to provide a tube core stack.

[0131] In another example, the above-mentioned active-area microelectronic device on the active area also includes a second stacked structure, which is interconnected to the upper end of the second through-substrate through-hole for conduction; and the metal layer of the third stacked structure near the lower surface of the second substrate is interconnected to the lower end of the second through-substrate through-hole for conduction.

[0132] In another example, a power distribution network layer of the active area microelectronic device above the active area has a lower resistivity relative to a plurality of metal layers disposed above the standard cells.

[0133] In another example, a power distribution network layer of the active area microelectronic device on the active area is at least twice as thick as a metal layer of the plurality of metal layers disposed above the standard cell.

[0134] In another example, an upper layer of a first stacking structure of an active area microelectronic device on the above-mentioned active area is configured to have a stacking resistance greater than 2 but less than 10 ohms, and the upper layer is arranged above a power distribution network layer; and a lower layer of the first stacking structure is configured to have a stacking resistance equal to or less than 1 ohm, and the lower layer is arranged between the standard unit and the power distribution network layer.

[0135] In another example, the first stacked structure of the active-area-on-active-area microelectronic device is configured to have a higher density of vias in lower layers of the plurality of metal layers than in upper layers of the plurality of metal layers to provide a lower resistivity path through the lower layers than through the upper layers.

[0136] In another example, a method of forming an active-area-on-active-area microelectronic device is provided, the method comprising obtaining a first die having a first substrate, the first substrate having a through-substrate via extending between an upper surface and a lower surface of the first substrate; obtaining a second die having a second substrate, the second substrate having an upper surface and a lower surface; interconnecting the first die on the second die with the lower surface of the first substrate facing the upper surface of the second substrate to provide a die stack; wherein the first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a plurality of metal layers for conducting electricity, respectively. A first stacking structure and a second stacking structure; wherein the first stacking structure is interconnected to the upper end of a through hole through the substrate for conduction; the interconnection includes connecting a metal layer of the second stacking structure near the lower surface of the first substrate to the lower end of the through hole through the substrate for conduction; wherein a power distribution network layer of the second stacking structure is located between lower and upper layers of its multiple metal layers; wherein the first target circuit and the second target circuit are at least partially located in the first substrate and the second substrate, respectively; and wherein the second target circuit is interconnected to the power distribution network layer to receive at least one of a power supply voltage or a ground.

[0137] In another example, the method further includes: the through-substrate via is a first through-substrate via; wherein the second die has a second through-substrate via extending between an upper surface and a lower surface of the second substrate; wherein the third die has a third substrate having an upper surface and a lower surface; wherein the third die has a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a third stacked structure for conduction; and interconnecting the second die on the third die so that the lower surface of the second substrate faces the upper surface of the third substrate to provide a die stack.

[0138] Although exemplary devices and / or methods are described above, other and further examples according to one or more aspects described herein may be devised without departing from the scope thereof, which is determined by the appended claims and their equivalents. The steps listed in the claims do not imply any order of the steps. Trademarks are property of their respective owners.

Claims

1. A semiconductor die, characterized in that: The semiconductor die comprises: A first die having through silicon vias (TSVs) and a chimney stack, wherein the TSVs and the chimney stack form a conductive path between an upper surface and a lower surface of the first die; a first standard cell disposed within the first die; and a first plurality of metal layers, the first plurality of metal layers being arranged within the first die on the first standard cell, the first plurality of metal layers forming part of a first BEOL stack, the first plurality of metal layers comprising a first metal layer closest to the first standard cell and a last metal layer farthest from the first standard cell, the first plurality of metal layers comprising: A first power distribution network layer, the first power distribution network layer is arranged above the first metal layer of the first plurality of metal layers and below the last metal layer, the first power distribution network layer includes a horizontal routing formed in a groove in an interlayer dielectric layer associated with the first power distribution network layer, and is configured to provide at least one of a power supply voltage or a ground to the first standard unit, wherein the first power distribution network layer, the first metal layer and the last metal layer include multiple portions of the chimney stack, and the first power distribution network layer is thicker than the first metal layer and the last metal layer.

2. The semiconductor die according to claim 1, characterized in that The chimney stack and the TSV are vertically aligned.

3. The semiconductor die according to claim 2, characterized in that The first power distribution network layer is at least twice as thick as the first metal layer and the last metal layer.

4. The semiconductor die according to claim 2, characterized in that The first power distribution network layer has a lower resistivity relative to the first plurality of metal layers disposed above and below the first power distribution network layer.

5. The semiconductor die according to claim 2, characterized in that The first plurality of metal layers arranged above the first power distribution network layer are configured to have a stack resistance greater than 2 ohms but less than 10 ohms, and the first plurality of metal layers arranged below the first power distribution network layer are configured to have a stack resistance equal to or less than 1 ohm.

6. An active area on active area microelectronic device, characterized in that: The active area microelectronic device on the active area includes: a first tube core; a second die having a standard cell formed therein; The first die is stacked on the second die to provide a die stack; The first die and the second die each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a first stacked structure and a second stacked structure, the first stacked structure and the second stacked structure forming a vertically aligned conductive path between an upper surface and a lower surface of each of the first die and the second die; The power distribution network layer of the second stacked structure is located between the first metal layer among the multiple metal layers closest to the standard cell and the last metal layer among the multiple metal layers farthest from the standard cell, the power distribution network layer includes horizontal routing formed in a groove in an interlayer dielectric layer associated with the power distribution network layer, and is configured to provide a power supply voltage or ground to the standard cell, wherein the power distribution network layer is thicker than the first metal layer and the last metal layer.

7. The active-area-on-active-area microelectronic device according to claim 6, characterized in that: The active area microelectronic device on the active area further comprises: a first through-substrate via extending through the first substrate of the first die, and a second through-substrate via extending through the second substrate of the second die, the first through-substrate via being coupled to the second through-substrate via by a bonding material disposed between the first die and the second die, and coupling the conductive path of each of the first die and the second die.

8. The active-area-on-active-area microelectronic device according to claim 7, characterized in that: The active area microelectronic device on the active area further comprises: a third tube core, the third tube core having a third substrate, the third substrate having an upper surface and a lower surface; The third die has a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a third stacked structure for conducting electricity; and The second die is on the third die, and the lower surface of the second substrate faces the upper surface of the third substrate to provide a die stack.

9. The active-area-on-active-area microelectronic device according to claim 8, characterized in that: The active area microelectronic device on the active area further comprises: The second stacked structure is interconnected to an upper end of the second through-substrate via for conduction; and The metal layer of the third stacked structure near the lower surface of the second substrate is interconnected to the lower end of the second through-substrate via for conduction.

10. The active-area-on-active-area microelectronic device according to claim 6, characterized in that: The power distribution network layer has a lower resistivity than the plurality of metal layers disposed above the standard cells.

11. The active-area-on-active-area microelectronic device according to claim 6, characterized in that: The thickness of the power distribution network layer is at least twice the thickness of a metal layer of the plurality of metal layers disposed above the standard cell.

12. The active-area-on-active-area microelectronic device according to claim 6, characterized in that: The plurality of upper layers of the first stack structure are configured to have a stack resistance greater than 2 ohms but less than 10 ohms, the upper layers being arranged above the power distribution network layer; and A plurality of lower layers of the first stack structure are configured to have a stack resistance equal to or less than 1 ohm, the lower layers being arranged between the standard cell and the power distribution network layer.

13. The active-area-on-active-area microelectronic device according to claim 12, characterized in that: The first stack structure is configured to have a higher density of vias in a lower layer of the plurality of metal layers than in an upper layer of the plurality of metal layers to provide a lower resistivity path through the lower layer than the upper layer.

14. A method for forming an active area on an active area microelectronic device, characterized in that: The method comprises: Acquire a first tube die having a first substrate, the first substrate having a through hole extending between an upper surface and a lower surface of the first substrate and penetrating the substrate, the first tube die having a first standard unit; Acquire a second tube die having a second substrate, the second substrate having an upper surface and a lower surface, the second tube die having a second standard cell; interconnecting the first die to the second die with the lower surface of the first substrate facing the upper surface of the second substrate to provide a die stack; wherein the first tube core and the second tube core each have a plurality of metal layers formed in a plurality of interlayer dielectric layers to respectively provide a first stacking structure exposed to an upper surface of the first tube core and a second stacking structure exposed to an upper surface of the second tube core, which are respectively located above the first standard cell and the second standard cell for conducting electricity; wherein the first stacked structure is interconnected to an upper end of a through hole penetrating the substrate for conducting electricity; The interconnection includes connecting the metal layer of the second stack structure near the lower surface of the first substrate to the lower end of the through-substrate via for conduction; wherein a power distribution network layer of the second stacked structure is located between multiple lower layers and multiple upper layers of its multiple metal layers, wherein the power distribution network layer is thicker than a first metal layer in the lower layers closest to the second standard cell and a last metal layer in the upper layers farthest from the second standard cell; wherein the first target circuit and the second target circuit are at least partially located in the first substrate and the second substrate respectively; and The second target circuit is interconnected to a horizontal trace of the power distribution network layer to receive at least one of a power supply voltage or a ground, wherein the horizontal trace is formed in a trench of one of a plurality of interlayer dielectric layers associated with the power distribution network layer.

15. The method according to claim 14, characterized in that The method further comprises: The through hole penetrating the substrate is a first through hole penetrating the substrate; wherein the second die has a second through-substrate through hole extending between the upper surface and the lower surface of the second substrate; wherein the third tube core has a third substrate, and the third substrate has an upper surface and a lower surface; wherein the third die has a plurality of metal layers formed in a plurality of interlayer dielectric layers to provide a third stacked structure for conducting electricity; and The second die is interconnected to the third die with the lower surface of the second substrate facing the upper surface of the third substrate to provide a die stack.

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